CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com CMOS QUAD BILATERAL SWITCH Check for Samples: CD4066B-Q1 FEATURES 1 • • • • • • • • • • • • • Qualified for Automotive Applications 15-V Digital or ±7.5-V Peak-to-Peak Switching 125-Ω Typical On-State Resistance for 15-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 kΩ High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD – VSS ≥ 10 V, RL = 10 kΩ Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at VDD – VSS = 10 V, TA = 25°C Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 1012 Ω Typical Low Crosstalk Between Switches: –50 dB Typical at fis = 8 MHz, RL = 1 kΩ Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch On = 40 MHz Typical 100% Tested for Quiescent Current at 20 V • • • 5-V, 10-V, and 15-V Parametric Ratings Latch-Up Exceeds 100mA per JESD78 - Class I Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of "B" Series CMOS Devices APPLICATIONS • • • • • Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch Digital Signal Switching/Multiplexing Transmission-Gate Logic Implementation Analog-to-Digital and Digital-to-Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain E, F, M, NS, OR PW PACKAGE (TOP VIEW) SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C VSS 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT DESCRIPTION/ORDERING INFORMATION The CD4066B-Q1 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B-Q1 consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE –40°C to 125°C SOIC – D Reel of 2500 ORDERABLE PART NUMBER TOP-SIDE MARKING CD4066BQDRQ1 CD4066BQ Switch Control In Vis p n p n Control VC † Out Vos n VSS VDD VSS † All control inputs are protected by the CMOS protection network. NOTES: A.All p substrates are connected to V DD. B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS C. Signal-level range: VSS ≤V is ≤ VDD Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) DC supply-voltage range, VDD (voltages referenced to VSS terminal) VALUE UNIT –0.5 to 20 V –0.5 to VDD + 0.5 V ±10 mA D package 86 °C/W Human-Body Model (HBM) 500 Input voltage range, Vis (all inputs) DC input current, IIN (any one input) Package thermal impedance, θJA (2) ESD Electrostatic discharge (3) Machine Model (MM) 150 Field_Induced_Charged Device Model (CDM) 1000 Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max Storage temperature range, Tstg (1) (2) (3) V 265 °C –65 to 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Tested in accordance with AEC-Q100. THERMAL INFORMATION CD4066B-Q1 THERMAL METRIC (1) D PACKAGE UNITS 14 PINS θJA Junction-to-ambient thermal resistance 92.4 θJCtop Junction-to-case (top) thermal resistance 52.5 θJB Junction-to-board thermal resistance 46.7 ψJT Junction-to-top characterization parameter 46.4 ψJB Junction-to-board characterization parameter 46.4 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS VDD Supply voltage TA Operating free-air temperature MIN MAX 3 18 V –40 125 °C Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 UNIT 3 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) LIMITS AT INDICATED TEMPERATURES PARAMETER IDD TEST CONDITIONS Quiescent device current VIN (V) VDD (V) –40°C 125°C 25°C UNIT TYP MAX 0.5 5 0.25 7.5 0.01 0.25 0.10 10 0.5 15 0.01 0.5 0.15 15 1 30 0.01 1 0.20 20 5 150 0.02 5 µA SIGNAL INPUTS (Vis) AND OUTPUTS (Vos) VC = VDD, RL = 10 kΩ returned ron Δron THD Iis tpd 5 850 1300 470 1050 10 330 550 180 400 to , Vis = VSS 2 to VDD 15 210 320 125 240 On-state resistance difference between any two switches 5 15 RL = 10 kΩ, VC = VDD 10 10 15 5 Total harmonic distortion VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 10 kΩ, fis = 1-kHz sine wave 3-dB cutoff frequency (switch on) VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ –50-dB feedthrough frequency (switch off) VC = VSS = –5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ Input/output leakage current (switch off) (max) VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V, Vis = 0 V, Vos = 18 V –50-dB crosstalk frequency VC(A) = VDD = 5 V, VC(B) = VSS = -5 V, Vis(A) = 5 Vp-p, 50-Ω source, RL = 1 kΩ Propagation delay (signal input to signal output) RL = 200 kΩ, VC = VDD, VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V), tr, tf = 20 ns On-state resistance (max) V DD V SS Ω Ω 0.4% 18 ±0.1 ±1 40 MHz 1 MHz ±10-5 ±0.1 8 µA MHz 5 20 40 10 10 20 15 7 15 ns Cis Input capacitance VDD = 5 V, VC = VSS = –5 V 8 pF Cos Output capacitance VDD = 5 V, VC = VSS = –5 V 8 pF Cios Feedthrough VDD = 5 V, VC = VSS = –5 V 0.5 pF 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) LIMITS AT INDICATED TEMPERATURES PARAMETER VIN (V) TEST CONDITIONS VDD (V) –40°C 125°C 25°C TYP UNIT MAX CONTROL (VC) VILC Control input, low voltage (max) |Iis| < 10 mA, Vis = VSS, VOS = VDD, and Vis = VDD, VOS = VSS 5 1 1 1 10 2 2 2 15 2 2 2 5 VIHC IIN Control input, low voltage 3.5 (MIN) 10 7 (MIN) 15 11 (MIN) ±10-5 Vis ≤ VDD, VDD – VSS = 18 V, VCC ≤ VDD – VSS 18 Crosstalk (control input to signal output) VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 kΩ 10 50 5 35 70 Turn-on and turn-off propagation delay VIN = VDD, tr, tf = 20 ns, CL = 50 pF, RL = 1 kΩ 10 20 40 15 15 30 Vis = VDD, VSS = GND, RL = 1 kΩ to GND, CL = 50 pF, VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz ±0.1 V Input current (max) Maximum control input repetition rate Ci See Figure 6 V ±1 5 6 10 9 15 9.5 Input capacitance ±0.1 µA mW ns MHz 5 pF SWITCHING CHARACTERISTICS SWITCH INPUT VDD (V) SWITCH OUTPUT, Vos (V) Vis (V) Iis (mA) –40°C 25°C 125°C 5 0 0.61 0.51 0.36 5 5 –0.61 –0.51 –0.36 10 0 1.5 1.3 0.9 10 10 –1.6 –1.3 –0.9 15 0 4 3.4 2.4 15 15 –4 –3.4 –2.4 MIN MAX 0.4 4.6 1.5 13.5 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 5 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) Supply Voltage (VDD − VSS) = 5 V TA = 125°C 500 400 300 +25°C 200 −55°C 100 0 −4 −3 −2 −1 0 1 2 Vis − Input Signal Voltage − V 3 4 ron − Channel On-State Resistance − Ω r − Channel On-State Resistance − Ω on 600 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 300 Supply Voltage (VDD − VSS) = 10 V 250 TA = 125°C 200 +25°C 150 −55°C 100 50 0 −10 −7.5 −5 −2.5 250 200 TA = 125°C 150 +25°C 100 −55°C 50 0 0 2.5 5 Vis − Input Signal Voltage − V 7.5 10 r − Channel On-State Resistance − Ω on r − Channel On-State Resistance − Ω on 300 −2.5 Iis 10 TA = 125°C 600 Supply Voltage (VDD − VSS) = 5 V 500 400 300 200 10 V −15 V 100 0 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 V is − Input Signal Voltage − V 92CS-27330RI 92CS-27329RI Figure 4. Vis 7.5 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) Supply Voltage (VDD − VSS) = 15 V −5 5 Figure 3. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) −7.5 2.5 Vis − Input Signal Voltage − V 92CS-27327RI 92CS-27326RI Figure 2. −10 0 Figure 5. CD4066B 1 of 4 Switches ron = Vos |Vis − Vos| |Iis| 92CS-30966 Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Keithley 160 Digital Multimeter VDD TG On 10 kΩ 1-kΩ Range Y X-Y Plotter VSS H. P. Moseley 7030A X 92CS-22716 Figure 7. Channel On-State Resistance Measurement Circuit TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY 6 4 TA = 25°C 2 103 1 0 VC = VDD −1 Vis Vos RL VSS −2 All unused terminals are connected to VSS −3 −3 −2 −1 0 1 2 VI − Input Voltage − V 3 2 10 V 102 VDD CD4066B 1 of 4 Switches Supply Voltage (VDD) = 15 V 6 4 4 5V 6 4 14 VO − Output Voltage − V 2 PD − Power Dissipation Per Package − μ W 104 3 5 2 6 101 12 6 4 13 CD4066B 7 2 10 10 2 4 6 102 2 VDD 4 VSS 6 103 92CS-30919 f − Switching Frequency − kHz Figure 8. 92C-30920 Figure 9. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 7 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Cios Vis = VDD VDD = 5 V VC = −5 V VDD VC = VSS Vos CD4066B 1 of 4 Switches CD4066B 1 of 4 Switches I VSS 92CS-30922 All unused terminals are connected to VSS. Cis VSS = −5 V Cos 92CS-30921 Measured on Boonton capacitance bridge, model 75a (1 MHz); test-fixture capacitance nulled out. Figure 10. Typical On Characteristics for One of Four Channels +10 V VDD VC = VDD Vis Figure 11. Off-Switch Input or Output Leakage CD4066B 1 of 4 Switches VSS Vos 50 pF VDD VC Vis tr = tf = 20 ns 1 kΩ 200 kΩ CD4066B 1 of 4 Switches Vos 10 kΩ VSS VDD 92CS-30924 tr = tf = 20 ns 92CS-30923 All unused terminals are connected to VSS. All unused terminals are connected to VSS. Figure 12. Propagation Delay Time Signal Input (Vis) to Signal Output (Vos) Figure 13. Crosstalk-Control Input to Signal Output VDD VDD tr = tf = 20 ns VC = VDD VDD CD4066B 1 of 4 Switches VSS 50 pF Vos 1 kΩ NOTES: A.All unused terminals are connected to V SS. B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off). 92CS-30925 Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) tr tf VC 10 V 90% 50% 10% 0V Repetition Rate tr = tf = 20 ns Vos V OS V OS at 1kHz 2 VDD = 10 V VC Vis = 10 V CD4066B 1 of 4 Switches V OS 50 pF V OS at 1kHz 2 1 kΩ VSS All unused terminals are connected to VSS. 92CS-30925 Figure 15. Maximum Allowable Control-Input Repetition Rate VDD Inputs VDD I VSS 92CS-27555 VSS Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only. Figure 16. Input Leakage-Current Test Circuit Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 9 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 10 Clock Reset 14 2 PE J1 J2 7 9 J3 J4 12 Clock J5 CD4018B 15 1 3 External Reset 13 14 1/4 CD4066B 1 PE J1 3 7 9 12 J2 J3 J4 J5 CD4018B Q1 Q2 1 4 2 15 Q1 Q2 5 10 5 2 4 13 1 3 7 2 2 1/3 CD4049B 5 6 4 9 8 5 6 1 2 6 1/3 CD4049B 5 4 CD4001B 3 12 8 9 CD4001B 10 10 11 4 3 10 9 5 6 12 12 13 6 5 Signal Outputs 11 11 13 Signal Inputs 11 12 Channel 1 Channel 2 CD4066B 4 Channel 3 1 5 3 8 9 11 10 3 4 4 Channel 4 1/4 CD4066B 3 8 LPF 9 10 kΩ Channel 2 Channel 3 10 kΩ VDD Clock Maximum Allowable Signal Level LPF 10 kΩ CD4066B 11 Package Count 2 - CD4001B 1 - CD4049B 3 - CD4066B 2 - CD4018B Channel 1 10 k Ω 1/6 CD4049B 2 1 LPF 2 12 LPF Channel 4 10 10 kΩ 30% (VDD − VSS) VSS Chan 1 Chan 2 Chan 3 Chan 4 92CM-30928 Figure 17. Four-Channel PAM Multiplex System Diagram 5V 0 −5 V Analog Inputs (±5 V) VDD = 5 V VDD = 5 V 5V SWA 0 IN CD4054B CD4066B SWB SWC SWD Digital Control Inputs VSS = 0 V VEE = −5 V Analog Outputs (±5 V) VSS = −5 V 92CS-30927 Figure 18. Bidirectional Signal Transmission Via Digital Control Logic 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 CD4066B-Q1 SCHS383 – APRIL 2011 www.ti.com APPLICATION INFORMATION In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B-Q1 bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B-Q1. In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 V (calculated from ron values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CD4066B-Q1 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) CD4066BQDRQ1 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 14 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -40 to 125 CD4066BQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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