Order Now Product Folder Support & Community Tools & Software Technical Documents LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 LMR23630 SIMPLE SWITCHER® 36-V, 3-A Synchronous Step-Down Converter 1 Features 3 Description • • • • • • • • The LMR23630 SIMPLE SWITCHER® is an easy-touse 36 V, 3 A synchronous step-down regulator. With a wide input range from 4.5 V to 36 V (HSOIC) and 4 V to 36 V (WSON), it is suitable for various industrial applications for power conditioning from unregulated sources. Peak-current-mode control is employed to achieve simple control-loop compensation and cycleby-cycle current limiting. A quiescent current of 75 μA makes the device suitable for battery-powered systems. An ultra-low 2 μA shutdown current can further prolong battery life. Internal loop compensation means that the user is free from the tedious task of loop compensation design. This also minimizes the external components. The device has an option for constant frequency FPWM mode to achieve small output-voltage ripple at light load. An extended family (HSOIC) is available in 1-A (LMR23610) and 2.5-A (LMR23625) load-current options in a pin-to-pin compatible package allowing simple, optimum PCB layout. A precision enable input allows simplification of regulator control and system power sequencing. Protection features include cycleby-cycle current limit, hiccup-mode short-circuit protection, and thermal shutdown due to excessive power dissipation. 1 • • • • • • • • • • • 4.5-V to 36-V Input Range (HSOIC) 4-V to 36-V Input Range (WSON) 3-A Continuous Output Current Integrated Synchronous Rectification Current-Mode Control Minimum Switch On-Time: 60 ns Internal Compensation for Ease of Use 400-kHz Switching Frequency and Adjustable Frequency Options PFM and Forced PWM Mode Options Frequency Synchronization to External Clock 75-µA Quiescent Current at No Load for PFM Option Soft Start into a Pre-Biased Load High Duty Cycle Operation Supported Precision Enable Input Output Short-Circuit Protection With Hiccup Mode Thermal Protection 8-Pin HHSOIC with PowerPAD™ Package 12-Pin WSON Wettable Flanks Package with PowerPAD™ Create a Custom Design Using the LMR23625 With the WEBENCH® Power Designer Device Information(1) PART NUMBER LMR23630 2 Applications • • • • • 90 Efficiency (%) VIN BOOT AGND L 3.00 mm × 3.00 mm 100 Simplified Schematic CBOOT WSON (12) Efficiency vs Load VIN = 12 V, PFM Option VIN up to 36 V EN/SYNC BODY SIZE (NOM) 4.89 mm × 3.90 mm (1) For detail part numbers for all available different options, see the orderable addendum at the end of the data sheet. Programmable Logic Controller Power Supply Multi-Function Printers HVAC Systems Industrial Power Supplies GSM, GPRS Modules for Fleet Management, Smart Grids, and Security CIN PACKAGE HSOIC (8) 80 70 60 VOUT SW 50 VOUT = 5 V VOUT = 3.3 V RFBT COUT VCC FB CVCC RFBB 40 0.0001 0.001 0.01 0.1 IOUT (A) 1 10 D001 PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 5 5 5 6 6 8 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 19 9 Application and Implementation ........................ 20 9.1 Application Information............................................ 20 9.2 Typical Applications ................................................ 20 10 Power Supply Recommendations ..................... 26 11 Layout................................................................... 26 11.1 11.2 11.3 11.4 11.5 Layout Guidelines ................................................. Layout Example .................................................... Compact Layout for EMI Reduction ...................... Ground Plane and Thermal Considerations.......... Feedback Resistors .............................................. 26 27 28 28 29 12 Device and Documentation Support ................. 30 12.1 12.2 12.3 12.4 12.5 12.6 Custom Design With WEBENCH® Tools ............. Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 30 30 30 30 30 30 13 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History Changes from Revision B (April 2017) to Revision C Page • Deleted Deleted "Automotive Battery Regulation" and reworded Applications ..................................................................... 1 • Added WSON Package and Options .................................................................................................................................... 1 • Added Device Comparison Table .......................................................................................................................................... 3 • Change EN Abs Max to EN/SYNC Abs Max ......................................................................................................................... 5 • Updating ESD Ratings to include HSOIC and WSON .......................................................................................................... 5 • Corrected Equation 17 denominator from "(VOUT x VOS)" to "(VOUT + VOS)" ......................................................................... 23 • clarified equations Equation 23 and Equation 24 ................................................................................................................. 28 Changes from Revision A (July 2016) to Revision B Page • Changed spec from 6.0 to 6.2 for max under Current Limit................................................................................................... 7 • Changed spec from 4.2 to 4.6 for max under Current Limit................................................................................................... 7 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2015) to Revision A • 2 Page Changed from Product Preview to Production Data with all the remaining sections added. ................................................. 1 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 5 Device Comparison Table PACKAGE HSOIC (8) WSON (12) (Pin 6 is RT) WSON (12) (Pin 6 is PGOOD) PART NUMBER FIXED 400 kHz ADJUSTABLE FREQUENCY RESISTOR POWER GOOD FPWM LMR23630ADDA yes no no no LMR23630AFDDA yes no no yes LMR23630DRR no yes no no LMR23630FDRR no yes no yes LMR23630APDRR yes no yes no 6 Pin Configuration and Functions DRR Package 12-Pin WSON With RT and Thermal Pad Top View DRR Package 12-Pin WSON With PGOOD and Thermal Pad Top View DDA Package 8-Pin HSOIC Top View SW 1 BOOT 2 VCC FB 8 PGND 7 VIN 3 6 AGND 4 5 EN/SYNC Thermal Pad (9) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 3 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Pin Functions PIN HSO IC I/O (1) DESCRIPTION WSON With RT WSON With PGOOD NAME 1 1, 2 1, 2 SW P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor. 2 3 3 BOOT P Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor from BOOT to SW. 3 4 4 VCC P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation. 4 5 5 FB A Feedback input to regulator, connect the midpoint of feedback resistor divider to this pin. N/A 6 N/A RT A Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 400-kHz default switching frequency. N/A N/A 6 PGOOD A Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 12 V. 5 8 8 EN/SYNC A Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust the input undervoltage lockout with two resistors. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. See Enable/Sync for details. 6 7 7 AGND G Analog ground pin. Ground reference for internal references and logic. Connect to system ground. 7 9, 10 9, 10 VIN P Input supply voltage. 8 12 12 PGND G Power ground pin, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible. 9 13 13 PAD G Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB. N/A 11 11 NC N/A (1) 4 Not for use. Leave this pin floating. A = Analog, P = Power, G = Ground. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 7 Specifications 7.1 Absolute Maximum Ratings (1) Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) PARAMETER Input voltages MIN MAX VIN to PGND –0.3 42 EN/SYNC to AGND –5.5 VIN+ 0.3 FB to AGND –0.3 4.5 RT to AGND –0.3 4.5 PGOOD to AGND –0.3 15 AGND to PGND –0.3 0.3 –1 VIN + 0.3 SW to PGND V –5 42 BOOT to SW –0.3 5.5 VCC to AGND –0.3 4.5 (2) TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C Output voltages (1) (2) SW to PGND less than 10 ns transients UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In shutdown mode, the VCC to AGND maximum value is 5.25 V. 7.2 ESD Ratings VALUE Human-body model (HBM) for HSOIC and WSON package V(ESD) (1) (2) Electrostatic discharge (1) ±2500 Charged-device model (CDM) for HSOIC and WSON RT (2) ±1000 Charged-device model (CDM) for WSON PGOOD (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) VIN (HSOIC) VIN (WSON) Input voltage EN/SYNC (1) MIN MAX 4.5 36 4 36 –5 36 FB –0.3 1.2 PGOOD –0.3 12 UNIT V Input current PGOOD pin current 0 1 mA Output voltage VOUT 1 28 V Output current IOUT 0 2.5 A Temperature Operating junction temperature, TJ –40 125 °C (1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 5 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 7.4 Thermal Information THERMAL METRIC (1) (2) DDA (8 PINS) DRR (12 PINS) UNIT RθJA Junction-to-ambient thermal resistance 42.0 41.5 °C/W ψJT Junction-to-top characterization parameter 5.9 0.3 °C/W ψJB Junction-to-board characterization parameter 23.4 16.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.8 39.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 3.4 °C/W RθJB Junction-to-board thermal resistance 23.4 16.3 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Determine power rating at a specific ambient temperature TA with a maximum junction temperature (TJ) of 125°C (see Recommended Operating Conditions ). 7.5 Electrical Characteristics Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY (VIN PIN) VIN Operation input voltage HSOIC package 4.5 36 WSON package 4 36 Rising threshold (HSOIC) VIN_UVLO Undervoltage lockout thresholds ISHDN Shutdown supply current IQ Operating quiescent current (nonswitching) 3.4 Falling hysteresis (HSOIC) 3.7 3.9 0.4 Rising threshold (WSON) 3.3 3.6 3.9 Falling threshold (WSON) 3 3.3 3.5 2 4 VEN = 0 V, VIN = 4.5 V to 36 V, TJ = –40°C to 125°C (HSOIC) VEN = 0 V, VIN = 12 V, TJ = –40°C to 125°C (WSON) VIN =12 V, VFB = 1.1 V, TJ = –40°C to 125°C, PFM mode 75 V V V μA μA ENABLE (EN PIN) VEN_H Enable rising threshold voltage VEN_HYS Enable hysteresis voltage VWAKE Wake-up threshold 1.4 Input leakage current at EN pin 1.7 0.4 V 10 VIN = 4 V to 36 V, VEN= 2 V (WSON) V V 0.4 VIN = 4.5 V to 36 V, VEN= 2 V (HSOIC) IEN 1.55 VIN = 4.5 V to 36 V, VEN= 36 V (HSOIC) 100 1 VIN = 4 V to 36 V, VEN= 36 V (WSON) nA nA μA μA VOLTAGE REFERENCE (FB PIN) VIN = 4.5 V to 36 V, TJ = 25 °C (HSOIC) VIN = 4.0 V to 36 V, TJ = 25 °C (WSON) VREF Reference voltage VIN = 4.5 V to 36 V, TJ = –40°C to 125°C (HSOIC) VIN = 4.0 V to 36 V, TJ = –40°C to 125°C (WSON) ILKG_FB 6 Input leakage current at FB pin VFB= 1 V Submit Documentation Feedback 0.985 1 1.015 V 0.98 1 1.02 V 10 nA Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD (PGOOD PIN) VPG_OV Power-good flag overvoltage tripping threshold % of reference voltage 104% 107% 110% VPG_UV Power-good flag undervoltage tripping threshold % of reference voltage 92% 94% 96.5% VPG_HYS Power-good flag recovery hysteresis % of reference voltage VIN_PG_MIN Minimum VIN for valid PGOOD output 50 μA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C 1.5 V 50 μA pullup to PGOOD pin, VIN = 1.5 V, VEN = 0 V 0.4 V 0.5 mA pullup to PGOOD pin, VIN = 13.5 V, VEN = 0 V 0.4 V VPG_LOW PGOOD low level output voltage 1.5% INTERNAL LDO (VCC PIN) VCC VCC_UVLO Internal LDO output voltage VCC undervoltage lockout thresholds 4.1 V Rising threshold 2.8 3.2 3.6 Falling threshold 2.4 2.8 3.2 HSOIC package 3.8 5 6.2 WSON package 4 5.5 6.6 HSOIC package 2.9 3.6 4.6 WSON package 2.9 3.6 4.2 V CURRENT LIMIT IHS_LIMIT Peak inductor current limit ILS_LIMIT Valley inductor current limit IL_ZC Zero cross current limit HSOIC and WSON package IL_NEG Negative current limit (FPWM option) SOIC and WSON package –0.04 –2.7 –2 A A A –1.3 A INTEGRATED MOSFETS RDS_ON_HS High-side MOSFET ON-resistance RDS_ON_LS Low-side MOSFET ON-resistance SOIC package, VIN = 12 V, IOUT = 1 A 185 WSON package, VIN = 12 V, IOUT = 1 A 160 SOIC package, VIN = 12 V, IOUT = 1 A 105 WSON package, VIN = 12 V, IOUT = 1 A mΩ mΩ 95 THERMAL SHUTDOWN TSHDN Thermal shutdown threshold THYS Hysteresis 162 170 178 15 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 °C °C 7 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 7.6 Timing Requirements Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT HICCUP MODE NOC (1) Number of cycles that LS current limit is tripped to enter hiccup mode TOC Hiccup retry delay time 64 SOIC package Cycles 5 WSON package ms 10 SOFT START TSS Internal soft-start time SOIC package, the time of internal reference to increase from 0 V to 1 V 2 WSON package, the time of internal reference to increase from 0 V to 1 V 6 ms ms POWER GOOD TPGOOD_RISE Power-good flag rising transition deglitch delay 150 μs TPGOOD_FALL Power-good flag falling transition deglitch delay 18 μs (1) Ensured by design. 7.7 Switching Characteristics Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) PARAMETER MIN TYP MAX UNIT SW (SW PIN) TON_MIN Minimum turnon time TOFF_MIN (1) Minimum turnoff time SOIC package 60 WSON package 60 ns 90 100 ns ns OSCILLATOR (RT and EN/SYNC PIN) fSW_DEFAULT fADJ Oscillator default frequency Fixed frequency version or RT pin open circuit 340 400 460 kHz Minimum adjustable frequency RT = 198 kΩ with 1% accuracy 150 200 250 kHz Maximum adjustable frequency RT = 17.8 kΩ with 1% accuracy 1750 2150 2425 kHz fSYNC SYNC frequency range 200 2200 kHz VSYNC Amplitude of SYNC clock AC signal (measured at SYNC pin) 2.8 5.5 TSYNC_MIN Minimum sync clock ON-time and OFF-time (1) 8 100 V ns Ensured by design. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 7.8 Typical Characteristics 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25°C. 60 50 40 PFM, VIN = 12 V PFM, VIN = 24 V PFM, VIN = 36 V FPWM, VIN = 12 V FPWM, VIN = 24 V FPWM, VIN = 36 V 30 20 10 0 1E-5 0.0001 0.001 fSW = 400 kHz 0.01 IOUT (A) 0.1 1 60 50 40 PFM, VIN = 12 V PFM, VIN = 24 V PFM, VIN = 36 V FPWM, VIN = 12 V FPWM, VIN = 24 V FPWM, VIN = 36 V 30 20 10 0 1E-5 10 VOUT = 5 V 90 90 80 80 70 70 60 50 40 PFM, VIN = 12 V PFM, VIN = 24 V PFM, VIN = 36 V FPWM, VIN = 12 V FPWM, VIN = 24 V FPWM, VIN = 36 V 30 20 10 0.001 fSW = 200 kHz (Sync) 0.01 IOUT (A) 0.1 1 0.1 1 10 D002 VOUT = 3.3 V 60 50 40 PFM, VIN = 12 V PFM, VIN = 24 V PFM, VIN = 36 V FPWM, VIN = 12 V FPWM, VIN = 24 V FPWM, VIN = 36 V 30 20 10 0 1E-5 10 0.0001 0.001 D003 VOUT = 5 V fSW = 200 kHz (Sync) Figure 3. Efficiency vs Load Current 0.01 IOUT (A) 0.1 1 10 D004 VOUT = 3.3 V Figure 4. Efficiency vs Load Current 5.015 5.09 VIN = 12 V VIN = 24 V VIN = 36 V VIN = 12 V VIN = 24 V VIN = 36 V 5.08 5.07 5.06 5.01 5.05 VOUT (V) VOUT (V) 0.01 IOUT (A) Figure 2. Efficiency vs Load Current 100 Efficiency (%) Efficiency (%) Figure 1. Efficiency vs Load Current 0.0001 0.001 fSW = 400 kHz 100 0 1E-5 0.0001 D001 5.04 5.03 5.005 5.02 5.01 5 5 4.99 0 0.5 PFM version 1 1.5 IOUT (A) 2 VOUT = 5 V 2.5 3 0 0.5 D004 FPWM Version Figure 5. Load Regulation 1 1.5 IOUT (A) 2 2.5 3 D005 VOUT = 5 V Figure 6. Load Regulation Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 9 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25°C. 5.5 3.6 5 4.5 VOUT (V) VOUT (V) 3.3 4 2.7 IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A 3.5 3 4 4.5 5 VIN (V) 5.5 3 IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A 2.4 3.3 6 3.5 3.7 D006 VOUT = 5 V 4.1 4.3 4.5 D007 VOUT = 3.3 V Figure 7. Dropout Curve Figure 8. Dropout Curve 3.67 VIN UVLO Rising Threshold (V) 80 75 IQ (µA) 3.9 VIN (V) 70 65 60 -50 0 50 Temperature (°C) VIN = 12 V 100 3.66 3.65 3.64 3.63 3.62 3.61 -50 150 0 D008 50 Temperature (°C) 100 150 D009 VFB = 1.1 V Figure 9. IQ vs Junction Temperature Figure 10. VIN UVLO Rising Threshold vs Junction Temperature 5.5 0.425 5 Current Limit (A) VIN UVLO Hysteresis (V) LS Limit HS Limit 0.42 0.415 4.5 4 3.5 0.41 -50 0 50 Temperature (°C) 100 150 3 -50 0 D010 50 Temperature (°C) 100 150 D011 VIN = 12 V Figure 11. VIN UVLO Hysteresis vs Junction Temperature 10 Figure 12. HS and LS Current Limit vs Junction Temperature Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 8 Detailed Description 8.1 Overview The LMR23630 SIMPLE SWITCHER® regulator is an easy-to-use synchronous step-down DC-DC converter operating from 4.5-V (HSOIC) and 4-V (WSON) to 36-V supply voltage. The device delivers up to 3-A DC load current with good thermal performance in a small solution size. For both the HSOIC and WSON packages, an extended family is available in multiple current options from 1 A to 3 A in pin-to-pin compatible packages. The LMR23630 employs constant frequency peak-current-mode control. The device enters PFM mode at light load to achieve high efficiency. A user-selectable FPWM version is provided to achieve low output voltage ripple, tight output voltage regulation, and constant switching frequency. The switching frequency is 400 kHz for the fixed-frequency version. For the version which has RT pin, the switching frequency is adjustable from 200 kHz to 2.2 MHz. The device is internally compensated, which reduces design time and requires few external components. The LMR23630 is capable of synchronization to an external clock within the range of 200 kHz to 2.2 MHz. Additional features such as precision enable, power-good flag, and internal soft-start provide a flexible and easyto-use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC undervoltage lockout, cycle-by-cycle current limit, and hiccup-mode short-circuit protection. The family requires very few external components and has a pinout designed for simple, optimum PCB layout. 8.2 Functional Block Diagram VCC EN/SYNC SYNC Signal SYNC Detector VCC Enable LDO VIN Precision Enable Internal SS CBOOT HS I Sense EA REF Rc TSD UVLO Cc (PGOOD) PWM CONTROL LOGIC PFM Detector OV/UV Detector SW FB Slope Comp Freq Foldback AGND Zero Cross HICCUP Detector SYNC Signal (RT) Oscillator LS I Sense FB PGND Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 11 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 8.3 Feature Description 8.3.1 Fixed Frequency Peak Current Mode Control The following operating description of the LMR23630 refers to the Functional Block Diagram and to the waveforms in Figure 13. The LMR23630 is a step-down synchronous buck regulator with integrated high-side (HS) and low-side (LS) switches (synchronous rectifier). The LMR23630 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON-time, the SW pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of a buck converter is defined as duty cycle D = tON / TSW, where tON is the high-side switch ON-time and TSW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. VSW SW Voltage D = tON/ TSW VIN tON tOFF t 0 -VD Inductor Current iL TSW ILPK IOUT 'iL t 0 Figure 13. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM) The LMR23630 employs fixed-frequency peak-current-mode control. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the peak current threshold to control the ON-time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load condition, the LMR23630 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode for low output-voltage ripple, tight output-voltage regulation, and constant switching frequency (FPWM option). 8.3.2 Adjustable Frequency The switching frequency can be programmed for the adjustable-switching-frequency version of LMR23630 by the impedance RT from the RT pin to ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the LMR23630 operates at 400-kHz default switching frequency. The RT pin is not designed to be shorted to ground. For a desired frequency, typical RT resistance can be found by Equation 1. Table 1 gives typical RT values for a given fSW. RT(kΩ) = 40200 / fSW(kHz) – 0.6 12 (1) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Feature Description (continued) 250 RT Resistance (kŸ) 200 150 100 50 0 0 500 1000 1500 2000 Switching Frequency (kHz) 2500 C008 Figure 14. RT vs Frequency Curve Table 1. Typical Frequency Setting RT Resistance fSW (kHz) RT (kΩ) 200 200 350 115 500 78.7 750 53.6 1000 39.2 1500 26.1 2000 19.6 2200 17.8 8.3.3 Adjustable Output Voltage A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the lowside resistor RFBB for the desired divider current and use Equation 2 to calculate high-side RFBT. RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. However, RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the output voltage regulation. VOUT RFBT FB RFBB Figure 15. Output Voltage Setting RFBT VOUT VREF u RFBB VREF (2) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 13 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 8.3.4 Enable/Sync The voltage on the EN pin controls the ON or OFF operation of LMR23630. A voltage less than 1 V (typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator. The EN pin is an input and cannot be left open or floating. The simplest way to enable the operation of the LMR23630 is to connect the EN to VIN. This allows self-start-up of the LMR23630 when VIN is within the operation range. Many applications can benefit from the employment of an enable divider RENT and RENB (Figure 16) to establish a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing and protection. VIN RENT EN/SYNC RENB Figure 16. System UVLO by Enable Divider The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC-coupling a positive edge into the EN pin. The AC-coupled peak-to-peak voltage at the EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock ON-time and OFF-time must be longer than 100 ns (typical). A 3.3-V or a higher amplitude pulse signal coupled through a 1-nF capacitor CSYNC is a good starting point. Keeping RENT // RENB (RENT parallel with RENB) in the 100 kΩ range is a good choice. RENT is required for this synchronization circuit, but RENB can be left unmounted if system UVLO is not needed. LMR23630 switching action can be synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 18 and Figure 19 show the device synchronized to an external system clock. VIN CSYNC RENT EN/SYNC RENB Clock Source Figure 17. Synchronize to External Clock 14 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Figure 18. Synchronizing in PWM Mode Figure 19. Synchronizing in PFM Mode 8.3.5 VCC, UVLO The LMR23630 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23630. VCC undervoltage lockout (UVLO) prevents the LMR23630 from operating until the VCC voltage exceeds 3.3 V (typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to temporary VIN drops. 8.3.6 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 60 ns in the LMR23630. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off. TOFF_MIN is typically 100 ns in the LMR23630. In CCM operation, TON_MIN and TOFF_MIN limit the voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is: DMIN = TON_MIN × fSW (3) And the maximum duty cycle allowed is: DMAX = 1 – TOFF_MIN × fSW (4) Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LMR23630, a frequency foldback scheme is employed to extend the maximum duty cycle when TOFF_MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions. Wide range of frequency foldback allows the LMR23630 output voltage stay in regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operation supply voltage can be found by: VOUT VIN _ MAX fSW u TON _ MIN (5) At lower supply voltage, the switching frequency decreases once TOFF_MIN is tripped. The minimum VIN without frequency foldback can be approximated by: VOUT VIN _ MIN 1 fSW u TOFF _ MIN (6) Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result calculated in Equation 5. With frequency foldback, VIN_MIN is lowered by decreased fSW. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 15 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 450 400 Frequency (kHz) 350 300 250 200 150 IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A 100 50 0 4.6 4.8 5 5.2 5.4 5.6 VIN (V) 5.8 6 6.2 6.4 D013 Figure 20. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 400 kHz) 8.3.7 Power Good (PGOOD) The power-good version of LMR23630 has a built in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage. Voltage detected by the PGOOD pin must never exceed 15 V, and limit the maximum current into this pin to 1 mA. A typical range of pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is within the power-good band, +6% above and –6% below the internal reference voltage VREF typically, the PGOOD switch is turned off, and the PGOOD voltage is as high as the pulled-up voltage. When the FB voltage is outside of the tolerance band, +7% above or –7% below VREF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled low to indicate power bad. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line and load transients. The values for the various filter and delay times can be found in the Timing Requirements table. Power-good operation can best be understood by reference to Figure 21. VREF 107% 106% 94% 93% PGOOD High Low Figure 21. Power-Good Flag 8.3.8 Internal Compensation and CFF The LMR23630 is internally compensated as shown in Functional Block Diagram. The internal compensation is designed so that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends an external feed-forward capacitor CFF be placed in parallel with the top resistor divider RFBT for optimum transient performance. 16 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 VOUT RFBT CFF FB RFBB Figure 22. Feed-forward Capacitor for Loop Compensation The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by: 1 fZ _ CFF 2S u CFF u RFBT (7) An additional pole is also introduced with CFF at the frequency of: 1 fP _ CFF 2S u CFF u RFBT //RFBB (8) The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover. Table 2 lists the combination of COUT, CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value, adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged. Designs with different combinations of output capacitors need different CFF. Different types of capacitors have different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF. Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at the output may not need any CFF. The location of this ESR zero frequency can be calculated with Equation 9: 1 fZ _ESR 2S u COUT u ESR (9) The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore, calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. 8.3.9 Bootstrap Voltage (BOOT) The LMR23630 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is 0.1 μF or higher. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higherfor stable performance over temperature and voltage. 8.3.10 Overcurrent and Short-Circuit Protection The LMR23630 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating. High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See the Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold IHS_LIMIT which is constant. Thus, the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 17 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor current begins to ramp down. The LS switch is not turned OFF at the end of a switching cycle if its current is above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch is turned OFF, and the HS switch is turned on after a dead time. This is somewhat different than the more typical peak current limit and results in Equation 10 for the maximum load current. VIN VOUT V IOUT _ MAX ILS _ LIMIT u OUT 2 u fSW u L VIN (10) If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms typically before the LMR23630 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, prevents over-heating and potential damage to the device. For FPWM version, the inductor current is allowed to go negative. If this current exceed IL_NEG, the LS switch is turned off until the next clock cycle. This is used to protect the LS switch from excessive negative current. 8.3.11 Thermal Shutdown The LMR23630 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature falls below 155°C (typical), the device reinitiates the power-up sequence controlled by the internal soft-start circuitry. 18 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 8.4 Device Functional Modes 8.4.1 Shutdown Mode The EN pin provides electrical ON and OFF control for the LMR23630. When VEN is below 1 V (typical), the device is in shutdown mode. The LMR23630 also employs VIN and VCC UVLO protection. If VIN or VCC voltage is below their respective UVLO level, the regulator is turned off. 8.4.2 Active Mode The LMR23630 is in active mode when VEN is above the precision enable threshold, VIN and VCC are above their respective UVLO level. The simplest way to enable the LMR23630 is to connect the EN pin to VIN pin. This allows self startup when the input voltage is in the operating range 4.5 V (HSOIC) and 4 V (WSON) to 36 V. See to VCC, UVLO and Enable/Sync for details on setting these operating levels. In active mode, depending on the load current, the LMR23625 is in one of four modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple (for both PFM and FPWM options). 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation (only for PFM option). 3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for PFM option). 4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for FPWM option). 8.4.3 CCM Mode CCM operation is employed in the LMR23630 when the load current is higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode, and the maximum output current of 3 A can be supplied by the LMR23630. 8.4.4 Light Load Operation (PFM Version) For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23630 operates in DCM, also known as diode emulation mode (DEM). In DCM, the LS switch is turned off when the inductor current drops to IL_ZC (–40 mA typical). Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load. At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum HS switch ON-time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN (300 mA typ) is reached, the switching frequency decreases to maintain regulation. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. The external clock synchronizing is not valid when the LMR23630 device enters into PFM mode. 8.4.5 Light Load Operation (FPWM Version) For FPWM version, LMR23630 is locked in PWM mode at full load range. This operation is maintained, even at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current limit of IL_NEG is imposed to prevent damage to the regulators low side FET. When in FPWM mode the converter synchronizes to any valid clock signal on the EN/SYNC input. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 19 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMR23630 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select components for the LMR23630. Alternately, the WEBENCH® software may be used to generate complete designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses comprehensive databases of components. See www.ti.com for more details. 9.2 Typical Applications The LMR23630 only requires a few external components to convert from a wide voltage-range supply to a fixed output voltage. Figure 23 shows a basic schematic. VIN 12 V BOOT VIN CBOOT 0.47 F L 10 H CIN 10 F EN/ SYNC SW PAD CFF 47 pF FB CVCC 2.2 F VOUT 5 V/3 A VCC RFBT 88.7 NŸ COUT 100 F RFBB 22.1 NŸ PGND AGND Figure 23. LM23630 Application Circuit The external components must fulfill the needs of the application, but also the stability criteria of the device control loop. Table 2 can be used to simplify the output filter component selection. Table 2. L, COUT, and CFF Typical Values fSW (kHz) 200 400 1000 2200 (1) 20 VOUT (V) L (µH) COUT (µF) CFF (pF) 3.3 15 300 150 RFBT (kΩ) 51 5 18 200 100 88.7 12 33 100 See (1) 243 24 33 47 See (1) 510 3.3 6.8 150 75 51 5 10 100 47 88.7 12 15 68 See (1) 243 24 15 47 See (1) 510 3.3 3.3 68 39 51 88.7 5 4.7 47 25 3.3 2.2 47 33 51 5 2.2 33 18 88.7 High ESR COUT gives enough phase boost and CFF not needed. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com 1. 2. 3. 4. SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Inductance value is calculated based on VIN = 36 V. All the COUT values are after derating. Add more when using ceramic capacitors. RFBT = 0 Ω for VOUT = 1 V. RFBB = 22.1 kΩ for all other VOUT setting. or designs with RFBT other than recommended value, please adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged. 9.2.1 Design Requirements Detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Example Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage, VIN 12 V typical, range from 8 V to 28 V Output voltage, VOUT 5V Maximum output current IO_MAX 3A Transient response 0.2 A to 2.5 A 5% Output voltage ripple 50 mV Input voltage ripple 400 mV Switching frequency fSW 400 kHz 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.2.2 Output Voltage Setpoint The output voltage of LMR23630 is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 11 is used to determine the output voltage: VOUT VREF u RFBB RFBT VREF (11) Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1 V, the RFBB value can then be calculated using Equation 11. The formula yields to a value 88.7 kΩ. 9.2.2.3 Switching Frequency The default switching frequency of the LMR23630 is 400 kHz. For other switching frequency, the device must be synchronized to an external clock, see Enable/Sync for more details. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 21 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 9.2.2.4 www.ti.com Inductor Selection The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use Equation 13 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND should be 20% to 40%. During an instantaneous short or overcurrent operation event, the RMS and peak inductor current can be high. The inductor current rating should be higher than the current limit of the device. 'iL LMIN VOUT u VIN _ MAX VOUT VIN _ MAX u L u fSW VIN _ MAX VOUT IOUT u KIND u (12) VOUT VIN _ MAX u fSW (13) In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However, inductance that is too low can generate an inductor current ripple that is too high so that overcurrent protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode control, TI does not recommend having an inductor current ripple that is too small. A larger peak-current ripple improves the comparator signal-to-noise ratio. For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 8.56 µH. Choose the nearest standard 8.2 μH ferrite inductor with a capability of 4-A RMS current and 6-A saturation current. 9.2.2.5 Output Capacitor Selection Choose the output capacitor(s), COUT, with care because it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load-current transients. The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the equivalent series resistance (ESR) of the output capacitors: 'VOUT_ESR 'iL u ESR KIND u IOUT u ESR (14) The other is caused by the inductor current ripple charging and discharging the output capacitors: KIND u IOUT 'iL 'VOUT _ C 8 u fSW u COUT 8 u fSW u COUT (15) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks. Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for four clock cycles to maintain the output voltage within the specified range. Equation 16 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. which results in an output voltage overshoot. Equation 17 calculates the minimum capacitance required to keep the voltage overshoot within a specified range. 22 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 COUT ! COUT ! 4 u IOH IOL fSW u VUS VOUT 2 IOL 2 VOS (16) 2 IOH 2 VOUT uL where • • • • IOL = Low level output current during load transient IOH = High level output current during load transient VUS = Target output voltage undershoot VOS = Target output voltage overshoot (17) For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and chose KIND = 0.4. Equation 14 yields ESR no larger than 41.7 mΩ and Equation 15 yields COUT no smaller than 7.5 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 108 μF and 28.5 μF by Equation 16 and Equation 17, respectively. Consider of derating, one 47-μF, 16-V and one 100-μF, 10-V ceramic capacitor with 5-mΩ ESR are used in parallel. 9.2.2.6 Feed-Forward Capacitor The LMR23630 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor COUT is dominated by low-ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency (fX) without CFF is shown in Equation 18, assuming COUT has very small ESR, and COUT value is after derating. 8.32 fX VOUT u COUT (18) Equation 19 for CFF was tested: 1 CFF 4S u fX u RFBT (19) For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from Equation 19 must reduced with medium ESR. Table 2 can be used as a quick starting point. For the application in this design example, a 47-pF, 50-V, COG capacitor is selected. 9.2.2.7 Input Capacitor Selection The LMR23630 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high-frequency decoupling capacitor is 4.7 μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating. To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LMR23630 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device pins. 9.2.2.8 Bootstrap Capacitor Selection Every LMR23630 design requires a bootstrap capacitor (CBOOT). TI recommends a capacitor of 0.47 μF, ated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability. 9.2.2.9 VCC Capacitor Selection The VCC pin is the output of an internal LDO for LMR23630. To insure stability of the device, place a minimum of 2.2-μF, 16V, X7R capacitor from this pin to ground. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 23 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 9.2.2.10 Undervoltage Lockout Setpoint The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO level. R RENB VIN _ RISING VENH u ENT RENB (20) The EN rising threshold (VENH) for LMR23630 is set to be 1.55 V (typical). Choose the value of RENB to be 287 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6 V, then the value of RENT can be calculated using Equation 21: § VIN _ RISING · RENT ¨¨ 1¸¸ u RENB V ENH © ¹ (21) Equation 21 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by Equation 22, where EN hysteresis (VEN_HYS) is 0.4 V (typical). R RENB VIN _ FALLING VENH VEN _ HYS u ENT RENB (22) 9.2.3 Application Curves Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25 °C. VOUT = 5 V IOUT = 3 A fSW = 400 kHz VOUT = 5 V Figure 24. CCM Mode VOUT = 5 V IOUT = 0 mA fSW = 400 kHz Figure 25. DCM Mode fSW = 400 kHz VOUT = 5 V Figure 26. PFM Mode 24 IOUT = 150 mA IOUT = 0 mA fSW = 400 kHz Figure 27. FPWM Mode Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 8.2 µH, COUT = 150 µF, TA = 25 °C. VIN = 12 V VOUT = 5 V IOUT = 2 A VIN = 12 V Figure 28. Start Up by VIN VIN = 12 V VOUT = 5 V IOUT = 2 A Figure 29. Start Up by EN IOUT = 0.3 A to 3 A, 100 mA / μs VOUT = 5 V IOUT = 3 A Figure 30. Load Transient VOUT = 5 V VOUT = 5 V VOUT = 7 V to 36 V, 2 V / μs Figure 31. Line Transient IOUT = 1 A to short VOUT = 5 V Figure 32. Short Protection IOUT = short to 1 A Figure 33. Short Recovery Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 25 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 10 Power Supply Recommendations The LMR23630 is designed to operate from an input voltage supply range between 4.5 V and 36 V for the HSOIC package and 4 V to 36 V for the WSON package. This input supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMR23630 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LMR23630, additional bulk capacitance may be required in addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice. 11 Layout 11.1 Layout Guidelines Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. 1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pin and PAD. 2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground. 3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer. 4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. 5. Have a single point ground connection to the plane. The ground connections for the feedback and enable components should be routed to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125 °C. 26 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 11.2 Layout Example Output Bypass Capacitor Output Inductor SW Input Bypass Capacitor PGND BOOT Capacitor BOOT VCC Capacitor VIN VCC AGND FB EN/ SYNC UVLO Adjust Resistor Output Voltage Set Resistor Thermal VIA VIA (Connect to GND Plane) Figure 34. Sample HSOIC Package Layout Output Inductor Output Bypass Capacitor BOOT Capacitor VCC Capacitor SW PGND SW NC BOOT VIN VCC VIN FB EN/SYNC RT AGND Input Bypass Capacitor UVLO Adjust Resistor RT Thermal VIA Output Voltage Set Resistor VIA (Connect to GND Plane) Figure 35. Sample WSON Package Layout Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 27 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 11.3 Compact Layout for EMI Reduction Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the exposed PAD. 11.4 Ground Plane and Thermal Considerations TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is connected to the source of the internal LS switch. They must be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes. TI also recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance. The thermal characteristics of the LMR23630 are specified using the parameter RθJA, which characterize the junction temperature of silicon to the ambient temperature in a specific system. Although the value of RθJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD × RθJA + TA PD = VIN × IIN × (1 – Efficiency) – 1.1 × IOUT2 × DCR in watt (23) where • • • • • TJ = junction temperature in °C PD = device power dissipation in watt RθJA = junction-to-ambient thermal resistance of the device in °C/W TA = ambient temperature in °C DCR = inductor DC parasitic resistance in ohm (24) The maximum operating junction temperature of the LMR23630 is 125°C. RθJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow. 28 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 11.5 Feedback Resistors To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to the feedback resistor divider should be routed away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage feedback path from EMI noises. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 29 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com 12 Device and Documentation Support 12.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 LMR23630 www.ti.com SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: LMR23630 31 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMR23630ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F30A LMR23630ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F30A LMR23630AFDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F30AF LMR23630AFDDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F30AF LMR23630APDRRR PREVIEW SON DRR 12 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 3630P LMR23630APDRRT PREVIEW SON DRR 12 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 3630P LMR23630DRRR PREVIEW SON DRR 12 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 23630 LMR23630DRRT PREVIEW SON DRR 12 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 23630 LMR23630FDRRR PREVIEW SON DRR 12 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 3630F LMR23630FDRRT PREVIEW SON DRR 12 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 3630F PLMR23630APDRRR ACTIVE SON DRR 12 3000 TBD Call TI Call TI -40 to 125 PLMR23630DRRR ACTIVE SON DRR 12 3000 TBD Call TI Call TI -40 to 125 PLMR23630FDRRR ACTIVE SON DRR 12 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2017 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMR23630 : • Automotive: LMR23630-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jun-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMR23630ADDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 LMR23630AFDDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jun-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR23630ADDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 LMR23630AFDDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 Pack Materials-Page 2 PACKAGE OUTLINE DRR0012D WSON - 0.8 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 (0.08) (0.05) SECTION A-A SECTION A-A SCALE 30.000 TYPICAL C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C EXPOSED THERMAL PAD (0.2) TYP 1.7 0.1 6 7 A 13 2X 2.5 A 2.5 0.1 1 12 10X 0.5 PIN 1 ID (OPTIONAL) 12X 12X 0.38 0.28 0.3 0.2 0.1 0.05 C A B C 4223146/B 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRR0012D WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.7) 12X (0.53) SYMM 1 12 12X (0.25) 13 SYMM 10X (0.5) (2.5) (1) (R0.05) TYP 6 7 (0.6) ( 0.2) VIA TYP (2.87) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4223146/B 05/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DRR0012D WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.47) 12X (0.53) 1 12 12X (0.25) METAL TYP (0.675) SYMM 13 10X (0.5) (1.15) (R0.05) TYP 6 7 (0.74) (2.87) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80.1% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4223146/B 05/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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