[AK4132] AK4132 96kHz 24bit Sample Rate Converter 1. General Description The AK4132 is an 2ch digital sample rate converter (SRC). It converts sample rate of the input audio source (from 8kHz to 96kHz) to 44.1kHz or 48kHz. It is possible also to convert 8kHz, 16kHz or 24kHz into 8kHz, 16kHz or 24kHz. The AK4132 has an internal oscillator and does not need any external master clocks. It contributes simplifying a system configuration. The AK4132 is suitable for the application interfacing to different sample rates such as Car Audio Systems and DVD recorders. 2. Features 2 channels Input/Output Asynchronous Sample Rate Converter Input Sample Rate Range (FSI): 8k ~ 96kHz Output Sample Rate (FSO): 44.1kHz, 48kHz (@fsi=8k~96kHz) 8kHz, 16kHz, 24kHz (@fsi=8kHz, 16kHz, 24kHz) Input to Output Sample Rate Ratio: FSO/FSI = 0.33 ~ 6 THD+N: Up to -90dB Dynamic Range: 100dB (A-weighted, Typ.) I/F format: MSB justified, I2S compatible Oscillator for Internal Operation Clock Clock for Master mode: 256fso Power Supply: DVDD= 3.0 ~ 3.6V or 1.7 ~ 1.9V (LDO OFF Mode) Operating Temperature: -40 ~ +105ºC Package: 16-pin TSSOP (0.65mm pitch) 015015036-E-03 2018/05 -1- [AK4132] 3. Table of Contents 1. 2. 3. 4. 5. General Description ............................................................................................................................ 1 Features .............................................................................................................................................. 1 Table of Contents ................................................................................................................................ 2 Block Diagram ..................................................................................................................................... 3 Pin Configurations and Functions ....................................................................................................... 3 ■ Pin Functions..................................................................................................................................... 4 ■ Handling of Unused Pin .................................................................................................................... 4 6. Absolute Maximum Ratings ................................................................................................................ 5 7. Recommended Operating Conditions................................................................................................. 5 8. SRC Characteristics ............................................................................................................................ 6 9. Consumption Current .......................................................................................................................... 7 ■ Internal Regulator (VSEL pin= “L”).................................................................................................... 7 ■ External VD18 (VSEL pin= “H”) ........................................................................................................ 7 10. Filter Characteristics ........................................................................................................................... 8 ■ Short Delay Sharp Roll-Off Filter Characteristics ............................................................................. 8 11. DC Characteristics .............................................................................................................................. 8 12. Switching Characteristics .................................................................................................................... 9 ■ Clock.................................................................................................................................................. 9 ■ Audio Interface Timing .................................................................................................................... 10 Reset Timing ..................................................................................................................................... 10 ■ Timing Diagram ................................................................................................................................11 13. Functional Description ...................................................................................................................... 14 ■ Input and Output sampling rate combination .................................................................................. 14 ■ System Clock and Audio Interface Format for Input Port ............................................................... 14 ■ System Clock for Output PORT ...................................................................................................... 16 ■ Audio Interface Format of the Output Port ...................................................................................... 16 ■ Regulator ......................................................................................................................................... 17 ■ Power Supply .................................................................................................................................. 17 ■ System Reset .................................................................................................................................. 17 ■ Clock Switch Sequence .................................................................................................................. 19 ■ Grounding and Power Supply Decoupling ...................................................................................... 20 14. Jitter Tolerance ................................................................................................................................. 21 15. Recommended External Circuits ...................................................................................................... 22 16. Package ............................................................................................................................................ 23 ■ Outline Dimensions ......................................................................................................................... 23 ■ Material & Lead Finish .................................................................................................................... 23 ■ Marking ............................................................................................................................................ 24 17. Ordering Guide.................................................................................................................................. 25 18. Revision History ................................................................................................................................ 25 IMPORTANT NOTICE .......................................................................................................................... 27 015015036-E-03 2018/05 -2- [AK4132] SDTI ILRCK IBICK PCM Input Serial Audio I/F COMB FIR PCM Output Serial Audio I/F SRC SDTO OLRCK OBICK Output PORT Input PORT IDIF ODIF 4. Block Diagram Internal OSC REF TEST Internal Regulator CM OMCLK DVSS DVDD VD18 VSEL PDN Clock Div. Figure 1. AK4132 Block Diagram OLRCK 9 8 OBICK 10 7 SDTI OMCLK SDTO 11 6 IBICK VD18 12 5 ILRCK DVSS 13 4 TEST DVDD VSEL 14 3 CM 15 2 IDIF PDN Pin Configurations and Functions 16 5. AK4132 ODIF 1 Top View Figure 2. Pin Layout 015015036-E-03 2018/05 -3- [AK4132] ■ Pin Functions No. Pin Name I/O ODIF IDIF I I PDN= “L” Status Function Audio Interface Format Select Pin for Output PORT Audio Interface Format Select Pin for Input PORT Output Port Mode Select Pin 3 CM I “H”: Slave Mode “L”: Master Mode Test pin. Must be connected to DVSS in normal use. It has a pull-down 4 TEST I resister 100k. 5 ILRCK I Channel Clock Input Pin for Input PORT 6 IBICK I Audio Serial Clock Input Pin for Input PORT 7 SDTI I Audio Serial Data Input Pin for Input PORT 8 OMCLK I External Master Clock Input 9 OLRCK O Channel Clock Output Pin for Output PORT in Master Mode I Channel Clock Input Pin for Output PORT in Slave Mode 10 OBICK O Audio Serial Clock Output Pin for Output PORT in Master Mode I Audio Serial Clock Input Pin for Output PORT in Slave Mode 11 SDTO O Audio Serial Data Output Pin for Output PORT I Internal Digital Power Supply Pin, 1.7 1.9V (VSEL= “H”) Regulator Output Pin, Typ. 1.8V (VSEL= “L”) Current must not be taken from this pin. A 10μF (±30%; including 12 VD18 O the temperature characteristics) capacitor should be connected between this pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. 13 DVSS - Digital Ground Pin 14 DVDD - Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V Internal Digital Power Supply Select Pin 15 VSEL I “H”: External Power Supply “L”: Internal Regulator Power-Down Mode Pin “H”: Power Up 16 PDN I “L”: Power Down and Reset The AK4132 should be reset once by bringing PDN pin = “L” upon power-up. Note 1. All input pins should not be allowed to float. Note 2. CM, ODIF and IDIF must be changed when the PDN pin = “L”. 1 2 - “L” “L” “L” “L” - - ■ Handling of Unused Pin Classification Digital Pin Name OMCLK Setting Connect to DVSS 015015036-E-03 2018/05 -4- [AK4132] 6. Absolute Maximum Ratings (DVSS=0V; Note 3) Parameter Digital Power Supplies Internal Digital Input Current, Any Pin Except Supplies Digital Input Voltage (Note 4) Symbol DVDD VD18 IIN VDIN Ta Tstg Min. 0.3 0.3 0.3 40 65 Max. 4.3 2.5 ±10 DVDD+0.3 105 150 Ambient Temperature (Power applied) (Note 5) Storage Temperature Note 3. All voltages with respect to ground. Note 4. ILRCK, IBICK, SDTI, IDIF, PDN, TEST, OMCLK, CM, ODIF, OBICK (Slave Mode), OLRCK (Slave Mode), VSEL pin Note 5. PCB drawing density should be 100% or more. Unit V V mA V ºC ºC WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (DVSS=0V; Note 3; VSEL= “L”) Parameter Symbol Power Supplies Digital DVDD Note 3. All voltages with respect to ground. (DVSS=0V; Note 3; VSEL= “H”) Parameter Digital Power Supplies Internal Digital (Note 6) Difference Symbol DVDD VD18 DVDD-VD18 Note 3. All voltages with respect to ground. Note 6. DVDD and VD18 must be connected externally. Min. 3.0 Typ. 3.3 Max. 3.6 Unit V Min. 1.7 1.7 - Typ. 1.8 1.8 0 Max. 1.9 1.9 - Unit V V V * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015015036-E-03 2018/05 -5- [AK4132] 8. SRC Characteristics (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7V 1.9V at VSEL pin= “H”; DVSS= 0V; Signal Frequency= 1kHz; measurement bandwidth = 20Hz FSO/2; unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 44.1 48 kHz Output Sample Rate (FSI: 8kHz, 16kHz, 24kHz) FSO 8 24 kHz THD+N (Input= 1kHz, 0dBFS, Note 7) FSO/FSI= 48kHz/48kHz 101 dB FSO/FSI= 48kHz/96kHz dB 102 FSO/FSI= 44.1kHz/96kHz dB 101 Worst Case (FSO/FSI=44.1kHz/32kHz) dB 99 Dynamic Range (Input= 1kHz, -60dBFS, Note 7) FSO/FSI= 48kHz/48kHz 101 dB FSO/FSI= 48kHz/96kHz 102 dB FSO/FSI= 44.1kHz/96kHz 102 dB Worst Case (FSO/FSI= 44.1kHz/32kHz) 101 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 7) FSO/FSI= 48kHz/48kHz 104 dB Ratio between Input and Output Sample Rate FSO/FSI 0.33 6 Note 7. Measured by Audio Precision, System Two. 015015036-E-03 2018/05 -6- [AK4132] 9. Consumption Current ■ Internal Regulator (VSEL pin= “L”) (Ta= -40 105ºC) Parameter Symbol Min. Power Supply Current Normal operation: FSI=FSO= 48kHz at Master Mode :DVDD= 3.3V DVDD= 3.6V FSI= 96kH, FSO= 48kHz at Master Mode :DVDD= 3.3V DVDD= 3.6V Power down: PDN = “L”(Note 8) DVDD=3.6V Note 8. All digital input pins including clock pins are connected to DVSS. Typ. Max. Unit 6 10 10 8 12 100 mA mA mA mA A Min. Typ. Max. Unit - 6 - 8 mA mA - 10 - 12 mA mA ■ External VD18 (VSEL pin= “H”) (Ta= 40 105ºC) Parameter Power Supply Current Normal operation: FSI=FSO=48kHz at Master Mode: DVDD=VD18=1.8V DVDD=VD18=1.9V FSI=96kH, FSO=48kHz at Master Mode: DVDD=VD18=1.8V DVDD=VD18=1.9V Power down: PDN = “L” (Note 9) DVDD=VD18=1.9V Symbol 10 100 Note 9. Except the VSEL pin, all digital input pins including clock pins are connected to DVSS. 015015036-E-03 A 2018/05 -7- [AK4132] 10. Filter Characteristics ■ Short Delay Sharp Roll-Off Filter Characteristics (Ta=-40 105C; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V) Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband PB 0 0.4583FSI kHz 0.985 FSO/FSI 6.000 0.01dB PB 0 0.4167FSI kHz 0.714 FSO/FSI 0.985 PB 0 0.2182FSI kHz 0.536 FSO/FSI 0.714 PB 0 0.2177FSI kHz 0.492 FSO/FSI 0.536 PB 0 0.1948FSI kHz 0.357 FSO/FSI 0.492 PB 0 0.0917FSI kHz 0.246 FSO/FSI 0.357 PB 0 0.0826FSI kHz 0.1667 FSO/FSI 0.246 Stopband SB 0.5417FSI kHz 0.985 FSO/FSI 6.000 SB 0.5021FSI kHz 0.714 FSO/FSI 0.985 SB 0.2974FSI kHz 0.536 FSO/FSI 0.714 SB 0.2813FSI kHz 0.492 FSO/FSI 0.536 SB 0.2604FSI kHz 0.357 FSO/FSI 0.492 SB 0.1573FSI kHz 0.246 FSO/FSI 0.357 SB 0.1471FSI kHz 0.1667 FSO/FSI 0.246 Passband Ripple PR ±0.01 dB 0.1667 FSO/FSI 6.000 Stopband Attenuation 0.985 FSO/FSI 6.000 SA dB 92.8 SA dB 0.714 FSO/FSI 0.985 93.5 SA dB 0.536 FSO/FSI 0.714 94.5 SA dB 0.492 FSO/FSI 0.536 92.9 SA dB 0.357 FSO/FSI 0.492 92.0 SA dB 0.246 FSO/FSI 0.357 94.4 SA dB 0.1667 FSO/FSI 0.246 93.8 Group Delay GD 18 1/fs (Note 10) Note 10. This value is the time from a rising edge of LRCK after L/R data is input to a rising edge of LRCK before the L/R data is output when there is no phase difference between the input and the output data. 11. DC Characteristics (Ta= -40 105C; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V) Parameter Symbol Min. Typ. Max. Unit High-Level Input Voltage (Note 11) VIH 70%DVDD V Low-Level Input Voltage (Note 11) VIL 30%DVDD V High-Level Output Voltage (Iout= 400A) (Note 12) VOH V DVDD0.4 VOL 0.4 V Low-Level Output Voltage (Iout= 400A) (Note 12) (Note 11, Except TEST pin) 10 10 A Input Leakage Current TEST pin Iin 72 10 A 100kΩ Pull down Note 11. ILRCK, IBICK, SDTI, IDIF, PDN, TEST, OMCLK, CM, ODIF, OBICK (Slave Mode), OLRCK (Slave Mode) and VSEL pin. Note 12. SDTO, OBICK (Master Mode) and OLRCK (Master Mode) pin 015015036-E-03 2018/05 -8- [AK4132] 12. Switching Characteristics ■ Clock (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; CL= 20pF) Parameter Symbol Min. Typ. Max. Unit Master Clock Input (OMCLK) 256 FSO : fCLK 2.048 12.288 MHz Frequency tCLKL 40 ns Pulse Width Low tCLKH 40 ns Pulse Width High Channel Clock for Input Port (ILRCK) Frequency Normal Speed Mode Double Speed Mode Duty Cycle Channel Clock for Output Port (OLRCK) Slave Mode Frequency (FSI: 8kHz~96kHz) Frequency (FSI: 8kHz, 16kHz, 24kHz) Duty Cycle Master Mode Frequency (FSI: 8kHz~96kHz) Frequency (FSI: 8kHz, 16kHz, 24kHz) Duty Cycle FSIN FSID dILRCK 8 54 48 50 54 96 52 kHz kHz % FSO FSO dOLRCK 44.1 8 48 50 48 24 52 kHz kHz % FSO FSO dOLRCK 44.1 8 - 50 48 24 - kHz kHz % 015015036-E-03 2018/05 -9- [AK4132] ■ Audio Interface Timing (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin=”H”; CL= 20pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing Input PORT IBICK Period Normal speed Mode tIBCK 1/256 FSIN ns Double speed Mode tIBCK 1/128 FSID ns IBICK Pulse Width Low tIBCKL 27 ns IBICK Pulse Width High tIBCKH 27 ns ILRCK Edge to IBICK “↑” (Note 13) tILRB 15 ns IBICK “↑” to ILRCK Edge (Note 13) tIBLR 15 ns SDTI Hold Time from IBICK “↑” tISDH 15 ns SDTI Setup Time to IBICK “↑” tISDS 15 ns Output PORT (Slave Mode) OBICK PeriodNormal speed Mode tOBCK 1/256 FSO ns OBICK Pulse Width Low tOBCKL 27 ns OBICK Pulse Width High tOBCKH 27 ns OLRCK Edge to OBICK “↑” (Note 13) tOLRB 20 ns OBICK “↑” to OLRCK Edge (Note 13) tOBLR 20 ns OLRCK to SDTO(MSB) (Except I2S Mode) tOLRS 20 ns OBICK “↓” to SDTO tOBSD 20 ns Output PORT (Master Mode) OBICK Frequency fOBCK 64 FSO Hz OBICK Duty dOBCK 50 % OBICK “↓” to OLRCK Edge tOMBLR 20 20 ns OBICK “↓” to SDTO tOBSD 20 ns 20 Reset Timing PDN Pulse Width (Note 14) tPD 150 ns PDN pin Pulse Width of Spike Noise tPDS 0 50 ns Suppressed by Input Filter (Note 15) Note 13. BICK rising edge must not occur at the same time as LRCK edge. Note 14. The AK4132 can be rest by bringing the PDN pin = “L”. Note 15. Spike noise width of “L” pulse suppressed by input filter of the PDN pin. 015015036-E-03 2018/05 - 10 - [AK4132] ■ Timing Diagram Master Clock 1/fCLK VIH OMCLK VIL tCLKH tCLKL Figure 3. OMCLK Clock Timing Input Port Clock 1/FSI VIH ILRCK VIL tILRCH tILRCL dILRCK=tILRCH(or tILRCL)FSI100 tIBCK VIH IBICK VIL tIBCKH tIBCKL Figure 4. ILRCK, IBICK Clock Timing Input Port Timing VIH ILRCK VIL tIBLR tILRB VIH IBICK VIL tISDS tISDH VIH SDTI VIL Figure 5. Input PORT Audio Interface Timing 015015036-E-03 2018/05 - 11 - [AK4132] Output Port Clock (Slave Mode) 1/FSO VIH OLRCK(I) VIL tOLRCH tOLRCL dOLRCK=tOLRCH(or tOLRCL)FSO100 tOBCK VIH OBICK(I) VIL tOBCKH tOBCKL Figure 6. OLRCK, OBICK Clock Timing (Slave Mode) Output Port Timing (Slave Mode) VIH OLRCK(I) VIL tOBLR tOLRB VIH OBICK(I) VIL tOLRS tOBSD 50%DVDD SDTO Figure 7. Output PORT Audio Interface Timing (Slave Mode) 015015036-E-03 2018/05 - 12 - [AK4132] Output Port Clock (Master Mode) 1/FSO 50%DVDD OLRCK(O) tOLRCH tOLRCL dOLRCK=tOLRCH(or tOLRCL)FSO100 1/fOBCK 50%DVDD OBICK(O) tOBCKH tOBCKL dOBCK=tOBCKH(or tOBCKL)fOBCK100 Figure 8. OLRCK, OBICK Clock Timing (Master Mode) Output Port Timing (Master Mode) 50%DVDD OLRCK(O) tOMBLR 50%DVDD OBICK(O) tOBSD 50%DVDD SDTO Figure 9. Output PORT Audio Interface Timing (Master Mode) Power-down Timing tPD VIH PDN VIL tPDS D Figure 10. Power Down and Reset Pulse 015015036-E-03 2018/05 - 13 - 13. Functional Description ■ Input and Output sampling rate combination The table below shows the possible combination of the input sampling rate and output sampling rate. FSI [kHz] 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 8 Y Y Y - 11.025 - Table 1. FSI/FSO Combination FSO [kHz] 12 16 22.05 24 Y Y Y Y Y Y - 32 - 44.1 48 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y: Available -: Not Available ■ System Clock and Audio Interface Format for Input Port The audio interface format is controlled by the IDIF pin. The data format is MSB first in 2's complement. The SDTI input data is clocked in on a rising edge of the IBICK. The audio interface format of the input port should be changed while the PDN pin = “L”. Table 2. Input PORT Audio Interface Format Mode IDIF Pin SDTI Format ILRCK IBICK 0 L 24-bit, MSB justified Input Input 24 or 16-bit, I2S Compatible 1 H 16-bit, I2S Compatible Note 16. When IBICK = 32FSI, only 16-bit I2S Compatible is supported. 14 IBICK Freq 256FSI or 64FSI 256FSI or 64FSI 32FSI (Note 16) [AK4132] ILRCK 0 1 2 23 24 25 32 33 63 0 1 2 23 24 25 32 33 63 0 1 IBICK(128fs) SDTI 23 22 1 0 23 22 1 0 23 1 0 1 2 12 13 14 24 25 IBICK(64fs) 31 0 1 2 12 13 14 24 25 31 0 1 4 SDTI 23 22 12 11 10 0 23 22 20 19 18 Lch Data 0 23 Rch Data 23: MSB, 0:LSB Figure 11. Mode0 Timing (24-bit MSB) LRCK 0 1 2 23 24 25 32 33 63 0 1 2 23 24 25 32 33 63 0 1 14 24 25 31 0 1 11 12 15 0 1 BICK(128fs) SDTI 23 0 1 2 2 1 12 0 13 23 14 24 25 31 0 1 2 2 1 12 0 13 BICK(64fs) SDTI 23 0 1 0 12 11 10 2 5 6 7 23 11 12 15 1 0 12 2 11 10 5 6 0 7 BICK(32fs) SDTI 0 15 12 11 10 6 5 2 1 0 15 12 11 10 Lch Data 6 5 2 1 0 Rch Data 15: MSB, 0:LSB Figure 12. Mode1 Timing (24-bit/16-bit I2S) 015015036-E-03 2018/05 - 15 - [AK4132] ■ System Clock for Output PORT The output ports work in both master mode and slave mode. In master mode, the output port is operated with OLRCK and OBICK generated from OMCLK. OLRCK and OBICK clocks are output from the OLRCK pin and OBICK pin, respectively. In slave mode, the output port is operated by input clocks from the OLRCK pin and the OBICK pin. The OMCLK pin is not used in slave mode. It must be connected to DVSS. The CM pin selects master or slave mode. Table 3. Output PORT Master/Slave Mode Control Mode 0 1 CM pin L H Master / Slave Master Slave OMCLK Frequency 256FSO Not used. (Note 17) Note 17. The OMCLK pin must be connected to DVSS in slave mode. ■ Audio Interface Format of the Output Port The ODIF pin controls the audio interface mode of the output port. The data format is MSB first in 2's complement. The data is output on a falling edge of OBICK from the SDTO pin. The audio interface format of the output port should be changed while the PDN pin = “L”. Mode 0 1 ODIF pin L H Table 4. Output PORT Audio Interface Format SDTO Format OBICK (Slave) MSB justified 48fs or 32fs I2S Compatible 48fs or 32fs OBICK (Master) 64fs 64fs OLRCK 0 1 2 15 16 19 20 23 24 31 0 1 2 15 16 19 20 23 24 31 0 1 25 31 0 1 OBICK(64fs) SDTO 23 22 4 19 18 0 23 22 19 4 18 Lch Data 0 Rch Data 23: MSB, 0:LSB @ 24-bit Figure 13. Mode 0 MSB Justified Timing OLRCK 0 1 2 15 16 19 20 24 25 31 0 1 2 15 16 19 20 24 OBICK(64fs) SDTO 23 20 19 5 0 23 20 19 Lch Data 5 0 Rch Data 23: MSB, 0:LSB @ 24-bit Figure 14. Mode 1 I2S Compatible Timing 015015036-E-03 2018/05 - 16 - [AK4132] ■ Regulator The AK4132 has an internal regulator which suppresses the voltage to 1.8V from DVDD (3.3V). The generated 1.8V power is used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current detection circuit works. When over-voltage is flowed to the regulator output, over-voltage detection circuit works. The regulator block is powered-down and the AK4132 becomes reset state when over-current detection circuit or over-voltage detection circuit is operated. The AK4132 does not return to normal operation without a reset by the PDN pin when these detection circuits are worked. When over-current or over-voltage is detected, the PDN pin should be brought into “L” at once, and should be set to “H” again to recover normal operation. ■ Power Supply The AK4132 supports both 1.8 V and 3.3 V power supplies. Set the VSEL pin according to the power supply voltage. When using a 3.3 V power, set the VSEL pin to “L”. The internal regulator is turned ON and starts generating a 1.8 V for internal circuits from a 3.3 V power supplied to the DVDD pin by the VSEL pin = “L”. When using a 1.8 V power, set the VSEL pin to “H”. The internal regulator is turned OFF and the VD18 pin will be a power supply pin for the internal circuits. In this case, supply a 1.8 V power to both the DVDD pin and the VD18 pin. ■ System Reset Bringing the PDN pin = “L” sets the AK4132 power-down mode and initializes the digital filters. The AK4132 should be reset once by bringing the PDN pin to “L” upon power-up. The internal SRC circuit is powered-up on an edge of ILRCK and OLRCK after a power-up period of the internal regulator (PDN pin = “H”). The data output time of the SDTO pin depends on the ILRCK and OLRCK input when the PDN pin = “H” as Figure 15 and Figure 16. Case 1: ILRCK and OLRCK are input when the PDN pin= “H” Case 1 External clocks (Input port) Don’t care Input Clocks 1 Input Clocks 2 Don’t care SDTI Don’t care Input Data 1 Input Data 2 Don’t care External clocks (Output port) Don’t care Output Clocks 1 Output Clocks 2 Don’t care (4) PDN (1) (2) (2) (3) < 25.2msec (Internal state) Power-down SDTO LDO up & Ratio detection & GD “0” data (3) < 25.2msec Normal operation LDO up & Ratio PD detection & GD Normal operation Power-down Normal data “0” data Normal data “0” data LDO: Internal Regurator GD: Group Delay PD: Power Down Figure 15. System Reset Case1 Notes: (1) The SDTO pin outputs “L” when the PDN pin= “L”. (2) The Internal regulator is powered up by bringing the PDN pin = “H” after operation clock is input. Then, SRC circuit is powered up and starts Ratio detection by ILRCK and OLRCK. SDTO is output after group delay period when Ratio detection is completed. Until then the SDTO outputs “L”. The time until SDTO output become enabled after setting the PDN pin to “H” is 25.2msec (Max.) 015015036-E-03 2018/05 - 17 - [AK4132] (3) SDTO data output becomes enabled. (4) The statuses of the CM, ODIF and IDIF pins should be changed while the PDN pin= “L”. Case2: ILRCK and OLRCK are not input when the PDN pin= “H” Case 2 External clocks (Input port) (No Clock) SDTI External clocks (Output port) PDN (1) (Internal state) Power-down SDTO Input Clocks Don’t care (Don’t care) Input Data Don’t care (Don’t care) Output Clocks Don’t care (2) <5ms LDO Up (3) < 20.2ms wait ILRCK “0” data Ratio detection & GD Normal operation Power-down Normal data “0” data (4) LDO: Internal Regurator GD: Group Delay Figure 16. System Reset Case2 Note: (1) The SDTO pin output is “L” when the PDN pin= “L”. (2) The internal regulator is powered up by PDN pin = “H” and wait for ILRCK and OLRCK. (3) SRC circuit is powered up and sampling frequency ratio detection starts when ILRCK and OLRCK are input. SDTO output starts after group delay period when the frequency ratio detection is completed. Until then, the SDTO output is “L”. The time until SDTO output becomes enabled after ILRCK and OLRCK input is 20.2msec (Max.). (4) SDTO output becomes enabled. 015015036-E-03 2018/05 - 18 - [AK4132] ■ Clock Switch Sequence The AK4132 must be reset by bringing the PDN pin to “L” when changing operation clocks. Clock change sequence is shown in Figure 17. External clocks (input port or output port) Clocks 1 (Don’t care) (1) PDN Clocks 2 (3) < 25.2ms (Internal state) normal operation SDTO Power down (2) LDO up & Ratio detection & GD normal operation (2) normal data normal data Figure 17. Clock Change Sequence Note: (1) Set the PDN pin to “L”, and change clock frequencies of the IDIF pin, ODIF pin and CM pin. (2) The data on SDTO may cause a clicking noise. (3) Set the PDN pin to “H” after changing the clock of the IDIF pin, ODIF pin or CM pin. The AK4132 has automatic internal reset function for when ILRCK or OLRCK frequency is changed. The behavior of the device when ILRCK or OLRCK frequency is changed is shown below. ▪ When the frequency of ILRCK at input port is changed without a reset by the PDN pin. When the difference of internal oscillator clock number in one ILRCK cycle between before and after changing ILRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO outputs “L” when the internal reset is made, and SRC data is output after 162/FSI(O). (FSI(O) is lower frequency between FSI and FSO.) When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed. It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (Note 18) to output normal SRC data. Distorted data may be output until normal SRC output. When ILRCK is stopped, an internal reset is executed automatically. It takes 162/FSI(O) to output normal SRC data after ILRCK is input again. 015015036-E-03 2018/05 - 19 - [AK4132] ▪ When the frequency of OLRCK at output port is changed without a reset by the PDN pin When the difference of internal oscillator clock number in one OLRCK cycle between before and after changing OLRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO outputs “L” when the internal reset is made, and SRC data is output after 162/FSI(O). When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed. It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (Note 18) to output normal SDTO data. Distorted data may be output until normal SDTO output. When OLRCK is stopped, an internal reset is executed automatically. It takes 162/FSI(O) to output normal SDTO data after ILRCK is input again. Note 18. When FSO/FSI ratio is changed from 1/6 to 1/5.99. ■ Grounding and Power Supply Decoupling The AK4132 requires careful attention to power supply and grounding arrangements. Decoupling capacitors should be placed as near as possible to the supply pins. 015015036-E-03 2018/05 - 20 - [AK4132] 14. Jitter Tolerance Figure 18 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 18. When the jitter amplitude is 0.02Uipp or less, the AK4132 operates normally regardless of the jitter frequency. AK4132 Jitter Tolerance Jittter Amplitude [UIpp] 10.00 1.00 0.10 (2) 0.01 (1) 0.00 1 10 100 1000 10000 100000 Jittter Frequency [Hz] Figure 18. Jitter Tolerance This is an evaluation result with synchronous input data to ILRCK and IBICK when jitter is added. The area (1) and (2) border is the the jitter amplitude of ILRCK just before THD+N degradation starts. Please use the jitter amplitude of the area (1). (1) Normal Operation (2) There is a possibility that the output data is lost. 1UI (Unit Interval) is one cycle of IBICK. 1[UIpp] = 1/48kHz = 20.8μsec when FSI is 48kHz. 015015036-E-03 2018/05 - 21 - [AK4132] 15. Recommended External Circuits Figure 19 and Figure 20 show the system connection diagram. Regulator: Enable Output PORT: Master Mode Control DSP1 Mater Clock 1 ODIF PDN 16 2 IDIF VSEL 15 3 CM DVDD 14 4 TEST DVSS 13 5 ILRCK VD18 12 6 IBICK SDTO 11 7 SDTI OBICK 10 Control 0.1 10 Digital 3.3V + + 0.1 10 DSP2 OLRCK 9 8 OMCLK AK4132 Top View Figure 19. Typical Connection Diagram (Output Port: Master Mode, Regulator: Enable) Regulator: Disable Output PORT: Slave Mode Control Digital 1.8V DSP1 1 ODIF PDN 16 2 IDIF VSEL 15 3 CM DVDD 14 4 TEST DVSS 13 5 ILRCK VD18 12 6 IBICK SDTO 11 7 SDTI OBICK 10 Control 0.1 10 + Digital 1.8V + 0.1 10 DSP2 OLRCK 9 8 OMCLK AK4132 Top View Figure 20. Typical Connection Diagram (Output Port: Slave mode, Regulator: Disable) 015015036-E-03 2018/05 - 22 - [AK4132] 16. Package 0.13～ 0.18 5±0.1 9 1 8 6.4±0.2 4.4±0.1 16 0.6±0.1 ■ Outline Dimensions 0.13 M 0゜～ 10゜ 1.1MAX 0.19～ 0.27 0.9±0.05 0.65 0.1 S 0.1±0.05 S ■ Material & Lead Finish Package Molding Compound: Epoxy Lead Frame Material: Cu Pin Surface Treatment: Solder (Pb free) Plate 015015036-E-03 2018/05 - 23 - [AK4132] ■ Marking 3) 4132VT XXXYY 2) 1) 1) 2) 3) Pin #1 indication Date Code: XXXYY (5 digits) XXX: Year & Week YY: Factory Control Code Marketing Code: 4132VT 015015036-E-03 2018/05 - 24 - [AK4132] 17. Ordering Guide AK4132VT AKD4132 -40 ~ 105ºC 16-pin TSSOP (0.65mm pitch) Evaluation Board for AK4132 18. Revision History Date (Y/M/D) 15/12/09 16/06/20 Revision 00 01 Reason First Edition Specification Addition Page Contents 1 General Description “It is possible also to convert 8kHz, 16kHz or 24kHz into 8kHz, 16kHz or 24kHz.” added Features Output Sample Rate (FSO): 8kHz, 16kHz, 24kHz (@FSI: 8kHz, 16kHz, 24kHz) added. Input to Output Sample Rate Ratio: FSO/FSI = 44.1/96 ~ 6 0.33 ~ 6 SRC Characteristics “Output Sample Rate (FSI: 8kHz,16kHz, 24kHz) min. 8kHz, max. 24kHz” added Ratio between Input and Output Sample Rate min.44.1/96 min. 0.33 Switching Characteristics Master Clock Input (OMCLK) 256 FSO: min.11.2896MHz min. 2.048MHz Switching Characteristics Channel Clock for Output Port (OLRCK) Slave Mode “Frequency (FSI: 8kHz, 16kHz, 24kHz) min.8kHz, max. 24kHz” added Master Mode Frequency (FSI: 8kHz, 16kHz, 24kHz) “min.8kHz, max. 24kHz” added Functional Description ”■Input and Output sampling rate combination” added. 1 6 10 10 14 16 ■ System Clock for Output PORT The FSO column deleted from Table 3 “Output PORT Master/Slave Mode Control”. (FSO has no meaning in Table 3.) 17 ■ System Reset 18 Figure 16 LDO up & Ratio detection & GD 9.6ms 25.2ms ■ System Reset Figure 17 Ratio detection & GD 4.6ms 20.2ms 015015036-E-03 2018/05 - 25 - [AK4132] Date (Y/M/D) 16/06/20 Revision 01 Reason Specification Addition Page 19 17/04/06 02 21 9 18 18/05/10 03 ■ Clock Switch Sequence Figure 18 LDO up & Ratio detection & GD 9.6ms 25.2 ms Description (Max. 116.7ms@FSO=44.1kHz) (Max. 643ms@FSO=8kHz) 20 Error Correction Error Correction Contents Specification Change 23 Error Correction 24 Error Correction 8 ■ Clock Switch Sequence Description (Max. 116.7ms@FSO=44.1kHz) (Max. 643ms@FSO=8kHz) Jitter Tolerance 0.01UIp 0.02UIpp Switching Characteristics Channel Clock for Input Port (ILRCK) Frequency Double Speed Mode Max. 108kHz 96kHz ■ Clock Switch Sequence LDO Up time in Figure 16: “5ms” “< 5ms” Package ■ Outline Dimensions Tolerances are narrowed down. Package ■ Marking ・Date Code: “XXYYY” “XXXYY” ・”XX: Lot#” “XXX: Year & Week” ・”YYY: Date Code” “YY: Factory Control Code” Frequency Range was modified in Filter Characteristics. ■ Short Delay Sharp Roll-Off Filter Characteristics Passband 0.324 FSO/FSI 0.492: 0.246 FSO/FSI 0.324: 0.357 FSO/FSI 0.492: 0.246 FSO/FSI 0.357: Stopband 0.324 FSO/FSI 0.492: 0.246 FSO/FSI 0.324: 0.357 FSO/FSI 0.492: 0.246 FSO/FSI 0.357: Passband Attenuation 0.324 FSO/FSI 0.492: 0.246 FSO/FSI 0.324: 0.357 FSO/FSI 0.492: 0.246 FSO/FSI 0.357: 015015036-E-03 Max. 0.1948FSI Max. 0.0917FSI Max. 0.1948FSI Max. 0.0917FSI min. 0.2604FSI min. 0.1573FSI min. 0.2604FSI min. 0.1573FSI min. 92.0dB min. 94.4dB min. 92.0dB min. 94.4dB 2018/05 - 26 - [AK4132] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015015036-E-03 2018/05 - 27 -