STMicroelectronics L4987Cxx50 Dropout control flag Datasheet

L4987Cxx
Very low drop voltage regulators
with inhibit and dropout control flag
Features
■
Very low dropout voltage (0.25 V typ.)
■
Dropout control flag
■
Very low quiescent current
■
(Typ. 90 mA in OFF Mode, 500 mA in ON
Mode)
■
Output current up to 200 mA
■
Logic-controlled electronic shutdown
■
Output voltages of 3.3 V, 5 V
■
Internal current and thermal limit
■
Only 2.2 µF for stability
■
Available in ± 2% selection at 25°C
■
Supply voltage rejection: 70 dB (typ.)
PPAK
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notebook) it is possible to use the flag to monitor
the battery charge status through the dropout of
the regulator.
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Description
The L4987 is a very low drop regulator available
in PPAK. The very low drop-voltage (0.5 V Max at
200 mA) and the very low quiescent current make
it particularly suitable for low noise, low power
applications, and in battery powered systems.
The input dump protection up to 40 V makes it
ideal for automotive applications. a shutdown
Logic Control function is available (pin 2, TTL
compatible). This means that when the device is
used as a local regulator, it is possible to put a
part of the board in standby, decreasing the total
power consumption. The regulator employs an
output pin (open collector) providing a logic signal
when the pass transistor is in saturation at low
input voltage, this signal can be used to prevent
the pop-up phenomenon in the car radio. In
battery powered systems (the cellular phone,
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Table 1.
Device summary
Part number
Order code
Output voltage
L4987Cxx33
L4987CPT33TR
3.3 V
L4987Cxx50
L4987CPT50TR
5.0 V
September 2007
Rev. 6
1/16
www.st.com
16
L4987Cxx
Contents
1
Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Application hint of L4987CPT33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . .r. . . . . . . . . . . . . 12
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Revision history . . . . . . . . . . . . . . . . . . . . . . .t. . . . . . . . . . . . . . . . . . . . 15
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8
9
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How to use the control flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
L4987Cxx
Schematic diagram
1
Schematic diagram
Figure 1.
Schematic diagram
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Pin configuration
L4987Cxx
2
Pin configuration
Figure 2.
Pin connections (top view)
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L4987Cxx
Maximum ratings
3
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
40
V
VI
DC Input voltage
IO
Output current
Internally Limited
Ptot
Power dissipation
Internally Limited
Tstg
Storage temperature range
-40 to 150
°C
Top
Operating junction temperature range
-40 to 125
°C
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied
Table 3.
Thermal data
Symbol
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Parameter
RthJC
Thermal resistance junction-case
RthJA
Thermal resistance junction-ambient
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PPAK
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Unit
8
°C/W
100
°C/W
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Electrical characteristics
L4987Cxx
4
Electrical characteristics
Table 4.
Electrical characteristics of L4987Cxx33 (refer to the test circuits, VI = 6.3 V, IO = 5 mA,
TJ = 25°C, CI = 0.1 µF, CO = 2.2 µF unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
IO = 200 mA, VI = 6.3 V
3.234
3.3
3.366
IO = 200 mA, VI = 6.3 V, TJ=-40 to 125°C
2.76
3.432
4
18
Unit
VO
Output voltage
VI
Operating input voltage
Iout
Output current limit
ΔVO
Line regulation
VI = 4.6 to 18 V, IO = 0.5 mA
2.4
14
mV
ΔVO
Load regulation
VI = 4.4 V, IO = 0.5 to 200 mA
3
20
mV
Quiescent current
ON MODE
VI = 4.6 to 18 V, IO = 0 mA
0.7
1
VI = 4.6 to 18 V, IO = 200 mA
1.5
6
OFF MODE
VI = 12 V
90
180
Supply voltage rejection
IO = 5 mA
VI = 5.6 ± 1 V
Id
V
IO = 200 mA
250
A
mA
IO = 200 mA
Vd
Dropout voltage
VIL
Control input logic low
TJ = -40 to 125°C
VIH
Control input logic high
TJ = -40 to 125°C
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Control input current
CO
Output bypass
capacitance
VFL
Control flag output low
IFH
Control flag output high
leakage current
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ESR = 0.5 to 10 Ω, IO = 0 to 200 mA
TJ= -40 to 125°C
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IO = 200 mA, TJ=-40 to 125°C
II
80
f = 1 KHz
f = 10 KHz
t(s
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f = 120 Hz
SVR
V
dB
60
0.25
0.5
V
0.7
0.8
2
2
µA
V
V
10
µA
10
µF
VI - VO < VCESAT power, IFL = 6mA
IO = 200mA
0.5
V
VI > 4 V, VOH = 15 V
10
µA
L4987Cxx
Table 5.
Electrical characteristics
Electrical characteristics of L4987Cxx50 (refer to the test circuits, VI = 8 V, IO = 5 mA,
TJ = 25°C, CI = 0.1 µF, CO = 2.2 µF unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
IO = 200 mA, VI = 8 V
4.9
5
5.1
IO = 200 mA, VI = 8 V, TJ = - 40 to 125°C
4.8
5.2
IO = 200 mA
5.7
18
Unit
VO
Output voltage
VI
Operating input voltage
Iout
Output current limit
ΔVO
Line regulation
VI = 6.3 to 18 V, IO = 0.5 mA
3
20
mV
ΔVO
Load regulation
VI = 6.3 V, IO = 0.5 to 200 mA
3
20
mV
Quiescent current
ON MODE
VI = 6.3 to 18 V, IO = 0 mA
0.7
1
VI = 6.3 to 18 V, IO = 200 mA
1.5
6
OFF MODE
VI = 12 V
90
180
Supply voltage rejection
IO = 5 mA
VI = 7.3 ± 1 V
Id
SVR
V
250
A
mA
f = 120 Hz
76
f = 1 KHz
71
f = 10 KHz
58
Dropout voltage
VIL
Control input logic low
TJ = -40 to 125°C
VIH
Control input logic high
TJ = -40 to 125°C
0.3
IO = 200 mA, TJ = -40 to 125°C
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0.5
V
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Control input current
µA
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IO = 200 mA
Vd
II
V
0.8
2
V
V
10
µA
10
µF
CO
Output bypass
capacitance
ESR = 0.5 to 10 Ω, IO = 0 to 200 mA
TJ= -40 to 125°C
VFL
Control flag output low
VI - VO < VCESAT power, IFL = 6 mA
IO = 200 mA
0.5
V
IFH
Control flag output high
leakage current
VI > 5.85 V, VOH = 15 V
10
µA
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Typical characteristics
L4987Cxx
5
Typical characteristics
Figure 3.
(Unless otherwise specified TJ = 25°C, CI = CO = 0.1 µF)
Output and flag voltage vs input
Figure 4.
Output voltage vs input voltage
voltage
Figure 5.
Output and flag voltage vs input
voltage
Figure 6.
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Output voltage vs input voltage
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Figure 7.
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Output and flag voltage vs inp. volt. Figure 8.
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Output voltage vs input voltage
L4987Cxx
Application hint of L4987CPT33
6
Application hint of L4987CPT33
6.1
How to use the control flag
The flag produces a logic "low" whenever the output drops out of regulation. An "out of
regulation condition can result from:
1) Low input voltage (VIN ≤VOUT + VDROP)
2) Current limiting
3) Thermal limiting
Figure 3. to Figure 4. show the typical behavior of the output voltage and the control flag
versus the input voltage and the temperature. No hysteresis is implemented; so the
response of VOUT and VFLAG are the same either when the VIN ramps up or down.
The control flag is an open collector which requires an external pull-up resistor. This may be
connected to the regulator output (Figure 11.) or some other supply voltage (Figure 12.).
Using the regulator output prevents an invalid "high" on the flag which occurs if it is pulled up
to an external voltage while the regulator input voltage is reduced below about 2 V (Figure
13.).
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Concerning the pull-up resistor its value must be properly chosen as suggested below.
When "low" as it is possible to see in Figure 7. the control flag voltage is:
VFLAG(LOW) = VCE = 0.5 = VSUPPLY - RPULL x IFL
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VSUPPLY is chosen by design and, thus is known, while IFL must be at maximum 10 mA.
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Then 0.5 V ≥ VSUPPLY - RPULL x 10 mA
The minimum value of RPULL, is, so, determined by the following equation:
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RPULL(min) ≥ VSUPPLY - 0.5/10 mA
Regarding the maximum value of RPULL note that its value depends of the type of logic used
(CMOS, TTL etc.), the transistor leakage current and the presence or not of a load on
VFLAG.
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The following example shows how to determine the RPULL max in the case of CMOS logic,
no load and 10 µA (for L4987 it is the maximum value of IFH) of control flag leakage current.
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Because of CMOS logic:
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VFLAG(HIGH) ≥ 2/3 VSUPPLY
but:
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VFLAG(HIGH) = VSUPPLY - RPULL x IFH ≥ 2/3 VSUPPLY
so, the maximum value is determined by the following equation:
RPULL(MAX) ≤(1/3 VSUPPLY)/10 mA
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Application hint of L4987CPT33
Figure 9.
L4987Cxx
Output and flag voltage vs input
Figure 10. Flag voltage vs input
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L4987Cxx
7
Test circuits
Test circuits
Figure 11. Test circuit
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Figure 12. Single antenna receiver with master receiver port
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Figure 13. Equivalent output circuit
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Figure 14. Output and flag voltage vs input
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Package mechanical data
8
L4987Cxx
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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L4987Cxx
Package mechanical data
PPAK mechanical data
mm.
inch.
Dim.
Min.
A
Typ.
2.2
Max.
Min.
Typ.
Max.
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.4
0.6
0.015
0.023
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
D1
E
5.1
6.4
0.201
6.6
0.252
0.260
E1
4.7
0.185
e
1.27
0.050
G
4.9
5.25
0.193
G1
2.38
2.7
0.093
H
9.35
10.1
0.368
L2
0.8
L4
0.6
L5
1
L6
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0.206
0.106
1
0.031
1
0.023
0.039
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2.8
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0.397
0.039
0.039
0.110
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0078180-E
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Package mechanical data
L4987Cxx
Tape & reel DPAK-PPAK mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
330
13.0
Max.
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
0.504
0.512
22.4
0.519
0.882
Ao
6.80
6.90
7.00
0.268
0.272
0.2.76
Bo
10.40
10.50
10.60
0.409
0.413
0.417
Ko
2.55
2.65
2.75
0.100
0.104
0.105
Po
3.9
4.0
4.1
0.153
0.157
0.161
P
7.9
8.0
8.1
0.311
0.315
0.319
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Typ.
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Revision history
9
Revision history
Table 6.
Document revision history
Date
Revision
Changes
22-Jun-2004
4
VO min and VO max values in Table 5, pag. 4 have been corrected.
04-Sep-2006
5
The IFH value on table 7 has been updated and new template.
26-Sep-2007
6
Add Table 1. in cover page.
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L4987Cxx
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