TI1 LP2982IM5X-5.0/NOPB Micropower ultra-low-dropout ldo in sot-23 package Datasheet

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LP2982
SNVS128K – MARCH 2000 – REVISED JUNE 2016
LP2982 50-mA Micropower Ultra-Low-Dropout LDO in SOT-23 Package
1 Features
3 Description
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The LP2982 is a 50-mA, fixed-output voltage LDO
designed to provide ultra-low dropout and lower noise
in battery-powered applications.
1
2.1-V to 16-V Input Voltage
Ultra-Low-Dropout Voltage
Ensured 50-mA Output Current
Typical Dropout Voltage 180 mV at 80 mA
Requires Minimum External Components
< 1 μA Quiescent Current When Shut Down
Low Ground Pin Current at All Loads
Output Voltage Accuracy 1% (A Grade)
High Peak Current Capability (150 mA Typical)
Wide Supply Voltage Range (16 V Maximum)
Low ZOUT 0.3 Ω Typical (10 Hz to 1 MHz)
Overtemperature and Overcurrent Protection
−40°C to +125°C Junction Temperature Range
Using an optimized vertically integrated PNP (VIP)
process, the LP2982 delivers unequaled performance
in all specifications critical to battery-powered
designs:
Dropout Voltage: Typically 120 mV at 50 mA load,
and 7 mV at 1 mA load.
Ground Pin Current: Typically 375 μA at 50 mA load,
and 80 μA at 1 mA load.
Sleep Mode: Less than 1-μA quiescent current when
ON/OFF pin is pulled low.
Precision Output: 1% tolerance output voltages
available (A grade).
2 Applications
•
•
•
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Low Noise: By adding an external bypass capacitor,
output noise can be reduced to 30 μV (typical).
Cellular Phones
Palmtop and Laptop Computers
Personal Digital Assistants (PDA)
Camcorders, Personal Stereos, Cameras
Device Information(1)
PART NUMBER
LP2982
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
IN
VIN
OUT
CIN
ON/OFF
ON
VOUT
COUT
ON/OFF BYPASS
OFF
GND
CBYPASS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP2982
SNVS128K – MARCH 2000 – REVISED JUNE 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Third-Party Products Disclaimer ...........................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (April 2013) to Revision K
Page
•
Deleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO" ........................... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last
paragraph of Description beginning "Four output voltage versions..." ................................................................................... 1
•
Deleted Lead temperature row from Abs Max; this information is in the POA; remove "(survival)" and "(operating)"
from rows in Abs Max table ................................................................................................................................................... 4
•
Added "ON/OFF input voltage" to ROC table ........................................................................................................................ 4
•
Changed VIN – VO to "VDO" .................................................................................................................................................... 5
Changes from Revision I (April 2013) to Revision J
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 18
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
Pin Descriptions
PIN
NUMBER
NAME
TYPE
1
IN
Input
2
GND
—
3
ON/OFF
Input
4
BYPASS
Input/Output
5
OUT
Output
DESCRIPTION
Input voltage
Common ground (device substrate)
Logic high enable input
Bypass capacitor for low noise operation
Regulated output voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating junction temperature
Power dissipation
(3)
MIN
MAX
UNIT
−40
125
°C
Internally limited
Input supply voltage
−0.3
16
V
Shutdown input voltage
−0.3
16
V
−0.3
9
V
Output voltage
(4)
IOUT
Short-circuit protected
Input-output voltage (5)
−0.3
16
V
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace-specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using P(MAX) = (TJ(MAX) – TA) / RθJA. The value of RθJA for the SOT-23 package is 169°C/W. Exceeding the maximum allowable power
dissipation causes excessive die temperature, and the regulator will go into thermal shutdown.
If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2982 output must be diode-clamped to
ground.
The output PNP structure contains a diode between the IN and OUT pins that is normally reverse-biased. Reversing the polarity from
VIN to VOUT turns on this diode (see Reverse Current Path).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Pins 1, 2 and 5
±2000
Pins 3 and 4
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating junction temperature
Input supply voltage
ON/OFF input voltage
4
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MIN
MAX
UNIT
−40
125
°C
2.1
16
V
0
16
V
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6.4 Thermal Information
LP2982
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance, High-K (2)
175.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
°C/W
RθJB
Junction-to-board thermal resistance
29.5
°C/W
ψJT
Junction-to-top characterization parameter
16.1
°C/W
ψJB
Junction-to-board characterization parameter
29.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
6.5 Electrical Characteristics
Unless otherwise specified: TJ = 25°C, VIN = VO(NOM) + 1 V, IL = 1 mA, COUT = 1 μF, VON/OFF = 2 V.
PARAMETER
TEST CONDITIONS
IL = 1 mA
ΔVO
ΔVO/ΔVIN
Output voltage
tolerance
Output voltage line
regulation
1 mA < IL < 50 mA
1 mA < IL < 50 mA
–40°C ≤ TJ ≤ 125°C
VO(NOM) + 1 V ≤ VIN ≤ 16 V
LP2982AI-XX (1)
MIN
TYP
−1.5
1.5
−2
2
−2
2
−3.5
3.5
0.007
VO(NOM) + 1 V ≤ VIN ≤ 16 V
–40°C ≤ TJ ≤ 125°C
IL = 10 mA, –40°C ≤ TJ ≤ 125°C
120
IL = 80 mA, –40°C ≤ TJ ≤ 125°C
IL = 0 mA, –40°C ≤ TJ ≤ 125°C
IL = 1 mA, –40°C ≤ TJ ≤ 125°C
IL = 10 mA, –40°C ≤ TJ ≤ 125°C
IL = 50 mA, –40°C ≤ TJ ≤ 125°C
IL = 80 mA, –40°C ≤ TJ ≤ 125°C
(1)
(2)
120
225
95
110
220
600
750
mV
150
225
180
225
325
65
95
125
80
110
170
140
220
460
375
1200
525
VON/OFF < 0.15 V
–40°C ≤ TJ ≤ 125°C
150
60
90
460
375
VON/OFF < 0.3 V
15
40
170
140
IL = 80 mA
60
%/V
5
125
80
IL = 50 mA
10
325
65
IL = 10 mA
7
225
180
IL = 1 mA
3
90
IL = 50 mA, –40°C ≤ TJ ≤ 125°C
IL = 0 mA
10
0.014
1
15
40
IL = 80 mA
3
%VNOM
0.032
5
7
IL = 50 mA
0.007
0.032
1
IL = 10 mA
0.014
UNIT
MAX
1
IL = 1 mA, –40°C ≤ TJ ≤ 125°C
Ground pin current
TYP
1.5
IL = 1 mA
IGND
MIN
−1
IL = 0 mA, –40°C ≤ TJ ≤ 125°C
Dropout voltage (2)
MAX
−1.5
IL = 0 mA
VDO
LP2982I-XX (1)
600
μA
1200
525
1400
750
1400
0.01
0.8
0.01
0.8
0.1
2
0.1
2
Temperature range are ensured through correlation using statistical quality control (SQC) methods. The limits are used to calculate
average outgoing quality level (AOQL).
Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a
1-V differential.
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Electrical Characteristics (continued)
Unless otherwise specified: TJ = 25°C, VIN = VO(NOM) + 1 V, IL = 1 mA, COUT = 1 μF, VON/OFF = 2 V.
PARAMETER
TEST CONDITIONS
LP2982AI-XX (1)
MIN
High = O/P ON
VON/OFF
ON/OFF input
voltage (3)
TYP
MIN
Low = O/P OFF
1.6
0.55
0.55
0.01
0.01
5
VON/OFF = 5 V
–40°C ≤ TJ ≤ 125°C
Peak output current
VOUT ≥ VO(NOM) − 5%
en
Output noise voltage
(RMS)
BW = 300 Hz to 50 kHz
COUT = 10 μF
–2
μA
5
15
150
UNIT
0.15
–2
VON/OFF = 5 V
MAX
V
0.15
VON/OFF = 0 V
–40°C ≤ TJ ≤ 125°C
IO(PK)
TYP
1.4
1.6
VON/OFF = 0 V
ON/OFF input current
MAX
1.4
High = O/P ON
–40°C ≤ TJ ≤ 125°C
Low = O/P OFF
–40°C ≤ TJ ≤ 125°C
ION/OFF
LP2982I-XX (1)
15
100
100
mA
30
30
μV
ΔVO/ΔVIN Ripple rejection
ƒ = 1 kHz, COUT = 10 μF
45
45
dB
IO(MAX)
RL = 0 Ω (steady state) (4)
150
150
mA
(3)
(4)
6
Short-circuit current
The ON/OFF inputs must be properly driven to prevent misoperation. For details, see Operation With ON/OFF Control.
See related curve(s) in Typical Characteristics section.
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6.6 Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 1. Output Voltage vs Temperature
Figure 2. Output Voltage vs Temperature
Figure 3. Output Voltage vs Temparature
Figure 4. Dropout Characteristics
Figure 5. Dropout Characteristics
Figure 6. Dropout Characteristics
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Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 7. Dropout Voltage vs Temperature
Figure 8. Dropout Voltage vs Load Current
Figure 9. GND Pin Current vs Temperature
Figure 10. GND Pin Current vs Load Current
Figure 12. Input Current vs VIN
Figure 11. Input Current vs VIN
8
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Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 13. Line Transient Response
Figure 14. Line Transient Response
Figure 15. Load Transient Response
Figure 16. Load Transient Response
Figure 17. Load Transient Response
Figure 18. Load Transient Response
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Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 19. Short-Circuit Current
Figure 20. Instantaneous Short-Circuit Current vs
Temperature
Figure 21. Short-Circuit Current
Figure 22. Instantaneous Short Circuit Current vs Output
Voltage
Figure 23. Output Impedance vs Frequency
10
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Figure 24. Output Impedance vs Frequency
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Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 25. ON/OFF Pin Current VsvON/OFF
Figure 26. ON/OFF Threshold vs Temperature
Figure 27. Input-to-Output Leakage vs Temperature
Figure 28. Output Reverse Leakage vs Temperature
Figure 30. Output Noise Density
Figure 29. Output Noise Density
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Typical Characteristics (continued)
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/OFF pin tied to
VIN.
Figure 31. Output Noise Density
Figure 32. Ripple Rejection
Figure 34. Turnon Waveform
Figure 33. Turnon Waveform
Figure 35. Turnon Waveform
12
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7 Detailed Description
7.1 Overview
The LP2982 is a 50-mA, fixed-output voltage regulator designed specifically to meet the requirements of batterypowered applications. Available in assorted output voltages (refer to the package option addendum (POA) at the
back of this datasheet for the available voltage and package options), the device has an output tolerance of 1%
for the A grade (1.5% for the non-A version). Using a VIP process, the LP2982 contains these features to
facilitate battery-powered designs:
• Fixed 5-V, 3.3-V, and 3-V output versions
• Very high-accuracy 1.23-V reference
• Low-dropout voltage, typical dropout of 120 mV at a 50-mA load current and 7 mV at 1-mA load
• Low ground current, typically 375 μA at 50-mA load and 80 μA at 1-mA load
• A sleep-mode feature is available, allowing the regulator to consume only 1 µA (typical) when the ON/OFF
pin is pulled low.
• Overtemperature protection and overcurrent protection circuitry is designed to safeguard the device during
unexpected conditions.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Multiple Voltage Options
To meet the different application requirements, the LP2982 provides multiple fixed output options (see POA).
7.3.2 High-Accuracy Output Voltage
With special careful design to minimize all contributions to the output voltage error, the LP2982 distinguishes
itself as a very high-accuracy output voltage micropower LDO. This includes a tight initial tolerance (1% typical),
extremely good line regulation (0.007%/V typical), and a very low output voltage temperature coefficient, making
the device an ideal low-power voltage reference.
7.3.3 Ultra-Low-Dropout Voltage
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (VDO = VIN – VOUT), where the main current pass element (PNP) is fully on and is characterized by the
classic VCE(SAT) of the transistor. VDO indirectly specifies a minimum input voltage above the nominal
programmed output voltage at which the output voltage is expected to remain within its accuracy boundary.
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Feature Description (continued)
7.3.4 Low Ground Current
The LP2982 uses a vertical PNP process which allows for quiescent currents that are considerably lower than
those associated with traditional lateral PNP regulators, typically 375 μA at 50-mA load and 80 μA at 1-mA load.
7.3.5 Sleep Mode
When pulling the ON/OFF pin to a low level (VON/OFF < 0.15 V), LP2982 enters sleep mode, and less than 1-μA
quiescent current is consumed. This function is designed for the application which needs a sleep mode to
effectively enhance battery life cycle.
7.3.6 Short-Circuit Protection (Current Limit)
The internal current-limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls when load impedance decreases. If a current limit occurs
and the resulting output voltage is low, excessive power may be dissipated across the LDO resulting in a thermal
shutdown of the output. A foldback feature limits the short-circuit current to protect the regulator from damage
under all load conditions. If OUT is forced below 0 V before EN goes high, and the load current required exceeds
the foldback current limit, the device may not start up correctly.
7.3.7 Thermal Protection
The LP2982 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is
dissipated in the LDO. The thermal time-constant of the semiconductor die is fairly short, and thus the output
cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced. The
internal protection circuitry of the LM2982 is designed to protect against thermal overload conditions. The
circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown
degrades its reliability.
7.4 Device Functional Modes
7.4.1 Operation with VOUT(TARGET) + 1 V ≤ VIN < 16 V
The device operates if the input voltage is equal to, or exceeds, VOUT(TARGET) + 0.6 V. At input voltages below the
minimum VIN requirement, the device does not operate correctly, and output voltage may not reach target value.
7.4.2 Operation With ON/OFF Control
If the voltage on the ON/OFF pin is less than 0.15 V, the device is disabled, and the shutdown current does not
exceed 1 μA. Raising ON/OFF above 1.4 V initiates the start-up sequence of the device.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP2982 is a linear voltage regulator operating from 2.1 V to 16 V on the input and regulates voltages
between 3 V to 5 V with 1% accuracy and 50-mA maximum output current. Efficiency is defined by the ratio of
output voltage to input voltage because the LP2982 is a linear voltage regulator. To achieve high efficiency, the
dropout voltage (VIN – VOUT) must be as small as possible, thus requiring a very-low-dropout LDO. Successfully
implementing an LDO in an application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must
be verified to ensure a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other
transient specification is required, then the design becomes more challenging.
8.2 Typical Application
IN
VIN
VOUT
OUT
CIN
COUT (Tantalum)
1 µF
ON/OFF
2.2 µF (5-V device)
4.7 µF (3-V and 3.3-V devices)
ON/OFF BYPASS
ON
CBYPASS
OFF
GND
0.01 µF
ON/OFF input must be actively terminated. Tie to VIN if this function is not to be used.
Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides
superior dynamic performance and additional stability margin (see Capacitor Characteristics).
Figure 36. LP2982 Typical Application
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
5 V ±10%
Output voltage
3.3 V ±3.5%
Output current
50 mA
Ambient temperature
85°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
Like any low-dropout regulator, the external capacitors used with the LP2982 must be carefully selected to
assure regulator loop stability.
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8.2.2.1.1 Input Capacitor
An input capacitor with a value ≥ 1 μF is required with the LP2982 (amount of capacitance can be increased
without limit).
This capacitor must be located a distance of not more than 0.5 inches from the input pin of the LP2982 and
returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor.
8.2.2.1.2 Output Capacitor
The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series
resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current
for various output voltages and capacitor values (refer to Figure 40 and Figure 41).
NOTE
Important: The output capacitor must maintain its ESR in the stable region over the full
operating temperature range to ensure stability. Also, capacitor tolerance and variation
with temperature must be considered to ensure the minimum amount of capacitance is
provided at all times.
This capacitor must be located not more than 0.5 inches from the OUT pin of the LP2982 and returned to a clean
analog ground.
IN
VIN
VOUT
OUT
COUT (MLCC)
CIN
1 µF
ON/OFF
ON
2.2 µF (5-V device)
4.7 µF (3-V and 3.3-V devices)
RESR
ON/OFF BYPASS
CBYPASS
1Ÿ
OFF
GND
0.01 µF
Figure 37. Typical Application With Ceramic COUT Series R
8.2.2.1.3 Bypass Capacitor
The 0.01-μF capacitor connected to the bypass pin to reduce noise must have very low leakage.
The current flowing out of the bypass pin comes from the bandgap reference, which is used to set the output
voltage.
This capacitor leakage current causes the output voltage to decline by an amount proportional to the current.
Typical values are −0.015%/nA at −40°C, −0.021%/nA at 25°C, and −0.035%/nA at 125°C.
This data is valid up to a maximum leakage current of about 500 nA, beyond which the bandgap is so severely
loaded that it can not function.
Care must be taken to ensure that the capacitor selected does not have excessive leakage current over the
operating temperature range of the application.
A high-quality ceramic capacitor which uses either NPO or COG type dielectric material typically has very low
leakage. Small surface mount polypropylene or polycarbonate film capacitors also have extremely low leakage,
but are slightly larger than ceramics.
16
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8.2.2.2 Capacitor Characteristics
8.2.2.2.1 Tantalum
Tantalum capacitors are the best choice for use with the LP2982. Most good quality tantalums can be used with
the LP2982, but check the manufacturer's data sheet to be sure the ESR is in range.
It is important to remember that ESR increases at lower temperatures and a capacitor that is near the upper limit
for stability at room temperature can cause instability when it gets cold.
In applications which must operate at very low temperatures, it may be necessary to parallel the output tantalum
capacitor with a ceramic capacitor to prevent the ESR from going up too high (see Ceramic for important
information on ceramic capacitors).
8.2.2.2.2 Ceramic
TI does not recommend use of ceramic capacitors at the output of the LP2982. This is because the ESR of a
ceramic can be low enough to go below the minimum stable value for the LP2982. A 2.2-μF ceramic was
measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.
If a ceramic capacitor is used on the output, a 1-Ω resistor must be placed in series with the capacitor.
8.2.2.2.3 Aluminum
Because of large physical size, aluminum electrolytics are not typically used with the LP2982. They must meet
the same ESR requirements over the operating temperature range, more difficult because of their steep increase
at cold temperature.
An aluminum electrolytic can exhibit an ESR increase of as much as 50× when going from 20°C to −40°C. Also,
some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze.
8.2.2.3 Reverse Current Path
The internal PNP power transistor used as the pass element in the LP2982 has an inherent diode connected
between the regulator output and input. During normal operation (where the input voltage is higher than the
output) this diode is reverse biased (see Figure 38).
VIN
VOUT
PNP
GND
Figure 38. LP2982 Reverse Current Path
However, if the input voltage is more than a VBE below the output voltage, this diode will turn ON and current will
flow into the regulator output. In such cases, a parasitic SCR can latch which will allow a high current to flow into
the VIN pin and out the ground pin, which can damage the part.
The internal diode can also be turned on if the input voltage is abruptly stepped down to a voltage which is a VBE
below the output voltage.
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In any application where the output voltage may be higher than the input voltage, an external Schottky diode
must be connected from VIN to VOUT (cathode on VIN, anode on VOUT; see Figure 39), to limit the reverse voltage
across the LP2982 to 0.3 V (see Absolute Maximum Ratings).
SCHOTTKY DIODE
VIN
VOUT
PNP
GND
Figure 39. Adding External Schottky Diode Protection
8.2.2.4 ON/OFF Input Operation
The LP2982 is shut off by pulling the ON/OFF input low, and turned on by driving the input high. If this feature is
not to be used, the ON/OFF input should be tied to VIN to keep the regulator on at all times (the ON/OFF input
must not be left floating).
To ensure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and
below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see Electrical
Characteristics).
The ON/OFF signal may come from either a totem-pole output, or an open-collector output with pullup resistor to
the LP2982 input voltage or another logic supply. The high-level voltage may exceed the LP2982 input voltage,
but must remain within the Absolute Maximum Ratings for the ON/OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/OFF input have a slew rate which is
greater than 40 mV/μs.
NOTE
IMPORTANT: The regulator shutdown function does not operate correctly if a slow-moving
signal is applied to the ON/OFF input.
8.2.2.5 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
PD(MAX) = (VIN(MAX) – VOUT) × IOUT
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage
drops result in better dynamic (that is, PSRR and transient) performance.
On the LP2982 SOT-23 (DBV) package, the primary conduction path for heat is through the five leads to the
PCB. The ground pin (pin 2) is attached directly to the back side of the die and should be accorded extra copper
area on the PCB. The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation
allowed (PD(MAX)) for the device package. Power dissipation and junction temperature are most often related by
the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature
of the ambient air (TA), according to Equation 2 or Equation 3:
18
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TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))
PD = (TJ(MAX) – TA(MAX)) / RθJA
(2)
(3)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copperspreading area and is to be used only as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the package junction-to-board thermal resistance (RθJB) plus
the thermal resistance contribution by the PCB copper area acting as a heat sink.
8.2.2.6 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 4 or Equation 5.
TJ(MAX) = TTOP + (ΨJT × PD(MAX))
where
•
•
PD(MAX) is explained in Equation 3
TTOP is the temperature measured at the center-top of the device package.
TJ(MAX) = TBOARD + (ΨJB × PD(MAX))
(4)
where
•
•
PD(MAX) is explained in Equation 3.
TBOARD is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(5)
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal
Metrics (SPRA953); for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics
(SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI
Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
(SZZA017). These application notes are available at www.ti.com.
8.2.3 Application Curves
Figure 40. 5-V, 2.2-μF ESR Curves
Figure 41. 3-V, 4.7-μF ESR Curves
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9 Power Supply Recommendations
The LP2982 is designed to operate from an input voltage supply range between between VOUT(NOM) + 1 V and
16 V. The input voltage range provides adequate headroom for the device to have a regulated output. This input
supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help
improve the output noise performance.
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference
plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB
opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise,
and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this
ground plane is necessary to meet thermal requirements.
10.2 Layout Example
VIN
Ground
CIN
IN
OUT
GND
ON/
OFF
COUT
CBYPASS
VOUT
Ground
BYPASS
Figure 42. LP2982 Layout Example
20
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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For additional information, see the following:
• TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
• TI Application Report Using New Thermal Metrics (SBVA025)
• TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
(SZZA017)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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21
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
LP2982AIM5-3.0/NOPB
Package Type Package Pins Package
Drawing
Qty
ACTIVE
SOT-23
DBV
5
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L20A
(4/5)
LP2982AIM5-3.3
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
L19A
LP2982AIM5-3.3/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L19A
LP2982AIM5-5.0
NRND
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
L18A
LP2982AIM5-5.0/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L18A
LP2982AIM5X-3.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L20A
LP2982AIM5X-3.3/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L19A
LP2982AIM5X-5.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L18A
LP2982IM5-3.0/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L20B
LP2982IM5-3.3/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L19B
LP2982IM5-5.0/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L18B
LP2982IM5X-3.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L20B
LP2982IM5X-3.3/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L19B
LP2982IM5X-5.0/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L18B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LP2982AIM5-3.0/NOPB
SOT-23
DBV
5
1000
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5-3.3
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5-3.3/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5-5.0
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5-5.0/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5X-3.0/NOPB SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5X-3.3/NOPB SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982AIM5X-5.0/NOPB SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5-3.0/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5-3.3/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5-5.0/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5X-3.0/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5X-3.3/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LP2982IM5X-5.0/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP2982AIM5-3.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982AIM5-3.3
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982AIM5-3.3/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982AIM5-5.0
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982AIM5-5.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982AIM5X-3.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP2982AIM5X-3.3/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP2982AIM5X-5.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP2982IM5-3.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982IM5-3.3/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982IM5-5.0/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LP2982IM5X-3.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP2982IM5X-3.3/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LP2982IM5X-5.0/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
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