TI1 LM5102MM/NOPB Lm5102 high voltage half-bridge gate driver with programmable delay Datasheet

LM5102
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SNVS268A – MAY 2004 – REVISED MARCH 2013
LM5102 High Voltage Half-Bridge Gate Driver with Programmable Delay
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FEATURES
DESCRIPTION
•
The LM5102 High Voltage Gate Driver is designed to
drive both the high side and the low side N-Channel
MOSFETs in a synchronous buck or a half bridge
configuration. The floating high-side driver is capable
of working with supply voltages up to 100V. The
outputs are independently controlled. The rising edge
of each output can be independently delayed with a
programming resistor. An integrated high voltage
diode is provided to charge the high side gate drive
bootstrap capacitor. A robust level shifter operates at
high speed while consuming low power and providing
clean level transitions from control logic to the high
side gate driver. Under-voltage lockout is provided on
both the low side and the high side power rails. This
device is available in the standard VSSOP-10 pin and
the WSON-10 pin packages.
1
•
•
•
•
•
•
•
Drives both a High Side and Low Side NChannel MOSFET
Independently Programmable High and Low
Side Rising Edge Delay
Bootstrap Supply Voltage Range up to 118V
DC
Fast Turn-Off Propagation Delay (25 ns
Typical)
Drives 1000 pF Loads with 15 ns Rise and Fall
Times
Supply Rail Under-Voltage Lockout
Low Power Consumption
Timer Can be Terminated Midway through
Sequence
Packages
TYPICAL APPLICATIONS
•
•
•
•
•
Current Fed Push-Pull Power Converters
Half and Full Bridge Power Converters
Synchronous Buck Converters
Two Switch Forward Power Converters
Forward with Active Clamp Converters
•
•
VSSOP-10
WSON-10 (4 mm x 4 mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM5102
SNVS268A – MAY 2004 – REVISED MARCH 2013
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Simplified Block Diagram
HB
HV
HO
LEVEL
SHIFT
UVLO
DRIVER
HS
HI
Adjustable
rising
edge delay
RT1
VDD
UVLO
LO
DRIVER
LI
Adjustable
rising
edge delay
RT2
VSS
2
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Connection Diagram
VDD
1
10
HB
2
9
VSS
HO
3
8
LI
HS
4
7
HI
RT1
5
6
RT2
LO
Figure 1. 10-Lead VSSOP, WSON
PIN FUNCTIONS
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
VSSOP
WSON (1)
1
1
VDD
Positive gate drive supply
Locally decouple to VSS using low ESR/ESL capacitor,
located as close to IC as possible.
2
2
HB
High-side gate driver bootstrap rail
Connect the positive terminal of bootstrap capacitor to the HB
pin and connect negative terminal of bootstrap capacitor to
HS. The Bootstrap capacitor should be placed as close to IC
as possible.
3
3
HO
High-side gate driver output
Connect to gate of high side MOSFET with short low
inductance path.
4
4
HS
High-side MOSFET source connection
Connect bootstrap capacitor negative terminal and source of
high side MOSFET.
5
5
RT1
High-side output edge delay
programming
Resistor from RT1 to ground programs the leading edge delay
of the high side gate driver. The resistor should be placed
close to the IC to minimize noise coupling from adjacent
traces.
6
6
RT2
Resistor from RT2 to ground programs the leading edge delay
Low-side output edge delay programming of the low side gate driver. The resistor should be placed close
to the IC to minimize noise coupling from adjacent traces.
7
7
HI
High-side driver control input
8
8
LI
Low-side driver control input
TTL compatible thresholds. Unused inputs should be tied to
ground and not left open
9
9
VSS
Ground return
All signals are referenced to this ground.
19
19
LO
Low-side gate driver output
Connect to the gate of the low side MOSFET with a short low
inductance path.
(1)
For the WSON package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane
on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat..
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
VDD to VSS
–0.3V to +18V
VHB to VHS
–0.3V to +18V
LI or HI Inputs to VSS
–0.3V to VDD + 0.3V
LO Output
–0.3V to VDD + 0.3V
HO Output
VHS – 0.3V to VHB + 0.3V
VHS to VSS
−1V to +100V
VHB to VSS
118V
RT1 & RT2 to VSS
–0.3V to 5V
Junction Temperature
+150°C
Storage Temperature Range
–55°C to +150°C
ESD Rating HBM (3)
(1)
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and
Pin 4 which are rated at 500V.
(2)
(3)
Recommended Operating Conditions
VDD
+9V to +14V
HS
–1V to 100V
HB
VHS + 8V to VHS + 14V
HS Slew Rate
< 50V/ns
Junction Temperature
–40°C to +125°C
Electrical Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT1 = RT2 = 100kΩ. No Load on LO or
HO.
Symbol
Parameter
Conditions
Min (1)
Typ
Max (1)
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
0.4
0.6
mA
IDDO
VDD Operating Current
f = 500 kHz
1.5
3
mA
IHB
Total HB Quiescent Current
LI = HI = 0V
0.06
0.2
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.3
3
mA
IHBS
HB to VSS Current, Quiescent
VHS = VHB = 100V
0.05
10
µA
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.08
mA
0.8
1.8
V
1.8
2.2
V
100
200
500
kΩ
2.7
3
3.3
V
0.75
1.5
2.25
mA
INPUT PINS
VIL
Low Level Input Voltage Threshold
VIH
High Level Input Voltage Threshold
RI
Input Pulldown Resistance
TIME DELAY CONTROLS
VRT
Nominal Voltage at RT1, RT2
IRT
RT Pin Current Limit
Vth
Timer Termination Threshold
TDL1, TDH1
Rising edge turn-on delay, RT = 10 kΩ
75
105
150
ns
TDL2, TDH2
Rising edge turn-on delay, RT = 100 kΩ
530
630
750
ns
(1)
4
RT1 = RT2 = 0V
1.8
V
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT1 = RT2 = 100kΩ. No Load on LO or
HO.
Symbol
Parameter
Conditions
Min (1)
Typ
Max (1)
Units
6.0
6.9
7.4
V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
0.5
5.7
6.6
V
7.1
V
0.4
V
BOOT STRAP DIODE
VDL
Low-Current Forward Voltage
IVDD-HB = 100 µA
0.60
0.9
VDH
High-Current Forward Voltage
IVDD-HB = 100 mA
0.85
1.1
V
V
RD
Dynamic Resistance
IVDD-HB = 100 mA
0.8
1.5
Ω
LO GATE DRIVER
VOLL
Low-Level Output Voltage
ILO = 100 mA
0.25
0.4
V
VOHL
High-Level Output Voltage
ILO = –100 mA,
VOHL = VDD – VLO
0.35
0.55
V
IOHL
Peak Pullup Current
VLO = 0V
1.6
A
IOLL
Peak Pulldown Current
VLO = 12V
1.8
A
HO GATE DRIVER
VOLH
Low-Level Output Voltage
IHO = 100 mA
0.25
0.4
V
VOHH
High-Level Output Voltage
IHO = –100 mA,
VOHH = VHB – VHO
0.35
0.55
V
IOHH
Peak Pullup Current
VHO = 0V
1.6
A
IOLH
Peak Pulldown Current
VHO = 12V
1.8
A
VSSOP
200
WSON-10 (3)
40
THERMAL RESISTANCE
θJA (2)
Junction to Ambient
°C/W
The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
(2)
(3)
Switching Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol
Parameter
Conditions
Min (1)
Typ
Max (1)
Units
tLPHL
Lower Turn-Off Propagation Delay LM5102
(LI Falling to LO Falling)
27
56
ns
tHPHL
Upper Turn-Off Propagation Delay LM5102
(HI Falling to HO Falling)
27
56
ns
tRC, tFC
Either Output Rise/Fall Time
CL = 1000 pF
15
ns
tR, tF
Either Output Rise/Fall Time (3V to 9V)
CL = 0.1 µF
0.6
µs
tBS
Bootstrap Diode Turn-Off Time
IF = 20 mA, IR = 200 mA
50
ns
(1)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
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Typical Performance Characteristics
IDD vs Frequency
Operating Current vs Temperature
2.2
100
VDD = 12V
RT = 10k
CL = 2200 pF
2.0
1.8
CURRENT (mA)
CL = 1000 pF
CURRENT (mA)
IDDO
CL = 470 pF
10
1.6
1.4
1.2
1.0
CL = 0 pF
1
10
1
100
IHBO
0.8
-50 -25
1000
0
25
50
75
100 125 150
TEMPERATURE (°C)
FREQUENCY (kHz)
Figure 2.
Figure 3.
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
1.20
1.20
IDD, RT = 10k
1.00
IDD, RT = 10k
CURRENT (mA)
CURRENT (mA)
1.00
0.80
0.60
IDD, RT = 100k
0.40
0.20
0.00
9
0.60
IDD, RT = 100k
0.40
0.20
IHB, RT = 10k, 100k
8
0.80
IHB, RT = 10k, 100k
0.00
-50
10 11 12 13 14 15 16 17 18
-25
0
VDD, VHB (V)
50
75 100 125 150
Figure 4.
Figure 5.
IHB vs Frequency
HO & LO Peak Output Current vs Output Voltage
100000
2.00
HB = 12V,
HS = 0V
VDD = VHB = 12V, HS = 0V
1.80
CL = 4400 pF
1.60
CL = 2200 pF
10000
1.40
CURRENT (A)
CURRENT (PA)
25
TEMPERATURE (°C)
CL = 1000 pF
1000
1.20
SOURCING
1.00
0.80
SINKING
0.60
100
0.40
CL = 0 pF
10
0.1
0.20
CL = 470 pF
0.00
1
10
100
1000
2
4
6
8
10
12
HO, LO (V)
FREQUENCY (kHz)
Figure 6.
6
0
Figure 7.
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Typical Performance Characteristics (continued)
Diode Forward Voltage
Undervoltage Threshold Hysteresis vs Temperature
0.60
1.00E-01
0.55
T = 150°C
1.00E-02
HYSTERESIS (V)
VDDH
T = 25°C
ID (A)
1.00E-03
1.00E-04
0.50
0.45
VHBH
0.40
T = -40°C
1.00E-05
1.00E-06
0.2
0.35
0.3
0.4
0.5
0.6
0.7
0.8
0.30
-50
0.9
-25
0
25
50
75
100 125 150
o
TEMPERATURE ( C)
VD (V)
Figure 8.
Figure 9.
Undervoltage Rising Threshold vs Temperature
LO & HO Gate Drive—High Level Output Voltage vs
Temperature
7.30
0.700
7.20
0.600
VDD = VHB = 8V
7.00
0.500
VDDR
6.90
VOH (V)
THRESHOLD (V)
7.10
6.80
6.70
VHBR
6.60
VDD = VHB = 12V
0.400
0.300
VDD = VHB = 16V
6.50
0.200
6.40
6.30
-50 -25
0
25
50
0.100
-50 -25
75 100 125 150
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10.
Figure 11.
LO & HO Gate Drive—Low Level Output Voltage vs
Temperature
Turn Off Propagation Delay vs Temperature
0.400
40.0
38.0
0.350
36.0
VDD = VHB = 8V
34.0
DELAY (ns)
VOL (V)
0.300
VDD = VHB = 12V
0.250
0.200
TLPHL
32.0
30.0
28.0
26.0
VDD = VHB = 16V
THPHL
24.0
0.150
22.0
0.100
-50
-25
0
25
50
75 100 125 150
20.0
-50 -25
TEMPERATURE (°C)
0
25
50
75 100 125 150
TEMPERATURE (°C)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Turn On Delay vs RT Resistor Value
Turn On Delay vs Temperature (RT = 10k)
700
145
VCC = 12V
600
135
125
HI to HO Delay
DELAY (ns)
DELAY (ns)
500
400
300
LI to LO Delay
115
105
200
95
100
85
75
0
0
-50
10 20 30 40 50 60 70 80 90 100
-25
0
25
50
75 100 125 150
TEMPERATURE (oC)
RT (k:)
Figure 14.
Figure 15.
Turn On Delay vs Temperature (RT = 100k)
750
725
DELAY (ns)
700
675
650
LI to LO Delay
625
600
HI to HO Delay
575
550
-50
-25
0
25
50
75
100 125 150
o
TEMPERATURE ( C)
Figure 16.
8
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LM5102 Waveforms
LI
VDD
HI
HB
HI
Driver
DLY
Logic
LI
HO
LO
HS
DLY
Logic
Driver
TDL = tP + tRT2
TDL
LO
tP
HO
LM5102
tP
VSS
RT1
TDH
TDH = tP + tRT1
RT2
Figure 17.
Figure 18. Application Timing Waveforms
Operational Notes
The LM5102 offers a unique flexibility with independently programmable delay of the rising edge for both high
and low side driver outputs independently. The delays are set with resistors at the RT1 and RT2 pins, and can
be adjusted from 100 ns to 600 ns. This feature reduces component count, board space and cost compared to
discrete solutions for adjusting driver dead time. The wide delay programming range provides the flexibility to
optimize drive signal timing for a wide range of MOSFETs and applications.
The RT pins are biased at 3V and current limited to 1 mA maximum programming current. The time delay
generator will accommodate resistor values from 5k to 100k with turn-on delay times that are proportional to the
RT resistance. In addition, each RT pin is monitored by a comparator that will bypass the turn-on delay if the RT
pin is pulled below the timer elimination threshold (1.8V typical). Grounding the RT pins programs the LM5102 to
drive both outputs with minimum turn-on delay.
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply
voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5102, the top
and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9V. Any UVLO condition on
the bootstrap capacitor will disable only the high side output (HO).
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LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
5. The resistors on the RT1 and RT2 timer pins must be placed very close to the IC and seperated from high
current paths to avoid noise coupling to the time delay generator which could disrupt timer operation.
POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL • VDD2
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
1.000
CL = 4400 pF
CL = 2200 pF
POWER (W)
0.100
CL = 1000 pF
0.010
CL = 470 pF
CL = 0 pF
0.001
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
Figure 19. Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
10
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The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation.
1.000
1.000
CL = 4400 pF
0.100
POWER (W)
POWER (W)
CL = 4400 pF
CL = 0 pF
0.010
0.100
CL = 0 pF
0.010
0.001
1.0 kHz
10.0 kHz
100.0 kHz
0.001
1.0 kHz
1000.0 kHz
SWITCHING FREQUENCY (kHz)
10.0 kHz
100.0 kHz
1000.0 kHz
SWITCHING FREQUENCY (kHz)
Figure 20. Diode Power Dissipation VIN = 80V
Figure 21. Diode Power Dissipation VIN = 40V
The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the
bootstrap diode losses for the intended application. Because the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode (refer to Figure 22) and can be helpful in removing
power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series
inductance and have a significantly lower forward voltage drop than the internal diode.
(Optional external
fast recovery diode)
VIN
VCC
RGATE
HB
VDD
VDD
OUT1
HI
HO
CBOOT
PWM
CONTROLLER
0.1 PF
HS
T1
LM5102
LI
OUT2
LO
RT1
0.47 PF
GND
RT2
VSS
Figure 22. LM5102 Driving MOSFETs Connected in Half-Bridge Configuration
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REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5102MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5102
LM5102MMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5102
LM5102SD
NRND
WSON
DPR
10
1000
TBD
Call TI
Call TI
-40 to 125
5102SD
LM5102SD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5102SD
LM5102SDX/NOPB
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5102SD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5102MM/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5102MMX/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5102SD
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5102SD/NOPB
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5102SDX/NOPB
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5102MM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5102MMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM5102SD
WSON
DPR
10
1000
210.0
185.0
35.0
LM5102SD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5102SDX/NOPB
WSON
DPR
10
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
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