Cypress CYW43907 Wicedâ ¢ ieee 802.11 a/b/g/n soc with anembedded applications processor Datasheet

PRELIMINARY
CYW43907
WICED™ IEEE 802.11 a/b/g/n SoC with an
Embedded Applications Processor
The Cypress CYW43907 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things applications. It supports
all rates specified in the IEEE 802.11 a/b/g/n specifications.The device includes an ARM Cortex-based applications processor, a single
stream IEEE 802.11n MAC/baseband/radio, a dual-band 5 GHz and 2.4 GHz transmit power amplifier (PA), and a receive low-noise
amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments.
The CYW43907 is an optimized SoC targeting embedded Internet-of-Things applications in the industrial and medical sensor, home
appliance, and embedded audio markets. Using advanced design techniques and process technology to reduce active and idle power,
the device is designed for embedded applications that require minimal power consumption and a compact size.
The device includes a PMU for simplifying system power topology and allows for direct operation from a battery while maximizing
battery life.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM43907
CYW43907
BCM43907KWBG
CYW43907KWBG
Features
Application Processor Features
Key IEEE 801.11x Features
■
ARM Cortex-R4 32-bit RISC processor.
■
IEEE 802.11n compliant.
■
2 MB of on-chip SRAM for code and data.
■
Single-stream spatial multiplexing up to 150 Mbps.
■
An on-chip cryptography core
■
Supports 20/40 MHz channels with optional SGI.
■
640 KB of ROM containing WICED SDK components such
as RTOS and TCP/IP stack.
■
Full IEEE 802.11 a/b/g legacy compatibility with enhanced
performance.
■
17 GPIOs supported.
■
■
Q-SPI serial flash interface to support up to 40 Mbps of peak
transfer.
TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
■
On-chip power and low-noise amplifiers.
■
An internal fractional nPLL allows support for a wide range of
reference clock frequencies.
■
Integrated ARM Cortex-R4 processor with tightly coupled
memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for
standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to future
features in the field).
■
Software architecture supported by standard WICED SDK
allows easy migration from existing discrete MCU designs
and to future devices.
■
Support for UART (3), SPI or CSC master (2),
CSC-only (2), and I2S (2) interfaces. (Cypress Serial Control
(CSC) is an I2C-compatible interface.)
■
Dedicated fractional PLL for audio clock (MCLK) generation.
■
USB 2.0 host and device modes.
■
SDIO 3.0 host and device modes.
Cypress Semiconductor Corporation
Document Number: 002-14829 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Friday, December 22, 2017
PRELIMINARY
■
Security support:
❐
❐
❐
❐
■
WPA and WPA2 (Personal) support for powerful
encryption and authentication.
AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility.
Reference WLAN subsystem provides Cisco Compatible
Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX
5.0).
Wi-Fi Protected Setup and Wi-Fi Easy-Setup
CYW43907
Worldwide regulatory support: Global products supported
with worldwide design approval.
General Features
■
Supports battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
■
Programmable dynamic power management.
■
6 Kb OTP memory for storing board parameters.
■
316-bump WLCSP
(4.583 mm × 5.533mm, 0.2mm pitch)..
Figure 1. Functional Block Diagram
CYW43907
2 MB RAM,
640 KB ROM
USB 2.0
UART
SDIO 3.0
CSC
PWM (6)
PWM
APPS ARM
Cortex-R4
32 KB (I),
32 KB (D)
ICACHE
SDIO
UART (3)
SPI
BSC (2)
GPIO
Crytography
Engine
JTAG
GPIO (17)
Audio PLL
RMII/MII
AXI
Audio
32 kHz
External LPO
AXI
DMA
I2S
I2S (2)
WLAN
ARM
Cortex-R4
AXI-to-AXI
Bridge
AXI to AXI
Bridge
USB
SPI (2)
TCM
512 KB RAM
320 KB ROM
WLAN
IEEE 802.11 MAC
APPS Domain
RF Switch Controls
1 x 1, IEEE 802.11n PHY
Always-On Domain
REG_ON
HIB_REG_ON_IN
RTC
PS
PS RAM
SR_Eng
CSC = Cypress Serial Control. An I2C‐compatible interface.
PMU
TX
Switch
VIO
LNA
PMU
Control
VBAT
AXI
37.4 MHz Crystal
2.4 GHz and 5 GHz Radio
AXI-to-AXI
Bridge
2.4 GHz
PA
LNA
5 GHz
PA
TX
Switch
WRF_PAOUT_5G
WRF_RFIN_5G
WRF_PAOUT_2G
WRF_RFIN_2G
Document Number: 002-14829 Rev. *J
Page 2 of 94
PRELIMINARY
CYW43907
Contents
1. Overview ............................................................ 5
1.1
1.2
7. Wireless LAN Subsystem .............................. 26
Introduction ......................................................... 5
7.1
WLAN CPU and Memory Subsystem ................26
1.1.1
7.2
IEEE 802.11n MAC ............................................26
7.2.1 PSM ........................................................27
7.2.2 WEP .......................................................27
Features ................................................. 5
Standards Compliance ........................................ 6
2. Power Supplies and Power Management ....... 7
2.1
Power Supply Topology ...................................... 7
2.2
CYW43907 Power Management Unit Features .. 7
2.3
Power Management ......................................... 10
2.4
PMU Sequencing .............................................. 10
2.5
Power-Off Shutdown ......................................... 11
2.6
Power-Up/Power-Down/Reset Circuits ............. 11
3. Frequency References ................................... 12
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.3
TXE .........................................................28
RXE ........................................................28
IFS ..........................................................28
TSF .........................................................28
NAV ........................................................28
MAC-PHY Interface ................................29
IEEE 802.11™ a/b/g/n PHY ................................29
8. WLAN Radio Subsystem ............................... 30
8.1
Receiver Path .....................................................30
3.1
Crystal Interface and Clock Generation ............ 12
8.2
Transmit Path .....................................................30
3.2
External Frequency Reference ......................... 13
8.3
Calibration ..........................................................30
3.3
External 32.768 kHz Low-Power Oscillator ....... 14
4. Applications Subsystem ................................ 15
4.1
Overview ........................................................... 15
4.2
Applications CPU and Memory Subsystem ...... 15
4.3
Memory-to-Memory DMA Core ......................... 15
4.4
Cryptography Core ............................................ 15
5. Applications Subsystem External Interfaces 16
9. Pinout and Signal Descriptions.................... 31
9.1
Bump List ...........................................................32
9.2
Signal Descriptions ............................................36
10. GPIO Signals and Strapping Options ........... 42
10.1 Overview ............................................................42
10.2 Weak Pull-Down and Pull-Up Resistances ........42
10.3 Strapping Options ..............................................42
5.1
Ethernet MAC Controller (MII/RMII) .................. 16
5.2
GPIO ................................................................. 16
5.3
Cypress Serial Control ...................................... 16
5.4
I2S ..................................................................... 16
12. I/O States ......................................................... 47
5.5
JTAG and ARM Serial Wire Debug ................... 18
13. Electrical Characteristics............................... 49
5.6
PWM ................................................................. 18
13.1 Absolute Maximum Ratings ...............................49
5.7
SDIO 3.0 ........................................................... 18
5.7.1 SDIO 3.0—Device Mode ....................... 18
13.2 Environmental Ratings .......................................50
5.7.2 SDIO 3.0—Host Mode .......................... 20
10.4 Alternate GPIO Signal Functions .......................43
11. Pin Multiplexing .............................................. 44
13.3 Electrostatic Discharge Specifications ...............50
5.8
S/PDIF ............................................................... 20
13.4 Recommended Operating Conditions and DC
Characteristics ...................................................50
5.9
SPI Flash ........................................................... 20
13.5 Power Supply Segments ....................................52
5.10 UART ................................................................ 21
13.6 Ethernet MAC Controller (MII/RMII) DC
Characteristics ...................................................52
5.11 USB 2.0 ............................................................. 21
5.11.1 Overview ................................................ 21
5.11.2 USB 2.0 Features .................................. 23
13.7 GPIO, UART, and JTAG Interfaces DC
Characteristics ...................................................52
5.12 SPI .................................................................... 23
14. WLAN RF Specifications................................ 53
6. Global Functions............................................. 24
14.1 Introduction ........................................................53
6.1
External Coexistence Interface ......................... 24
14.2 2.4 GHz Band General RF Specifications ..........53
6.2
One-Time Programmable Memory .................... 24
6.3
Hibernation Block .............................................. 24
14.3 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................54
6.4
System Boot Sequence ..................................... 25
Document Number: 002-14829 Rev. *J
14.4 WLAN 2.4 GHz Transmitter Performance ..............
Specifications 56
Page 3 of 94
PRELIMINARY
CYW43907
14.5 WLAN 5 GHz Receiver Performance
Specifications .................................................... 57
17.5 SPI Flash Timing ................................................79
17.5.1 Read-Register Timing .............................79
14.6 WLAN 5 GHz Transmitter Performance
Specifications .................................................... 59
17.5.2 Write-Register Timing .............................80
14.7 General Spurious Emissions Specifications ...... 59
14.7.1 Transmitter Spurious Emissions
Specifications ........................................ 60
14.7.2 Receiver Spurious Emissions
Specifications ........................................ 61
17.5.4 Memory-Write Timing .............................82
15. Internal Regulator Electrical Specifications. 62
15.1 Core Buck Switching Regulator ........................ 62
15.2 3.3V LDO (LDO3P3) ......................................... 63
17.5.3 Memory Fast-Read Timing .....................81
17.5.5 SPI Flash Parameters ............................83
17.6 USB PHY Electrical Characteristics and Timing 84
17.6.1 USB 2.0 and USB 1.1 Electrical and
Timing Parameters .................................84
17.6.2 USB 2.0 Timing Diagrams ......................86
18. Power-Up Sequence and Timing................... 88
15.5 BBPLL LDO ....................................................... 66
18.1 Sequencing of Reset and Regulator Control
Signals ...............................................................88
18.1.1 Description of Control Signals ................88
18.1.2 Control Signal Timing Diagrams .............88
16. System Power Consumption ......................... 67
19. Thermal Information ....................................... 89
16.1 WLAN Current Consumption ............................. 67
16.1.1 2.4 GHz Mode ....................................... 67
16.1.2 5 GHz Mode .......................................... 68
19.1 Package Thermal Characteristics ......................89
17. Interface Timing and AC Characteristics...... 69
19.3 Environmental Characteristics ...........................89
17.1 Ethernet MAC (MII/RMII) Interface Timing ........ 69
17.1.1 MII Receive Packet Timing .................... 69
20. Mechanical Information.................................. 90
15.3 CLDO ................................................................ 64
15.4 LNLDO .............................................................. 65
19.2 Junction Temperature Estimation and PSIJT
Versus THETAJC ............................................................. 89
17.1.2 MII Transmit Packet Timing ................... 69
21. Ordering Information...................................... 91
17.1.3 RMII Receive Packet Timing ................. 70
22. Additional Information ................................... 91
17.1.4 RMII Transmit Packet Timing ................ 71
17.2 I2S Master and Slave Mode TX Timing ............. 72
22.1 Acronyms and Abbreviations .............................91
17.3 SDIO Interface Timing ....................................... 74
17.3.1 SDIO Default-Speed Mode Timing ........ 74
22.3 IoT Resources ....................................................91
17.3.2 SDIO High-Speed Mode Timing ............ 75
17.3.3 SDIO Bus Timing Specifications in
SDR Modes ........................................... 76
Document History Page ................................................. 92
22.2 References .........................................................91
22.4 Errata .................................................................91
Sales, Solutions, and Legal Information ...................... 94
17.4 S/PDIF Interface Timing .................................... 77
Document Number: 002-14829 Rev. *J
Page 4 of 94
PRELIMINARY
CYW43907
1. Overview
1.1 Introduction
The Cypress CYW43907 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with
integrated IEEE 802.11 a/b/g/n MAC/baseband/radio and a separate ARM Cortex-R4 applications processor. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with
flexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet the
needs of highly embedded systems that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43907 and their associated external interfaces, which are
described in greater detail in Section 5. “Applications Subsystem External Interfaces”.
Figure 2. Block Diagram and I/O
CYW43907
SPI Flash
GPIO[16:0]
RF TX
APPS Subsystem
WLAN Subsystem
ARM Cortex‐R4
320 MHz
32 KB I‐cache
32 KB D‐cache
ARM Cortex‐R4
160 MHz
448 KB ROM TCM
576 KB SRAM TCM
2 MB SRAM
640 KB ROM
802.11n
1x1
2.4 GHz and 5 GHz
RF RX
2x 2-Wire UART
4-Wire UART
2x I2S
2x SPI/CSC
2x CSC
JTAG/SWD
10/100 Ethernet
Switch Control
Antenna Diversity
SDIO 3.0/gSPI
VDDIOs
USB 2.0
GND
WAKE
1.1.1 Features
The CYW43907 supports the following features:
■
ARM Cortex-R4 clocked at 160 MHz (in 1× mode) or up to 320 MHz (in 2× mode).
■
2 MB of SRAM and 640 KB ROM available for the applications processor.
■
One high-speed 4-wire UART interface with operation up to 4 Mbps.
■
Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins.
■
Two dedicated CSC1 interfaces.
■ Two SPI master interfaces with operation up to 24 MHz.
Note: Either or both of the SPI interfaces can be used as CSC master interfaces. This is in addition to the two dedicated CSC
interfaces.
■
One SPI master interface for serial flash.
1. Cypress Serial Control (CSC) is an I2C-compatible interface.
Document Number: 002-14829 Rev. *J
Page 5 of 94
PRELIMINARY
■
Six dedicated PWM outputs.
■
Two I2S interfaces.
■
17 GPIOs.
■
IEEE 802.11 a/b/g/n 1×1 2.4 GHz and 5 GHz radio.
■
Single- and dual-antenna support.
CYW43907
1.2 Standards Compliance
The CYW43907 supports the following standards:
■
IEEE 802.11n
■
IEEE 802.11b
■
IEEE 802.11g
■
IEEE 802.11d
■
IEEE 802.11h
■
IEEE 802.11i
■
Security:
■
❐
WEP
❐
WPA Personal
❐
WPA2 Personal
❐
WMM
❐
WMM-PS (U-APSD)
❐
WMM-SA
❐
AES (hardware accelerator)
❐
TKIP (hardware accelerator)
❐
CKIP (software support)
Proprietary Protocols:
❐
CCXv2
❐
CCXv3
❐
CCXv4
❐
CCXv5
❐
WFAEC
The CYW43907 supports the following additional standards:
■
IEEE 802.11r—Fast Roaming (between APs)
■
IEEE 802.11w—Secure Management Frames
■
IEEE 802.11 Extensions:
❐
IEEE 802.11e QoS enhancements (already supported as per the WMM specification)
❐
IEEE 802.11i MAC enhancements
❐
IEEE 802.11k radio resource measurement
Document Number: 002-14829 Rev. *J
Page 6 of 94
PRELIMINARY
CYW43907
2. Power Supplies and Power Management
2.1 Power Supply Topology
One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43907. All
regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in
embedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW43907.
The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO,
LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when
REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband.
The CYW43907 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shut down. When
in this state, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the CYW43907 with all required
voltages.
2.2 CYW43907 Power Management Unit Features
The CYW43907 supports the following Power Management Unit (PMU) features:
■
VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator
■
VBAT to 3.3Vout (450 mA maximum) LDO3P3
■
1.35V to 1.2Vout (150 mA maximum) LNLDO
■
1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for deep-sleep
■
1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL
■
Additional internal LDOs (not externally accessible)
■
PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from the low power-consumption mode.
Figure 3 and Figure 4 show the regulators and a typical power topology.
Document Number: 002-14829 Rev. *J
Page 7 of 94
PRELIMINARY
CYW43907
Figure 3. Typical Power Topology (Page 1 of 2)
WLRF TX Mixer and PA (not always)
CYW43907 1.2V
VBAT
Operational:
2.3V to 4.8V
Performance:
3.0V to 4.8V
Absolute Maximum: 5.5V
VDDIO
Operational:
3.3V
Cap-less
LNLDO
1.2V
Cap-less
LNLDO
1.2V
Cap-less
VCOLDO
Cap-less
LNLDO
1.2V
Cap-less
LNLDO
1.2V
15 mA
XTAL LDO
1.2V
1.2V
Mini‐PMU
(Inside WL Radio)
VBAT
1.35V
LPLDO1
WLRF LNA
WLRF AFE and TIA
WLRF TX
WLRF ADC REF
WLRF XTAL
WLRF RFPLL, PFD, and MMD
1.2V
LNLDO
Core Buck
Regulator
(CBUCK)
VDDIO
WLRF LOGEN
1.35V
BBPLL
LNLDO
Audio PLL
1.2V
WL BBPLL/DFLL
REG_ON
CLDO
1.3V, 1.2V,
.095V (AVS)
WLAN/CLB/Top, Always On
WL PHY
WL Subcore
Supply ball
Supply bump/pad
Power
switch
Ground ball
Ground bump/pad
No power switch
WLAN reset
ball
External to chip
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14829 Rev. *J
WL VDDM (SRAMS in AOS)
APPS VDDM
APPS SOCSRAM
APPS Subcore
Page 8 of 94
PRELIMINARY
CYW43907
Figure 4. Typical Power Topology (Page 2 of 2)
CYW43907 2.5V and 3.3V
450 to
800 mA
WLRF PA(2.4 GHz and 5 GHz)
3.3V
VBAT
LDO3P3
WLRF Pad (2.4 GHz and 5 GHz)
VDDIO_RF
WL OTP 3.3V
2.5V Cap-less
LNLDO
WL RF RX, TX, NMOS, Mini-PMU LDOs
2.5V Cap-less
LNLDO
2.5V
2.5V Cap-less
LNLDO
2.5V
WL RF VCO
WL RF CP
VCOLDO2P5
Inside WL Radio
Supply ball
Supply bump/pad
Power
switch
Ground ball
Ground bump/pad
No power switch
External to chip
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14829 Rev. *J
Page 9 of 94
PRELIMINARY
CYW43907
2.3 Power Management
The CYW43907 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43907 includes an advanced Power Management Unit (PMU) sequencer. The PMU
sequencer provides significant power savings by putting the CYW43907 into various power management states appropriate to the
environment and activities that are being performed. The power management unit enables and disables internal regulators, switches,
and other blocks based on a computation of the required resources and a table that describes the relationship between resources
and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters
(running at a 32.768 kHz LPO clock) in the PMU sequencer are used to turn on and turn off individual regulators and power switches.
Clock speeds are dynamically changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever
possible.
Table 2 provides descriptions for the CYW43907 power modes.
Table 2. CYW43907 Power Modes
Mode
Description
Active
All WLAN blocks in the CYW43907 are powered up and fully functional with active carrier sensing and frame
transmission and receiving.
All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds
are dynamically adjusted by the PMU sequencer.
Doze
The radio, analog domains, and most of the linear regulators are powered down.
The rest of the CYW43907 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or TCXO)
are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for the PMU
sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active
mode. In Doze mode, the primary power consumed is due to leakage current.
Deep-sleep
Most of the chip, including both analog and digital domains and most of the regulators, is powered off.
Logic states in the digital core are saved and preserved in a retention memory in the Always-On domain before
the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt, or a host
resume through the USB bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid
lengthy HW reinitialization.
Power-down
The CYW43907 is effectively powered off by shutting down all internal regulators.
The chip is brought out of this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable
them.
Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■
enabled
■
disabled
■
transition_on
■
transition_off
The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loaded
with the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled and
decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to
enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0
Document Number: 002-14829 Rev. *J
Page 10 of 94
PRELIMINARY
CYW43907
indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence
refer to either the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■
Computes the required resource set based on requests and the resource dependency table.
■
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource
and inverts the ResourceState bit.
■
Compares the request with the current resource status and determines which resources must be enabled or disabled.
■
Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents.
■
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Power-Off Shutdown
The CYW43907 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system
devices remain operational. When the CYW43907 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO
remains powered. This allows the CYW43907 to be effectively off while keeping the I/O pins powered so that they do not draw extra
current from devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43907, all outputs are tristated and most inputs
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43907 to be fully integrated in an embedded device while
taking full advantage of the lowest power-saving modes.
When the CYW43907 is powered on from this state, it is the same as a normal power-up and does not retain any information about
its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW43907 has two signals (see Table 3) that enable or disable circuits and the internal regulator blocks, allowing the host to
control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 18. “Power-Up
Sequence and Timing”.
Table 3. Power-Up/Power-Down/Reset Control Signals
Signal
Description
REG_ON
This signal is used by the PMU to power up the CYW43907. It controls the internal CYW43907 regulators.
When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device
is in reset and the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled
by default. It can be disabled through programming.
HIB_REG_ON_IN
This signal is used by the hibernation block to decide whether or not to power down the internal CYW43907
regulators. If HIB_REG_ON_IN is low, the regulators will be disabled. For a signal at HIB_REG_ON_IN to
function as intended, HIB_REG_ON_OUT must be connected to REG_ON.
Document Number: 002-14829 Rev. *J
Page 11 of 94
PRELIMINARY
CYW43907
3. Frequency References
An external crystal is used for generating all radio frequencies and normal-operation clocking. As an alternative, an external frequency
reference can be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43907 can use an external crystal to provide a frequency reference. The recommended crystal oscillator configuration,
including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
Device boundary
C
WRF_XTAL_XON
1.3 pF
27 pF
37.4 MHz
C
x ohms
27 pF
Programmable internal shunt caps are
from 0 pF to 7.5 pF in steps of 0.5 pF.
WRF_XTAL_XOP
0.4 pF
External resistor and programmable
internal resistor value is determined
by crystal drive level.
Programmable internal series resistor is from 50 ohms to 500 ohms
in steps of 50 ohms. Boot‐up ROM value is 50 ohms.
Note: A reference schematic is available for further details. Contact your Broadcom FAE.
A fractional-N synthesizer in the CYW43907 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate
using a wide selection of frequency references.
The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in
Table 4.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
Document Number: 002-14829 Rev. *J
Page 12 of 94
PRELIMINARY
CYW43907
3.2 External Frequency Reference
As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise requirements listed in Table 4.
If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown
in Figure 6. The internal clock buffer connected to this pin will be turned off when the CYW43907 goes into sleep mode. When the
clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.
Figure 6. Recommended Circuit to Use With an External Reference Clock
1000 pF
Reference
Clock
WRF_XTAL_XON
NC
WRF_XTAL_XOP
Table 4. Crystal Oscillator and External Clock—Requirements and Performance
Parameter
2.4 GHz and 5 GHz bands:
IEEE 802.11a/b/g/n operation
Frequency
Frequency tolerance over the
lifetime of the equipment,
Without trimming
including temperaturec
External Frequency
Referenceb c
Crystala
Conditions/Notes
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
–
37.4
–
–
–37.4
–
MHz
–20
–
20
–20
–
20
ppm
Crystal load capacitance
–
–
16
–
–
–
–
pF
ESR
–
–
–
60
–
–
–
Ω
Drive level
External crystal must be able to tolerate
this drive level.
200
–
–
–
–
–
µW
Input impedance (WRF_XTAL_XON)
Resistive
–
–
–
30k
100k
–
Ω
Capacitive
–
–
7.5
–
–
7.5
pF
WRF_XTAL_XON
Input low level
DC-coupled digital signal
–
–
–
0
–
0.2
V
WRF_XTAL_XON
Input high level
DC-coupled digital signal
–
–
–
1.0
–
1.26
V
WRF_XTAL_XON
input voltage
(see Figure 6)
IEEE 802.11a/b/g operation only
–
–
–
400
–
1200
mVp-p
WRF_XTAL_XON
input voltage
(see Figure 6)
IEEE 802.11n AC-coupled analog input
–
–
–
1
–
–
Vp-p
Duty cycle
37.4 MHz clock
–
–
–
40
50
60
%
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–129
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–136
dBc/Hz
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–137
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–144
dBc/Hz
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–134
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–141
dBc/Hz
noised
Phase
(IEEE 802.11b/g)
noised
Phase
(IEEE 802.11a)
d
Phase noise
(IEEE 802.11n, 2.4 GHz)
Document Number: 002-14829 Rev. *J
Page 13 of 94
PRELIMINARY
CYW43907
Table 4. Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Parameter
Phase noised
(IEEE 802.11n, 5 GHz)
External Frequency
Referenceb c
Crystala
Conditions/Notes
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–142
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–149
dBc/Hz
a. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP.
b. See “External Frequency Reference” for alternative connection methods.
c. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
d. Assumes that external clock has a flat phase noise response above 100 kHz.
3.3 External 32.768 kHz Low-Power Oscillator
The CYW43907 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one tradeoff caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 5.
Table 5. External 32.768 kHz Sleep Clock Specifications
Parameter
Nominal input frequency
Frequency accuracy
Duty cycle
Input signal amplitude
Signal type
Input impedancea
Clock jitter (during initial start-up)
LPO Clock
Units
32.768
kHz
±200
ppm
30–70
%
200–3300
mV, p-p
Square-wave or sine-wave
–
>100k
<5
Ω
pF
<10,000
ppm
a. When power is applied or switched off.
Document Number: 002-14829 Rev. *J
Page 14 of 94
PRELIMINARY
CYW43907
4. Applications Subsystem
4.1 Overview
The Applications subsystem contains the general use CPU, memory, the standalone DMA core, the cryptography core, and the
majority of the external interfaces.
4.2 Applications CPU and Memory Subsystem
This subsystem has an integrated 32-bit ARM Cortex-R4 processor with an internal 32 KB D-cache and an internal 32 KB I-cache.
The ARM Cortex-R4 is a low-power processor that features a low gate count, low interrupt latency, and low-cost debugging capabilities. It is intended for deeply embedded applications that require fast interrupt response features. The ARM Cortex-R4 implements
the ARM v7-R architecture and supports the Thumb-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit
devices on a MIPS/µW basis. It also supports integrated sleep modes.
Using multiple technologies to reduce cost, the ARM Cortex-R4 enables improved memory utilization, reduced pin overhead, and
reduced silicon area. It also has extensive debugging features, including real-time tracing of program execution.
On-chip memory for the CPU includes 2 MB SRAM, 640 KB ROM, and an 8 KB RAM powered independently of the application
subsystem.
4.3 Memory-to-Memory DMA Core
The CYW43907 memory-to-memory DMA (M2MDMA) engine contains eight DMA channel pairs, each containing one transmit/pull
engine and one receive/push engine.
The DMA engine provides general purpose data movement between memories that can be on the device, attached directly to the
device, or accessed through a host interface. The transmit/pull engine reads data from the source memory and immediately passes
it to the paired receive/push engine, which proceeds to write it to the destination memory. Multiple masters can program the individual
channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters.
4.4 Cryptography Core
This core provides general purpose data movement between memories, which may be either on the device, attached directly to the
device, or accessed through a host interface. The transmit/pull engine reads data from the source memory and passes it immediately
to the paired receive/push engine that proceeds to write it to the destination memory. Multiple masters may program the individual
channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters.
The cryptography block provides a hardware accelerator for enciphering and deciphering data that has undergone processing using
standards-based encryption algorithms. The cryptography block includes the following primary features:
■
Encryption and hash engines that support single pass AUTH-ENC or ENC-AUTH processing.
■
A scalable AES module that supports CBC, ECB, CTR, CFB, OFB, and XTS encryption with 128-, 192-, and 256-bit key sizes.
■
A scalable DES module that supports DES and 3DES in ECB and CBC modes.
■
An RC4 stream cipher module that supports state initialization, state update, and key-stream generation.
■
MD5, SHA1, SHA224, and SHA256 engines that support pure hash or HMAC operations.
■
A built-in 512-byte key cache for locally protected key storage.
OTP memory is used to store authentication keys.
Document Number: 002-14829 Rev. *J
Page 15 of 94
PRELIMINARY
CYW43907
5. Applications Subsystem External Interfaces
5.1 Ethernet MAC Controller (MII/RMII)
The CYW43907 integrates a high performance Ethernet MAC controller. The controller interfaces to an external PHY either over a
Media Independent Interface (MII) or a Reduced Media Independent Interface (RMII). The controller can transmit and receive data at
10 Mbps and 100 Mbps.
5.2 GPIO
There are 17 general-purpose I/O (GPIO) pins available on the CYW43907. The GPIOs can be used to connect to various external
devices.
Upon power-up and reset, these pins are tristated. Subsequently, they can be programmed to be either input or output pins via the
GPIO control register. In addition, the GPIO pins can be assigned to various other functions.
Apart from other functions, GPIOs are used to set bootstrap options and use the JTAG interface for debugging during software
development.
5.3 Cypress Serial Control
The CYW43907 has two Cypress Serial Control (CSC2) master interfaces for external communication with codecs, DACs, NVRAM,
etc. The I/O pads can be configured as pull-ups or pull-ups can be installed on the reference design to support a multimaster on an
open drain bus.
The I2C0 CSC master interface can support repeated start, however it does not support clock stretching. The I2C1 CSC master
interface does not support repeated start or clock stretching. The CSC master can support a maximum clock frequency of 400kHz.
If clock stretching is required a bit banging driver is recommended. Cypress's WICED SDK provides and example of such a bit banging
I2C driver. Note that only I2C0 mentioned in Table 11 is multiplexed with GPIOs and supports bit banging. I2C1 is not multiplexed with
GPIOs and therefore cannot support bit banging.
5.4 I2S
The CYW43907 has two I2S interfaces for audio signal data. The two interfaces are identical. Each interface supports both Master
and Slave modes.
The following signals apply to the first I2S interface:
■
I2S bit clock: I2S_SCLK0 (sometimes referred to as I2S_BITCLK)
■
I2S word select: I2S_LRCK0 (sometimes referred to as I2S_WS)
■
I2S serial data out: I2S_SDATAO0
■
I2S serial data in: I2S_SDATAI0
■
I2S master clock: I2S_MCLK0
The following signals apply to the second I2S interface:
■
I2S bit clock: I2S_SCLK1 (sometimes referred to as I2S_BITCLK)
■
I2S word select: I2S_LRCK1 (sometimes referred to as I2S_WS)
■
I2S serial data out: I2S_SDATAO1
■
I2S serial data in: I2S_SDATAI1
■
I2S master clock: I2S_MCLK1
I2S_SDATAO0 and I2S_SDATAO1 are outputs.
I2S_MCLK, I2S_SCLK and I2S_LRCLK can be configured as either inputs or outputs depending on whether the master clock source
is on- or off-chip and whether the I2S is operating in Slave or Master mode.
Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel
data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit-clock cycle
2. Cypress Serial Control is an I2C compatible interface.
Document Number: 002-14829 Rev. *J
Page 16 of 94
PRELIMINARY
CYW43907
after the I2S_LRCK transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S_LRCK is
low, and right-channel data is transmitted when I2S_LRCK is high. An embedded 128 × 32-bit single-port SRAM for data processing
enhances the performance of the interface.
An audio PLL generates an internal master clock (for I2S_MCLK0 and I2S_MCLK1) that provides support for various sampling rates.
Note: In I2S slave mode if LRCLK changes on the rising edge of the bit clock, the MSB data bit is set half of a bit cycle after LRCLK.
Table 6 shows the MCLK rates (in MHz) associated with each of the various sample rates. In the table, FS refers to the sample rate
in kHz and typical MCLK rates are shaded.
Table 6. Variable Sample Rate and MCLK Rate Supporta
MCLK Rate (MHz)b
Sample
Rate (kHz)
128 × FS
192 × FS
256 × FS
384 × FS
512 × FS
640 × FS
768 × FS
1152 × FS
8
1.024
1.536
2.048
3.072
4.096
5.12
6.144
9.216
11.025
1.4112
2.1168
2.8224
4.2336
5.6448
7.056
8.4672
12.7008
12
1.536
2.304
3.072
4.608
6.144
7.68
9.216
13.824
16
2.048
3.072
4.096
6.144
8.192
10.24
12.288
18.432
22.05
2.8224
4.2336
5.6448
8.4672
11.2896
14.112
16.9344
25.4016
24
3.072
4.608
6.144
9.216
12.288
15.36
18.432
27.648
32
4.096
6.144
8.192
12.288
16.384
20.48
24.576
36.864
44.1
5.6448
8.4672
11.2896
16.9344
22.5792
28.224
33.8688
–
48
6.144
9.216
12.288
18.432
24.576
30.72
36.864
–
64
8.192
12.288
16.384
24.576
32.768
–
–
–
88.2
11.2896
16.9344
22.5792
33.8688
–
–
–
–
96
12.288
18.432
24.576
36.864
–
–
–
–
192
24.576
36.864
–
–
–
–
–
–
a. All data in the table assumes a crystal frequency of 37.4 MHz.
b. MCLK frequency errors are less than 1 ppb.
For an MCLK specification, see Table 45.
Document Number: 002-14829 Rev. *J
Page 17 of 94
PRELIMINARY
CYW43907
5.5 JTAG and ARM Serial Wire Debug
The CYW43907 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
The CYW43907 also supports ARM Serial Wire Debug (SWD) for connecting a JTAG debugger directly to both ARM Cortex-R4s. For
SWD, the combination of a clock and a bidirectional signal (on a single pin) provides normal JTAG debug and test functionality. The
reduced pin-count SWD interface is a high-performance alternative to the JTAG interface.
Table 7 shows the JTAG_SEL and TAP_SEL states for test and debug function selection. Test and debug function selection is
independent of the debugging interface (JTAG or SWD) being used.
Table 7. JTAG_SEL and TAP_SEL States for Test and Debug Function Selection
JTAG_SEL State
TAP_SEL State
Test and Debug Function
0
0
JTAG not used.
0
1
JTAG not used.
1
0
Access the LV tap directly for ATE and bring-up.
1
1
Access either of the ARM Cortex-R4’s directly via either the 5-pin JTAG port or the 2-pin
SWD configuration.
Note: JTAG_SEL is exposed on a dedicated physical pin. TAP_SEL uses the GPIO_8 physical pin.
5.6 PWM
The CYW43907 provides up to six independent pulse width modulation (PWM) channels. The following features apply to the PWM
channels:
■
Each channel is a square wave generator with a programmable duty cycle.
■
Each channel generates its duty cycle by dividing down the input clock.
■
Both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register.
■
Each channel can work independently or update simultaneously.
■
Pairs of PWM outputs can be inverted for devices that need a differential output.
■
Continuous or single pulses can be generated.
■
The input clock can either be a high-speed clock from a PLL channel or a lower speed clock at the crystal frequency.
5.7 SDIO 3.0
5.7.1 SDIO 3.0—Device Mode
Description
The CYW43907 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■
DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■
HS: High-speed up to 50 MHz (3.3V signaling).
■
SDR12: SDR up to 25 MHz (1.8V signaling).
■
SDR25: SDR up to 50 MHz (1.8V signaling).
Note: The CYW43907 is backward compatible with SDIO v2.0 host interfaces.
The following three functions are supported:
■
Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B)
■
Function 1 Backplane Function to access the internal SoC address space (max. BlockSize/ByteCount = 64B)
Document Number: 002-14829 Rev. *J
Page 18 of 94
PRELIMINARY
■
CYW43907
Function 2 WLAN Function for efficient WLAN packet transfer through DMA (max. BlockSize/ByteCount = 512B)
SDIO Pins
Table 8. SDIO Pin Descriptions
SD 4-Bit Mode
SD 1-Bit Mode
DATA0
Data line 0
DATA Data line
DATA1
Data line 1 or Interrupt
IRQ
Interrupt
DATA2
Data line 2 or Read Wait
RW
Read Wait
DATA3
Data line 3
N/C
Not used
CLK
Clock
CLK
Clock
CMD
Command line
CMD Command line
Figure 7. Signal Connections to an SDIO Host (SD 4-Bit Mode)
CLK
CMD
CYW43907
SD Host
DAT[3:0]
Figure 8. Signal Connections to an SDIO Host (SD 1-Bit Mode)
CLK
CMD
SD Host
DATA
CYW43907
IRQ
RW
Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four data (DATA) lines and
the command (CMD) line. This requirement must be met during all operating states either through the use of external pull-up
resistors or through proper programming of the SDIO host’s internal pull-ups
Document Number: 002-14829 Rev. *J
Page 19 of 94
PRELIMINARY
CYW43907
5.7.2 SDIO 3.0—Host Mode
The CYW43907 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■
DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■
HS: High-speed up to 50 MHz (3.3V signaling).
■
SDR12: SDR up to 25 MHz (1.8V signaling).
■ SDR25: SDR up to 50 MHz (1.8V signaling).
Note: The CYW43907 is backward compatible with SDIO v2.0 devices.
In this mode, the device supports the following features:
■
ADMA2.
■
Out-of-band signaling for card detection, write protection, and I/O voltage levels (which are available on GPIOs).
■
Dynamic, specification-compliant shifting from 3.3V to 1.8V I/Os.
5.8 S/PDIF
S/PDIF is a serial audio data transport format used to connect consumer audio devices such as CD players, DVD players, and
surround-sound receivers. Although S/PDIF can be used to transport uncompressed audio formats, the primary use case for the
CYW43907 S/PDIF interface is to transport multichannel compressed audio for surround-sound applications, especially Dolby Digital
and DTS, to an auxiliary external audio processor.
The CYW43907 can support two S/PDIF interfaces via the I2S_SDATA00 and I2S_SDATA01 pins. Because each S/PDIF interface
uses an I2S data line, only I2S or S/PDIF functionality can be enabled on each I2S interface.
Each S/PDIF interface has the following key requirements:
■
S/PDIF transmissions that conform with IEC 60958-1 (receiver not required).
■
Support for linear PCM audio data that conforms with IEC 60948-3.
■
Support for nonlinear PCM audio data that conforms with IEC 60948-3.
■
Support for priority payload formats that include IEC 61937-3 (AC-3) and IEC 61937-5 (DTS).
■
Support for sample rates from 32 kHz to 192 kHz.
■
Support for 16, 20, and 24-bit audio samples.
■
Support for only one concurrent compressed audio stream.
5.9 SPI Flash
The SPI flash interface supports the following features:
■
A SPI-compatible serial bus.
■
An 80 MHz (maximum) clock frequency.
■
Increased Throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode3.
■
Support for either ×1 or ×4 addresses with ×4 data.
■
3-bytes and 4-byte addressing modes.
■
A configurable dummy-cycle count that is programmable from 1 to 15.
■
Programmable instructions output to serial flash.
■
An option to change the sampling edge from rising-edge to falling-edge for read-back data when in high-speed mode.
3.
Note that the clock needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures. The throughput of the SPI Flash block is therefore
restricted to ~13 MBps for Quad mode and ~3 MBps for single mode.
Document Number: 002-14829 Rev. *J
Page 20 of 94
PRELIMINARY
CYW43907
5.10 UART
A high-speed 4-wire CTS/RTS UART interface can be enabled by software and has dedicated pins. Provided primarily for debugging
during development, this UART enables the CYW43907 to operate as RS-232 data termination equipment (DTE) for exchanging and
managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 × 8
in each direction.
There are two low-speed UART interfaces on the CYW43907. Each functions as a standard 2-wire UART. They are also enabled as
alternate functions on GPIOs and can be enabled independently of the 4-wire fast UART.
Note: The high-speed, 4-wire UART interface is identified as UART0 in this document and in reference schematics. The two lowspeed,2-wire UART interfaces are identified as UART1 and UART2 in this document and in the reference schematics.
5.11 USB 2.0
5.11.1 Overview
The USB 2.0 host controller (HC) and device controller (DC) interface to a backplane via Advanced eXtensible Interface (AXI) and
Advanced Peripheral Bus (APB). They interface externally through a USB 2.0 and HSIC interfaces.
Figure 9 shows the topology of the USB 2.0 core.
Figure 9. Topology of the USB 2.0 Core
AXI/APB
USB Device
Controller
APB
USB Host
Controller
UTMI/ULPI
Host/
Device
Select
UTMI/ULPI
Multiplexer
UTMI/ULPI
USB 2.0 PHY
Chip
Boundary
USB I/F
The CYW43907 contains both a USB 2.0 HC and DC. Therefore, it can operate in the host-only, device-only, and dual-role device
(DRD) modes. In DRD mode, the CYW43907 can be configured as either the host or a device on the fly but must remain in the same
mode until the next boot cycle. The restriction that the host or device mode remains fixed during a boot cycle is what differentiates
DRD from On-the-Go (OTG).
The state of the USB2_DSEL pin sets the mode as either host or device for USB Type A and Type B connectors. For a USB MicroAB connector, the USB2_DSEL pin sets the mode as either host or device while the overall mode is DRD.
Document Number: 002-14829 Rev. *J
Page 21 of 94
PRELIMINARY
CYW43907
Table 9 shows the supported application cases. The table also shows the USB mode and PHY type, the connector type, and the
USB2_DSEL state associated with each case.
Table 9. USB Application Cases
Application Case Shorthand
Mode
PHY
USB2_DSEL
Connector Information
DRD-Host
USB 2.0
0
DRD-Device
USB 2.0
1
Type: Micro-AB
Connect USB2_DSEL to the ID pin of the Micro-AB
receptacle.
Host + USB 2.0 PHY
Host
USB 2.0
0
Type A
Device + USB2.0 PHY
Device
USB 2.0
1
Type B
DRD + USB 2.0 PHY
Note: In host mode, the USB core can process an overcurrent event and take the appropriate action. The overcurrent event is input
into the CYW43907 via the alternative mode pin USB20H_CTL.
Figure 10 shows the CYW43907 configured to operate in DRD mode with a USB 2.0 PHY.
Figure 10. CYW43907 Configured as a DRD + USB 2.0 PHY
AXI/APB
PPC
EHC/OHC
DWDC/DMA
OVC
UTMI
UTMI
Multiplexer
UTMI
Demulitplexer
VBUS
UTMI
USB 2.0 PHY
D+/D–
5V
VBUS
Switch
USB 2.0
Micro-AB ID
Connector
USB2_DSEL
Chip Boundary
EHC:
OHC:
OVC:
PPC:
UTMI:
Enhanced Host Controller
Open Host Controller
Overcurrent indication
Port power control
USB
Document Number: 002-14829 Rev. *J
USB 2.0
Host
or Device
Page 22 of 94
PRELIMINARY
CYW43907
The following information pertains to Figure 10:
■
The Micro-AB receptacle connects the CYW43907 to an external host or device.
■
The Micro-AB connector ID pin is connected to the CYW43907 USB2_DSEL pin.
■
The CYW43907 GPIO_9 pin is high in order to select the USB 2.0 PHY.
■
The PPC line indicates whether the USB 2.0 host controller supports port power control.
■
The OVC line is used to indicate an overcurrent condition.
■
Standard differential signal lines D+ (DP) and D– (DM) are used for the USB 2.0 interface
5.11.2 USB 2.0 Features
The following capabilities and features apply to the CYW43907 USB 2.0 PHY:
■
Compliant with the UTMI+ level 2 specification.
■
Functions as a host or device.
■
Supports high speed (HS) at 480 Mbps, full speed (FS) at 12 Mbps, and low speed (LS) at 1.5 Mbps.
■
Integrates pull-up and pull-down terminations with resistor support (per an engineering change notice to the USB 2.0 specification).
■
Contains a calibrated 45Ω termination for HS TX/RX.
■
Uses half-duplex differential data signaling with NRZI encoding.
■
Recovers the data and clock from the data stream.
■
Integrates a 960 MHz PLL with a single-ended reference clock.
■
Supports host resume and remote wake-up.
■
Supports L1 and L2 suspend, shallow sleep, and Link-Power Management (LPM).
■
Supports legacy USB 1.1 devices through a serial interface.
■
Supports dribble bits.
■
Supports LS keep-alive packets (LS EOP).
■
Support HS keep-alive packets (HS SYNC).
■
Contains an onboard BERT for self-testing (PRBS and fixed patterns).
■
Dissipates a maximum power of 150 mW for 1-port in loop-back mode.
■
Contains an integrated 3.3V to 1.2V LDO.
■
Uses 3.3V.
5.12 SPI
CYW43907 contains 2 SPI blocks. These blocks support a fixed SPI mode (CPOL = 0, CPHA = 0) and 8-bit data read/write.
CPOL = 0: Clock idles at 0, and each cycle consists of a pulse of 1. The leading edge is a rising edge, and the trailing edge is a falling
edge. CPHA = 0: The "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the
data on (or shortly after) the leading edge of the clock cycle.
The SPI hardware blocks support a hold time of 25ns and a maximum clock frequency of 40MHz.
If a SPI slave does not support the above mode or requires a hold time greater than 25ns, a bit banging software SPI driver should
be used. Cypress's WICED SDK provides and example of such a driver. Note that the maximum SPI frequency support by a software
SPI driver is much lower than 40 MHz.
SPI0 mentioned in Table 11 is multiplexed with GPIOs and can therefore support a bit banging based software SPI driver. SPI1 is not
multiplexed with GPIOs and cannot support a bit banging based software SPI driver
Document Number: 002-14829 Rev. *J
Page 23 of 94
PRELIMINARY
CYW43907
6. Global Functions
6.1 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external colocated wireless device, such
as Bluetooth, to manage wireless medium sharing for optimum performance.
Figure 11 shows the coexistence interface.
Figure 11. Cypress 2-Wire External Coexistence Interface
CYW54907
WLAN
GCI
BT\IC
SECI_OUT
SECI_IN
UART_IN
UART_OUT
NOTES:
 SECI_OUT/BT_TXD and SECI_IN/BT_RXD are multiplexed on the GPIOs.
 The 2‐wire coexistence interface is intended for future compatibility with the BT SIG 2‐wire interface that is being standardized for Core 4.1.
Note: SECI UART is the same as UART2, one of the low-speed UART interfaces mentioned in section 5.10 and in the reference
schematics.
6.2 One-Time Programmable Memory
Various hardware configuration parameters can be stored in an internal 6144-bit (768 bytes) One-Time Programmable (OTP) memory
that is read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and
MAC address can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP memory device is 0. After any bit is programmed to a 1, it cannot be reprogrammed
to 0. The entire OTP memory array can be programmed in a single write-cycle using a utility provided with the Cypress WLAN
manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits that are
still in the 0 state can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file. The nvram.txt file is
provided with the reference board design package.
6.3 Hibernation Block
The Hibernation (HIB) block is a self-contained power domain that can be used to completely shut down the rest of the CYW43907.
This optional block uses the HIB_REG_ON_OUT pin to drive the REG_ON pin. Therefore, for the HIB block to work as designed, the
HIB_REG_ON_OUT pin must be connected to the REG_ON pin. To use the HIB block, software programs the HIB block with a wake
count and then asserts a signal indicating that the chip should be put into hibernation. After assertion, the HIB block drives
HIB_REG_ON_OUT low for the number of 32 kHz clock cycles programmed as the wake count. After the wake-count timer expires,
HIB_REG_ON_OUT is driven high. Other than the logic state of the HIB block, no state is saved in the CYW43907 during hibernation.
Document Number: 002-14829 Rev. *J
Page 24 of 94
PRELIMINARY
CYW43907
6.4 System Boot Sequence
The following general sequence occurs after a CYW43907 is powered on:
1. Either REG_ON or HIB_REG_ON_IN is asserted.
Note: For HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON.
2. The core LDO (CLDO) and LDO3P3 outputs stabilize.
3. The OTP memory bits are used to initialize various functions, such as PMU trimming, package selection, memory size selection,
etc.
4. The APP and WLAN cores are powered up.
5. The XTAL is powered up.
6. The APP and WLAN CPU bootup sequences start.
Document Number: 002-14829 Rev. *J
Page 25 of 94
PRELIMINARY
CYW43907
7. Wireless LAN Subsystem
7.1 WLAN CPU and Memory Subsystem
The CYW43907 WLAN section includes an integrated 32-bit ARM Cortex-R4 processor with internal RAM and ROM. The ARM CortexR4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. It is intended
for deeply embedded applications that require fast interrupt response features. Delivering more than a 30% performance gain over
ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb-2 instruction set.
At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It also supports integrated sleep modes.
On-chip memory for this CPU includes 576 KB of SRAM and 448 KB of ROM.
7.2 IEEE 802.11n MAC
The CYW43907 WLAN media access controller (MAC) is designed to support high-throughput operation with low power consumption.
It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In
addition, several power-saving modes have been implemented that allow the MAC to consume very little power while maintaining
network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 12.
The following sections provide an overview of the important MAC modules.
Figure 12. WLAN MAC Architecture
Embedded CPU Interface
Host Registers, DMA Engines
TX‐FIFO
32 KB
PMQ
RX‐FIFO
10 KB
PSM
PSM
UCODE
Memory
IFS
Backoff, BTCX
WEP
TKIP, AES, WAPI
TSF
SHM
BUS
IHR
NAV
EXT‐ IHR
BUS
TXE
TX A‐MPDU
RXE
RX A‐MPDU
Shared Memory
6 KB
MAC‐PHY Interface
Document Number: 002-14829 Rev. *J
Page 26 of 94
PRELIMINARY
CYW43907
The CYW43907 WLAN MAC supports features specified in the IEEE 802.11 base standard and amended by IEEE 802.11n. The key
MAC features include:
■
Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT).
■
Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP), and multiphase PSMP
operation.
■
Support for immediate ACK and Block-ACK policies.
■
Interframe space timing support, including RIFS.
■
Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.
■
Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.
■
Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.
■
Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.
■
Support for coexistence with Bluetooth and other external radios.
■
Programmable independent basic service set (IBSS) or infrastructure basic service set functionality.
■
Statistics counters for MIB support.
7.2.1 PSM
The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware in order
to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are
predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general,
allowing algorithms to be optimized very late in the design process. It also allows for changes to the algorithms to track evolving IEEE
802.11 specifications.
The PSM fetches instructions from microcode memory. It uses the shared memory to obtain operands for instructions, as a data store,
and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad memory
(similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are colocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,
or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
7.2.2 WEP
The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform encryption and decryption as well
as MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2
AES-CCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to use. It supplies the
keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and compute
the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames.
Document Number: 002-14829 Rev. *J
Page 27 of 94
PRELIMINARY
CYW43907
7.2.3 TXE
The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames
in the TXFIFO. It interfaces with the WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the
appropriate time determined by the channel-access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC has multiple logical queues to support traffic streams
that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue
from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise
timing trigger received from the IFS module.
The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
7.2.4 RXE
The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames
from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The
decrypted data is stored in the RXFIFO.
The RXE module contains filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver
address, BSSID, and certain frame types.
The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.
7.2.5 IFS
The IFS module contains the timers required to determine interframe-space timing including RIFS timing. It also contains multiple
backoff engines required to support prioritized access to the medium as specified by WMM.
The interframe-spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).
The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the backoff counters. When the backoff counters reach 0, the TXE gets notified so that it may commence frame transmission.
In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power
save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by
the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. When the timer
expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the
TSF is synchronized to the network.
The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
7.2.6 TSF
The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon
and probe response frames in order to maintain synchronization with the network.
The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
7.2.7 NAV
The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration
field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.
Document Number: 002-14829 Rev. *J
Page 28 of 94
PRELIMINARY
CYW43907
7.2.8 MAC-PHY Interface
The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an
programming interface that can be controlled either by the host or the PSM to configure and control the PHY.
7.3 IEEE 802.11™ a/b/g/n PHY
The CYW43907 WLAN digital PHY complies with IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 150 Mbps for low-power, high-performance, handheld applications.
The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates
optimized implementations of filters, FFTs, and Viterbi-decoder algorithms. Efficient algorithms have been designed to achieve
maximum throughput and reliability, including algorithms for carrier sensing and rejection, frequency/phase/timing acquisition and
tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carriersensing algorithm provides high throughput for IEEE 802.11b/g hybrid networks with Bluetooth coexistence.
The key PHY features include:
■
Programmable data rates from MCS0–7 in 20 MHz and 40 MHz channels.
■
Support for Optional Short GI and Green Field modes in TX and RX.
■
TX and RX LDPC for improved range and power efficiency.
■
All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive
direction.
■
Support for IEEE 802.11h/k for worldwide operation.
■
Advanced algorithms for low power consumption and enhanced sensitivity, range, and reliability.
■
Algorithms to improve performance in the presence of externally received Bluetooth signals.
■
An automatic gain control scheme for blocking and nonblocking cellular applications.
■
Closed loop transmit power control.
■
Digital RF chip calibration algorithms to handle CMOS RF chip process, voltage, and temperature (PVT) variations.
■
On-the-fly channel frequency and transmit power selection.
■
Per-packet RX antenna diversity.
■
Available per-packet channel quality and signal-strength measurements.
■
Compliance with FCC and other worldwide regulatory requirements.
Figure 13. WLAN PHY Block Diagram
Filte rs
an d
R ad io
Com p
A FE
an d
R ad io
R ad io
C o n tro l
B lo ck
Com m on
Lo gic
B lo ck
Filte rs
an d
R ad io
Com p
C C K/D SSS
D e m o d u late
Freq u e n cy
an d Tim in g
Syn ch
C arrier Sen se,
A G C , an d R x
FSM
Tx FSM
O FD M
D e m o d u late
B u ffe rs
V iterb i D e co d e r
D e scram b le
an d D e fram e
FFT/IFFT
M AC
In te rface
M o d u latio n
an d C o d in g
Fram e an d
Scram b le
PA Com p
Document Number: 002-14829 Rev. *J
M o d u late /
Sp re ad
C O EX
Page 29 of 94
PRELIMINARY
CYW43907
8. WLAN Radio Subsystem
The CYW43907 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz
Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating
in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering,
mixing, and gain control functions.
Ten RF control signals are available to drive external RF switches. In addition, these control signals can be used to support optional
external 5 GHz band power and low-noise amplifiers. See the reference board schematics for more information.
A block diagram of the radio subsystem is shown in Figure 14. Note that integrated on-chip baluns (not shown) convert the fully
differential transmit and receive paths to single-ended signal pins.
8.1 Receiver Path
The CYW43907 has a wide dynamic range, direct conversion receiver that employs high-order on-chip channel filtering to ensure
reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The 2.4 GHz and 5 GHz paths each have a dedicated
on-chip low-noise amplifier (LNA).
8.2 Transmit Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively. Linear on-chip power amplifiers
deliver high output powers while meeting IEEE 802.11a/b/g/n specifications without the need for external PAs. When using the internal
PA, which is required in the 2.4 GHz band and optional in the 5 GHz band, closed-loop output power control is completely integrated.
8.3 Calibration
The CYW43907 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations
across components. These calibration routines are performed periodically during the course of normal radio operation. Examples of
some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and LOFT
calibration for carrier leakage reduction. In addition, I/Q calibration and VCO calibration are performed on-chip. No per-board
calibration is required during manufacturing testing. This helps to minimize the test time and cost in large-volume production environments.
Figure 14. Radio Functional Block Diagram
W L T X 2 .4 G H z M ix e r
TX M ode
S w it c h
W L DAC
W L PA
W L TXLPF
W L DAC
W L A ‐P A
W L A ‐P A D
W L TXLPF
W L T X 5 G H z M ix e r
W L R X 5 G H z M ix e r
W LA N B B
V o lt a g e
R e g u la t o r s
W L ADC
W L A ‐L N A 1 1
W L A ‐L N A 1 2
W L R XLPF
W L ADC
TX M ode
S w it c h
W L ‐G ‐L N A 1 1
W L G ‐L N A 1 2
W L R XLPF
W L R X 2 .4 G H z M ix e r
W L 5 GHz TX
W L 5 GHz RX
W L 2 .4 G H z T X
W L 2 .4 G H z R X
W L LO G EN
W L PLL
XON
Sh a re d X O
LP O /E xt LP O /R C A L
Document Number: 002-14829 Rev. *J
XOP
Page 30 of 94
PRELIMINARY
CYW43907
9. Pinout and Signal Descriptions
Figure 15 shows the bump map of the WLCSP package.
Figure 15. 316-Bump WLCSP Map
Document Number: 002-14829 Rev. *J
Page 31 of 94
PRELIMINARY
CYW43907
9.1 Bump List
Table 10 contains the WLCSP bump names.
Table 10. WLCSP Bump Names
Bump
Name
1
NO_CONNECT
2
NO_CONNECT
3
NO_CONNECT
4
NO_CONNECT
5
NO_CONNECT
6
VSSC
7
NO_CONNECT
8
NO_CONNECT
9
NO_CONNECT
10
NO_CONNECT
11
NO_CONNECT
12
NO_CONNECT
13
NO_CONNECT
14
VSSC
15
VSSC
16
NO_CONNECT
17
NO_CONNECT
18
NO_CONNECT
19
NO_CONNECT
20
NO_CONNECT
21
VSSC
22
VSSC
23
NO_CONNECT
24
NO_CONNECT
25
VSSC
26
NO_CONNECT
27
NO_CONNECT
28
NO_CONNECT
29
NO_CONNECT
30
NO_CONNECT
31
NO_CONNECT
32
NO_CONNECT
33
NO_CONNECT
34
NO_CONNECT
35
VSSC
36
NO_CONNECT
37
NO_CONNECT
38
NO_CONNECT
39
VSSC
Document Number: 002-14829 Rev. *J
Page 32 of 94
PRELIMINARY
Bump
40
Name
CYW43907
Bump
Name
VSSC
82
SPI0_CS
41
NO_CONNECT
83
SPI1_CLK
42
VSSC
84
SPI1_MISO
43
NO_CONNECT
85
UART0_CTS
44
NO_CONNECT
86
SPI1_SISO
45
NO_CONNECT
87
UART0_TXD
46
NO_CONNECT
88
UART0_RXD
47
NO_CONNECT
89
I2C1_CLK
48
NO_CONNECT
90
I2C1_SDATA
49
NO_CONNECT
91
UART0_RTS
50
VSSC
92
I2C0_CLK
51
NO_CONNECT
93
I2C0_SDATA
52
VSSC
94
GPIO_9
53
VSSC
95
GPIO_7
54
NO_CONNECT
96
VSSC
55
NO_CONNECT
97
PMU_AVSS
56
VSSC
98
SR_VLX
57
VSSC
99
SR_VLX
58
VSSC
100
REG_ON
59
VSSC
101
SR_VLX
60
VSSC
102
SR_VLX
61
NO_CONNECT
103
VOUT_CLDO_SENSE
62
NO_CONNECT
104
VSSC
63
NO_CONNECT
105
VDDIO
64
NO_CONNECT
106
VOUT_LNLDO
65
NO_CONNECT
107
VOUT_BBPLLOUT
66
NO_CONNECT
108
SR_VDDBAT5V
67
NO_CONNECT
109
SR_VLX
68
NO_CONNECT
110
SR_PVSS
69
NO_CONNECT
111
SR_PVSS
70
NO_CONNECT
112
SR_VLX
71
SFL_IO1
113
SR_VDDBAT5V
72
SFL_IO3
114
VOUT_CLDO
73
SFL_IO0
115
LDO_VDD1P5
74
SFL_CS
116
LDO_VDD1P5
75
SFL_IO2
117
VOUT_3P3_SENSE
76
SPI0_CLK
118
VOUT_3P3
77
SFL_CLK
119
VOUT_3P3
78
SPI0_MISO
120
LDO_VDD1P5
79
VSSC
121
VOUT_CLDO
80
SPI1_CS
122
SR_VDDBAT5V
81
SPI0_SISO
123
SR_PVSS
Document Number: 002-14829 Rev. *J
Page 33 of 94
PRELIMINARY
Bump
124
Name
CYW43907
Bump
Name
SR_PVSS
166
USB2_AVDD33
125
SR_VDDBAT5V
167
USB2_DP
126
VOUT_CLDO
168
USB2_AVSS
127
LDO_VDD1P5
169
USB2_RREF
128
LDO_VDDBAT5V
170
USB2_DM
129
LDO_VDDBAT5V
171
USB2_DVSS
130
GPIO_14
172
USB2_AVSSBG
131
GPIO_13
173
USB2_AVDD33LDO
132
GPIO_5
174
VDDIO
133
GPIO_6
175
USB2_MONCDR
134
GPIO_8
176
USB2_AVDD33IO
135
VSSC
177
VSSC
136
GPIO_4
178
VSSC
137
GPIO_16
179
NO_CONNECT
138
VDDC
180
NO_CONNECT
139
GPIO_2
181
NO_CONNECT
140
GPIO_11
182
VSSC
141
GPIO_0
183
VSSC
142
GPIO_1
184
USB2_MONPLL
143
GPIO_12
185
PWM0
144
GPIO_3
186
PWM1
145
GPIO_15
187
PWM4
146
GPIO_10
188
PWM5
147
SDIO_DATA_3
189
PWM3
148
SDIO_DATA_2
190
PWM2
149
SDIO_DATA_1
191
AVSS_AUDIO
150
SDIO_DATA_0
192
AVDD1P2_AUDIO
151
SDIO_CMD
193
JTAG_SEL
152
SDIO_CLK
194
CLK_REQ
153
I2S_MCLK0
195
VDDIO
154
I2S_SCLK0
196
RF_SW_CTRL_9
155
I2S_SDATAO1
197
VSSC
156
I2S_SDATAI1
198
SRSTN
157
VDDIO_I2S
199
VDDIO_RF
158
I2S_MCLK1
200
RF_SW_CTRL_8
159
VDDIO_I2S
201
RF_SW_CTRL_7
160
I2S_SCLK1
202
RF_SW_CTRL_6
161
I2S_SDATAO0
203
OTP_VDD3P3
162
I2S_LRCLK1
204
AVDD1P2
163
I2S_LRCLK0
205
RF_SW_CTRL_3
164
I2S_SDATAI0
206
RF_SW_CTRL_4
165
USB2_DSEL
207
RF_SW_CTRL_5
Document Number: 002-14829 Rev. *J
Page 34 of 94
PRELIMINARY
Bump
Name
CYW43907
Bump
Name
208
VDDIO_RF
250
HIB_XTALOUT
209
VSSC
251
VSSC
210
VSSC
252
VDDC
211
RF_SW_CTRL_2
253
VSSC
212
AVSS
254
VDDC
213
LPO_XTAL_IN
255
VDDIO_SD
214
RF_SW_CTRL_1
256
VSSC
215
RF_SW_CTRL_0
257
VDDIO
216
VDDC
258
VDDIO
217
VDDC
259
VSSC
218
WRF_AFE_GND
260
VSSC
219
WRF_AFE_GND
261
VDDIO
220
WRF_XTAL_VDD1P2
262
VSSC
221
WRF_XTAL_VDD1P35
263
VDDIO
222
WRF_XTAL_XOP
264
VSSC
223
WRF_SYNTH_VDD3P3
265
VSSC
224
WRF_AFE_GND
266
VSSC
225
WRF_AFE_GND
267
VDDC
226
WRF_XTAL_XON
268
VDDC
227
WRF_PMU_VDD1P35
269
VDDIO
228
WRF_PMU_VDD1P35
270
HIB_VDDO
229
WRF_SYNTH_VDD1P2
271
VDDC
230
WRF_AFE_GND
272
VSSC
231
WRF_AFE_VDD1P35
273
VSSC
232
WRF_AFE_GND
274
VSSC
233
WRF_RFIN_5G
275
VDDC
234
WRF_AFE_GND
276
VDDC
235
WRF_EXT_TSSIA
277
VDDC
236
WRF_AFE_GND
278
HIB_REG_ON_OUT
237
WRF_GPAIO_OUT
279
HIB_WAKE_B
238
WRF_AFE_GND
280
VDDC
239
WRF_PAOUT_5G
281
VDDC
240
WRF_PA_VDD3P3
282
HIB_REG_ON_IN
241
WRF_PA_VDD3P3
283
HIB_LPO_SELMODE
242
WRF_AFE_GND
284
RMII_G_TXD3
243
WRF_AFE_GND
285
VDDC
244
WRF_TXMIX_VDD
286
VDDC
245
WRF_PAOUT_2G
287
VSSC
246
WRF_RFIN_2G
288
RMII_MDIO
247
WRF_AFE_GND
289
VDDC
248
VSSC
290
VSSC
249
HIB_XTALIN
291
VSSC
Document Number: 002-14829 Rev. *J
Page 35 of 94
PRELIMINARY
Bump
CYW43907
Name
292
VSSC
293
RMII_G_COL
294
RMII_G_TXC
295
RMII_G_RXD2
296
RMII_G_RXD3
297
RMII_G_RXC
298
RMII_G_CRS
299
RMII_G_RXD1
300
RMII_G_TXD2
301
VSSC
302
VSSC
303
RMII_G_RXD0
304
RMII_G_TXD0
305
VDDIO_RMII
306
RMII_G_TXEN
307
VDDIO_RMII
308
VSSC
309
VDDC
310
RMII_MDC
311
RMII_G_TXD1
312
RMII_G_RXDV
313
VSSC
314
VDDC
315
VSSC
316
VDDC
9.2 Signal Descriptions
Table 11 provides the signal name, type, and description for each CYW43907 bump. The symbols shown under Type indicate pin
directions (I/O = bidirectional, I = input, and O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up
resistor and PD = weak internal pull-down resistor), if any.
Table 11. Signal Descriptions
Bump Number
Signal Name
Type
Description
Cypress Serial Control (CSC) Interfaces
92
I2C0_CLK
O
CSC master clock.
93
I2C0_SDATA
I/O
CSC serial data
89
I2C1_CLK
O
CSC master clock
90
I2C1_SDATA
I/O
CSC serial data
Clocks
222
WRF_XTAL_XOP
I
XTAL oscillator input.
226
WRF_XTAL_XON
O
XTAL oscillator output.
213
LPO_XTAL_IN
I
External sleep clock input (32.768 kHz).
249
HIB_XTALIN
I
3.3V 32 kHz crystal input
Document Number: 002-14829 Rev. *J
Page 36 of 94
PRELIMINARY
CYW43907
Table 11. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
250
HIB_XTALOUT
O
3.3V 32 kHz crystal output
194
CLK_REQ
O
Reference clock request
297
RMII_G_RXC
I
MII receive clock
293
RMII_G_COL
I
MII collision detection
298
RMII_G_CRS
I
MII carrier sense
Ethernet MAC Interface (MII/RMII)
294
RMII_G_TXC
I
MII/RMII transmit clock
304
RMII_G_TXD0
O
MII/RMII transmit signal
311
RMII_G_TXD1
O
MII/RMII transmit signal
300
RMII_G_TXD2
O
MII transmit signal
284
RMII_G_TXD3
O
MII transmit signal
303
RMII_G_RXD0
I
MII/RMII receive signal
299
RMII_G_RXD1
I
MII/RMII receive signal
295
RMII_G_RXD2
I
MII receive signal
296
RMII_G_RXD3
288
RMII_MDIO
I/O
I
MII/RMII management data
MII receive signal
310
RMII_MDC
O
MII/RMII management clock
306
RMII_G_TXEN
O
MII/RMII transmit enable
312
RMII_G_RXDV
I
MII/RMII receive data valid
GPIO Interface (WLAN)
141
GPIO_0
I/O
142
GPIO_1
I/O
139
GPIO_2
I/O
144
GPIO_3
I/O
136
GPIO_4
I/O
132
GPIO_5
I/O
133
GPIO_6
I/O
95
GPIO_7
I/O
134
GPIO_8
I/O
94
GPIO_9
I/O
146
GPIO_10
I/O
140
GPIO_11
I/O
143
GPIO_12
I/O
131
GPIO_13
I/O
130
GPIO_14
I/O
145
GPIO_15
I/O
137
GPIO_16
Programmable GPIO pins.
I/O
Ground
218, 219, 224, 225, 230, 232, 234, 236,
WRF_AFE_GND
238, 242, 243, 247
Document Number: 002-14829 Rev. *J
GND
AFE ground
Page 37 of 94
PRELIMINARY
CYW43907
Table 11. Signal Descriptions (Cont.)
Bump Number
Signal Name
6, 14, 15, 21, 22, 25, 35, 39, 40, 42, 50,
52, 53, 56–60, 79, 96, 104, 135, 177, 178,
182, 183, 197, 209, 210, 248, 251, 253, VSSC
256, 259, 260, 262, 264–266, 272–274,
287, 290–292, 301, 302, 308, 313, 315
Type
Description
GND
Core ground for WLAN and APP sections
SR_PVSS
GND
Power ground
97
PMU_AVSS
GND
Quiet ground
212
AVSS
GND
Baseband PLL ground
110, 111, 123, 124
191
AVSS_AUDIO
GND
AUDIO PLL ground
168
USB2_AVSS
GND
USB 2.0 analog ground
172
USB2_AVSSBG
GND
USB 2.0 analog ground
171
USB2_DVSS
GND
USB 2.0 digital ground
Hibernation Block, Power-Down/Power-Up, and Reset
100
REG_ON
I
Used by PMU to power up or power down the
internal CYW43907 regulators used by the
WLAN and APP sections. Also, when
deasserted, this pin holds the WLAN and
APP sections in reset. This pin has an
internal 200 kΩ pull-down resistor that is
enabled by default. It can be disabled
through programming.
282
HIB_REG_ON_IN
I
Used by the hibernation block to power up or
power down the internal CYW43907
regulators. For applications that use the
hibernation block, HIB_REG_ON_OUT must
connect to REG_ON. Also, when
deasserted, this pin holds the WLAN and
APP sections in reset.
278
HIB_REG_ON_OUT
O
REG_ON output signal generated by the
hibernation block.
279
HIB_WAKE_B
I
Wake up chip from hibernation mode.
283
HIB_LPO_SELMODE
I
Select precise or coarse 32 kHz clock.
I
System reset. This active-low signal resets
the backplanes.
198
SRSTN
I2S Interface
153
I2S_MCLK0
I/O
M clock
154
I2S_SCLK0
I/O
S clock
163
I2S_LRCLK0
I/O
LR clock
164
I2S_SDATAI0
I
I2S data input
161
I2S_SDATAO0
O
I2S data output
158
I2S_MCLK1
I/O
M clock
160
I2S_SCLK1
I/O
S clock
162
I2S_LRCLK1
I/O
156
I2S_SDATAI1
I
I2S data input
155
I2S_SDATAO1
O
I2S data output
I
JTAG select. This pin must be connected to
ground if the JTAG interface is not used.
LR clock
JTAG Interface
193
Document Number: 002-14829 Rev. *J
JTAG_SEL
Page 38 of 94
PRELIMINARY
CYW43907
Table 11. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
No Connects
1–5, 7–13, 16–20, 23, 24, 26–34, 36–38,
NO_CONNECT
41, 43–49, 51, 54, 55, 61–70, 179–181
–
No connect
Power Supplies (Miscellaneous)
PWR
OTP 3.3V supply
138, 216, 217, 252, 254, 267, 268, 271,
275–277, 280, 281, 285, 286, 289, 309, VDDC
314, 316
203
OTP_VDD3P3
PWR
1.2V core supply for WLAN
105, 174, 195, 257, 258, 261, 263, 269
VDDIO
PWR
I/O supply
199, 208
VDDIO_RF
PWR
I/O supply for RF switch control pads (3.3V).
157, 159
VDDIO_I2S
PWR
I/O supply for I2S
305, 307
VDDIO_RMII
PWR
I/O supply for RMII
255
VDDIO_SD
PWR
I/O supply for SDIO
270
HIB_VDDO
PWR
I/O supply for hibernation block
204
AVDD1P2
PWR
1.2V supply for baseband PLL
192
AVDD1P2_AUDIO
PWR
1.2V supply for audio PLL
166
USB2_AVDD33
PWR
3.3V supply for USB 2.0
173
USB2_AVDD33LDO
PWR
3.3V supply for USB 2.0
176
USB2_AVDD33IO
PWR
3.3V supply for USB 2.0
Power Supplies (WLAN)
WRF_SYNTH_VDD3P3
PWR
Synthesizer VDD 3.3V supply
240, 241
223
WRF_PA_VDD3P3
PWR
2.4 GHz and 5 GHz PA 3.3V VBAT supply
227, 228
WRF_PMU_VDD1P35
PWR
PMU 1.35V supply
244
WRF_TXMIX_VDD
PWR
3.3V supply for TX mixer
229
WRF_SYNTH_VDD1P2
PWR
1.2V supply for synthesizer
231
WRF_AFE_VDD1P35
PWR
1.35V supply for the analog front end
(AFE)
185
PWM0
O
Pulse width modulation bit 0.
186
PWM1
O
Pulse width modulation bit 1
190
PWM2
O
Pulse width modulation bit 2
189
PWM3
O
Pulse width modulation bit 3
187
PWM4
O
Pulse width modulation bit 4
188
PWM5
O
Pulse width modulation bit 5
PWM Interface
RF Signal Interface (WLAN)
246
WRF_RFIN_2G
I
2.4 GHz WLAN receiver input
233
WRF_RFIN_5G
I
5 GHz WLAN receiver input
245
WRF_PAOUT_2G
O
2.4 GHz WLAN PA output
239
WRF_PAOUT_5G
O
5 GHz WLAN PA output
235
WRF_EXT_TSSIA
I
5 GHz TSSI input from an optional external
power amplifier/power detector
237
WRF_GPAIO_OUT
I/O
Document Number: 002-14829 Rev. *J
Analog GPIO
Page 39 of 94
PRELIMINARY
CYW43907
Table 11. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
RF Switch Control Lines
215
RF_SW_CTRL_0
O
214
RF_SW_CTRL_1
O
211
RF_SW_CTRL_2
O
205
RF_SW_CTRL_3
O
206
RF_SW_CTRL_4
O
207
RF_SW_CTRL_5
I/O
202
RF_SW_CTRL_6
I/O
201
RF_SW_CTRL_7
I/O
200
RF_SW_CTRL_8
I/O
196
RF_SW_CTRL_9
I/O
Programmable RF switch control lines. The
control lines are programmable via the driver
and nvram.txt file.
SDIO Interface
152
SDIO_CLK
I/O
SDIO cock
151
SDIO_CMD
I/O
SDIO command line
150
SDIO_DATA_0
I/O
SDIO data line 0
149
SDIO_DATA_1
I/O
SDIO data line 1
148
SDIO_DATA_2
I/O
SDIO data line 2
147
SDIO_DATA_3
I/O
SDIO data line 3
S/PDIF Interface
Note: Supported via 161 (I2S_SDATAO0) and 155 (I2S_SDATAO1).
SPI Flash Interface
77
SFL_CLK
O
Flash clock
73
SFL_IO0
I/O
Flash data
71
SFL_IO1
I/O
Flash data
75
SFL_IO2
I/O
Flash data
72
SFL_IO3
I/O
Flash data
74
SFL_CS
O
Flash slave select
SPI Interfaces
Note: Each SPI interface can alternatively be configured and used as a CSC interfacea.
76
SPI0_CLK
O
SPI clock
78
SPI0_MISO
I
SPI data master in
81
SPI0_SISO
O
SPI data master out
82
SPI0_CS
O
SPI slave select
83
SPI1_CLK
O
SPI clock
84
SPI1_MISO
I
SPI data master in
86
SPI1_SISO
O
SPI data master out
80
SPI1_CS
O
SPI slave select
85
UART0_CTS
I
UART clear-to-send
91
UART0_RTS
O
UART request-to-send
88
UART0_RXD
I
UART serial input
87
UART0_TXD
O
UART serial output
UART Interface
Document Number: 002-14829 Rev. *J
Page 40 of 94
PRELIMINARY
CYW43907
Table 11. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
USB 2.0
170
USB2_DM
I/O
USB 2.0 data
167
USB2_DP
I/O
169
USB2_RREF
I
USB 2.0 reference resistor connection
175
USB2_MONCDR
O
USB 2.0 CDR monitor
184
USB2_MONPLL
O
USB 2.0 PLL monitor
165
USB2_DSEL
I
USB 2.0 host and device mode selection
USB 2.0 data
Voltage Regulators (Integrated)
108, 113, 122, 125
SR_VDDBAT5V
I
VBAT.
98, 99, 101, 102, 109, 112
SR_VLX
O
CBUCK switching regulator output
115, 116, 120, 127
LDO_VDD1P5
I
LNLDO input
128, 129
LDO_VDDBAT5V
I
LDO VBAT
221
WRF_XTAL_VDD1P35
I
XTAL LDO input (1.35V)
220
WRF_XTAL_VDD1P2
O
XTAL LDO output (1.2V)
106
VOUT_LNLDO
O
Output of LNLDO
114, 121, 126
VOUT_CLDO
O
Output of core LDO
118, 119
VOUT_3P3
O
LDO 3.3V output
117
VOUT_3P3_SENSE
O
Voltage sense pin for LDO 3.3V output
103
VOUT_CLDO_SENSE
O
Voltage sense pin for core LDO
107
VOUT_BBPLLOUT
O
Output of baseband PLL
a. The SPI blocks can be re-purposed as I2C, however the WICED SDK does not support this. Certain I2C features are not available when using
the SPI blocks as I2C. Therefore Cypress does not recommend using the SPI blocks as I2C interfaces.
Document Number: 002-14829 Rev. *J
Page 41 of 94
PRELIMINARY
CYW43907
10. GPIO Signals and Strapping Options
10.1 Overview
This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various
operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each
pin assumes the GPIO or alternative function specified in Table 13. Each strapping option pin has an internal pull-up (PU) or pull-down
(PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to
ground, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
10.2 Weak Pull-Down and Pull-Up Resistances
At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of VDDO) are 37.99 kΩ,
44.57 kΩ, and 51.56 kΩ, respectively. At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-up resistances (for a
pin voltage of 0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively.
10.3 Strapping Options
Table 12 provides the strapping options.
Table 12. Strapping Options
Pin Name
Strap
Bump #
Default Internal
Pull During Strap
Description
GPIO_1
GSPI_MODE
142
PD
Enable gSPI interface
GPIO_7
WCPU_BOOT_MODE
95
PD
Boot from SoC SROM or SoC SRAM
GPIO_11
ACPU_BOOT_MODE
140
PD
Boot from tightly coupled memory (TCM) ROM or TC
GPIO_13
SDIO_MODE
131
PD
Select either SDIO host mode or SDIO device mode
GPIO_15
VTRIM_EN
145
PD
Enable PMU voltage trimming
RF_SW_CTRL_5
DAP_CLK_SEL
207
PD
Select XTAL clock or the test clock (tck) for the debu
RF_SW_CTRL_7
RSRC_INIT_MODE
201
PD
PMU resource initialization mode selection
Document Number: 002-14829 Rev. *J
Page 42 of 94
PRELIMINARY
CYW43907
10.4 Alternate GPIO Signal Functions
Table 13 provides the alternate signal functions of the GPIO signals.
Table 13. Alternate GPIO Signal Functions
GPIO
Default
JTAG_SEL
Default Pull
GPIO_0
GPIO_1
HOLD/PDLOW/PDHIGH
Strap
Comments
USB20H_CTL
–
No pull
–
–
Down
HOLD
–
8 mA
HOLD
GSPI_MODE
GPIO_2
GCI_GPIO(0)
JTAG_TCK
No pull
8 mA
HOLD
–
8 mA
GPIO_3
GCI_GPIO(1)
JTAG_TMS
GPIO_4
GCI_GPIO(2)
JTAG_TDI
No pull
HOLD
–
8 mA
No pull
HOLD
–
8 mA
GPIO_5
GCI_GPIO(3)
JTAG_TDO
No pull
HOLD
–
8 mA
GPIO_6
GCI_GPIO(4)
JTAG_TRST
No pull
GPIO_7
–
–
Down
HOLD
–
8 mA
HOLD
WCPU_BOOT_MODE
GPIO_8
GPIO_8
–
No pull
HOLD
8 mA
–
8 mA
GPIO_9
GPIO_9
–
Down
HOLD
–
8 mA
GPIO_10
GPIO_10
–
No pull
HOLD
–
8 mA
GPIO_11
–
–
Down
HOLD
ACPU_BOOT_MODE
8 mA
GPIO_12
GPIO_12
–
No pull
HOLD
–
8 mA
GPIO_13
–
–
Down
HOLD
SDIO_MODE
8 mA
GPIO_14
GPIO_14
–
No pull
HOLD
–
8 mA
GPIO_15
–
–
Down
HOLD
VTRIM_EN
8 mA
GPIO_16
–
–
No pull
HOLD
–
8 mA
Document Number: 002-14829 Rev. *J
Page 43 of 94
PRELIMINARY
CYW43907
11. Pin Multiplexing
Table 14 shows the pin multiplexing functions.
Table 14. Pin Multiplexing
Pin
Function
2
3
GPIO_0
GPIO_0
1
UART0_RXD
I2C1_SDATA
PWM0
SPI1_MISO
PWM2
GPIO_12
GPIO_8
–
PWM4
USB20H_CTL
GPIO_1
GPIO_1
UART0_TXD
I2C1_CLK
PWM1
SPI1_CLK
PWM3
GPIO_13
GPIO_9
–
PWM5
–
GPIO_2
GPIO_2
–
–
GCI_GPIO_0
–
–
–
–
TCK
–
GPIO_3
GPIO_3
–
–
GCI_GPIO_1
–
–
–
–
TMS
–
–
GPIO_4
GPIO_4
–
–
GCI_GPIO_2
–
–
–
–
TDI
–
–
GPIO_5
GPIO_5
–
–
GCI_GPIO_3
–
–
–
–
TDO
–
–
GPIO_6
GPIO_6
–
GCI_GPIO_4
–
TRST_L
–
GPIO_7
GPIO_7
UART0_
RTS_OUT
PWM1
PWM3
SPI1_CS
GPIO_8
GPIO_8
SPI1_MISO
PWM2
PWM4
UART0_RXD
–
GPIO_9
GPIO_9
SPI1_CLK
PWM3
PWM5
UART0_TXD
–
GPIO_10
GPIO_10
SPI1_MOSI
PWM4
I2C1_SDATA
UART0_
CTS_IN
GPIO_11
GPIO_11
SPI1_CS
PWM5
I2C1_CLK
GPIO_12
GPIO_12
I2C1_SDATA
UART0_RXD
GPIO_13
GPIO_13
I2C1_CLK
GPIO_14
GPIO_14
GPIO_15
–
4
5
–
6
–
I2C1_CLK
7
8
–
10
GPIO_11
PMU_TEST_O
GPIO_16
GPIO_12
TAP_SEL_P
GPIO_0
GPIO_13
PWM0
GPIO_1
GPIO_14
PWM2
UART0_
RTS_OUT
PWM1
GPIO_7
GPIO_15
PWM3
SPI1_MISO
PWM2
PWM4
GPIO_8
GPIO_16
PWM0
UART0_TXD
SPI1_CLK
PWM3
PWM5
GPIO_9
GPIO_0
PWM1
PWM0
UART0_
CTS_IN
SPI1_MOSI
I2C1_SDATA
GPIO_10
–
PWM4
GPIO_15
PWM1
UART0_
RTS_OUT
SPI1_CS
I2C1_CLK
GPIO_11
GPIO_7
PWM5
GPIO_16
GPIO_16
UART0_
CTS_IN
PWM0
PWM2
SPI1_MOSI
GPIO_14
GPIO_10
RF_
DISABLE_L
–
SDIO_CLK
SDIO_CLK
SDIO_CMD
SDIO_CMD
SDIO_
DATA_0
SDIO_D0
SDIO_
DATA_1
SDIO_D1
SDIO_
DATA_2
SDIO_D2
–
–
I2C1_SDATA
GPIO_15
9
–
–
–
–
PWM5
I2C1_SDATA
PWM0
I2C1_CLK
PWM1
SDIO_SEP_INT SDIO_SEP_IN
T_0D
–
–
SDIO_SEP_INT SDIO_SEP_IN
_0D
T
–
–
–
–
–
–
–
–
–
–
SDIO_AOS_
CLK
–
–
–
–
–
–
–
–
SDIO_AOS_
CMD
–
–
–
–
–
–
–
–
SDIO_AOS_
D0
–
–
–
–
–
–
–
–
SDIO_AOS_
D1
–
–
–
–
–
–
–
–
SDIO_AOS_
D2
–
Document Number: 002-14829 Rev. *J
11
–
PWM2
PWM3
PWM4
–
–
–
–
–
Page 44 of 94
PRELIMINARY
CYW43907
Table 14. Pin Multiplexing
Pin
Function
1
2
3
4
5
6
7
8
9
11
–
–
–
–
SDIO_D3
–
–
–
–
–
–
–
RF_SW_
CTRL_5
RF_SW_
CTRL_5
GCI_GPIO_5
–
–
–
–
–
–
–
RF_SW_
CTRL_6
RF_SW_
CTRL_6
UART_
DBG_RXa
SECI_IN a
–
–
–
–
–
–
RF_SW_
CTRL_7
RF_SW_
CTRL_7
UART_
DBG_TX a
SECI_OUT a
–
–
–
–
–
–
RF_SW_
CTRL_8
RF_SW_
CTRL_8
SECI_IN a
UART_
DBG_RX a
–
–
–
–
–
–
RF_SW_
CTRL_9
RF_SW_
CTRL_9
SECI_OUT a
UART_
DBG_TX a
–
–
–
–
–
–
PWM0
PWM0
GPIO_2
GPIO_18
–
–
–
–
–
–
–
–
PWM1
PWM1
GPIO_3
GPIO_19
–
–
–
–
–
–
–
–
PWM2
PWM2
GPIO_4
GPIO_20
–
–
–
–
–
–
–
–
PWM3
PWM3
GPIO_5
GPIO_21
–
–
–
–
–
–
–
–
PWM4
PWM4
GPIO_6
GPIO_22
–
–
–
–
–
–
–
–
PWM5
PWM5
GPIO_8
GPIO_23
–
–
–
–
–
–
–
–
SPI0_MISO
SPI0_MISO
GPIO_17
GPIO_24
–
–
–
–
–
–
–
–
SPI0_CLK
SPI0_CLK
GPIO_18
GPIO_25
–
–
–
–
–
–
–
–
SPI0_MOSI
SPI0_MOSI
GPIO_19
GPIO_26
–
–
–
–
–
–
–
–
SPI0_CS
SPI0_CS
GPIO_20
GPIO_27
–
–
–
–
–
–
–
–
I2C0_SDATA
I2C0_SDATA
GPIO_21
GPIO_28
–
–
–
–
–
–
–
–
I2C0_CLK
I2C0_CLK
GPIO_22
GPIO_29
–
–
–
–
–
–
–
–
I2S_MCLK0
I2S_MCLK0
GPIO_23
GPIO_0
–
–
–
–
–
–
–
–
2S_SCLK0
I2S_SCLK0
GPIO_24
GPIO_2
–
–
–
–
–
–
–
–
2S_LRCLK0
I2S_LRCLK0
GPIO_25
GPIO_3
–
–
–
–
–
–
–
–
I
I
Document Number: 002-14829 Rev. *J
SDIO_AOS_
D3
10
SDIO_
DATA_3
–
–
–
–
–
–
–
–
Page 45 of 94
PRELIMINARY
CYW43907
Table 14. Pin Multiplexing
Function
Pin
3
4
5
6
7
8
9
GPIO_26
GPIO_4
–
–
–
–
–
–
DATAI0
I2S_
SDATAI0
I2S_
SDATAO0
I2S_
SDATAO0
GPIO_27
GPIO_5
–
–
–
–
–
–
I2S_
SDATAO1
I2S_
SDATAO1
GPIO_28
GPIO_6
–
–
–
–
–
–
I2S_SDATAI1 I2S_SDATAI1 GPIO_29
GPIO_8
–
–
–
–
–
–
–
–
I2S_S
1
2
10
–
–
–
11
–
–
–
I2S_MCLK1
I2S_MCLK1
GPIO_30
GPIO_17
–
–
–
–
–
–
–
–
I2S_SCLK1
I2S_SCLK1
GPIO_31
GPIO_30
–
–
–
–
–
–
–
–
I2S_LRCLK1
I2S_LRCLK1
GPIO_0
GPIO_31
–
–
–
–
–
–
–
–
a. UART_DBG_TX and UART_DBG_RX are for UART1 mentioned in section 5.10 and in the reference schematics. SECI_IN and SECI_OUT are for UART2 mentioned in section 5.10 and
in the reference schematics.
Document Number: 002-14829 Rev. *J
Page 46 of 94
PRELIMINARY
CYW43907
12. I/O States
Table 15 provides I/O state information for the signals listed.
The following notations are used in Table 15:
■
I: Input signal
■
O: Output signal
■
I/O: Input/Output signal
■
PU = Pulled up
■
PD = Pulled down
■
NoPull = Neither pulled up nor pulled down
Table 15. I/O States
Low Power State/Sleep (All Power
Present)
Powerdownb(REG_ON
Held Low)
Out-of-Reset; Before Power
Software Download
Rail
(REG_ON High)
Ball Name
I/O
Keepera
HIB_REG_ON_IN
I
N
Input; PD (Pull-down can be disabled.) Input; PD (Pull-down can be disabled.) Input
REG_ON
I
N
Input; PD (Pull-down can be disabled.) Input; PD (Pull-down can be disabled.) Input; PD (of 200 kΩ) Input; PD (of 200 kΩ)
CLK_REQ
I/O
Y
Open drain or push-pull (programmable). Active high.
Open drain or push-pull (programmable). Active high.
High-Z, NoPull
Open drain; active
high
VDDO
GPIO_0
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
GPIO_1
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_2
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_3
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
GPIO_4
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_5
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
Active Mode
Document Number: 002-14829 Rev. *J
Input
–
–
Page 47 of 94
PRELIMINARY
CYW43907
Table 15. I/O States
Low Power State/Sleep (All Power
Present)
Powerdownb(REG_ON
Held Low)
Out-of-Reset; Before Power
Software Download
Rail
(REG_ON High)
I/O
Keepera
GPIO_6
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_7
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_8
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
GPIO_9
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
GPIO_10
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_11
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
Input/Output; PU, PD, or NoPull
(programmable [Default: PD])
High-Z, NoPull
Input; PD
VDDIO
GPIO_12
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_13
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_14
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_15
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
GPIO_16
I/O
Y
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
Input/Output; PU, PD, or NoPull
(programmable [Default: NoPull])
High-Z, NoPull
Input; NoPull
VDDIO
RF_SW_CTRL
(0 to 9)
I/O
Y
Output; NoPull
Output; NoPull
High-Z
Output; NoPull
VDDIO
_RF
Ball Name
Active Mode
a. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in power-down state. If there is no keeper, and it is an input and there is NoPull, then the
pad should be driven to prevent leakage due to floating pad (WL_REG_ON, for example).
b. In the power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied.
Document Number: 002-14829 Rev. *J
Page 48 of 94
PRELIMINARY
CYW43907
13. Electrical Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
13.1 Absolute Maximum Ratings
Caution! The absolute maximum ratings in Table 16 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief
duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term
reliability of the device.
Table 16. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC supply for VBAT and PA driver supply a
VBAT
–0.5 to +5.5
V
DC supply voltage for digital I/O
VDDIO
–0.5 to 3.9
V
DC supply voltage for I2S I/O
VDDIO_I2S
–0.5 to 3.9
V
DC supply voltage for RF switch I/O
VDDIO_RF
–0.5 to 3.9
V
DC supply voltage for Ethernet I/O
VDDIO_RMII
–0.5 to 3.9
V
DC supply voltage for SDIO I/O
VDDIO_SD
–0.5 to 3.9
V
DC input supply voltage for CLDO, LNLDO, and BBPLL LDOb
–0.5 to 1.575
V
3.3V DC supply for USB
USB2_AVDD33
USB2_AVDD33LDO
USB2_AVDD33IO
–
–0.5 to 3.9
V
3.3V DC supply voltage for RF analogc
VDD3P3RF
–0.5 to 3.6
V
1.35V DC supply voltage for RF analogd
VDD1P35RF
–0.5 to 1.5
V
1.2V DC supply voltage for RF analoge
VDD1P2RF
–0.5 to 1.26
V
1.2V DC supply voltage for analog circuitsf
VDD1P2A
–0.5 to 1.26
V
DC supply voltage for the coreg
VDDC
–0.5 to 1.32
V
DC supply voltage for OTP memory
OTP_VDD3P3
–0.5 to 3.9
V
Maximum undershoot voltage for I/O
Vundershoot
–0.5
V
Maximum junction temperature
Tj
125
°C
a. For the SR_VDDBAT5V and LDO_VDDBAT5V supplies.
b. For the LDO_VDD1P5 and WRF_XTAL_VDD1P35 supplies.
c. For the WRF_SYNTH_VDD3P3, WRF_PA_VDD3P3, and WRF_TXMIX_VDD supplies.
d. For WRF_PMU_VDD1P35 and WRF_AFE_VDD1P35 supplies.
e. For the WRF_SYNTH_VDD1P2 supply.
f. For the AVDD1P2_AUDIO, AVDD1P2, and HSIC_AVDD12 supplies.
g. For the VDD, HSIC_DVDD12, and HSIC2_DVDD2 supplies.
Document Number: 002-14829 Rev. *J
Page 49 of 94
PRELIMINARY
CYW43907
13.2 Environmental Ratings
The environmental ratings are shown in Table 17.
Table 17. Environmental Ratings
Characteristic
Value
Units
Conditions/Comments
Ambient temperature (TA)
–30 to +85
°C
Storage temperature
–40 to +125
°C
Less than 60
%
Storage
Less than 85
%
Operation
Relative humidity
Functional operation
–
13.3 Electrostatic Discharge Specifications
Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 18. ESD Specifications
Pin Type
Symbol
Condition
ESD
Rating
Unit
ESD
ESD_HAND_HBM
Human body model contact discharge per JEDEC EID/
JESD22-A114
1.5 k
V
CDM
ESD_HAND_CDM
Charged device model contact discharge per JEDEC EIA/
JESD22-C101
250
V
13.4 Recommended Operating Conditions and DC Characteristics
Caution! Functional operation is not guaranteed outside of the limits shown in Table 19. Operation outside these limits for extended
periods can adversely affect long-term reliability of the device.
Table 19. Recommended Operating Conditions and DC Characteristics
Parameter
DC supply voltage for VBAT
DC supply voltage for digital I/O
DC supply voltage for
I2S
I/O
Symbol
Value
Maximum
Unit
Minimum
Typical
VBAT
2.3a
3.6
4.8
V
VDDIO
1.71
–
3.63
V
VDDIO_I2S
1.71
–
3.63
V
DC supply voltage for RF switch I/Os
VDDIO_RFb
3.13
3.3
3.6
V
DC supply voltage for Ethernet I/O
VDDIO_RMII
1.71
–
3.63
V
VDDIO_SD
1.71
–
3.63
V
–
1.3
1.35
1.5
V
USB2_AVDD33
USB2_AVDD33LDO
USB2_AVDD33IO
2.97
3.3
3.63
V
3.3V DC supply voltage for RF analog
VDD3P3RFc
3
3.3
3.45
V
1.35V DC supply voltage for RF analog
VDD1P35RFc
1.3
1.35
1.5
V
1.2V DC supply voltage for RF analog
VDD1P2RFc
1.1
1.2
1.26
V
DC supply voltage for SDIO I/O
DC input supply voltage for CLDO, LNLDO, and BBPLL
LDO
3.3V DC supply for USB
1.2V DC supply voltage for analog
DC supply voltage for core
DC supply voltage for OTP memory
DC supply voltage for TCXO input buffer
Document Number: 002-14829 Rev. *J
VDD1P2Ac
1.1
1.2
1.26
V
VDDC
1.14
1.2
1.26
V
OTP_VDD3P3b
2.97
3.3
3.63
V
WRF_TCXO_VDDc
1.62
1.8
1.98
V
Page 50 of 94
PRELIMINARY
CYW43907
Table 19. Recommended Operating Conditions and DC Characteristics (Cont.)
Parameter
Value
Symbol
Internal POR threshold
Vth_POR
Unit
Minimum
Typical
Maximum
0.4
–
0.7
V
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage
VIH
1.27
–
–
V
Input low voltage
VIL
–
–
0.58
V
Output high voltage @ 2 mA
VOH
1.40
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.45
V
Input high voltage
VIH
0.625 ×
VDDIO
–
–
V
Input low voltage
VIL
–
–
0.25 ×
VDDIO
V
Output high voltage @ 2 mA
VOH
0.75 × VDDIO
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.125 ×
VDDIO
V
0.65 × VDDIO
–
–
V
V
For VDDIO_SD = 3.3V:
Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage
VIH
VIL
–
–
0.35 ×
VDDIO
Output high voltage @ 2 mA
VOH
VDDIO – 0.45
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.45
V
Input high voltage
VIH
2.00
–
–
V
Input low voltage
VIL
–
–
0.80
V
Output high voltage @ 2 mA
VOH
VDDIO – 0.4
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.40
V
Input low voltage
For VDDIO = 3.3V:
RF Switch Control Output Pins
d
For VDDIO_RF = 3.3V:
Output high voltage @ 2 mA
VOH
VDDIO – 0.4
–
–
V
Output low voltage @ 2 mA
VOL
–
–
0.40
V
Input capacitance
CIN
–
–
5
pF
a. The CYW43907 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only
for 3V < VBAT < 4.8V.
b. VDD3P3RF, which is an internally generated supply, can drive this node. There is sufficient current and the appropriate state is maintained
during hibernation and sleep cycles.
c. Internally generated supply.
d. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.
Document Number: 002-14829 Rev. *J
Page 51 of 94
PRELIMINARY
CYW43907
13.5 Power Supply Segments
The digital I/O's are placed in physical segments. The supply voltage for each segment can be independently selected.
Table 20 shows the power supply segments and the I/O pins associated with each segment.
Table 20. Power Supply Segments
Power Supply
Segment
Pins
VDDIO
CLK_REQ, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, GPIO_8, GPIO_9,
GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, GPIO_15, GPIO_16, I2C0_CLK, I2C0_SDATA, I2C1_CLK,
I2C1_SDATA, JTAG_SEL, PWM0, PWM1, PWM2, PWM3, PWM4, PWM5, SFL_CLK, SFL_CS, SFL_IO0,
SFL_IO1, SFL_IO2, SFL_IO3, SPI0_CLK, SPI0_CS, SPI0_MISO, SPI0_SISO, SPI1_CLK, SPI1_CS,
SPI1_MISO, SPI1_SISO, SRSTN, UART0_CTS, UART0_RTS, UART0_RXD, UART0_TXD, USB2_DSEL
VDDIO_I2S
I2S_LRCLK0, I2S_LRCLK1, I2S_MCLK0, I2S_MCLK1, I2S_SCLK0, I2S_SCLK1, I2S_SDATAI0, I2S_SDATAI1,
I2S_SDATAO0, I2S_SDATAO1
VDDIO_RF
RF_SW_CTRL_0, RF_SW_CTRL_1, RF_SW_CTRL_2, RF_SW_CTRL_3, RF_SW_CTRL_4, RF_SW_CTRL_5,
RF_SW_CTRL_6, RF_SW_CTRL_7, RF_SW_CTRL_8, RF_SW_CTRL_9
VDDIO_RMII
RMII_G_COL, RMII_G_CRS, RMII_G_RXC, RMII_G_RXD0, RMII_G_RXD1, RMII_G_RXD2, RMII_G_RXD3,
RMII_G_RXDV, RMII_G_TXC, RMII_G_TXD0, RMII_G_TXD1, RMII_G_TXD2, RMII_G_TXD3, RMII_G_TXEN,
RMII_MDC, RMII_MDIO
13.6 Ethernet MAC Controller (MII/RMII) DC Characteristics
Table 21. MII Recommended Operating Condition
Parameter
Supply voltage
Symbol
GMAC_VDDIO (MII/RMII)
Minimum
Maximum
Units
3.14
3.47
V
13.7 GPIO, UART, and JTAG Interfaces DC Characteristics
Table 22. GPIO, UART, and JTAG Interfaces
Parameter
Symbol
Minimum
Maximum
Units
Conditions
Logic input high voltage
VIH
2.0
VDDIO + 0.5
V
–
Logic input low voltage
VIL
–0.5
0.8
V
–
Logic output high voltage
VOH
2.4
–
V
–
Logic output low voltage
VOL
–
0.4
V
–
Document Number: 002-14829 Rev. *J
Page 52 of 94
PRELIMINARY
CYW43907
14. WLAN RF Specifications
14.1 Introduction
The CYW43907 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section
describes the RF characteristics of the 2.4 GHz and 5 GHz radio.
Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results.
Unless otherwise stated, limit values apply for the conditions specified in Table 17: “Environmental Ratings” and
Table 19: “Recommended Operating Conditions and DC Characteristics”. Typical values apply for the following conditions:
■
VBAT = 3.6V
■
Ambient temperature +25°C
Figure 16. Port Locations for WLAN Testing
Chip Output Port
CYW43907
2.4 GHz WLAN TX
(WRF_PAOUT_2G)
2.4 GHz WLAN RX
(WRF_RFIN_2G)
Chip Input Port
Diplexer
Chip Output Port
5 GHz WLAN TX
(WRF_PAOUT_5G)
RF Port
TR Switch
5 GHz WLAN RX
(WRF_RFIN_5G)
Chip Input Port
14.2 2.4 GHz Band General RF Specifications
Table 23. 2.4 GHz Band General RF Specifications
Minimum
Typical
Maximum
Unit
TX/RX switch time
Item
Including TX ramp down
–
–
5
µs
RX/TX switch time
Including TX ramp up
–
–
2
µs
Power-up and power-down ramp time
DSSS/CCK
modulations
–
–
<2
µs
Document Number: 002-14829 Rev. *J
Condition
Page 53 of 94
PRELIMINARY
CYW43907
14.3 WLAN 2.4 GHz Receiver Performance Specifications
Note: The specifications shown in Table 24 apply at the chip ports, unless otherwise defined.
Table 24. WLAN 2.4 GHz Receiver Performance Specifications
Parameter
Condition/Notes
Minimum
–
Frequency range
1 Mbps DSSS
2 Mbps DSSS
RX sensitivity IEEE 802.11b
(8% PER for 1024 octet PSDU) 5.5 Mbps DSSS
RX sensitivity IEEE 802.11g
(10% PER for 1024 octet
PSDU)
Typical
Maximum
Unit
2400
–
2500
MHz
–
–98.9
–
dBm
–
–96.0
–
dBm
–
–93.9
–
dBm
11 Mbps DSSS
–
–90.4
–
dBm
6 Mbps OFDM
–
–95.0
–
dBm
9 Mbps OFDM
–
–93.8
–
dBm
12 Mbps OFDM
–
–92.7
–
dBm
18 Mbps OFDM
–
–90.3
–
dBm
24 Mbps OFDM
–
–87.1
–
dBm
36 Mbps OFDM
–
–83.6
–
dBm
48 Mbps OFDM
–
–79.3
–
dBm
54 Mbps OFDM
–
–78.0
–
dBm
MCS0
–
–94.6
–
dBm
MCS1
–
–92.1
–
dBm
MCS2
–
–89.8
–
dBm
MCS3
–
–86.6
–
dBm
MCS4
–
–83.0
–
dBm
MCS5
–
–78.3
–
dBm
MCS6
–
–76.6
–
dBm
MCS7
–
–75.0
–
dBm
20 MHz channel spacing for all MCS rates
RX sensitivity IEEE 802.11n
(10% PER for 4096 octet
PSDU) a Defined for default
parameters: 800 ns GI and
non-STBC.
Input in-band IP3
Maximum receive level
@ 2.4 GHz
Maximum LNA gain
–
–8
–
dBm
Minimum LNA gain
–
+9
–
dBm
@ 1, 2 Mbps (8% PER, 1024 octets)
–3.5
–
–
dBm
@ 5.5, 11 Mbps (8% PER, 1024 octets)
–9.5
–
–
dBm
@ 6, 9, 12 Mbps (10% PER, 1024 octets)
–9.5
–
–
dBm
@ MCS0–2 rates (10% PER, 4095 octets)
–9.5
–
–
dBm
@ 18, 24, 36, 48, 54 Mbps (10% PER, 1024 octets)
–14.5
–
–
dBm
@ MCS3–7 rates
(10% PER, 4095 octets)
–14.5
–
–
dBm
Adjacent channel rejection1 Mbps DSSS
DSSS
(Difference between interfering 2 Mbps DSSS
and desired signal at 8% PER
for 1024 octet PSDU with
desired signal level as
5.5 Mbps DSSS
specified in Condition/Notes.)
11 Mbps DSSS
Document Number: 002-14829 Rev. *J
Desired and interfering signal 30 MHz apart
–74 dBm
35
–
–
dB
–74 dBm
35
–
–
dB
Desired and interfering signal 25 MHz apart
–70 dBm
35
–
–
dB
–70 dBm
35
–
–
dB
Page 54 of 94
PRELIMINARY
CYW43907
Table 24. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Adjacent channel rejectionOFDM
(Difference between interfering
and desired signal (25 MHz
apart) at 10% PER for 1024
octet PSDU with desired signal
level as specified in Condition/
Notes.)
Adjacent channel rejection
MCS0–7
(Difference between interfering
and desired signal (25 MHz
apart) at 10% PER for 4096
octet PSDU with desired signal
level as specified in Condition/
Notes.)
Condition/Notes
Minimum
Typical
Maximum
Unit
6 Mbps OFDM
–79 dBm
16
–
–
dB
9 Mbps OFDM
–78 dBm
15
–
–
dB
12 Mbps OFDM
–76 dBm
13
–
–
dB
18 Mbps OFDM
–74 dBm
11
–
–
dB
24 Mbps OFDM
–71 dBm
8
–
–
dB
36 Mbps OFDM
–67 dBm
4
–
–
dB
48 Mbps OFDM
–63 dBm
0
–
–
dB
54 Mbps OFDM
–62 dBm
–1
–
–
dB
MCS0
–79 dBm
16
–
–
dB
MCS1
–76 dBm
13
–
–
dB
MCS2
–74 dBm
11
–
–
dB
MCS3
–71 dBm
8
–
–
dB
MCS4
–67 dBm
4
–
–
dB
MCS5
–63 dBm
0
–
–
dB
MCS6
–62 dBm
–1
–
–
dB
MCS7
–61 dBm
–2
–
–
dB
Maximum receiver gain
–
–
–
66
–
dB
Gain control step
–
–
–
3
–
dB
–5
–
5
dB
Range above –30 dBm
–8
–
8
dB
Return loss
Zo = 50Ω, across the dynamic range
10
11.5
13
dB
Receiver cascaded noise
figure
At maximum gain
–
4
–
dB
RSSI accuracyb
Range
–95c
dBm to –30 dBm
a. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.
b. The minimum and maximum values shown have a 95% confidence level.
c. –95 dBm with calibration at time of manufacture, –92 dBm without calibration.
Document Number: 002-14829 Rev. *J
Page 55 of 94
PRELIMINARY
CYW43907
14.4 WLAN 2.4 GHz Transmitter Performance Specifications
Note: Unless otherwise noted, the values shown in Table 25 apply at the chip ports.
Table 25. WLAN 2.4 GHz Transmitter Performance Specifications
Parameter
Condition/Notes
Minimum
–
Frequency range
RF port TX power EVMa
(highest power setting, 25°C, and
VBAT = 3.6)
OFDM EVMb
(25°C, VBAT = 3.6V)
Phase noise
Unit
2400
–
2500
MHz
–
20.5
–
dBm
–9 dB
OFDM, BPSK
–8 dB
–
20
–
dBm
OFDM, QPSK
–13 dB
–
20
–
dBm
OFDM, 16-QAM
–19 dB
–
19
–
dBm
OFDM, 64-QAM (R = 3/4) –25 dB
–
19
–
dBm
OFDM, 64-QAM (MCS7,
HT20)
–27 dB
–
18.5
–
dBm
OFDM, BPSK
5 dBm
–29
–31
–
dB
OFDM, 64-QAM
5 dBm
–31
–33
–
dB
MCS7
5 dBm
–33
–35
–
dB
37.4 MHz crystal, integrated from 10 kHz to
10 MHz
–
0.45
–
Degrees
–
10
–
–
dB
Across full temperature and voltage range.
Applies to 10 dBm to 20 dBm output power
range.
–
–
±1.5
dB
–
15
–
–
dBc
–
–
0.25
–
dB
–
6
–
dB
Carrier suppression
Gain control step
Return loss at Chip port TX
Maximum
DSS/CCK
TX power control dynamic range
Closed-loop TX power variation at
highest power level setting
Typical
Zo = 50Ω
a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power).
The ratio (dB) in the Conditions/Notes column is the EVM.
b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/Notes column is the TX power
specification in dBm.
Document Number: 002-14829 Rev. *J
Page 56 of 94
PRELIMINARY
CYW43907
14.5 WLAN 5 GHz Receiver Performance Specifications
Note: Unless otherwise noted, the values shown in Table 26 apply at the chip ports.
Table 26. WLAN 5 GHz Receiver Performance Specifications
Parameter
Condition/Notes
Minimum
–
Frequency range
RX sensitivity a IEEE 802.11a (10%
PER for 1000 octet PSDU)
Typical
Maximum
Unit
4900
–
5845
MHz
6 Mbps OFDM
–
–93.6
–
dBm
9 Mbps OFDM
–
–92.4
–
dBm
12 Mbps OFDM
–
–91.3
–
dBm
18 Mbps OFDM
–
–88.9
–
dBm
24 Mbps OFDM
–
–85.7
–
dBm
36 Mbps OFDM
–
–82.3
–
dBm
48 Mbps OFDM
–
–77.9
–
dBm
54 Mbps OFDM
–
–76.6
–
dBm
MCS0
–
–93.2
–
dBm
MCS1
–
–90.7
–
dBm
MCS2
–
–88.4
–
dBm
MCS3
–
–85.2
–
dBm
MCS4
–
–81.6
–
dBm
MCS5
–
–76.9
–
dBm
MCS6
–
–75.2
–
dBm
MCS7
–
–73.6
–
dBm
MCS0
–
–90.3
–
dBm
MCS1
–
–87.5
–
dBm
MCS2
–
–84.9
–
dBm
MCS3
–
–81.8
–
dBm
MCS4
–
–78.3
–
dBm
MCS5
–
–73.9
–
dBm
MCS6
–
–72.7
–
dBm
MCS7
–
–71.2
–
dBm
Maximum LNA gain
–
–12
–
dBm
20 MHz channel spacing for all MCS rates
RX sensitivity a IEEE 802.11n (10%
PER for 4096 octet PSDU)
Defined for default parameters:
800 ns GI and non-STBC.
40 MHz channel spacing for all MCS rates
RX sensitivity a IEEE 802.11n (10%
PER for 4096 octet PSDU)
Defined for default parameters:
800 ns GI and non-STBC.
Input in-band IP3
Maximum receive level @ 5 GHz
Document Number: 002-14829 Rev. *J
Minimum LNA gain
–
+4
–
dBm
@ 6, 9, 12 Mbps (10% PER, 1024 octets)
–9.5
–
–
dBm
@ MCS0–2 rates (10% PER, 4095 octets)
–9.5
–
–
dBm
@ 18, 24, 36, 48, 54 Mbps (10% PER, 1024
octets)
–14.5
–
–
dBm
@ MCS3–7 rates (10% PER, 4095 octets)
–14.5
–
–
dBm
Page 57 of 94
PRELIMINARY
CYW43907
Table 26. WLAN 5 GHz Receiver Performance Specifications (Cont.)
Parameter
Adjacent channel rejection
(Difference between interfering and
desired signal (20 MHz apart) at 10%
PER for 1000 octet PSDU with desired
signal level as specified in Condition/
Notes)
Alternate adjacent channel rejection
(Difference between interfering and
desired signal (40 MHz apart) at 10%
PER for 1000b octet PSDU with
desired signal level as specified in
Condition/Notes)
Condition/Notes
Minimum
Typical
Maximum
Unit
6 Mbps OFDM
–79 dBm
16
–
–
dB
9 Mbps OFDM
–78 dBm
15
–
–
dB
12 Mbps OFDM
–76 dBm
13
–
–
dB
18 Mbps OFDM
–74 dBm
11
–
–
dB
24 Mbps OFDM
–71 dBm
8
–
–
dB
36 Mbps OFDM
–67 dBm
4
–
–
dB
48 Mbps OFDM
–63 dBm
0
–
–
dB
54 Mbps OFDM
–62 dBm
–1
–
–
dB
65 Mbps OFDM
–61 dBm
–2
–
–
dB
6 Mbps OFDM
–78.5 dBm
32
–
–
dB
9 Mbps OFDM
–77.5 dBm
31
–
–
dB
12 Mbps OFDM
–75.5 dBm
29
–
–
dB
18 Mbps OFDM
–73.5 dBm
27
–
–
dB
24 Mbps OFDM
–70.5 dBm
24
–
–
dB
36 Mbps OFDM
–66.5 dBm
20
–
–
dB
48 Mbps OFDM
–62.5 dBm
16
–
–
dB
54 Mbps OFDM
–61.5 dBm
15
–
–
dB
65 Mbps OFDM
–60.5 dBm
14
–
–
dB
Maximum receiver gain
–
–
66
–
dB
Gain control step
–
–
3
–
dB
Range –92 dBm to –30 dBm
–5
–
5
dB
Range above –30 dBm
–8
–
8
dB
Return loss
Zo = 50Ω, across the dynamic range
10
–
13
dB
Receiver cascaded noise figure
At maximum gain
–
5
–
dB
RSSI accuracyc
a. For PCIE derate the 5 GHz RX sensitivity by 1.5 dB
b. For 65 Mbps, the size is 4096.
c. The minimum and maximum values shown have a 95% confidence level.
Document Number: 002-14829 Rev. *J
Page 58 of 94
PRELIMINARY
CYW43907
14.6 WLAN 5 GHz Transmitter Performance Specifications
Note: Unless otherwise noted, the values shown in Table 27 apply at the chip ports.
Table 27. WLAN 5 GHz Transmitter Performance Specifications
Parameter
Condition/Notes
Minimum
–
Frequency range
RF port TX power EVMa
(highest power setting, 25°C, and
VBAT = 3.6)
OFDM EVMb
(25°C, VBAT = 3.6V)
Typical
Maximum
Unit
4900
–
5845
MHz
OFDM, QPSK
–13 dB
–
20
–
dBm
OFDM, 16-QAM
–19 dB
–
18.5
–
dBm
OFDM, 64-QAM (R –25 dB
= 3/4)
–
17
–
dBm
OFDM, 64-QAM
(MCS7, HT20)
–
16.5
–
dBm
–27 dB
OFDM, BPSK
0 dBm
–
–30
–
dB
OFDM,64-QAM
0 dBm
–
–33
–
dB
MCS7
0 dBm
–
–34
–
dB
37.4 MHz Crystal, Integrated from 10 kHz
to 10 MHz
–
0.5
–
Degrees
TX power control dynamic range
–
10
–
–
dB
Closed loop TX power variation at
highest power level setting
Across full-temperature and voltage range.
Applies across 10 to 20 dBm output power
range.
–
–
±2.0
dB
–
15
–
–
dBc
–
–
0.25
–
dB
–
6
–
dB
Phase noise
Carrier suppression
Gain control step
Return loss
Zo = 50Ω
a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power).
The ratio (dB) in the Conditions/Notes column is the EVM.
b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/Notes column is the TX power
specification in dBm.
14.7 General Spurious Emissions Specifications
This section provides the TX and RX spurious emissions specifications for the WLAN 2.4 GHz and 5 GHz bands. The recommended
spectrum analyzer settings for the spurious emissions specifications are provided in Table 28.
Table 28. Recommended Spectrum Analyzer Settings
Parameter
Setting
Resolution bandwidth (RBW)
1 MHz
Video bandwidth (VBW)
1 MHz
Sweep
Span
Auto
100 MHz
Detector
Maximum peak
Trace
Maximum hold
Modulation
Document Number: 002-14829 Rev. *J
OFDM
Page 59 of 94
PRELIMINARY
CYW43907
14.7.1 Transmitter Spurious Emissions Specifications
2.4 GHz Band Spurious Emissions
20-MHz Channel Spacing
Table 29. 2.4 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications
2G - 20 MHz BW
Spurious Emissions Level (dBm)
Emissions Frequency Range (MHz)
Channel Power (dBm)
CH2442
1000-2000
21
–50
2000-2400
21
–40
2500-3000
21
–40
3000-4000
21
–39
4000-5000
21
–24
5000-6000
21
–48
6000-7000
21
–49
7000-8000
21
–13
8000-10000
21
–43
10000-12000
21
–52
12000-15000
21
–50
15000-20000
21
–49
5 GHz Band Spurious Emissions
20-MHz Channel Spacing
Table 30. 5 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications
5G - 20 MHz BW
Spurious Emissions Level (dBm)
Emissions Frequency Range (MHz) Channel Power (dBm)
CH5180
CH5500
CH5825
1000-2000
19
–50
–51
–50
2000-3000
19
–48
–48
–49
3000-4000
19
–42
–43
–40
4000-5000
19
–42
–46
–48
5000-6000
19
–41
–40
–40
6000-7000
19
–48
–49
–47
7000-8000
19
–50
–49
–49
8000-10000
19
–53
–52
–53
10000-12000
19
–10
–13
–17
12000-15000
19
–51
–51
–51
15000-20000
19
–19
–19
–20
Document Number: 002-14829 Rev. *J
Page 60 of 94
PRELIMINARY
CYW43907
40-MHz Channel Spacing
Table 31. 5 GHz Band, 40-MHz Channel Spacing TX Spurious Emissions Specifications
5G - 40 MHz BW
Emissions Frequency
Range (MHz)
Spurious Emissions Level (dBm)
Channel Power (dBm)
CH5190m
CH5510m
CH5795m
1000-2000
19
–50
–52
–52
2000-3000
19
–49
–50
–49
3000-4000
19
–43
–42
–39
4000-5000
19
–42
–44
–48
5000-6000
19
–40
–40
–38
6000-7000
19
–48
–48
–48
7000-8000
19
–49
–48
–48
8000-10000
19
–52
–53
–53
10000-12000
19
–12
–15
–19
12000-15000
19
–51
–51
–51
15000-20000
19
–24
–22
–24
14.7.2 Receiver Spurious Emissions Specifications
Table 32. 2G and 5G General Receiver Spurious Emissions
Band
2G
5G
Frequency Range
Typical
Maximum
Unit
2.4 GHz < f < 2.5 GHz
–75.5
–74.1
dBm
3.6 GHz < f < 3.8 GHz
–52.8
–50.9
dBm
5150 MHz < f < 5850 MHz
–57.7
–56.1
dBm
3.45 GHz < f < 3.9 GHz
–48.6
–47.6
dBm
Document Number: 002-14829 Rev. *J
Page 61 of 94
PRELIMINARY
CYW43907
15. Internal Regulator Electrical Specifications
15.1 Core Buck Switching Regulator
Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Note: Functional operation is not guaranteed outside of the specification limits provided in this section.
Table 33. Core Buck Switching Regulator (CBUCK) Specifications
Specification
Notes
Input supply voltage (DC)
DC voltage range inclusive of disturbances.
PWM mode switching frequency
CCM, load > 100 mA VBAT = 3.6V.
PWM output current
–
Output current limit
–
Min.
Typ.
Max.
Unit
3.0
3.6
4.8a
V
–
4
–
MHz
–
–
550
mA
–
1400
–
mA
Output voltage range
Programmable, 30 mV steps. Default = 1.35V.
1.2
1.35
1.5
V
PWM output voltage DC accuracy
Includes load and line regulation. Forced PWM mode.
–4
–
4
%
PWM ripple voltage, static
Measure with 20 MHz bandwidth limit.
Static load. Max. ripple based on VBAT = 3.6V, Vout = 1.35V,
Fsw = 4 MHz,
2.2 μH inductor with min. effective L > 1.05 μH,
cap. + board total – ESR < 20 mΩ,
Cout > 1.9 μF, ESL<200 pH
–
7
20
mVpp
PWM mode peak efficiency
Peak efficiency at 200 mA load.
78
86
–
%
PFM mode efficiency
10 mA load current.
70
81
–
%
Start-up time from power down
VIO already ON and steady. Time from REG_ON rising edge
to CLDO reaching 1.2V.
–
400
500
µs
External inductor
0806 size, 2.2 µH, DCR = 0.11Ω,
ACR = 1.18Ω @ 4 MHz.
–
2.2
–
µH
External output capacitor
Ceramic, X5R, 0402, ESR <30 mΩ at 4 MHz, 4.7 µF ±20%,
6.3V.
2.0b
4.7
10c
µF
External input capacitor
For SR_VDDBAT5V pin, ceramic, X5R, 0603, ESR < 30 mΩ
at 4 MHz, ±4.7 µF ±20%, 6.3V.
0.67b
4.7
–
µF
Input supply voltage ramp-up time
0 to 4.3V.
40
–
–
µs
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
c. Total capacitance includes those connected at the far end of the active load.
Document Number: 002-14829 Rev. *J
Page 62 of 94
PRELIMINARY
CYW43907
15.2 3.3V LDO (LDO3P3)
Table 34. LDO3P3 Specifications
Specification
Input supply voltage, Vin
Notes
Min.
Typ.
Max.
Units
Min. = Vo + 0.2V = 3.5V dropout voltage requirement
must be met under maximum load for performance
specifications.
3.0
3.6
4.8a
V
–
0.001
–
450
mA
Output current
Nominal output voltage, Vo
Default = 3.3V.
–
3.3
–
V
Dropout voltage
At max. load.
–
–
200
mV
Output voltage DC accuracy
Includes line/load regulation.
–5
–
+5
%
Quiescent current
No load.
–
–
85
µA
Line regulation
Vin from (Vo + 0.2V) to 4.8V, max. load.
–
–
3.5
mV/V
Load regulation
Load from 1 mA to 450 mA.
–
–
0.3
mV/mA
PSRR
Vin ≥ Vo + 0.2V, Vo = 3.3V, Co = 4.7 µF,
Max load, 100 Hz to 100 kHz.
20
–
–
dB
LDO turn-on time
Chip already powered up.
–
160
250
µs
External output capacitor, Co
Ceramic, X5R, 0402, (ESR: 5 mΩ–240 mΩ),
± 10%, 10V.
1.0b
4.7
10
µF
External input capacitor
For LDO_VDDBAT5V pin (shared with band gap)
ceramic, X5R, 0402, (ESR: 30mΩ–200 mΩ), ± 10%,
10V. Not needed if sharing 4.7 µF VBAT capacitor
with SR_VDDBAT5V.
–
4.7
–
µF
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-14829 Rev. *J
Page 63 of 94
PRELIMINARY
CYW43907
15.3 CLDO
Table 35. CLDO Specifications
Specification
Input supply voltage, Vin
Notes
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement
must be met under maximum load.
Output current
–
Min.
Typ.
Max.
Units
1.3
1.35
1.5
V
0.2
–
350
mA
Output voltage, Vo
Programmable in 10 mV steps. Default = 1.2.V.
0.95
1.2
1.26
V
Dropout voltage
At max. load.
–
–
150
mV
Output voltage DC accuracy
Includes line/load regulation.
–4
–
+4
%
No load.
–
26
–
µA
200 mA load.
–
2.48
–
mA
Vin from (Vo + 0.15V) to 1.5V, maximum load.
–
–
5
mV/V
Load from 1 mA to 300 mA.
–
0.02
0.05
mV/mA
Power down.
–
10
40
µA
6
µA
Quiescent current
Line regulation
Load regulation
Leakage current
Bypass mode.
–
2
PSRR
@1 kHz, Vin ≥ 1.35V, Co = 4.7 µF.
20
–
Start-up time of PMU
VIO up and steady. Time from the REG_ON rising edge to
the CLDO reaching 1.2V.
–
–
700
µs
LDO turn-on time
LDO turn-on time when the rest of the chip is up.
–
140
180
µs
3.76a
4.7
–
µF
–
1
2.2
µF
External output capacitor, Co
Total ESR: 5 mΩ–240 mΩ.
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
dB
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-14829 Rev. *J
Page 64 of 94
PRELIMINARY
CYW43907
15.4 LNLDO
Table 36. LNLDO Specifications
Specification
Input supply voltage, Vin
Notes
Min.
Typ.
Max.
Units
Min. VIN = VO + 0.15V = 1.35V (where VO = 1.2V)dropout
voltage requirement must be met under maximum load.
1.3
1.35
1.5
V
–
0.1
–
150
mA
Output current
Output voltage, Vo
Programmable in 25 mV steps. Default = 1.2V.
1.1
1.2
1.275
V
Dropout voltage
At maximum load.
–
–
150
mV
Includes line/load regulation.
–4
–
+4
%
No load.
–
44
–
µA
Output voltage DC accuracy
Quiescent current
Max. load.
–
970
990
µA
Line regulation
Vin from (Vo + 0.1V) to 1.5V, 150 mA load.
–
–
5
mV/V
Load regulation
Load from 1 mA to 150 mA.
–
0.02
0.05
mV/mA
Leakage current
Power-down.
–
–
10
µA
Output noise
@30 kHz, 60–150 mA load Co = 2.2 µF.
@100 kHz, 60–150 mA load Co = 2.2 µF.
–
–
60
35
nV/rt Hz nV/
rt Hz
PSRR
@ 1kHz, Input > 1.35V, Co= 2.2 µF, Vo = 1.2V.
20
–
–
dB
LDO turn-on time
LDO turn-on time when the rest of the chip is up.
–
140
180
µs
0.5a
2.2
4.7
µF
–
1
2.2
µF
External output capacitor, Co
Total ESR (trace/capacitor): 5 mΩ–240 mΩ.
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ.
a. Minimum capacitor value refe rs to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-14829 Rev. *J
Page 65 of 94
PRELIMINARY
CYW43907
15.5 BBPLL LDO
Table 37. BBPLL LDO Specifications
Parameter
Min.
Typ.
Max.
Units
Input supply voltage, Vin
Min. Vin= Vo + 0.15V = 1.35V (for Vo = 1.2V).
The dropout voltage requirement must be met under
maximum load.
1.3
1.35
1.5
V
Output voltage, Vo
Programmable in 25 mV steps. Default = 1.2V.
1.1
1.2
1.275
V
Dropout voltage
At max. load
–
–
150
mV
Output voltage DC accuracy
Includes line/load regulation.
–4
–
+4
%
Output current
Peak load = 80 mA, average = 35 mA
Quiescent current
Conditions and Comments
0.1
–
55
mA
No load
–
10
12
µA
55 mA load
–
550
570
µA
Line regulation
Vin from (Vo + 0.15V) to 1.5V; 200 mA load
–
–
5
mV/V
Load regulation
load from 1mA to 200 mA; Vin ≥ (Vo + 0.15V)
–
0.025
0.045
mV/mA
Powered down. Junction temperature is 85°C.
–
5
20
µA
Bypass mode
–
0.2
1.5
µA
PSRR
@1 kHz, Vin ≥ Vo + 0.15V, Co = 4.7 µF
20
–
–
dB
Start-up time of PMU
VIO up and steady. Time from REG_ON rising edge to CLDO
reaching 99% of Vo.
–
530
700
us
Leakage current
LDO turn-on time
The LDO turn-on time when the rest of the chip is up.
–
140
180
us
Inrush current
Vin=Vo+0.15V to 1.5V, Co=0.47uF, no load
–
60
70
mA
External output capacitor, Co
Ceramic, X5R, size 0201, max. 6.3V, 20% tolerance
0.27
0.47
–
µF
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
–
1
–
µF
Document Number: 002-14829 Rev. *J
Page 66 of 94
PRELIMINARY
CYW43907
16. System Power Consumption
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
Note: Unless otherwise stated, these values apply for the conditions specified in Table 19: “Recommended Operating Conditions and
DC Characteristics”.
16.1 WLAN Current Consumption
The tables in this subsection show the typical, total current used by the CYW43907. Current values may be measured with the APPS
core powered off. The first column of the table, the mode description, will state the power condition of the APPS core.
16.1.1 2.4 GHz Mode
Table 38. 2.4 GHz Mode WLAN Current Consumption
VBAT = 3.6V a
(µA)
Mode
VDDIO =
VDDIO_HIB = 3.3V a, b, c
(µA)
Sleep Modes
Radio off
d
3
3
6
160
IEEE Power Save, DTIM=1, single RX, APPS powered down g
2180
160
IEEE Power Save, DTIM=3, single RX, APPS powered down h
680
160
IEEE Power Save, DTIM=9, single RX, APPS powered down
233
160
Continuous RX mode MCS7, HT20, 1SS, APPS powered up i, j
57,200
60
CRS-HT20, APPS powered up k
55,200
60
325,000
60
302,900
60
336,000
60
6
160
Sleep e, f
Active Modes
Continuous TX mode 1 Mbps, APPS powered up
l
Continuous TX mode MCS7, HT20, 1SS, 1 TX, APPS powered up m
Ping Modes
Ping to associated access point l
Sleep
a. Typical silicon.
b. VIO is specified with all pins idle (not switching) and not driving any loads.
c. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD.
d. REG_ON is low or the device is in hibernation, and all supplies are present.
e. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up.
f. Inter-beacon current.
g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
j. Measured using packet engine test mode.
k. Carrier sense (CCA) when no carrier present.
l. Duty cycle is 100%. TX power at chip output ~17.7 dBm.
m.Duty cycle is 100%. TX power at chip output ~15.2 dBm.
Document Number: 002-14829 Rev. *J
Page 67 of 94
PRELIMINARY
CYW43907
16.1.2 5 GHz Mode
Table 39. 5 GHz Mode WLAN Current Consumption
Mode
VBAT = 3.6V a
(µA)
VDDIO = VDDIO_HIB =
3.3V a, b, c
(µA)
3
3
Sleep Modes
Radio off d
Sleep
e, f
6
160
1390
160
IEEE Power Save, DTIM=3, single RX, APPS powered down h
470
160
IEEE Power Save, DTIM=9, single RX, APPS powered down
160
160
Continuous RX mode MCS7, HT20, 1SS, APPS powered up i, j
72,400
60
i, j
84,700
60
70,200
60
IEEE Power Save, DTIM=1, single RX, APPS powered down g
Active Modes
Continuous RX mode MCS7, HT40, 1SS, APPS powered up
CRS-HT20, APPS powered up k
CRS-HT40, APPS powered up
k
79,500
60
Continuous TX mode MCS7, HT20, 1SS, 1 TX, APPS powered up l
312,000
60
Continuous TX mode MCS7, HT40, 1SS, 1 TX, APPS powered up m
309,000
60
Ping Modes
Ping to associated access point l
327,000
60
6
160
Sleep
a. Typical silicon.
b. VIO is specified with all pins idle (not switching) and not driving any loads.
c. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD.
d. REG_ON is low or the device is in hibernation, and all supplies are present.
e. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up.
f. Inter-beacon current.
g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
j. Measured using packet engine test mode.
k. Carrier sense (CCA) when no carrier present.
l. Duty cycle is 100%. TX power at chip output ~13.9 dBm.
m.Duty cycle is 100%. TX power at chip output ~12.9 dBm.
Document Number: 002-14829 Rev. *J
Page 68 of 94
PRELIMINARY
CYW43907
17. Interface Timing and AC Characteristics
17.1 Ethernet MAC (MII/RMII) Interface Timing
17.1.1 MII Receive Packet Timing
Figure 17 and Table 40 provide the MII receive packet timing.
Figure 17. MII Receive Packet Timing
t4 0 4
t4 0 2
t4 0 1
t4 0 3
RXC
RXDV
R X D [3 :0 ]
Table 40. MII Receive Packet Timing Parameters
Parameter
t401
t402
Description
–
Maximum
Units
10
–
–
ns
RXC clock period (10BASE-T mode)
–
400
–
ns
–
40
–
ns
160
–
240
ns
RXC low/high time (10BASE-T mode)
t404
Typical
RXDV and RXD[3:0] to RXC rising setup time
RXC clock period (100BASE-TX mode)
t403
Minimum
RXC low/high time (100BASE-TX mode)
16
–
24
ns
RXDV and RXD[3:0] to RXC rising hold time
10
–
–
ns
Duty cycle
40
50
60
%
17.1.2 MII Transmit Packet Timing
Figure 18 and Table 41 provide the MII transmit packet timing.
Figure 18. MII Transmit Packet Timing
TXC
TXEN
T X D [3 :0 ]
Table 41. MII Transmit Packet Timing Parameters
Parameter
Description
Minimum
Typical
Maximum
Units
t405
TXC high to TXEN and TXD[3:0] valid
0
–
25
ns
t406
TXC high to TXEN and TXD[3:0] invalid (hold)
0
–
–
ns
Document Number: 002-14829 Rev. *J
Page 69 of 94
PRELIMINARY
CYW43907
17.1.3 RMII Receive Packet Timing
Figure 19 and Table 42 provide the RMII receive packet timing.
Figure 19. RMII Receive Packet Timing
REF_CLK
CRS_DV
RXD[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
0
RXD[0]
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
X
X
X
X
0
/J /
/K/
Preamble
SFD
Data
Table 42. RMII Receive Packet Timing
Symbol
Minimum
Typical
Maximum
Unit
REF_CLK Cycle Time
Parameter
–
–
20
–
ns
RXD[1:0], RXER, CRS_DV Output delay from REF_CLK rising
–
2
–
10
ns
Notes:
1. In 10 Mbps mode, there are ten REF_CLK periods per data period.
2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity
buffering.
Document Number: 002-14829 Rev. *J
Page 70 of 94
PRELIMINARY
CYW43907
17.1.4 RMII Transmit Packet Timing
Figure 20 and Table 43 provide the RMII transmit packet timing.
Figure 20. RMII Transmit Packet Timing
REF_CLK
T X _E N
T XD[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
0
T XD[0]
0
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
Preamble
S FD
Data
Table 43. RMII Transmit Packet Timing Parameters
Parameter
REF_CLK Cycle Time
Symbol
Minimum
Typical
Maximum
Unit
–
–
20
–
ns
TXEN, TXER, TXD[1:0] setup time to REF_CLK rising
TXEN_SETUP
4
–
–
ns
TXEN, TXER, TXD[1:0] hold time from REF_CLK rising
TXEN_HOLD
2
–
–
ns
Notes:
1. TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted.
2. In 10 Mbps mode, there are ten REF_CLK periods per data period.
Document Number: 002-14829 Rev. *J
Page 71 of 94
PRELIMINARY
CYW43907
17.2 I2S Master and Slave Mode TX Timing
Figure 21 and Table 44 provide the I2S Master mode transmitter timing.
Figure 21. I2S Master Mode Transmitter Timing
T
t RC
I2S_SCLK
t HC = 0.35T
V
t LC = 0.35T
t htr = 0
V
H = 2.0V
L = 0.8V
t dtr = 0.8T
I2S_SDATO
and I2S_LRCK
T = Clock period.
Ttr = Minimum allowed clock period for transmitter.
T > Ttr.
tRC is only relevant for transmitters in Slave mode.
Figure 22 and Table 44 provide the I2S Slave mode receiver timing.
Figure 22. I2S Slave Mode Receiver Timing
T
I2S_SCLK
tHC = 0.35T
V
tLC = 0.35T
tsr = 0.2T
V
H = 2.0V
L = 0.8V
thr = 0
I2S_SDATAI
and I2S_LRCK
T = Clock period.
Tr = Minimum allowed clock period for the transmitter.
T > Tr.
Document Number: 002-14829 Rev. *J
Page 72 of 94
PRELIMINARY
CYW43907
Table 44. Timing for I2S Transmitters and Receivers
Transmitter
Parameter
Receiver
Lower Limit
Upper Limit
Lower Limit
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Ttr
–
–
–
Ttr
–
Clock period T
Slave mode:
Clock HIGH, tHC
–
0.35Tr
–
–
–
0.35Tr
Clock LOW, tLC
–
0.35Tr
–
–
–
0.35Tr
Clock rise time, tRC
–
–
0.15Ttr
–
–
–
Transmitter delay, tdtr
–
–
–
0.8T
–
–
Transmitter hold time, thtr
0
–
–
–
–
–
Receiver setup time, tsr
–
–
–
–
–
0.2Tr
Receiver hold time, thr
–
–
–
–
–
0
Table 45 provides the I2S_MCLK specification.
Table 45. I2S_MCLK Specification
Minimum
Typical
Maximum
Unit
Frequency range
Parameter
1
–
40
MHz
Frequency accuracy (with respect to the XTAL frequency)
–
1
–
ppb
Tuning resolution
–
50
–
ppb
Tuning range
–
1000
–
ppm
Tuning step size
–
–
10
ppm
Tuning rate
–
1
–
ppm/ms
Baseband jitter (100 Hz to 40 kHz)
–
–
100
ps rms
Wideband jitter (100 Hz to 1 MHz)
–
–
200
ps rms
Figure 23 shows the I2S frame-level timing.
Figure 23. I2S Frame-Level Timing
1/fs
I2S_LRCLK
Left Channel
Right Channel
I2S_SCLK
1 clock
1
I/O Data
2
1 clock
3
MSB
Document Number: 002-14829 Rev. *J
n– 2 n–1
n
1
LSB
MSB
2
3
n–2 n–1
n
LSB
Page 73 of 94
PRELIMINARY
CYW43907
17.3 SDIO Interface Timing
17.3.1 SDIO Default-Speed Mode Timing
SDIO default-speed (DS) mode timing is shown by the combination of Figure 24 and Table 46.
Figure 24. SDIO Bus Timing (Default-Speed Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 46. SDIO Bus Timinga Parameters (Default-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer mode
fPP
0
–
25
MHz
Frequency – Identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock low time
tTHL
–
–
10
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
5
–
–
ns
tIH
5
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
tODLY
0
–
14
ns
Output delay time – Identification mode
tODLY
0
–
50
ns
a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Document Number: 002-14829 Rev. *J
Page 74 of 94
PRELIMINARY
CYW43907
17.3.2 SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 25 and Table 47.
Figure 25. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tISU
tTLH
tIH
Input
Output
tODLY
tOH
Table 47. SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer Mode
fPP
0
–
50
MHz
Frequency – Identification Mode
fOD
0
–
400
kHz
Clock low time
tWL
7
–
–
ns
Clock high time
tWH
7
–
–
ns
Clock rise time
tTLH
–
–
3
ns
Clock low time
tTHL
–
–
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
6
–
–
ns
tIH
2
–
–
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
tODLY
–
–
14
ns
Output hold time
tOH
2.5
–
–
ns
Total system capacitance (each line)
CL
–
–
40
pF
a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Document Number: 002-14829 Rev. *J
Page 75 of 94
PRELIMINARY
CYW43907
17.3.3 SDIO Bus Timing Specifications in SDR Modes
Clock Timing
SDIO clock timing in the SDR modes is shown by the combination of Figure 26 and Table 48.
Figure 26. SDIO Clock Timing (SDR Modes)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 48. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter
Symbol
–
tCLK
–
Clock duty cycle
Minimum
Maximum
Unit
Comments
40
–
ns
SDR12 mode
20
–
ns
SDR25 mode
tCR, tCF
–
0.2 × tCLK
ns
CCARD = 10 pF
–
30
70
%
–
Device Input Timing
SDIO device input timing in the SDR modes is shown by the combination of Figure 27 and Table 49.
Figure 27. SDIO Bus Input Timing (SDR Modes)
SDIO_CLK
tIS
tIH
CMD input
DAT[3:0] input
Table 49. SDIO Bus Input Timing Parameters (SDR Modes)
Symbol
Minimum
Maximum
Unit
tIS
3.00
–
ns
CCARD = 10 pF, VCT = 0.975V
tIH
0.80
–
ns
CCARD = 5 pF, VCT = 0.975V
Document Number: 002-14829 Rev. *J
Comments
Page 76 of 94
PRELIMINARY
CYW43907
Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of Figure 28 and Table 50.
Figure 28. SDIO Bus Output Timing (SDR Modes up to 50 MHz)
t C LK
S D IO _ C L K
t O D LY
tOH
C M D in p u t
D A T [3 :0 ] in p u t
Table 50. SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
Symbol
Minimum
Maximum
Unit
Comments
tODLY
–
14.0
ns
tCLK ≥ 20 ns CL= 40 pF
tOH
1.5
–
ns
Hold time at the tODLY (min.) CL= 15 pF
17.4 S/PDIF Interface Timing
The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC).
Figure 29 shows the S/PDIF interface timing.
Figure 29. S/PDIF Interface Timing
C lo c k
D a ta
1
0
0
1
1
0
1
0
0
1
0
E n c o d e d (B M C )
Figure 30 shows the S/PDIF data output timing.
Figure 30. S/PDIF Data Output Timing
tC LK
S P D IF _ O U T
tC R
Document Number: 002-14829 Rev. *J
tC F
tC R
Page 77 of 94
PRELIMINARY
CYW43907
Table 51 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 30).
Table 51. SPDIF Biphase Mark Code Timing Parameters
Parameter
Symbol
Minimum
Maximum
Unit
–
tCLK
40
–
ns
–
tCR, tCF
–
0.3 × tCLK
ns
–
–
30
70
%
–
Duty cycle
Comments
192 kHz sample rate
Table 52 provides the S/PDIF biphase mark code sample rate and receiver clock frequency.
Table 52. SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency
Parameter
Sampling frequency
Component clock
frequency
Symbol
Minimum
Maximum
Unit
fS
–
192
kHz
192 kHz sample rate maximum.
fCLOCK
–
25
MHz
Typical is 128 × fS, max is 192 × fS.
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.
Document Number: 002-14829 Rev. *J
Comments
Page 78 of 94
PRELIMINARY
CYW43907
17.5 SPI Flash Timing
17.5.1 Read-Register Timing
Figure 31 shows the SPI flash extended and quad read-register timing.
Note: Regarding Figure 31: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile
Configuration Register operation will output data starting from the least significant byte.
Figure 31. SPI Flash Read-Register Timing
Extended
0
7
8
9
10
11
12
13
14
C
LSB
DQ0
Command
MSB
DQ1
High-Z
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Quad
0
1
2
3
C
LSB
DQ[3:0]
Command
MSB
Document Number: 002-14829 Rev. *J
LSB
DOUT
DOUT
DOUT
Don’t care
MSB
Page 79 of 94
DOUT
PRELIMINARY
CYW43907
17.5.2 Write-Register Timing
Figure 32 shows the SPI flash extended and quad write-register timing.
Note: Regarding Figure 32:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended for each protocol: to 23 for extended and five for quad.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Figure 32. SPI Flash Write-Register Timing
Extended
0
7
8
9
10
11
12
13
14
15
C
LSB
LSB
DQ0
Command
DIN
MSB
Quad
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
MSB
0
1
2
3
C
LSB
DQ[3:0]
LSB
DIN
Command
MSB
Document Number: 002-14829 Rev. *J
DIN
DIN
MSB
Page 80 of 94
PRELIMINARY
CYW43907
17.5.3 Memory Fast-Read Timing
Figure 33 shows the SPI flash extended and quad memory fast-read timing.
Note: Regarding Figure 33:
1. 24-bit addressing is used, so A[MAX] = A[23] and A[MIN] = A[0].
2. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
3. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 33. Memory Fast-Read Timing
Extended
0
7
8
Cx
C
A[MIN]
LSB
Command
DQ0
MSB
DQ1
A[MAX]
LSB
DOUT
High-Z
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Dummy Cycles
Quad
0
1
2
Cx
C
LSB
A[MIN]
LSB
DQ[3:0]
Command
MSB
DOUT
A[MAX]
DOUT
MSB
Dummy Cycles
Document Number: 002-14829 Rev. *J
DOUT
Don’t care
Page 81 of 94
PRELIMINARY
CYW43907
17.5.4 Memory-Write Timing
Figure 34 shows the SPI flash extended and quad memory-write (Page Program) timing.
Note: Regarding Figure 34:
1. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
2. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 34. Memory-Write Timing
Extended
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
Command
DQ0
MSB
Quad
A[MAX]
0
1
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
MSB
2
Cx
C
LSB
A[MIN]
LSB
DQ[3:0]
Command
MSB
Document Number: 002-14829 Rev. *J
DIN
A[MAX]
DIN
DIN
MSB
Page 82 of 94
PRELIMINARY
CYW43907
17.5.5 SPI Flash Parameters
The combination of Figure 35 and Table 53 provide the SPI flash timing parameters.
Figure 35. SPI Flash Timing Parameters Diagram
T_DVCH
Clock (C)
T_CHDX
Data in (DIN)
(DQ1 in Serial [Extended] mode)
(DQ[3:0] in Quad mode)
T_CLQX
Data out (DOUT)
(DQ0 in Serial [Extended] mode)
(DQ[3:0] in Quad mode)
T_CLQV
Table 53. SPI Flash Timing Parameters
Parameter
Description
Minimum
Maximum
Units
T_DVCH
Data setup time
2
–
ns
T_CHDX
Data hold time
3
–
ns
T_CLQX
Output hold time
1
–
ns
T_CLQV
Output valid time (with a 10 pF load)
–
5
ns
Document Number: 002-14829 Rev. *J
Page 83 of 94
PRELIMINARY
CYW43907
17.6 USB PHY Electrical Characteristics and Timing
17.6.1 USB 2.0 and USB 1.1 Electrical and Timing Parameters
Table 54 provides electrical and timing parameters for USB 2.0.
Table 54. USB 2.0 Electrical and Timing Parameters
Parameter
Symbol
Baud rate
Minimum
Typical
Maximum
Units
Conditions
BPS
–
480
–
Mbps
–
UI
–
2083
–
ps
–
–
mV
Unit interval
Receiver – HS Mode
Differential input voltage sensitivity
Input common mode voltage range
Receiver jitter tolerance
VHSDI
VHSCM
THSRX
Input impedance
RIN
300
–
Static | VIDP – VIDN |
–50
–
500
mV
–
–0.15
–
0.15
UI
–
40.5
45
49.5
Ω
Single ended
Transmitter – HS Mode
Output high voltage
VHSOH
360
400
440
mV
Static condition
Output low voltage
VHSOL
–10
0
10
mV
Static condition
Output rise time
THSR
500
–
–
ps
10% to 90%
Output fall time
THSF
500
–
–
ps
90% to 10%
 THSTX
–0.05
–
0.05
UI
Transmit output jitter
RO
40.5
45
49.5
Ω
Single ended
Chirp-J output voltage (differential)
VCHIRPJ
700
–
1100
mV
HS termination disabled. 1.5
kΩ ± 5% pull-up resistor
connected.
Chirp-K output voltage (differential)
VCHIRPK
–900
–
–500
mV
HS termination disabled. 1.5
kΩ ± 5% pull-up resistor
connected.
Transmitter jitter
Output impedance
Note: Refer to Section 7 of the USB 2.0 specification (www.usb.org) for more information on the receiver eye diagram template.
Table 55 provides electrical and timing parameters for USB 1.1.
Table 55. USB 1.1 FS/LS Electrical and Timing Parameters a
Parameter
Symbol
Value
Minimum
Typical
Maximum
Unit
Condition
Baud Rate
FS
BPS
–
12
–
Mbps
–
LS
BPS
–
1.5
–
Mbps
–
Unit Interval
FS
UI
–
83.33
–
ns
–
LS
UI
–
666.67
–
ns
–
Differential input sensitivity
VFSDI
200
–
–
mV
Input common mode range
Receiver
Static |VIDP – VIDN |
VFSCM
0.8
–
2.5
V
–
Input impedance
ZIN
300
–
–
kΩ
–
Input high voltage
VFSIH
2.0
–
–
V
Static
Input low voltage
VFSIL
–
–
0.8
V
Static
Document Number: 002-14829 Rev. *J
Page 84 of 94
PRELIMINARY
CYW43907
Table 55. USB 1.1 FS/LS Electrical and Timing Parameters (Cont.)a
Parameter
Symbol
Value
Minimum
Typical
Maximum
Unit
Condition
Transmitter
Output high voltage
VFSOH
2.8
–
–
V
Static
Output low voltage
VFSOL
–
–
0.3
V
Static
Output rise/fall time for fast speed
TR,TF
4
–
20
ns
10 to 90%
Output rise/fall time for low speed
TR,TF
75
–
300
ns
10 to 90%
Fast-speed jitter
Low-speed jitter
Output impedance
FSTX
LSTX
–2
–
2
ns
–
–25
–
25
ns
–
RO
28
–
44
Ω
Single ended
a. For more details, refer to the USB 1.1 Specification.
Document Number: 002-14829 Rev. *J
Page 85 of 94
PRELIMINARY
CYW43907
17.6.2 USB 2.0 Timing Diagrams
Figure 36 shows the important timing parameters associated with a post-reset transition to high-speed (HS) operation.
Figure 36. USB 2.0 Bus Reset to High-Speed Mode Operation
40 to 60 μs
< 100 μs
DP
100 to 500 μs
Idle
HS Data
HighSpeed
Chirp
DM
Device
K-Chirp
Idle
3 to 3.125 ms
HS Data
> 1.0 ms
100 to
875 μs
< 7 ms
> 10 ms
Start of
Reset
Start of Host
(Hub) Chirp
Device Goes
into FullSpeed Mode
End of Host
(Hub) Chirp
End of
Reset
Device Tests for
Single-Ended Zero
(SE0) State
Figure 37 shows the USB 2.0 HS Mode transmit timing.
Figure 37. USB 2.0 High-Speed Mode Transmit Timing
96 bits
DP/DM
Latency = 42 bits
CLK60
PID
TXDATA
B0
B1
TXVALID
TXREADY
XVERSEL
00
OPMODE
00
TERMSEL
0
TX driver is enabled here.
Document Number: 002-14829 Rev. *J
Page 86 of 94
PRELIMINARY
CYW43907
Figure 38 shows the USB 2.0 HS Mode receive timing.
Figure 38. USB 2.0 High-Speed Mode Receive Timing
Latency = 72 bits
64 bits
DP/DM
CLK60
RXACTIVE
RXVALID
B0
RXDATA
XVERSEL
00
OPMODE
00
TERMSEL
0
Document Number: 002-14829 Rev. *J
B1
B2
Page 87 of 94
PRELIMINARY
CYW43907
18. Power-Up Sequence and Timing
18.1 Sequencing of Reset and Regulator Control Signals
The CYW43907 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks.
These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various
operational states (see Figure 39 and Figure 40). The timing values indicated are minimum required values; longer delays are also
acceptable.
18.1.1 Description of Control Signals
■
REG_ON: Used by the PMU to power-up the CYW43907. It controls the internal CYW43907 regulators. When this pin is high, the
regulators are enabled and the device is out of reset. When this pin is low the regulators are disabled.
HIB_REG_ON_IN: Used by the Hibernation (HIB) block to power up the internal CYW43907 regulators. If the HIB_REG_ON_IN
pin is low, the regulators are disabled. For the HIB_REG_ON_IN pin to work as designed, HIB_REG_ON_OUT must be connected
to REG_ON.
Note: The CYW43907 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after
VDDC and VDDIO have both passed the POR threshold.
Note: The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as
VDDIO. VDDIO should not be present first or be held high before VBAT is high.
■
18.1.2 Control Signal Timing Diagrams
Figure 39. REG_ON = High, No HIB_REG_ON_OUT Connection to REG_ON
3 2 .6 7 8 k H z
S le e p C lo c k
VBAT
V D D IO
~ 2 S le e p C y c le s
REG_O N
H IB _ R E G _ O N _ IN
Figure 40. HIB_REG_ON_IN = High, HIB_REG_ON_OUT Connected to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
~ 2 Sleep Cycles
HIB_REG_ON_IN
Document Number: 002-14829 Rev. *J
Page 88 of 94
PRELIMINARY
CYW43907
19. Thermal Information
19.1 Package Thermal Characteristics
Table 56. Package Thermal Characteristicsa
Characteristic
WLCSP
JA (°C/W) (value in still air)
JB (°C/W)
JC (°C/W)
33.74
JT (°C/W)
JB (°C/W)
5.86
11.52
Maximum Junction Temperature Tj (°C)
116.7
Maximum power dissipation (W)
1.38
5.5
1.74
a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7. Air velocity is 0 m/s.
19.2 Junction Temperature Estimation and PSIJT Versus THETAJC
Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is
dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom
and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation
for calculating the device junction temperature is:
TJ = TT + P x JT
Where:
■
TJ = Junction temperature at steady-state condition (°C)
■
TT = Package case top center temperature at steady-state condition (°C)
■
P = Device power dissipation (Watts)
■
JT = Package thermal characteristics; no airflow (°C/W)
19.3 Environmental Characteristics
For environmental characteristics data, see Table 17: “Environmental Ratings”.
Document Number: 002-14829 Rev. *J
Page 89 of 94
PRELIMINARY
CYW43907
20. Mechanical Information
Figure 41. WLCSP Package
Document Number: 002-14829 Rev. *J
Page 90 of 94
PRELIMINARY
CYW43907
21. Ordering Information
Package
Description
Operating Ambient
Temperature
4.583 mm x 5.533 mm, 316-pin WLCSP
–
–30°C to +85°C
Part Number
CYW43907KWBG
22. Additional Information
22.1 Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in
Cypress documents, go to: http://www.cypress.com/glossary.
22.2 References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) and
Downloads and Support site (see IoT Resources).
Number
Source
1. USB 2.0 specification
Document (or Item) Name
–
www.usb.org
2. USB 1.1 Specification
–
www.usb.org
22.3 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(https://community.cypress.com/)
22.4 Errata
1. The RTC block has been deprecated from this datasheet in revision *A and later. This block is used by Cypress for internal
testing/validation/verification and is not intended for customers to use.
2. The details of the SPI hardware blocks were missing from this datasheet till revision *H. Revision *I adds this in section 5.12.SPI
Note that the SPI hardware blocks can only support a hold time of 25ns and a fixed SPI mode (CPHA=0, CPOL = 0). For slaves
that require higher hold times or a different mode a bit banging based SPI driver is recommended.
3. The clock for the SPI Flash block needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures.
The throughput of the SPI Flash block is therefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode.
Document Number: 002-14829 Rev. *J
Page 91 of 94
PRELIMINARY
CYW43907
Document History Page
Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
-
-
11/03/2014
43907-DS100-R
Initial release
*A
-
-
03/10/2015
43907-DS101-R
See the revision history of the applicable release.
10/15/2015
43907-DS102-R
Updated:
Figure 3: “Typical Power Topology (Page 1 of 2)”.
Table 3: “Crystal Oscillator and External Clock — Requirements and
Performance”
“Transmit Path”.
Figure 14: “Radio Functional Block Diagram”.
“Calibration”.
Table 17: “Strapping Options”.
Table 23: “ESD Specifications”.
Table 24: “Recommended Operating Conditions and DC
Characteristics”.
“Introduction”.
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
Section 18: “System Power Consumption”
Table 56: “SDIO Bus Input Timing Parameters (SDR Modes)”.
Table 64: “Package Thermal Characteristics”.
*B
*C
-
-
-
-
11/03/2015
43907-DS103-R
Updated:
Table 21: “Absolute Maximum Ratings”.
Table 24: “Recommended Operating Conditions and DC
Characteristics”
Table 30: “WLAN 2.4 GHz Receiver Performance Specifications”
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
*D
-
-
03/12/2016
*E
5525655
UTSV
11/17/2016
*F
5553590
UTSV
01/17/2017
43907-DS104-R
Updated:
General edits
Added Cypress Part Numbering Scheme and Mapping Table
Updated to Cypress template.
Updated:
Two SPI master interfaces with operation up to 24 MHz. in page 5.
*G
5730057
NIBK
Document Number: 002-14829 Rev. *J
05/10/2017 Updated Cypress Logo and Copyright.
Page 92 of 94
PRELIMINARY
CYW43907
Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision
*H
*I
*J
ECN
5812137
5954959
5999198
Orig. of
Change
UTSV
Submission
Date
Description of Change
Replaced BSC to CSC throughout the datasheet.
Updated Figure 1, Figure 2, Table 4, Table 14.
Removed 3.3 Frequency Selection.
Updated 5.9 SPI Flash:
- Replaced Quad I/O, which Provides increased throughput to 40 MB/
07/14/2017 s to Increased Throughput to 40 MBps in Quad-mode or upto 10
MBps in single Mode.
Added Footnote for Table 14.
Updated Contents in the Table 29, Table 30, Table 31.
Updated Table 18 on page 50.
Added SPI section.
Added a Note: “The SPI blocks can be re-purposed as I2C,
however the WICED SDK does not support this. Certain I2C
features may be unavailable when using the SPI blocks as I2C.
Therefore Cypress recommends using the the CSC blocks or a bit
banging I2C driver over GPIOs instead.” below Table 11 on
page 36.
Added a 22.4.Errata section.
Replaced BCS to CSC throughot the document.
UTSV
11/02/2017
UTSV
Updated Revisions details in the section 22.4.Errata.
Updated Note “Note that the clock needs to be constrained to
~26.67MHz
for reliable operation at high operating temperatures.
12/22/2017
The throughput of the SPI Flash block is therefore restricted to
~13 MBps for Quad mode and ~3 MBps for single mode” for
5.9.SPI Flash.
Document Number: 002-14829 Rev. *J
Page 93 of 94
PRELIMINARY
CYW43907
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs | Training
| Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-14829 Rev. *J
Revised December 22, 2017
Page 94 of 94