ELM GD25Q21B Uniform sector dual and quad serial flash Datasheet

http://www.elm-tech.com
GD25Q21B
DATASHEET
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
- Content 1. FEATURES
Page
-------------------------------------------------------------------------------------------------
2. GENERAL DESCRIPTION
4
-----------------------------------------------------------------------------
5
--------------------------------------------------------------------------
6
4. DEVICE OPERATION
----------------------------------------------------------------------------------
6
5. DATA PROTECTION
------------------------------------------------------------------------------------
7
6. STATUS REGISTER
-------------------------------------------------------------------------------------
9
3. MEMORY ORGANIZATION
7. COMMANDS DESCRIPTION
Table of ID Definition
-------------------------------------------------------------------------
10
---------------------------------------------------------------------------------------
13
7.1. Write Enable (WREN) (06H)
-----------------------------------------------------------------------
14
7.2. Write Disable (WRDI) (04H)
-----------------------------------------------------------------------
14
7.3. Write Enable for Volatile Status Register (50H)
--------------------------------------------------
15
-----------------------------------------------------
15
7.5. Write Status Register (WRSR) (01H)
--------------------------------------------------------------
16
7.6. Write Status Register (WRSR) (31H)
-------------------------------------------------------------
17
--------------------------------------------------------------------
18
7.4. Read Status Register (RDSR) (05H or 35H)
7.7. Read Data Bytes (READ) (03H)
7.8. Read Data Bytes at Higher Speed (Fast Read) (0BH)
-------------------------------------------
18
7.9. Dual Output Fast Read (3BH)
----------------------------------------------------------------------
19
7.10. Quad Output Fast Read (6BH)
----------------------------------------------------------------------
20
7.11. Dual I/O Fast Read (BBH)
-------------------------------------------------------------------------
20
7.12. Quad I/O Fast Read (EBH)
-------------------------------------------------------------------------
22
7.13. Quad I/O Word Fast Read (E7H)
------------------------------------------------------------------
23
7.14. Set Burst with Wrap (77H)
--------------------------------------------------------------------------
25
7.15. Page Program (PP) (02H)
---------------------------------------------------------------------------
26
7.16. Quad Page Program (32H)
--------------------------------------------------------------------------
27
-----------------------------------------------------------------------------
28
7.17. Sector Erase (SE) (20H)
7.18. 32KB Block Erase (BE) (52H)
---------------------------------------------------------------------
28
7.19. 64KB Block Erase (BE) (D8H)
---------------------------------------------------------------------
29
--------------------------------------------------------------------------
29
---------------------------------------------------------------------
30
7.20. Chip Erase (CE) (60/C7H)
7.21. Deep Power-Down (DP) (B9H)
7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) 31
7.23. Read Manufacture ID/Device ID (REMS) (90H)
-------------------------------------------------
32
7.24. Read Manufacture ID/Device ID Dual I/O (92H)
------------------------------------------------
33
7.25. Read Manufacture ID/Device ID Quad I/O (94H)
-----------------------------------------------
34
------------------------------------------------------------------
35
7.26. Read Identification (RDID) (9FH)
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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.27. High Performance Mode (HPM) (A3H)
7.28. Erase Security Registers (44H)
-----------------------------------------------------------
36
----------------------------------------------------------------------
36
------------------------------------------------------------------
37
----------------------------------------------------------------------
38
7.29. Program Security Registers (42H)
7.30. Read Security Registers (48H)
7.31. Continuous Read Mode Reset (CRMR) (FFH)
---------------------------------------------------
39
7.32. Program/Erase Suspend (PES) (75H)
--------------------------------------------------------------
39
7.33. Program/Erase Resume (PER) (7AH)
--------------------------------------------------------------
40
---------------------------------------------------------------
41
-------------------------------------------------------------------------------------
41
----------------------------------------------------------------------------------
41
8. ELECTRICAL CHARACTERISTICS
8.1. Power-ON timing
8.2. Initial delivery state
8.3. Data retention and endurance
8.4. Latch up characteristics
-----------------------------------------------------------------------
41
-----------------------------------------------------------------------------
41
-------------------------------------------------------------------------
42
8.5. Absolute maximum ratings
8.6. Capacitance measurement conditions
-------------------------------------------------------------
42
8.7. DC characteristics
-----------------------------------------------------------------------------------
43
8.8. AC characteristics
-----------------------------------------------------------------------------------
44
9. ORDERING INFORMATION
-------------------------------------------------------------------------
46
10. PACKAGE INFORMATION
---------------------------------------------------------------------------
47
10.1. Package SOP8 150MIL
----------------------------------------------------------------------------
47
10.2. Package SOP8 208MIL
----------------------------------------------------------------------------
48
-----------------------------------------------------------------------
49
10.3. Package USON8 (3x2MM)
49 - 3
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
1. FEATURES
♦ 2M-bit Serial Flash
♦ Program/Erase Speed
- 256K-byte
- 256 bytes per programmable page
♦ Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
♦ High Speed Clock Frequency
- 104MHz for fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 416Mbits/s
♦ Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin
- Top or Bottom, Sector or Block selection
- Page Program time: 0.35ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.18/0.25s typical
- Chip Erase time: 0.8s typical
♦ Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
♦ Low Power Consumption
- 12mA maximum active current
- 5μA maximum power down current
♦ Single Power Supply Voltage
- Full voltage range: 2.7~3.6V
♦ Minimum 100,000 Program/Erase Cycles
♦ Advanced security Features
- Power Supply Lock-Down
- 3×512-Byte Security Registers With OTP Locks
- Volatile and Non-volatile Status Register Bits
49 - 4
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
2. GENERAL DESCRIPTION
The GD25Q21B Serial flash supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2
(WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock
rates of 208MHz for Dual Output & Dual I/O read command, and 416MHz for Quad output & Quad I/O read
command.
Connection Diagram
8-LEAD SOP
8-LEAD USON
Pin Description
Pin Name
I/O
Description
CS#
I
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output ( Data Input Output 1 )
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
I
Data Input ( Data Input Output 0 )
Serial Clock Input
HOLD# (IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Chip Select Input
Block Diagram
Write Control
Logic
Status
Register
HOLD#(IO3)
SCLK
CS#
SPI
Command &
Control Logic
High Voltage
Generators
Page Address
Latch/Counter
Write Protect Logic
and Row Decode
WP#(IO2)
Flash
Memory
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
49 - 5
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
3. MEMORY ORGANIZATION
GD25Q21B
Each device has
Each block has
Each sector has
Each page has
256K
64/32K
4K
256
bytes
1K
256/128
16
-
pages
64
16/8
-
-
sectors
4/8
-
-
-
blocks
Uniform Block Sector Architecture
GD25Q21B 64K Bytes Block Sector Architecture
Block
Sector
Address range
3
64
-----
03F000H
-----
03FFFFH
-----
----47
----02F000H
----02FFFFH
2
----32
31
----020000H
01F000H
----020FFFH
01FFFFH
1
----16
15
----010000H
00F000H
----010FFFH
00FFFFH
0
----0
----000000H
----000FFFH
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q21B feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q21B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
49 - 6
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Quad SPI
The GD25Q21B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”, “Quad I/O Word Fast Read”, ”Quad Page Program” (6BH, EBH, E7H, 32H) commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When
using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in
Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and
starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD
operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with
SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is
high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be
at high and then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25Q21B provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
- Erase Security Register / Program Security Register
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
49 - 7
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Table1.0 GD25Q21B Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
0
×
×
0
0
0
0
×
0
1
0
0
×
1
0
0
1
×
0
1
0
1
×
1
0
0
×
×
1
1
1
×
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
×
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
×
1
1
1
1
0
1
×
1
1
1
Blocks
NONE
3
2 and 3
0
0 and 1
0 to 3
NONE
3
3
3
3
3
0
0
0
0
0
0 to 3
Addresses
NONE
030000H-03FFFFH
020000H-03FFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
NONE
03F000H-03FFFFH
03E000H-03FFFFH
03C000H-03FFFFH
038000H-03FFFFH
038000H-03FFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
000000H-03FFFFH
Density
NONE
64KB
128KB
64KB
128KB
256KB
NONE
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB
256KB
Portion
NONE
Upper 1/4
Upper 1/2
Lower 1/4
Lower 1/2
ALL
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/8
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/8
ALL
Density
256KB
192KB
128KB
192KB
128KB
NONE
256KB
252KB
248KB
240KB
224KB
224KB
252KB
248KB
240KB
224KB
224KB
NONE
Portion
ALL
Lower 3/4
Lower 1/2
Upper 3/4
Upper 1/2
NONE
ALL
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 7/8
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 7/8
NONE
Table1.0. GD25Q21B Protected area size (CMP=1)
Status Register Content
BP4 BP3 BP2 BP1 BP0
0
×
×
0
0
0
0
×
0
1
0
0
×
1
0
0
1
×
0
1
0
1
×
1
0
0
×
×
1
1
1
×
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
×
1
0
1
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
×
1
1
1
1
0
1
×
1
1
1
Memory Content
Blocks
0 to 3
0 to 2
0 and 1
1 to 3
2 and 3
NONE
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
NONE
Addresses
000000H-03FFFFH
000000H-02FFFFH
000000H-01FFFFH
010000H-03FFFFH
020000H-03FFFFH
NONE
000000H-03FFFFH
000000H-03EFFFH
000000H-03DFFFH
000000H-03BFFFH
000000H-037FFFH
000000H-037FFFH
001000H-03FFFFH
002000H-03FFFFH
004000H-03FFFFH
008000H-03FFFFH
008000H-03FFFFH
NONE
49 - 8
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
6. STATUS REGISTER
S15
SUS
S14
CMP
S13
LB3
S12
LB2
S11
LB1
S10
HPF
S9
QE
S8
SRP1
S7
SRP0
S6
BP4
S5
BP3
S4
BP2
S3
BP1
S2
BP0
S1
WEL
S0
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when
WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile (Default Value is 0). They define the size
of the area to be software protected against Program and Erase commands. These bits are written with the Write
Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE)
and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided
that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block
Protect (BP4, BP3, BP2, BP1, BP0) bits are set to “None protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply lockdown or one time programmable protection.
SRP1 SRP0 #WP
Status Register
Description
0
0
×
Software Protected
WP# pin has no control. The Status Register can be written to
after a Write Enable command, WEL=1.(Default)
0
1
0
Hardware Protected
When WP# pin is low the Status Register locked and can not be
written to.
0
1
1
Hardware Unprotected
When WP# pin is high the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
Power Supply
Status Register is protected and can not be written to again until
the next Power-Down, Power-Up cycle.
Lock-Down(1)
1
1
×
One Time Program(2) Status Register is permanently protected and can not be written to.
NOTE: (1). When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
(2). This feature is available on special order. Please contact ELM for details.
1
0
×
49 - 9
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1,
the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
HPF bit.
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit
sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is
not in High Performance Mode.
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0,
the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become
read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
SUS bit.
The SUS bit is read only bit in the status register (S15) that is set to 1 after executing an Erase/Program
Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a
power-down, power-up cycle.
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit
on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last
bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or
Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a dataout sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock
pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte
is not a full byte, nothing will happen and WEL will not be reset.
49 - 10
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Table2. Commands
Command Name
Byte 1
Byte 2
Write Enable
Write Disable
Volatile SR Write Enable
Read Status Register
Read Status Register-1
Write Status Register
Write Status Register-1
Read Data
Fast Read
Dual Output Fast Read
06H
04H
50H
05H
35H
01H
31H
03H
0BH
3BH
(S7-S0)
(S15-S8)
(S7-S0)
(S15-S8)
A23-A16
A23-A16
A23-A16
Dual I/O Fast Read
BBH
A23-A8 (3)
Quad Output Fast Read
6BH
Quad I/O Fast Read
EBH
A23-A16
A23-A0
M7-M0 (5)
A23-A0
M7-M0 (5)
Byte 3
Byte 4
Byte 5
Byte 6
(continuous)
(continuous)
(S15-S8) (1)
A15-A8
A15-A8
A15-A8
A7-A0
M7-M0 (3)
A15-A8
n-Bytes
A7-A0
A7-A0
A7-A0
(D7-D0) (Next byte) (continuous)
dummy
(D7-D0) (continuous)
dummy D7-D0 (2) (continuous)
(D7-D0) (2)
A7-A0
(continuous)
dummy
(D7-D0) (4) (continuous)
dummy (6)
(D7-D0) (4)
(continuous)
dummy (7)
(D7-D0) (4)
(continuous)
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
dummy
dummy
dummy
(DID7DID0)
90H
dummy
dummy
00H
(MID7MID0)
92H
A23-A8
Manufacturer/
Device ID by Quad I/O
94H
A23-A0,
M7-M0
Read Identification
9FH
(M7-M0)
Quad I/O Word Fast
Read (8)
Continuous Read Reset
Page Program
Quad Page Program
Sector Erase
Block Erase (32K)
Block Erase (64K)
Chip Erase
E7H
FFH
02H
32H
20H
52H
D8H
C7/60H
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
Set Burst with Wrap
77H
dummy (10)
W7-W0
Program/Erase Suspend
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down,
And Read Device ID
75H
7AH
B9H
Release From Deep
Power-Down
Manufacturer/
Device ID
Manufacturer/
Device ID by Dual I/O
ABH
D7-D0
D7-D0 (4)
Next byte
(continuous)
ABH
A7-A0,
(MID7-MID0)
M7-M0
(DID7-DID0
(11)
dummy
(MID7- MID0)
(DID7-DID0)
(JDID15(JDID7JDID8)
JDID0)
49 - 11
(DID7DID0)
(continuous)
(continuous)
(continuous)
(continuous)
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Command Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
High Performance Mode
Erase Security
Registers (9)
Program Security
Registers (9)
Read Security
Registers (9)
A3H
dummy
dummy
dummy
44H
A23-A16
A15-A8
A7-A0
42H
A23-A16
A15-A8
A7-A0
(D7-D0)
(D7-D0)
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
n-Bytes
NOTE:
(1) Write Status Register (01H)
Normally, Write Status Register (01H) is used to write both lower status register and higher status register;
However, if CS# goes up at the eighth bit of the data byte, the data byte would be written as lower byte of
status register, without changing the higher byte of status register.
(2) Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(3) Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
(4) Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
(5) Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
(6) Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
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(7) Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
(8) Fast Word Read Quad I/O Data: the lowest address bit must be 0.
(9) Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000b, A8-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000b, A8-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000b, A8-A0= Byte Address.
(10) Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
(11) Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …)
Table of ID Definitions:
GD25Q21B
Operation Code
M7-M0
ID15-ID8
ID7-ID0
9FH
C8
40
12
90H
ABH
C8
11
11
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7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE)
and Write Status Register (WRSR), Program Security Register, Erase Security Register command. The Write
Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Program Security Register, Erase Security Register commands.
Figure 3. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
Command
04H
High-Z
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7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable
for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
SI
SO
High-Z
7.4. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will
output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 5. Read Status Register Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Command
05H or 35H
High-Z
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
MSB
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
7
MSB
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7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) (01H) command has no effect on S15, S10, S1 and S0 of the Status
Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the
Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction is
entered by driving CS# low, sending the instruction code “01h”, and then writing the status register data byte.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon
power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP3,
BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The
Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1
and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and
SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The
Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
6
Command
SI
SO
01H
Status Register in
MSB
5
4
3
2
1
0 15 14 13 12 11 10 9
8
High-Z
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7.6. Write Status Register (WRSR) (31H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command (31H) has no effect on S15 and S10 of the Status Register. CS#
must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register
(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write
Enable Latch (WEL) is reset.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction is
entered by driving CS# low, sending the instruction code “31h”, and then writing the status register data byte.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon
power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined
in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect
(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is
entered.
Figure 7. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
Command
SI
SO
31H
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register in
15 14 13 12 11 10 9 8
MSB
High-Z
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7.7. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 8. Read Data Bytes Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
8
Command
03H
High-Z
9 10
28 29 30 31 32 33 34 35 36 37 38 39
24-bit address
23 22 21
3
2
1
0
MSB
MSB
7
6
5
Data Out1
4 3 2 1
Data Out2
0
7.8. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Figure 9. Read Data Bytes at Higher Speed Sequence Diagram
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7.9. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure10. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Figure 10. Dual Output Fast Read Sequence Diagram
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7.10. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle
from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure11. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out.
Figure 11. Quad Output Fast Read Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10
Command
SI(IO0)
24-bit address
6BH
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
SCLK
3
23 22 21
SO(IO1)
CS#
28 29 30 31
2
1
0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SI(IO0)
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
7.11. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure12. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed
once, prior to the Dual I/O Fast Read command.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0)
=AXH, then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the
BBH command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode”
bits (M7-0) are any value other than AXH, the next command requires the first BBH command code, thus
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returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before
issuing normal command.
Figure 12. Dual I/O Fast Read Sequence Diagram (M7-0 = 0XH or not AXH)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Command
SI(IO0)
BBH
SO(IO1)
A23-16
A15-8
A7-0
M7-0
CS#
SCLK
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
Figure 13. Dual I/O Fast Read Sequence Diagram (M7-0 = AXH)
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
6
4
2
0
6
5
3
1
7
5
3
1
7
5
3
1
7
7
A23-16
A15-8
A7-0
4
2
0
5
3
1
M7-0
CS#
SCLK
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
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7.12. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must
be set to enable for the Quad I/O Fast read command. To ensure optimum performance the High Performance
Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0)
=AXH, then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the
EBH command code. The command sequence is shown in followed Figure15. If the “Continuous Read Mode”
bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus
returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before
issuing normal command.
Figure 14. Quad I/O Fast Read Sequence Diagram (M7-0 = 0XH or not AXH)
CS#
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
0
SCLK
1
2
3
4
5
6
7
Command
SI(IO0)
EBH
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1 Byte2
Figure 15. Quad I/O Fast Read Sequence Diagram (M7-0 = AXH)
CS#
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0 M7-0
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Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or
disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
7.13. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure16.
The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set
to enable for the Quad I/O Word Fast read command. To ensure optimum performance the High Performance
Mode (HPM) command (A3h) must be executed once, prior to the Quad I/O Word Fast Read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0)
=AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not
require the E7H command code. The command sequence is shown in followed Figure17. If the “Continuous
Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first E7H command
code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0)
before issuing normal command.
Figure 16. Quad I/O Word Fast Read Sequence Diagram (M7-0 = 0XH or not AXH)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
Command
SI(IO0)
E7H
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
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Figure 17. Quad I/O Word Fast Read Sequence Diagram (M7-0 = AXH)
CS#
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable
or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
49 - 24
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http://www.elm-tech.com
7.14. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI
mode. The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command →
Send 24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high.
W6, W5
W4=0
W4=1 (default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0, 0
0, 1
Yes
Yes
8-byte
16-byte
No
No
N/A
N/A
1, 0
1, 1
Yes
Yes
32-byte
64-byte
No
No
N/A
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and
“Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within
any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
command should be issued to set W4=1.
Figure 18. Set Burst with Wrap Sequence Diagram
CS#
8
9 10 11 12 13 14 15
x
x
x
x
x
x
4
x
SO(IO1)
x
x
x
x
x
x
5
x
WP#(IO2)
x
x
x
x
x
x
6
x
HOLD#(IO3)
x
x
x
x
x
x
x
x
SCLK
0
1
2
3
4
5
6
7
Command
SI(IO0)
77H
W6-W4
49 - 25
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.15. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is shown in Figure19.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes
are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the
Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) is not executed.
Figure 19. Page Program Sequence Diagram
49 - 26
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.16. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the
Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the
command code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure20. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, and BP0) is not executed.
Figure 20. Quad Page Program Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
8
7
24-bit address
Command
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
537
539
540
541
542
543
Byte1 Byte2
0 4
538
SI(IO0)
28 29 30 31 32 33 34 35 36 37 38 39
9 10
23 22 21
32H
2
3
1
MSB
SO(IO1)
SCLK
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11 Byte12
536
CS#
Byte256
Byte253
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
49 - 27
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GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.17. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)
command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address
inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire
duration of the sequence.
The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on
SI → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon
as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector
Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase
(SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see
Table1.) is not executed.
Figure 21. Sector Erase Sequence Diagram
CS#
SCLK
1
0
2
3
4
5
6
8
7
9
24 Bits Address
Command
SI
29 30 31
23 22
MSB
20H
0
1
2
7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address on SI→ CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.
Figure 22. 32KB Block Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
29 30 31
24 Bits Address
Command
52H
9
23 22
MSB
49 - 28
2
1
0
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.19. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte
address on SI → CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.
Figure 23. 64KB Block Erase Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9
24 Bits Address
Command
SI
29 30 31
23 22
MSB
D8H
2
1
0
7.20. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code
has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block
Protect (BP4,BP3,BP2, BP1, BP0) bits are set to “None protected”. The Chip Erase (CE) command is ignored if
one or more sectors are protected.
Figure 24. Chip Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
60H or C7H
49 - 29
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode
can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep
Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#
goes high. The command sequence is shown in Figure25. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep PowerDown Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 25. Deep Power-Down Sequence Diagram
CS#
SCLK
SI
tDP
0 1 2 3 4 5 6 7
Command
Stand-by mode Deep Power-down mode
B9H
49 - 30
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode/Device ID command is a multi-purpose command.
It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices
electronic identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving
the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from
Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal
operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27.
The Device ID value for the GD25Q21B is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the
same as previously described, except that after CS# is driven high it must remain high for a time duration of
tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down/Device ID command is issued while an Erase,
Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects
on the current cycle.
Figure 26. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
t RES1
Command
ABH
Deep Power-down mode
Stand-by mode
Figure 27. Release Power-Down and Read Device ID Sequence Diagram
49 - 31
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
7.23. Read Manufacture ID/Device ID (REMS) (90H)
http://www.elm-tech.com
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure28. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 28. Read Manufacture ID/Device ID Sequence Diagram
49 - 32
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.24. Read Manufacture ID/Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure29. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 29. Read Manufacture ID/Device ID Dual I/O Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
5
3
1
7
Command
SI(IO0)
92H
SO(IO1)
7
A23-16
4
2
0
6
5
3
1
7
A15-8
4
2
0
6
5
3
1
7
A7-0
4
2
0
5
3
1
M7-0
CS#
SCLK
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SI(IO0)
6
SO(IO1)
7
4
2
0
6
4
2
0
6
5
3
1
7
5
3
1
7
MFR ID
Device ID
4
2
0
6
4
2
0
6
5
3
1
7
5
3
1
7
MFR ID
(Repeat)
Device ID
(Repeat)
49 - 33
4
2
0
6
4
2
0
5
3
1
7
5
3
1
MFR ID
(Repeat)
Device ID
(Repeat)
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.25. Read Manufacture ID/Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure30. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 30. Read Manufacture ID/Device ID Quad I/O Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7 3 7 3
7
Command
SI(IO0)
94H
SO(IO1)
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
MFR ID DID
CS#
SCLK
24 25 26 27 28 29 30 31
SI(IO0)
4
0
SO(IO1)
5
1 5 1 5 1 5 1
WP#(IO2)
6 2 6 2 6 2 6 2
4
0 4 0 4 0
HOLD#(IO3) 7 3 7 3 7 3 7 3
MFR ID DID MFR ID DID
(Repeat)(Repeat)(Repeat)(Repeat)
49 - 34
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.26. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by
two bytes of device identification. The device identification indicates the memory type in the first byte, and the
memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase
or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read
Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure31. The Read Identification (RDID) command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute commands.
Figure 31. Read Identification ID Sequence Diagram
CS#
0
SCLK
SI
1
2
3
4
5
6
8
9 10 11 12 13 14 15
7
6
9FH
SO
CS#
7
MSB
Manufacturer ID
5 4 3 2 1
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
Memory Type ID15-ID8
6 5 4 3 2 1 0
MSB
7
Capacity ID7-ID0
6 5 4 3 2 1
0
MSB
49 - 35
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.27. High Performance Mode (HPM) (A3H)
It is recommended to execute High Performance Mode (HPM) command prior to Dual or Quad I/O commands
when operating at high frequencies (see fC in AC Electrical Characteristics). This command allows pre-charging
of internal charge pumps so the voltages required for accessing the flash memory array are readily available.
The command sequence: CS# goes low → Sending A3H command → Sending 3-dummy byte → CS# goes
high. See Figure32. After the HPM command is executed, the device will maintain a slightly higher standby
current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can
be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also
release the device from HPM mode back to deep power down state.
Figure 32. High Performance Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
Command
A3H
7
8
9
29 30 31
t HPM
3 Dummy Bytes
2
23 22
MSB
1
0
SO
High Performance Mode
7.28. Erase Security Registers (44H)
The GD25Q21B provides three 512-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command
→ CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon
as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While
the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write
in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect
the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase
Security Registers command will be ignored.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Do not care
Security Register #2
00H
0010
000
Do not care
Security Register #3
00H
0011
000
Do not care
49 - 36
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 33. Erase Security Registers command Sequence Diagram
CS#
1
0
SCLK
2
3
4
5
6
7
8
9
24 Bits Address
Command
SI
29 30 31
23 22
MSB
44H
2
1
0
7.29. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
Security Register #2
00H
00H
0001
0010
000
000
Byte Address
Byte Address
Security Register #3
00H
0011
000
Byte Address
Figure 34. Program Security Registers command Sequence Diagram
CS#
5
6
7
8
24-bit address
42H
23 22 21
3
2
Data Byte 1
0 7
1
MSB
6
5
4
3
2
1
2078
Command
SI
28 29 30 31 32 33 34 35 36 37 38 39
9 10
2079
4
2076
3
2077
2
2075
1
2074
0
SCLK
1
0
0
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
CS#
2072
MSB
7
6
SCLK
SI
Data Byte 3
Data Byte 2
7
MSB
6
5
4
3
2
1
0 7
6
5
4
3
2
MSB
Data Byte 256
1
0
5
4
3
2
MSB
49 - 37
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.30. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches the
last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Byte Address
Security Register #2
Security Register #3
00H
00H
0010
0011
000
000
Byte Address
Byte Address
Figure 35. Read Security Registers command Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
8
7
28 29 30 31
24-bit address
Command
SI
9 10
48H
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO
Dummy Byte
7
6
5
4
3
2
1
0
7 6
MSB
49 - 38
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.31. Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further
reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not
require the BBH/EBH/E7H command code.
If the system controller is reset during operation it will likely send a standard SPI command, such as Read ID
(9FH) or Fast Read (0BH), to the device. Because the GD25Q21B has no hardware reset pin, so if Continuous
Read Mode bits are set to “AXH”, the GD25Q21B will not recognize any standard SPI commands. So
Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and
allow standard SPI command to be recognized. The command sequence is show below.
Figure 36. Continuous Read Mode Reset Sequence Diagram
Mode Bit Reset for Quad/Dual I/O
CS#
0
1
2
3
4
5
6
7
SCLK
SI(IO0)
FFH
SO(IO1)
Don`t Care
WP#(IO2)
Don`t Care
HOLD#(IO3)
Don`t Care
7.32. Program/Erase Suspend (PES) (75H)
The Erase/Program Suspend instruction “75H”, allows the system to interrupt a sector/block erase or page
program operation and then read data from any other sector or block. The Write Status Register command (01H),
Page Program command (02H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during
suspend. Erase/Program Suspend is valid only during the sector/block erase or page program operation. A
maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
While the Erase/Program suspend cycle is in progress, the Read Status Register command may still be
accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Erase/Program suspend cycle
and becomes a 0 when the cycle is finished and the device is ready to accept read command. A power-off during
the suspend period will reset the device and release the suspend state. The command sequence is show below.
Figure 37. Program/Erase Suspend Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
tSUS
Command
75H
High-Z
Accept read command
49 - 39
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
7.33. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the sector/block erase or program operation
after a Program/Erase Suspend command. After issued the BUSY bit in the status register will be set to 1 and the
sector/block erase or program operation will completed. The Program/Erase Resume command will be ignored
unless a Program/Erase Suspend is active. The command sequence is show below.
Figure 38. Program/Erase Resume Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
7AH
SO
Resume Erase/Program
49 - 40
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
8. ELECTRICAL CHARACTERISTICS
8.1. Power-On Timing
Figure 39. Power-on Timing Sequence Diagram
Table3. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
tVSL
VCC(min) To CS# Low
10
tPUW
VWI
Time Delay Before Write Instruction
Write Inhibit Voltage
1
2.1
Typ
Max
Unit
us
10
2.5
2.3
ms
V
8.2. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status
Register contains 00H (all Status Register bits are 0).
8.3. Data Retention and Endurance
Parameter
Minimum Pattern Data Retention Time
Erase/Program Endurance
Test Condition
Min
Unit
150°C
10
Years
125°C
-40 to 85°C
20
100K
Years
Cycles
8.4. Latch Up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
VCC Current
49 - 41
Min
Max
-1.0V
VCC+1.0V
-100mA
100mA
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
8.5. Absolute Maximum Ratings
Parameter
Ambient Operating Temperature
Storage Temperature
Output Short Circuit Current
Applied Input/Output Voltage
VCC
0.8VCC
Input timing reference level
0.7VCC
0.2VCC
0.1VCC
Value
Unit
-40 to 85
°C
-65 to 150
°C
200
-0.5 to 4.0
mA
V
-0.5 to 4.0
V
Output timing reference level
AC Measurement Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
8.6. Capacitance Measurement Conditions
Symbol
CIN
COUT
CL
Parameter
Min
Typ
Max
Unit
Conditions
Input Capacitance
6
pF
VIN=0V
Output Capacitance
Load Capacitance
Input Rise And Fall time
8
VOUT=0V
5
pF
pF
ns
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
V
V
V
30
Input Pulse Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Figure 40. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
49 - 42
20ns
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
8.7. DC Characteristics
Symbol
(T= -40°C~85°C, VCC=2.7~3.6V)
Max.
Unit.
Input Leakage Current
±2
μA
ILO
ICC1
Output Leakage Current
Standby Current
CS#=VCC, VIN=VCC or VSS
20
±2
30
μA
μA
ICC2
Deep Power-Down Current
CS#=VCC, VIN=VCC or VSS
1
5
μA
CLK=0.1VCC/0.9VCC at 104MHz,
Q=Open(*1,*2,*4 I/O)
15
mA
CLK=0.1VCC/0.9VCC at 80MHz,
Q=Open(*1,*2,*4 I/O)
12
mA
CLK=0.1VCC/0.9VCC at 33MHz,
Q=Open(*1,*2,*4 I/O)
6
mA
ILI
ICC3
Parameter
Operating Current (Read)
Test Condition
Min.
Typ.
ICC4
Operating Current (PP)
CS#=VCC
10
15
mA
ICC5
Operating Current (WRSR) CS#=VCC
8
12
mA
ICC6
ICC7
Operating Current (SE)
Operating Current (BE)
10
10
15
15
mA
mA
ICC8
ICC9
Operating Current (CE)
High Performance Current
10
400
15
600
mA
μA
VIL
Input Low Voltage
-0.5
0.2VCC
V
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
0.7VCC
VCC+0.4
0.4
V
V
V
CS#=VCC
CS#=VCC
IOL=1.6mA
IOH=-100μA
VCC-0.2
49 - 43
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
8.8. AC Characteristics
Symbol
(T= -40°C~85°C, VCC=2.7~3.6V, CL=30pf)
Parameter
Min.
Typ.
Max.
Unit.
fC
Serial Clock Frequency For: FAST_READ, PP, SE, BE, DP,
RES, WREN, WRDI, WRSR, RDSR, RDID (*1,*2,*4 I/O)
DC.
104
MHz
fR
Serial Clock Frequency For: Read
DC.
80
MHz
tCLH
Serial Clock High Time
3.5
ns
tCLL
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
3.5
0.2
ns
V/ns
tCHCL Serial Clock Fall Time (Slew Rate)
0.2
V/ns
tSLCH CS# Active Setup Time
tCHSH CS# Active Hold Time
5
5
ns
ns
tSHCH CS# Not Active Setup Time
tCHSL CS# Not Active Hold Time
5
5
ns
ns
tSHSL CS# High Time (Read/Write)
20
ns
tCLCH
tSHQZ Output Disable Time
tCLQX Output Hold Time
6
1.2
ns
ns
2
5
ns
ns
tHLCH Hold# Low Setup Time (Relative to Clock)
3.5
ns
tHHCH Hold# High Setup Time (Relative to Clock)
tCHHL Hold# High Hold Time (Relative to Clock)
tCHHH Hold# Low Hold Time (Relative to Clock)
3.5
3.5
3.5
ns
ns
ns
tDVCH Data In Setup Time
tCHDX Data In Hold Time
tHLQZ Hold# Low To High-Z Output
tHHQX Hold# Low To Low-Z Output
tCLQV Clock Low To Output Valid
6
6
6
tWHSL Write Protect Setup Time Before CS# Low
tSHWL Write Protect Hold Time After CS# High
tDP
ns
ns
ns
20
100
ns
ns
tRES1
tRES2
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
0.1
5
5
μs
μs
μs
tHPM
tSUS
tW
CS# High To High Performance Mode
CS# High To Next Command After Suspend
Write Status Register Cycle Time
0.2
20
30
μs
μs
ms
tPP
tSE
tBE
Page Programming Time
Sector Erase Time
Block Erase Time(32K/64K)
10
0.35
2.4
50
200/400(1)
0.18/0.25 0.6/0.8
tCE Chip Erase Time
0.8
Note:
(1). Max Value tSE with <50K cycles is 200 ms and >50K & <100K cycles is 400 ms.
49 - 44
1.5
ms
ms
s
s
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure41. Serial Input Timing
tSHSL
CS#
tCHSL
SCLK
tSLCH
tDVCH
tCHSH
MSB
SO
High-Z
tCHCL
tCLCH
tCHDX
SI
tSHCH
LSB
Figure42. Output Timing
CS#
tCLH
SCLK
tCLQV
tCLQX
tCLQV
tSHQZ
tCLL
tCLQX
LSB
SO
SI
Least significant address bit (LIB) in
Figure43. Hold Timing
CS#
SCLK
SO
tCHHL
tHLCH
tCHHH
tHLQZ
tHHCH
tHHQX
HOLD#
SI do not care during HOLD operation.
49 - 45
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
9. ORDERING INFORMATION
GD 25 Q 21 B x I G x
Packing Type
Y: Tray
R: Tape & Reel
Green Code
G: Pb Free & Halogen Free Green Package
Temperature Range
I: Industrial(-40°C to +85°C)
Package Type
T: SOP8 150mil
S: SOP8 208mil
U: USON8 (3×2mm)
Generation
B: Version
Density
21: 2Mb
Series
Q: 2.7~3.6V, 4KB Uniform Sector, Quad I/O
Product Family
25: Serial Flash
49 - 46
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
10. PACKAGE INFORMATION
10.1 Package SOP8 150MIL
8
�
5
E1
E
L
1
4
L1
C
D
A2
A1
b
e
A
Seating plane
0.10
Dimensions
Symbol
Unit
A
A1
A2
b
1.35
-
0.05
-
1.35 0.31
-
c
D
0.15
-
4.77
4.90
E
E1
e
L
L1
θ
ɑ
ß
mm
Min
Nom
1.27
0.40
-
0.85
1.06
0°
-
6°
7°
11°
12°
Inch
Max 1.75 0.25 1.55 0.51 0.25 5.03 6.20 4.00
0.90 1.27
Min 0.053 0.002 0.053 0.012 0.006 0.188 0.228 0.149 - 0.016 0.033
Nom
- 0.016 - 0.193 0.236 0.154 0.050 0 0.042
8°
0°
-
8°
6°
7°
13°
11°
12°
8°
8°
13°
5.80 3.80
6.00 3.90
Max 0.069 0.010 0.061 0.020 0.010 0.198 0.244 0.158
Note: Both package length and width do not include mold flash.
49 - 47
-
0.035 0.050
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
10.2 Package SOP8 208MIL
8
�
5
E1
E
L1
L
1
4
C
D
A2
Dimensions
Symbol
A1
b
e
A
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
2.16
0.05
0.15
0.25
1.70
1.80
1.91
0.31
0.41
0.51
0.18
0.21
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
1.27
-
0.50
0.67
0.85
1.21
1.31
1.41
0°
5°
8°
Min
0.002 0.067 0.012 0.007 0.202 0.303
Inch Nom
0.006 0.071 0.016 0.008 0.206 0.311
Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319
Note: Both package length and width do not include mold flash.
0.204
0.208
0.212
0.050
-
0.020
0.026
0.033
0.048
0.052
0.056
0°
5°
8°
Unit
mm
Min
Nom
Max
49 - 48
Rev.1.1
GD25Q21BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
10.3 Package USON8 (3×2mm)
D
A2
E
y
A
Top View
A1
Side View
D1
L
1
b
E1
e
Bottom View
Dimensions
Symbol
A
A1
A2
b
D
D1
E
E1
e
y
L
0.50
0.55
0.60
0.05
0.13
0.15
0.18
0.18
0.25
0.30
2.90
3.00
3.10
0.15
0.20
0.30
1.90
2.00
2.10
1.50
1.60
1.70
0.50
-
0.00
0.05
0.30
0.35
0.45
Min
0.020
0.005 0.007 0.114 0.006
Inch
Nom
0.022
0.006 0.010 0.118 0.008
Max
0.024 0.002 0.007 0.012 0.122 0.012
Note: Both package length and width do not include mold flash.
0.075
0.079
0.083
0.059
0.063
0.067
0.020
-
0.000
0.002
0.012
0.014
0.018
Unit
mm
Min
Nom
Max
49 - 49
Rev.1.1
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