ON MTB50N06VT4 Nâ channel power mosfet Datasheet

MTB50N06V
Preferred Device
Power MOSFET
42 Amps, 60 Volts
N−Channel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
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42 AMPERES
60 VOLTS
RDS(on) = 28 mΩ
N−Channel
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−Source Voltage
VDSS
60
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 25
Vdc
Vpk
ID
ID
42
30
147
Adc
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 1)
PD
125
0.83
3.0
Watts
W/°C
Watts
Operating and Storage Temperature
Range
TJ, Tstg
− 55 to
175
°C
MARKING DIAGRAM
& PIN ASSIGNMENT
EAS
400
mJ
4
Drain
RθJC
RθJA
RθJA
1.2
62.5
50
°C/W
MTB50N06V
AYWW
TL
260
Rating
Drain Current − Continuous @ 25°C
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 μs)
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 42 Apk, L = 0.454 μH, RG = 25 Ω)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
IDM
Apk
G
S
4
2
1
3
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
D2PAK
CASE 418B
STYLE 2
1
Gate
A
Y
WW
2
Drain
3
Source
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB50N06V
D2PAK
50 Units/Rail
MTB50N06VT4
D2PAK
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 5
1
Publication Order Number:
MTB50N06V/D
MTB50N06V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
−
69
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
2.7
3.0
4.0
−
Vdc
mV/°C
−
0.025
0.028
Ohm
−
−
1.4
−
1.7
1.6
gFS
16
23
−
mhos
Ciss
−
1644
2320
pF
Coss
−
465
660
Crss
−
112
230
td(on)
−
12
20
tr
−
122
250
td(off)
−
64
110
tf
−
54
90
QT
−
47
70
Q1
−
9
−
Q2
−
21
−
Q3
−
16
−
−
−
1.06
0.99
2.5
−
trr
−
84
−
ta
−
73
−
tb
−
11
−
QRR
−
0.28
−
−
−
3.5
4.5
−
−
−
7.5
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
μAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 21 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 42 Adc)
(ID = 21 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
(VDD = 25 Vdc, ID = 42 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 42 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 2)
(IS = 42 Adc, VGS = 0 Vdc)
(IS = 42 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(See Figure 14)
(IS = 42 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored
Charge
VSD
Vdc
ns
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
nH
nH
MTB50N06V
TYPICAL ELECTRICAL CHARACTERISTICS
100
9V
7V
60
6V
40
5V
20
0
1.6
0.8
2.4
3.2
25°C
60
TJ = − 55°C
40
20
1
3
2
5
4
7
6
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
TJ = 100°C
25°C
0.022
0.016
− 55°C
0
20
40
60
80
100
0.033
9
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.028
TJ = 25°C
0.03
0.027
VGS = 10 V
15 V
0.024
0.021
20
0
40
60
80
100
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
2.5
2
VGS = 0 V
VGS = 10 V
ID = 21 A
TJ = 125°C
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
100°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.034
0.01
80
0
4
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.04
VDS ≥ 10 V
8V
80
0
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
VGS = 10 V
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
100
1.5
1
100
100°C
10
25°C
0.5
0
− 50
− 25
0
25
50
75
100
125
150
1
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
60
MTB50N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
VDS = 0 V
5000
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Crss
2000
Ciss
1000
Coss
Crss
0
10
5
5
0
VGS
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
56
12
48
QT
10
40
VGS
8
Q1
32
Q2
6
24
ID = 42 A
TJ = 25°C
4
16
8
2
0
Q3
0
10
VDS
20
30
QT, TOTAL CHARGE (nC)
40
0
50
1000
t, TIME (ns)
14
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTB50N06V
VDD = 25 V
ID = 42 A
VGS = 10 V
TJ = 25°C
100
tr
tf
td(off)
10
td(on)
1
1
10
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.5
0.6
0.7
0.8
0.9
1
1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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5
MTB50N06V
SAFE OPERATING AREA
400
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10μs
10
100μs
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
dc
1ms
10ms
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
ID = 42 A
320
240
160
80
0
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
175
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
0.05
0.1
P(pk)
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
0.02
0.01
t1
SINGLE PULSE
0.01
1.0E−05
t2
DUTY CYCLE, D = t1/t2
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
3
PD, POWER DISSIPATION (WATTS)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
2.5
2.0
1.5
1
0.5
0
IS
RθJA = 50°C/W
Board material = 0.065 mil FR−4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (°C)
Figure 15. D2PAK Power Derating Curve
Figure 14. Diode Reverse Recovery Waveform
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6
175
MTB50N06V
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
4
1
2
3
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
A
S
−T−
SEATING
PLANE
V
W
K
J
G
D 3 PL
0.13 (0.005)
W
H
M
T B
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm Ǔ
ǒinches
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