LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 LM6132/LM6134 Dual and Quad Low Power 10 MHz Rail-to-Rail I/O Operational Amplifiers Check for Samples: LM6132 FEATURES DESCRIPTION • • • • • • • • • • The LM6132/34 provides new levels of speed vs. power performance in applications where low voltage supplies or power limitations previously made compromise necessary. With only 360 μA/amp supply current, the 10 MHz gain-bandwidth of this device supports new portable applications where higher power devices unacceptably drain battery life. 1 2 (For 5V Supply, Typ Unless Noted) Rail-to-Rail Input CMVR −0.25V to 5.25V Rail-to-Rail Output Swing 0.01V to 4.99V High Gain-Bandwidth, 10 MHz at 20 kHz Slew Rate 12 V/μs Low Supply Current 360 μA/Amp Wide Supply Range 2.7V to over 24V CMRR 100 dB Gain 100 dB with RL = 10k PSRR 82 dB APPLICATIONS • • • • • Battery Operated Instrumentation Instrumentation Amplifiers Portable Scanners Wireless Communications Flat Panel Display Driver The LM6132/34 can be driven by voltages that exceed both power supply rails, thus eliminating concerns over exceeding the common-mode voltage range. The rail-to-rail output swing capability provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. The LM6132/34 can also drive large capacitive loads without oscillating. Operating on supplies from 2.7V to over 24V, the LM6132/34 is excellent for a very wide range of applications, from battery operated systems with large bandwidth requirements to high speed instrumentation. Connection Diagram Figure 1. 8-Pin SOIC/PDIP (Top View) See Package Number D and P Figure 2. 14-Pin SOIC/PDIP (Top View) See Package Number D and NFF0014A These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com Absolute Maximum Ratings (1) (2) ESD Tolerance (3) 2500V Differential Input Voltage 15V (V+)+0.3V, (V−)−0.3V Voltage at Input/Output Pin Supply Voltage (V+–V−) 35V Current at Input Pin ±10 mA Current at Output Pin (4) ±25 mA Current at Power Supply Pin 50 mA Lead Temp. (soldering, 10 sec.) 260°C −65°C to +150°C Storage Temperature Range Junction Temperature (5) (1) (2) (3) (4) (5) 150°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Human body model, 1.5 kΩ in series with 100 pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/θJA. All numbers apply for packages soldered directly into a PC board. Operating Ratings (1) 1.8V ≤ V+ ≤ 24V Supply Voltage −40°C ≤ TJ ≤ +85°C Junction Temperature Range LM6132, LM6134 Thermal resistance (θJA) P Package, 8-pin PDIP 115°C/W D Package, 8-pin SOIC 193°C/W NFF0014A Package, 14-pin PDIP D Package, 14-pin SOIC (1) 2 81°C/W 126°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical characteristics. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 5.0V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes Symbol Parameter Conditions LM6134AI LM6132AI Limit LM6134BI LM6132BI Limit 2 4 6 8 110 140 300 180 350 nA max 3.4 30 50 30 50 nA max Typ (1) (2) VOS Input Offset Voltage TCVOS Input Offset Voltage Average Drift IB Input Bias Current IOS Input Offset Current RIN Input Resistance, CM CMRR Common Mode Rejection Ratio 0.25 104 100 75 70 75 70 0V ≤ VCM ≤ 5V 80 60 55 60 55 ±2.5V ≤ V+ ≤ ±12V 82 78 75 78 75 dB min −0.25 5.25 0 5.0 0 5.0 V 100 25 8 15 6 V/mV min 4.992 4.98 4.93 4.98 4.93 V min 0.007 0.017 0.019 0.017 0.019 V max 4.952 4.94 4.85 4.94 4.85 V min 0.032 0.07 0.09 0.07 0.09 V max 4.923 4.90 4.85 4.90 4.85 V min 0.051 0.095 0.12 0.095 0.12 V max 4 2 2 2 1 mA min 3.5 1.8 1.8 1.8 1 mA min 3 2 1.6 2 1 mA min 3.5 1.8 1.3 1.8 1 mA min 400 450 400 450 μA max Power Supply Rejection Ratio VCM Input Common-Mode Voltage Range AV Large Signal Voltage Gain RL = 10k VO Output Swing 100k Load 10k Load 5k Load Output Short Circuit Current LM6132 Sourcing Sinking ISC Output Short Circuit Current LM6134 Sourcing Sinking IS (1) (2) Supply Current MΩ 0V ≤ VCM ≤ 4V PSRR ISC mV max μV/C 5 0V ≤ VCM ≤ 5V Units (2) Per Amplifier 360 dB min Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 3 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com 5.0V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5.0V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes Symbol Parameter Conditions LM6134AI LM6132AI Limit LM6134BI LM6132BI Limit 14 8 7 8 7 V/μs min 10 7.4 7 7.4 7 MHz min Typ (1) (2) Units (2) SR Slew Rate ±4V @ VS = ±6V RS < 1 kΩ GBW Gain-Bandwidth Product f = 20 kHz θm Phase Margin RL = 10k 33 deg Gm Gain Margin RL = 10k 10 dB en Input Referred Voltage Noise f = 1 kHz 27 nV/√Hz in Input Referred Current Noise f = 1 kHz 0.18 pA/√Hz (1) (2) Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme Symbol Parameter Conditions Typ (1) LM6134AI LM6132AI Limit LM6134BI LM6132BI Limit 2 8 6 12 (2) 0.12 Units (2) VOS Input Offset Voltage IB Input Bias Current IOS Input Offset Current 2.8 nA RIN Input Resistance 134 MΩ CMRR Common Mode Rejection Ratio 82 dB 0V ≤ VCM ≤ 2.7V 0V ≤ VCM ≤ 2.7V + ±1.35V ≤ V ≤ ±12V PSRR Power Supply Rejection Ratio VCM Input Common-Mode Voltage Range AV Large Signal Voltage Gain RL = 10k VO Output Swing RL = 100k IS (1) (2) Supply Current Per Amplifier 90 mV max nA 80 dB 2.7 0 2.7 0 0.03 0.08 0.112 0.08 0.112 V max 2.66 2.65 2.25 2.65 2.25 V min 100 V V/mV μA 330 Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. 2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Symbol Parameter Conditions Typ (1) LM6134AI LM6132AI Limit (2) LM6134BI LM6132BI Limit Units (2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 7 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin 12 dB (1) (2) 4 Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 24V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extreme Symbol Parameter Conditions Typ (1) LM6134AI LM6132AI Limit LM6134BI LM6132BI Limit 3 5 7 9 (2) 1.7 Units (2) VOS Input Offset Voltage IB Input Bias Current IOS Input Offset Current 4.8 nA RIN Input Resistance 210 MΩ CMRR Common Mode Rejection Ratio 80 dB 0V ≤ VCM ≤ 24V 0V ≤ VCM ≤ 24V + 2.7V ≤ V ≤ 24V PSRR Power Supply Rejection Ratio VCM Input Common-Mode Voltage Range AV Large Signal Voltage Gain RL = 10k VO Output Swing RL = 10k IS (1) (2) Supply Current 125 Per Amplifier nA 82 −0.25 24.25 mV max dB 0 24 0 24 102 V min V max V/mV 0.075 23.86 0.15 23.8 0.15 23.8 390 450 490 450 490 V max V min μA max Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. 24V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 24V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Symbol Parameter Conditions Typ (1) LM6134AI LM6132AI Limit (2) LM6134BI LM6132BI Limit Units (2) GBW Gain-Bandwidth Product RL = 10k, f = 20 kHz 11 MHz θm Phase Margin RL = 10k 23 deg Gm Gain Margin RL = 10k 12 dB THD + N Total Harmonic Distortion and Noise AV = +1, VO = 20VP-P f = 10 kHz 0.0015 % (1) (2) Typical Values represent the most likely parametric normal. All limits are guaranteed by testing or statistical analysis. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 5 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics TA = 25°C, RL = 10 kΩ unless otherwise specified 6 Supply Current vs. Supply Voltage Offset Voltage vs. Supply Voltage Figure 3. Figure 4. dVOS vs. VCM dVOS vs. VCM Figure 5. Figure 6. dVOS vs. VCM IBIAS vs. VCM Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) TA = 25°C, RL = 10 kΩ unless otherwise specified IBIAS vs. VCM IBIAS vs. VCM Figure 9. Figure 10. Input Bias Current vs. Supply Voltage Negative PSRR vs. Frequency Figure 11. Figure 12. Positive PSSR vs. Frequency dVOS vs. Output Voltage Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 7 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) TA = 25°C, RL = 10 kΩ unless otherwise specified 8 dVOS vs. Output Voltage dVOS vs. Output Voltage Figure 15. Figure 16. CMRR vs. Frequency Output Voltage vs. Sinking Current Figure 17. Figure 18. Output Voltage vs. Sinking Current Output Voltage vs. Sinking Current Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) TA = 25°C, RL = 10 kΩ unless otherwise specified Output Voltage vs. Sourcing Current Output Voltage vs. Sourcing Current Figure 21. Figure 22. Output Voltage vs. Sourcing Current Noise Voltage vs. Frequency Figure 23. Figure 24. Noise Current vs. Frequency NF vs. Source Resistance Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 9 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) TA = 25°C, RL = 10 kΩ unless otherwise specified 10 Gain and Phase vs. Frequency Gain and Phase vs. Frequency Figure 27. Figure 28. Gain and Phase vs. Frequency GBW vs. Supply Voltage at 20 kHz Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 LM6132/34 APPLICATION INFORMATION The LM6132 brings a new level of ease of use to op amp system design. With greater than rail-to-rail input voltage range concern over exceeding the common-mode voltage range is eliminated. Rail-to-rail output swing provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. The high gain-bandwidth with low supply current opens new battery powered applications, where high power consumption, previously reduced battery life to unacceptable levels. To take advantage of these features, some ideas should be kept in mind. ENHANCED SLEW RATE Unlike most bipolar op amps, the unique phase reversal prevention/speed-up circuit in the input stage eliminates phase reversal and allows the slew rate to be very much a function of the input signal amplitude. Figure 32 shows how excess input signal is routed around the input collector-base junctions directly to the current mirrors. The LM6132/34 input stage converts the input voltage change to a current change. This current change drives the current mirrors through the collectors of Q1–Q2, Q3–Q4 when the input levels are normal. If the input signal exceeds the slew rate of the input stage and the differential input voltage rises above a diode drop, the excess signal bypasses the normal input transistors, (Q1–Q4), and is routed in correct phase through the two additional transistors, (Q5, Q6), directly into the current mirrors. This rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 31). As the overdrive increases, the op amp reacts better than a conventional op amp. Large fast pulses will raise the slew- rate to around 25V to 30 V/μs. Slew Rate vs. Differential VIN VS = ±12V Figure 31. This effect is most noticeable at higher supply voltages and lower gains where incoming signals are likely to be large. This speed-up action adds stability to the system when driving large capacitive loads. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 11 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com DRIVING CAPACITIVE LOADS Capacitive loads decrease the phase margin of all op amps. This is caused by the output resistance of the amplifier and the load capacitance forming an R-C phase lag network. This can lead to overshoot, ringing and oscillation. Slew rate limiting can also cause additional lag. Most op amps with a fixed maximum slew-rate will lag further and further behind when driving capacitive loads even though the differential input voltage raises. With the LM6132, the lag causes the slew rate to raise. The increased slew-rate keeps the output following the input much better. This effectively reduces phase lag. After the output has caught up with the input, the differential input voltage drops down and the amplifier settles rapidly. Figure 32. These features allow the LM6132 to drive capacitive loads as large as 500 pF at unity gain and not oscillate. The scope photos (Figure 33 and Figure 34) above show the LM6132 driving a 500 pF load. In Figure 33 , the lower trace is with no capacitive load and the upper trace is with a 500 pF load. Here we are operating on ±12V supplies with a 20 VPP pulse. Excellent response is obtained with a Cf of 39 pF. In Figure 34, the supplies have been reduced to ±2.5V, the pulse is 4 VPP and CF is 39 pF. The best value for the compensation capacitor should be established after the board layout is finished because the value is dependent on board stray capacity, the value of the feedback resistor, the closed loop gain and, to some extent, the supply voltage. Another effect that is common to all op amps is the phase shift caused by the feedback resistor and the input capacitance. This phase shift also reduces phase margin. This effect is taken care of at the same time as the effect of the capacitive load when the capacitor is placed across the feedback resistor. The circuit shown in Figure 35 was used for these scope photos. Figure 33. 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 Figure 34. Figure 35. Figure 36 shows a method for compensating for load capacitance (CO) effects by adding both an isolation resistor RO at the output and a feedback capacitor CFdirectly between the output and the inverting input pin. Feedback capacitor CF compensates for the pole introduced by RO and CO, minimizing ringing in the output waveform while the feedback resistor RF compensates for dc inaccuracies introduced by RO. Depending on the size of the load capacitance, the value of ROis typically chosen to be between 100Ω to 1 kΩ. Figure 36. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 13 LM6132 SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 www.ti.com Typical Applications 3 OP AMP INSTRUMENTATION AMP WITH RAIL-TO-RAIL INPUT AND OUTPUT Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made. These features make these instrumentation amplifiers ideal for single supply systems. Some manufacturers use a precision voltage divider array of 5 resistors to divide the common-mode voltage to get an input range of rail-to-rail or greater. The problem with this method is that it also divides the signal, so to even get unity gain, the amplifier must be run at high closed loop gains. This raises the noise and drift by the internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMR as well. Using the LM6134, all of these problems are eliminated. In this example, amplifiers A and B act as buffers to the differential stage (Figure 37). These buffers assure that the input impedance is over 100 MΩ and they eliminate the requirement for precision matched resistors in the input stage. They also assure that the difference amp is driven from a voltage source. This is necessary to maintain the CMR set by the matching of R1–R2 with R3–R4. Figure 37. FLAT PANEL DISPLAY BUFFERING Three features of the LM6132/34 make it a superb choice for TFT LCD applications. First, its low current draw (360 μA per amplifier @ 5V) makes it an ideal choice for battery powered applications such as in laptop computers. Second, since the device operates down to 2.7V, it is a natural choice for next generation 3V TFT panels. Last, but not least, the large capacitive drive capability of the LM6132 comes in very handy in driving highly capacitive loads that are characteristic of LCD display drivers. The large capacitive drive capability of the LM6132/34 allows it to be used as buffers for the gamma correction reference voltage inputs of resistor-DAC type column (Source) drivers in TFT LCD panels. This amplifier is also useful for buffering only the center reference voltage input of Capacitor-DAC type column (Source) drivers such as the LMC750X series. Since for VGA and SVGA displays, the buffered voltages must settle within approximately 4 μs, the well known technique of using a small isolation resistor in series with the amplifier's output very effectively dampens the ringing at the output. With its wide supply voltage range of 2.7V to 24V), the LM6132/34 can be used for a diverse range of applications. The system designer is thus able to choose a single device type that serves many sub-circuits in the system, eliminating the need to specify multiple devices in the bill of materials. Along with its sister parts, the LM6142 and LM6152 that have the same wide supply voltage capability, choice of the LM6132 in a design eliminates the need to search for multiple sources for new designs. 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 LM6132 www.ti.com SNOS751D – APRIL 2000 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision C (February 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM6132 15 PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM6132AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61 32AIM LM6132AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61 32AIM LM6132AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32AIM LM6132BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61 32BIM LM6132BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61 32BIM LM6132BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61 32BIM LM6132BIN LIFEBUY PDIP P 8 40 TBD Call TI Call TI -40 to 85 LM6132 BIN LM6132BIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6132 BIN LM6134AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134AIM LM6134AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134AIMX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LM6134AIM LM6134AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM LM6134BIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134BIM LM6134BIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM LM6134BIN LIFEBUY PDIP NFF 14 25 TBD Call TI Call TI -40 to 85 LM6134BIN LM6134BIN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LM6134BIN Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2014 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM6132AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM6132AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM6132BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM6132BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM6134AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LM6134AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LM6134BIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM6132AIMX SOIC D 8 2500 367.0 367.0 35.0 LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX SOIC D 8 2500 367.0 367.0 35.0 LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM6134AIMX SOIC D 14 2500 367.0 367.0 35.0 LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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