on C EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet The Blue Gecko Bluetooth Smart family of SoCs is part of the Wireless Gecko portfolio. Blue Gecko SoCs are ideal for enabling energy-friendly Bluetooth Smart networking for IoT devices. KEY FEATURES • 32-bit ARM® Cortex®-M4 core with 40 MHz maximum operating frequency • Scalable Memory and Radio configuration options available in footprint-compatible CSP packaging Blue Gecko applications include: • 12-channel Peripheral Reflex System enabling autonomous interaction of MCU peripherals IoT Sensors and End Devices Health and Wellness Home and Building Automation Accessories Human Interface Devices Metering Commercial and Retail Lighting and Sensing Clock Management Memory Protection Unit RAM Memory Debug Interface DMA Controller Energy Management High Frequency RC Oscillator Voltage Regulator Voltage Monitor CRYPTO Low Frequency RC Oscillator Auxiliary High Frequency RC Oscillator DC-DC Converter Power-On Reset CRC Low Frequency Crystal Oscillator Ultra Low Frequency RC Oscillator Brown-Out Detector 32-bit bus FRC DEMOD LNA PGA IFADC I/O Ports Timers and Triggers External Interrupts Timer/Counter Protocol Timer ADC Low Energy UARTTM General Purpose I/O Low Energy Timer Watchdog Timer Analog Comparator I2C Pin Reset Pulse Counter Real Time Counter and Calendar IDAC AGC Frequency Synthesizer RAC Q Analog I/F USART RF Frontend PA CRC BALUN I BUFC Serial Interfaces l Radio Transceiver Other High Frequency Crystal Oscillator Peripheral Reflex System RFSENSE • Integrated DC-DC with RF noise mitigation tia Flash Program Memory • Integrated 2.4 GHz balun and PA with up to 19.5 dBm transmit power • Also Available: Certified modules with compatible tools and software Core / Memory ARM CortexTM M4 processor with DSP extensions and FPU • Autonomous Hardware Crypto Accelerator and Random Number Generator en • • • • • • • fid The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup times, a scalable power amplifier, an integrated balun and no-compromise MCU features. MOD Pin Wakeup Cryotimer Lowest power mode with peripheral operational: EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop silabs.com | Smart. Connected. Energy-friendly. This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). EM4—Hibernate EM4—Shutoff Preliminary Rev. 1.1 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Feature List 1. Feature List The EFR32BG1 highlighted features are listed below. • Wide selection of MCU peripherals • 12-bit 1 Msps SAR Analog to Digital Converter (ADC) • 2× Analog Comparator (ACMP) • Digital to Analog Current Converter (IDAC) • Up to 19 pins connected to analog channels (APORT) shared between Analog Comparators, ADC, and IDAC • Up to 19 General Purpose I/O pins with output state retention and asynchronous interrupts • 8 Channel DMA Controller • 12 Channel Peripheral Reflex System (PRS) • 2×16-bit Timer/Counter • 3 + 4 Compare/Capture/PWM channels • 32-bit Real Time Counter and Calendar • 16-bit Low Energy Timer for waveform generation • 32-bit Ultra Low Energy Timer/Counter for periodic wake-up from any Energy Mode • 16-bit Pulse Counter with asynchronous operation • Watchdog Timer with dedicated RC oscillator @ 50nA • 2×Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S) • Low Energy UART (LEUART™) fid on C • Low Power Wireless System-on-Chip. • High Performance 32-bit 40 MHz ARM Cortex®-M4 with DSP instruction and floating-point unit for efficient signal processing • Up to 256 kB flash program memory • Up to 32 kB RAM data memory • 2.4 GHz radio operation • TX power up to 19.5 dBm • Low Energy Consumption • 8.7 mA RX current at 2.4 GHz • 8.2 mA TX current @ 0 dBm output power at 2.4 GHz • 63 μA/MHz in Active Mode (EM0) • 2.5 μA EM2 DeepSleep current (full RAM retention and RTCC running from LFXO) • 0.58 μA EM4H Hibernate Mode (128 byte RAM retention) • Wake on Radio with signal strength detection, preamble pattern detection, frame detection and timeout • High Receiver Performance • -91 dBm sensitivity @ 1 Mbit/s GFSK (2.4GHz) • Supported Modulation Format • GFSK • 2-FSK / 4-FSK with fully configurable shaping (EFR32BG1P OPNs) • Shaped OQPSK / (G)MSK (EFR32BG1P OPNs) • Configurable DSSS and FEC (EFR32BG1P OPNs) • Supported Protocol: • Bluetooth® Smart tia en • Proprietary Protocols (EFR32BG1P OPNs) • Support for Internet Security • General Purpose CRC • Random Number Generation • Hardware Cryptographic Acceleration for AES 128/256, SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC • I2C interface with SMBus support and address recognition in EM3 Stop • Wide Operating Range • 1.85 V to 3.8 V single power supply • Integrated DC-DC, down to 1.8 V output with up to 200 mA load current for system • -40 °C to 85 °C • 43-pin CSP 3.3x3.14 mm Package l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 1 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Ordering Information 2. Ordering Information Ordering Code Protocol Stack Frequency Band Flash (kB) RAM (kB) 2.4 GHz @ 19.5 dBm 256 32 @ Max TX Power EFR32BG1P332F256GJ43-C0 • Bluetooth Smart • Proprietary EFR32BG1B232F256GJ43-C0 Bluetooth Smart 2.4 GHz @ 10.5 dBm 256 32 EFR32BG1V132F256GJ43-C0 Bluetooth Smart 2.4 GHz @ 0 dBm 256 16 C EFR32 X G 1 P 132 F 256 G M 32 – C0 R on Tape and Reel (Optional) Revision Pin Count Package – M (QFN), J (CSP) Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C) Flash Memory Size in kB fid Memory Type (Flash) Feature Set Code – r2r1r0 r2: Reserved r1: RF Type – 3 (TRX), 2 (RX), 1 (TX) r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band) Performance Grade – P (Performance), B (Basic), V (Value) Series Gecko en Family – M (Mighty), B (Blue), F (Flex) Wireless Gecko 32-bit Figure 2.1. OPN Decoder tia l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 2 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3. System Overview 3.1 Introduction The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual. A block diagram of the EFR32BG1 family is shown in Figure 3.1 Detailed EFR32BG1 Block Diagram on page 3. The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Ordering Information. Port I/O Configuration RF Frontend I IFADC PGA FRC DEMOD BUFC C Digital Peripherals LETIMER PA Frequency Synthesizer Q AGC MOD Energy Management RFVDD Voltage Monitor DVDD USART Up to 256 KB ISP Flash Program Memory LEUART Memory Protection Unit Floating Point Unit bypass VREGSW RTC / RTCC ARM Cortex-M4 Core DC-DC Converter DECOUPLE RESETn Watchdog Timer Brown Out / Power-On Reset ULFRCO AUXHFRCO LFRCO HFRCO HFXTAL_P A A H P B B CRYPTO CRC Analog Peripherals Internal Reference VDD LFXTAL_P / N LFXO HFXO HFXTAL_N PBn Port C Drivers PCn Port D Drivers PDn Port F Drivers PFn IDAC VREF Clock Management Reset Management Unit Port B Drivers en VSS VREGVSS RFVSS PAVSS Serial Wire Debug / Programming PAn Port Mapper DMA Controller Voltage Regulator Port A Drivers I2C Up to 32 KB RAM AVDD VREGVDD PCNT fid IOVDD CRYOTIMER 12-bit ADC VDD APORT PAVDD IOVDD TIMER RAC BALUN CRC 2G4RF_IOP 2G4RF_ION on LNA Input MUX RFSENSE Radio Transciever Temp Sensor + Analog Comparator tia Figure 3.1. Detailed EFR32BG1 Block Diagram 3.2 Radio The Blue Gecko family features a radio transceiver supporting Bluetooth Smart® and proprietary short range wireless protocols. l 3.2.1 Antenna Interface The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The 2G4RF_ION pin should be grounded externally. The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching Networks section. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 3 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.2.2 Fractional-N Frequency Synthesizer The EFR32BG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly generate the modulated RF carrier. The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to optimize system energy consumption. 3.2.3 Receiver Architecture C The EFR32BG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC). The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, providing flexibility with respect to known interferers at the image frequency. on The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity and blocking performance. Devices are production-calibrated to improve image rejection performance. Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow receive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS). 3.2.4 Transmitter Architecture fid A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF channel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received frame and the dynamic RSSI measurement can be monitored throughout reception. The EFR32BG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shaping. en Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by the EFR32BG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth between devices that otherwise lack synchronized RF channel access. 3.2.5 Wake on Radio The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, using a subsystem of the EFR32BG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals. tia 3.2.6 RFSENSE The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4. RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy consumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by enabling normal RF reception. l Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using available timer peripherals. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 4 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.2.7 Flexible Frame Handling 3.2.8 Packet and State Trace fid on C EFR32BG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols. The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodulator: • Highly adjustable preamble length • Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts • Frame disassembly and address matching (filtering) to accept or reject frames • Automatic ACK frame assembly and transmission • Fully flexible CRC generation and verification: • Multiple CRC values can be embedded in a single frame • 8, 16, 24 or 32-bit CRC value • Configurable CRC bit and byte ordering • Selectable bit-ordering (least significant or most significant bit first) • Optional data whitening • Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding • Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing • Optional symbol interleaving, typically used in combination with FEC • Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware • UART encoding over air, with start and stop bit insertion / removal • Test mode support, such as modulated or unmodulated carrier output • Received frame timestamping The EFR32BG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It features: • Non-intrusive trace of transmit data, receive data and state information • Data observability on a single-pin UART data output, or on a two-pin SPI data output • Configurable data output bitrate / baudrate • Multiplexed transmitted data, received data and state / meta information in a single serial data stream en 3.2.9 Data Buffering The EFR32BG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64 bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations. 3.2.10 Radio Controller (RAC) 3.2.11 Random Number Generator tia The Radio Controller controls the top level state of the radio subsystem in the EFR32BG1. It performs the following tasks: • Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry • Run-time calibration of receiver, transmitter and frequency synthesizer • Detailed frame transmission timing, including optional LBT or CSMA-CA l The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain. The data is suitable for use in cryptographic applications. Output from the random number generator can be used either directly or as a seed or entropy source for software-based random number generator algorithms such as Fortuna. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 5 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.3 Power The EFR32BG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor. AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components. Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB components, supplying up to a total of 200 mA. 3.3.1 Energy Management Unit (EMU) C The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold. on 3.3.2 DC-DC Converter fid The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2 and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients. 3.4 General Purpose Input/Output (GPIO) EFR32BG1 has up to 19 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts. 3.5.1 Clock Management Unit (CMU) en 3.5 Clocking 3.5.2 Internal and External Oscillators tia The Clock Management Unit controls oscillators and clocks in the EFR32BG1. Individual enabling and disabling of clocks to all peripheral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators. l The EFR32BG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below. • A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can also be applied to the HFXO input for improved accuracy over temperature. • A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes. • An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range. • An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial Wire debug port with a wide frequency range. • An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required. • An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 6 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.6 Counters/Timers and PWM 3.6.1 Timer/Counter (TIMER) TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit TIMER_0 only. C 3.6.2 Real Time Counter and Calendar (RTCC) The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes. on 3.6.3 Low Energy Timer (LETIMER) The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC. fid 3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation. en 3.6.5 Pulse Counter (PCNT) The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. 3.6.6 Watchdog Timer (WDOG) 3.7 Communications and Other Digital Peripherals 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) tia The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by PRS. l The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting: • ISO7816 SmartCards • IrDA • I2S silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 7 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication possible with a minimum of software intervention and energy consumption. 3.7.3 Inter-Integrated Circuit Interface (I2C) C The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated transfers. Automatic recognition of slave addresses is provided in active and low energy modes. 3.7.4 Peripheral Reflex System (PRS) on The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement. Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows peripheral to act autonomously without waking the MCU core, saving power. 3.8 Security Features 3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) fid The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the needs of the application. 3.8.2 Crypto Accelerator (CRYPTO) The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256). en Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM. Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233. The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations. 3.9.1 Analog Port (APORT) tia 3.9 Analog The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped by X/Y pairs. l 3.9.2 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the programmable threshold. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 8 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.9.3 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. 3.9.4 Digital to Analog Current Converter (IDAC) The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of various step sizes. C 3.10 Reset Management Unit (RMU) The RMU is responsible for handling reset of the EFR32BG1. A wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset. on 3.11 Core and Memory 3.11.1 Processor Core fid The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: • ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz • Memory Protection Unit (MPU) supporting up to 8 memory segments • Up to 256 kB flash program memory • Up to 32 kB RAM data memory • Configuration and event handling of all modules • 2-pin Serial-Wire debug interface 3.11.2 Memory System Controller (MSC) 3.11.3 Linked Direct Memory Access Controller (LDMA) en The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep. tia The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 9 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview 3.12 Memory Map The EFR32BG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration. en fid on C Figure 3.2. EFR32BG1 Memory Map — Core Peripherals and Code Space tia l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 10 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet System Overview en fid on C Figure 3.3. EFR32BG1 Memory Map — Peripherals 3.13 Configuration Summary tia The features of the EFR32BG1 are a subset of the feature set described in the device reference manual. The table below describes device specific implementation of the features. Remaining modules support full configuration. Table 3.1. Configuration Summary Configuration USART0 IrDA SmartCard USART1 IrDA I2S SmartCard TIMER0 with DTI. TIMER1 silabs.com | Smart. Connected. Energy-friendly. Pin Connections US0_TX, US0_RX, US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS l Module TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[3:0] Preliminary Rev. 1.1 | 11 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4. Electrical Specifications 4.1 Electrical Characteristics All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: • Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization. • Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna. • Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise. tia en fid on C Refer to Table 4.2 General Operating Conditions on page 14 for more details about operational supply and temperature limits. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 12 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.1 Absolute Maximum Ratings Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx. Table 4.1. Absolute Maximum Ratings Symbol Storage temperature range TSTG Test Condition Min Typ Max Unit -50 — 150 °C External main supply voltage VDDMAX 0 — 3.8 V External main supply voltage VDDRAMPMAX ramp rate — — 1 V / μs -0.3 — Min of 5.25 and IOVDD +2 V -0.3 — IOVDD+0.3 V -0.3 — 1.4 V C Parameter VDIGPIN on Voltage on any 5V tolerant GPIO pin1 Voltage on non-5V tolerant GPIO pins VHFXOPIN Input RF level on pins 2G4RF_IOP and 2G4RF_ION PRFMAX2G4 — — 10 dBm Voltage differential between RF pins (2G4RF_IOP 2G4RF_ION) VMAXDIFF2G4 -50 — 50 mV -0.3 — 3.3 V Absolute Voltage on RF pins VMAX2G4 2G4RF_IOP and 2G4RF_ION Total current into VDD power IVDDMAX lines (source) Total current into VSS ground lines (sink) IVSSMAX Current per I/O pin (sink) IIOMAX Current for all I/O pins (sink) IIOALLMAX Current for all I/O pins (source) ΔVDD Junction Temperature TJ — 200 mA — — 200 mA — — 50 mA — — 50 mA — — 200 mA — — 200 mA — — 0.3 V -40 — 105 °C Note: 1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD. silabs.com | Smart. Connected. Energy-friendly. l Voltage difference between AVDD and VREGVDD — tia Current per I/O pin (source) en fid Voltage on HFXO pins Preliminary Rev. 1.1 | 13 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.2 Operating Conditions When assigning supply sources, the following requirements must be observed: • VREGVDD must be the highest voltage in the system • VREGVDD = AVDD • DVDD ≤ AVDD • IOVDD ≤ AVDD • RFVDD ≤ AVDD • PAVDD ≤ AVDD 4.1.2.1 General Operating Conditions C Parameter Table 4.2. General Operating Conditions Symbol Test Condition Typ Max Unit -40 25 85 °C 1.85 3.3 3.8 V DCDC in regulation 2.4 3.3 3.8 V DCDC in bypass, 50mA load 1.85 3.3 3.8 V DCDC not in use. DVDD externally shorted to VREGVDD 1.85 3.3 3.8 V — — 200 mA 1.62 — VVREGVDD V 1.62 — VVREGVDD V on Min Operating temperature range TOP AVDD Supply voltage1 -G temperature grade, Ambient Temperature VAVDD VREGVDD Operating supply VVREGVDD voltage1 2 fid VREGVDD Current IVREGVDD RFVDD Operating supply voltage VRFVDD DCDC in bypass DVDD Operating supply volt- VDVDD age VPAVDD IOVDD Operating supply voltage VIOVDD HFCLK frequency fCORE 0 wait-states (MODE = WS0) 3 1 wait-states (MODE = WS1) 3 1.62 — VVREGVDD V 1.62 — VVREGVDD V — — 0.1 V tia Difference between AVDD dVDD and VREGVDD, ABS(AVDDVREGVDD) en PAVDD Operating supply voltage — — 26 MHz — 38.4 40 MHz 3. In MSC_READCTRL register silabs.com | Smart. Connected. Energy-friendly. l Note: 1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate. 2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for other loads can be calculated as VDVDD_min+ILOAD * RBYP_max Preliminary Rev. 1.1 | 14 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.3 DC-DC Converter Test conditions: LDCDC=4.7 µH (Murata LQH3NPN4R7MM0L), CDCDC=1.0 µF (Murata GRM188R71A105KA61D), VDCDC_I=3.3 V, VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration, FDCDC_LN=7 MHz, unless otherwise indicated. Table 4.3. DC-DC Converter Symbol Test Condition Min Typ Max Unit Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50 mA 1.85 — VVREGVDD_ V Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA 2.4 Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 200 mA 2.6 on C Parameter VDCDC_O Regulation DC Accuracy ACCDC Regulation Window2 WINREG VR Output voltage under/overshoot VOV VVREGVDD_ V MAX — VVREGVDD_ V MAX — VVREGVDD V Low noise (LN) mode, 1.8 V target output 1.7 — 1.9 V Low power (LP) mode, LPCMPBIAS3 = 0, 1.8 V target output, IDCDC_LOAD ≤ 75 μA 1.63 — 2.2 V Low power (LP) mode, LPCMPBIAS3 = 3, 1.8 V target output, IDCDC_LOAD ≤ 10 mA 1.63 — 2.1 V — 3 — mVpp Radio disabled. en Steady-state output ripple — 1.8 fid Output voltage programmable range1 MAX — — 150 mV DCM Mode (LNFORCECCM3 = 0), Load changes between 0 mA and 10 mA — — 150 mV Overshoot during LP to LN CCM/DCM mode transitions compared to DC level in LN mode — 200 — mV Undershoot during BYP/LP to LN CCM (LNFORCECCM3 = 1) mode transitions compared to DC level in LN mode — 50 — mV — 125 — mV l Undershoot during BYP/LP to LN DCM (LNFORCECCM3 = 0) mode transitions compared to DC level in LN mode tia CCM Mode (LNFORCECCM3 = 1), Load changes between 0 mA and 100 mA DC line regulation VREG Input changes between VVREGVDD_MAX and 2.4 V — 0.1 — % DC load regulation IREG Load changes between 0 mA and 100 mA in CCM mode — 0.1 — % silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 15 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Max load current ILOAD_MAX C DCDC nominal output capacitor CDCDC Typ Max Unit Low noise (LN) mode, Heavy Drive4 — — 200 mA Low noise (LN) mode, Medium Drive4 — — 100 mA Low noise (LN) mode, Light Drive4 — — 50 mA Low power (LP) mode, LPCMPBIAS3 = 0 — — 75 μA Low power (LP) mode, LPCMPBIAS3 = 3 — — 10 mA 25% tolerance 1 1 1 μF 4.7 4.7 4.7 μH — 1.2 2.5 Ω on Min DCDC nominal output induc- LDCDC tor Resistance in Bypass mode 20% tolerance RBYP Note: 1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD tia en fid 2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits 3. In EMU_DCDCMISCCTRL register 4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 16 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.4 Current Consumption 4.1.4.1 Current Consumption 3.3 V without DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. TOP = 25 °C. EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.1 EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64. Table 4.4. Current Consumption 3.3V without DC/DC C Parameter Symbol Current consumption in EM0 IACTIVE Active mode with all peripherals disabled Test Condition Typ Max Unit 38.4 MHz crystal, CPU running while loop from flash1 — 130 — μA/MHz 38 MHz HFRCO, CPU running Prime from flash — 88 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 100 105 μA/MHz 38 MHz HFRCO, CPU running CoreMark from flash — 112 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 102 106 μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 222 350 μA/MHz 38.4 MHz crystal1 — 65 — μA/MHz 38 MHz HFRCO — 35 38 μA/MHz 26 MHz HFRCO — 37 41 μA/MHz Current consumption in EM1 IEM1 Sleep mode with all peripherals disabled en fid on Min — 157 275 μA/MHz Full RAM retention and RTCC running from LFXO — 3.3 — μA 4 kB RAM retention and RTCC running from LFRCO — 3 6.3 μA Current consumption in EM3 IEM3 Stop mode Full RAM retention and CRYOTIMER running from ULFRCO — 2.8 6 μA Current consumption in EM4H Hibernate mode 128 byte RAM retention, RTCC running from LFXO Current consumption in EM2 IEM2 Deep Sleep mode. IEM4 128 byte RAM retention, CRYOTIMER running from ULFRCO 128 byte RAM retention, no RTCC IEM4S no RAM retention, no RTCC — 1.1 — μA — 0.65 — μA — 0.65 1.3 μA — 0.04 0.11 μA l Current consumption in EM4S Shutoff mode tia 1 MHz HFRCO Note: 1. CMU_HFXOCTRL_LOWPOWER=0 silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 17 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.4.2 Current Consumption 3.3 V using DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC output. TOP = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64. Table 4.5. Current Consumption 3.3V with DC-DC Parameter Symbol Min Typ Max Unit 38.4 MHz crystal, CPU running while loop from flash2 — 88 — μA/MHz 38 MHz HFRCO, CPU running Prime from flash — 63 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 71 — μA/MHz 38 MHz HFRCO, CPU running CoreMark from flash — 78 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 76 — μA/MHz 38.4 MHz crystal, CPU running while loop from flash2 — 98 — μA/MHz 38 MHz HFRCO, CPU running Prime from flash — 75 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 81 — μA/MHz 38 MHz HFRCO, CPU running CoreMark from flash — 88 — μA/MHz on C Current consumption in EM0 IACTIVE Active mode with all peripherals disabled, DCDC in Low Noise DCM mode1. Test Condition Current consumption in EM1 IEM1 Sleep mode with all peripherals disabled, DCDC in Low Noise DCM mode1. 26 MHz HFRCO, CPU running while loop from flash — 94 — μA/MHz 38.4 MHz crystal2 — 49 — μA/MHz 38 MHz HFRCO — 32 — μA/MHz 26 MHz HFRCO — 38 — μA/MHz 38.4 MHz crystal2 — 61 — μA/MHz — 45 — μA/MHz — 58 — μA/MHz — 2.5 — μA — 2.3 — μA 38 MHz HFRCO 26 MHz HFRCO tia Current consumption in EM1 Sleep mode with all peripherals disabled, DCDC in Low Noise CCM mode3. en fid Current consumption in EM0 Active mode with all peripherals disabled, DCDC in Low Noise CCM mode3. Full RAM retention and RTCC running from LFXO Current consumption in EM3 IEM3 Stop mode Full RAM retention and CRYOTIMER running from ULFRCO — 2.1 Current consumption in EM4H Hibernate mode 128 byte RAM retention, RTCC running from LFXO — 128 byte RAM retention, CRYOTIMER running from ULFRCO 128 byte RAM retention, no RTCC IEM4 silabs.com | Smart. Connected. Energy-friendly. 4 kB RAM retention and RTCC running from LFRCO l Current consumption in EM2 IEM2 Deep Sleep mode. DCDC in Low Power mode4. — μA 0.86 — μA — 0.58 — μA — 0.58 — μA Preliminary Rev. 1.1 | 18 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Current consumption in EM4S Shutoff mode IEM4S no RAM retention, no RTCC Min Typ Max Unit — 0.04 — μA Note: 1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD 2. CMU_HFXOCTRL_LOWPOWER=0 3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD 4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DVDD tia en fid on C l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 19 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.4.3 Current Consumption 1.85 V without DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. TOP = 25 °C. EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.1 EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64. Table 4.6. Current Consumption 1.85V without DC/DC Parameter Symbol Min Typ Max Unit 38.4 MHz crystal, CPU running while loop from flash1 — 131 — μA/MHz 38 MHz HFRCO, CPU running Prime from flash — 88 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 100 — μA/MHz 38 MHz HFRCO, CPU running CoreMark from flash — 112 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 102 — μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 220 — μA/MHz 38.4 MHz crystal1 — 65 — μA/MHz 38 MHz HFRCO — 35 — μA/MHz 26 MHz HFRCO — 37 — μA/MHz 1 MHz HFRCO — 154 — μA/MHz Full RAM retention and RTCC running from LFXO — 3.2 — μA 4 kB RAM retention and RTCC running from LFRCO — 2.8 — μA Current consumption in EM3 IEM3 Stop mode Full RAM retention and CRYOTIMER running from ULFRCO — 2.7 — μA Current consumption in EM4H Hibernate mode 128 byte RAM retention, RTCC running from LFXO — 1 — μA Current consumption in EM1 IEM1 Sleep mode with all peripherals disabled IEM4 128 byte RAM retention, CRYOTIMER running from ULFRCO 128 byte RAM retention, no RTCC Current consumption in EM4S Shutoff mode IEM4S silabs.com | Smart. Connected. Energy-friendly. — 0.62 — μA — 0.62 — μA — 0.02 — μA l Note: 1. CMU_HFXOCTRL_LOWPOWER=0 No RAM retention, no RTCC tia en Current consumption in EM2 IEM2 Deep Sleep mode fid on C Current consumption in EM0 IACTIVE Active mode with all peripherals disabled Test Condition Preliminary Rev. 1.1 | 20 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.4.4 Current Consumption Using Radio Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. TOP = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 or Figure 5.1 EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64. Table 4.7. Current Consumption Using Radio 3.3 V with DC-DC Symbol Test Condition Current consumption in receive mode, active packet reception (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled) IRX Current consumption in transmit mode (MCU in EM1 @ 38.4 MHz, peripheral clocks disabled) ITX Min Typ Max Unit 1 Mbit/s, 2GFSK, F = 2.4 GHz, Radio clock prescaled by 4 — 8.7 — mA F = 2.4 GHz, CW, 0 dBm output power, Radio clock prescaled by 3 — 8.2 — mA F = 2.4 GHz, CW, 3 dBm output power — 16.5 — mA F = 2.4 GHz, CW, 8 dBm output power — 23.3 — mA F = 2.4 GHz, CW, 10.5 dBm output power — 32.7 — mA F = 2.4 GHz, CW, 16.5 dBm output power, PAVDD connected directly to external 3.3V supply — 83.9 — mA F = 2.4 GHz, CW, 19.5 dBm output power, PAVDD connected directly to external 3.3V supply — 126.7 — mA — 51 — nA RFSENSE current consump- IRFSENSE tion tia en fid on C Parameter l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 21 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.5 Wake up times Table 4.8. Wake up times Symbol Test Condition Wake up from EM2 Deep Sleep tEM2_WU Wakeup time from EM1 Sleep tEM1_WU C Parameter Wake up from EM3 Stop tEM3_WU Typ Max Unit Code execution from flash — 10.7 — μs Code execution from RAM — 3 — μs Executing from flash — 3 — AHB Clocks Executing from RAM — 3 — AHB Clocks Executing from flash — 10.7 — μs Executing from RAM — 3 — μs Executing from flash — 60 — μs — 290 — μs Min Typ Max Unit on Min Wake up from EM4H Hibernate1 tEM4H_WU Wake up from EM4S Shutoff1 tEM4S_WU Note: 1. Time from wakeup request until first instruction is executed. Wakeup results in device reset. fid 4.1.6 Brown Out Detector Table 4.9. Brown Out Detector Symbol Test Condition DVDDBOD threshold VDVDDBOD DVDD rising — — 1.62 V DVDD falling 1.35 — — V — 24 — mV en Parameter VDVDDBOD_HYST DVDD response time tDVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs AVDD BOD threshold VAVDDBOD — — 1.85 V 1.62 — — V — 21 — mV — 2.4 — μs — — 1.7 V 1.45 — — V — 46 — mV — 300 — μs AVDD rising AVDD falling AVDD BOD hysteresis VAVDDBOD_HYST AVDD response time tAVDDBOD_DELAY Supply drops at 0.1V/μs rate EM4 BOD threshold VEM4DBOD AVDD rising EM4 BOD hysteresis VEM4BOD_HYST EM4 response time tEM4BOD_DELAY silabs.com | Smart. Connected. Energy-friendly. Supply drops at 0.1V/μs rate l AVDD falling tia DVDD BOD hysteresis Preliminary Rev. 1.1 | 22 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.7 Frequency Synthesizer Characteristics Table 4.10. Frequency Synthesizer Characteristics Symbol Test Condition Min Typ Max Unit RF Synthesizer Frequency range FRANGE_2400 2.4 GHz frequency range 2400 — 2483.5 MHz LO tuning frequency resolution with 38.4 MHz crystal FRES_2400 2400 - 2483.5 MHz — — 73 Hz — — 1677 kHz C Parameter Maximum frequency deviation with 38.4 MHz crystal ΔFMAX_2400 tia en fid on l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 23 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8 2.4 GHz RF Transceiver Characteristics 4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.11. RF Transmitter General Characteristics for 2.4 GHz Band C Parameter Symbol Test Condition Typ Max Unit Maximum TX power1 POUTMAX 19.5 dBm-rated part numbers. PAVDD connected directly to external 3.3V supply2 — 19.5 — dBm 10.5 dBm-rated part numbers — 10.5 — dBm 0 dBm-rated part numbers — 0 — dBm -30 — dBm on Min POUTMIN CW Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB 0 dBm < output power < POUTMAX — 0.5 — dB 1.85 V < VVREGVDD < 3.3 V, PAVDD connected directly to external supply, for output power > 10.5 dBm. — 4.5 — dB 1.85 V < VVREGVDD < 3.3 V, PAVDD connected directly to external supply, for output power = 10.5 dBm. — 3.8 — dB 1.85 V < VVREGVDD < 3.3 V using DC-DC converter — 2.2 — dB From -40 to +85 °C, PAVDD connected to DC-DC output — 1.5 — dB From -40 to +85 °C, PAVDD connected to external supply — 1.5 — dB Output power variation vs supply at POUTMAX POUTVAR_V POUTVAR_T RF tuning frequency range FRANGE Over RF tuning frequency range tia Output power variation vs RF POUTVAR_F frequency at POUTMAX en Output power variation vs temperature at POUTMAX fid Minimum active TX Power — 0.4 — dB 2400 — 2483.5 MHz l Note: 1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices covered in this datasheet can be found in the Max TX Power column of 2. Ordering Information 2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 24 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.12. RF Receiver General Characteristics for 2.4 GHz Band Symbol RF tuning frequency range FRANGE Receive mode maximum spurious emission SPURRX C Parameter Min Typ Max Unit 2400 — 2483.5 MHz 30 MHz to 1 GHz — -57 — dBm 1 GHz to 12 GHz — -47 — dBm 216 MHz to 960 MHz, Conducted Measurement — -55.2 — dBm Above 960 MHz, Conducted Measurement — -47.2 — dBm CW at 2.45 GHz — -24 — dBm — -50 — dBm 2 Mbps 2GFSK signal2 — -89.2 — dBm 250 kbps 2GFSK signal — -99.1 — dBm on Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) Test Condition RFSENSETRIG Level below which RFSENSE will not trigger1 RFSENSETHRES 1% PER Sensitivity SENS2GFSK 0.1% BER Sensitivity fid Level above which RFSENSE will trigger1 Note: 1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range. 2. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83dBm on this channel. tia en l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 25 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.44 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.13. RF Transmitter Characteristics for Bluetooth Smart in the 2.4GHz Band Symbol Min Typ Max Unit Transmit 6dB bandwidth TXBW — 740 — kHz Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -6.5 — dBm/ 3kHz Per FCC part 15.247 at 20 dBm — -2.6 — dBm/ 3kHz Per ETSI 300.328 at 10 dBm/1 MHz — 10 — dBm Occupied channel bandwidth OCPETSI328 per ETSI EN300.328 99% BW at highest and lowest channels in band — 1.1 — MHz In-band spurious emissions at 10 dBm, with allowed exceptions1 At ±2 MHz — -39.8 — dBm At ±3 MHz — -42.1 — dBm At ±2 MHz — — -20 dBm At ±3 MHz — — -30 dBm 2nd,3rd, 5, 6, 8, 9,10 harmonics; continuous transmission of modulated carrier — -47 — dBm Spurious emissions out-ofSPUROOB_FCC band, per FCC part 15.247, excluding harmonics captured in SPURHARM,FCC. Restricted Bands Above 2.483 GHz or below 2.4 GHz; continuous transmission of modulated carrier3 — -47 — dBm Spurious emissions out-ofband, per FCC part 15.247, excluding harmonics captured in SPURHARM,FCC. Non Restricted Bands Above 2.483 GHz or below 2.4 GHz; continuous transmission of modulated carrier — -26 — dBc Test Condition on C Parameter Emissions of harmonics outof-band, per FCC part 15.247 SPURHRM_FCC [2400-BW to 2400] MHz, [2483.5 to 2483.5+BW] MHz -16 — dBm — -26 — dBm 47-74 MHz,87.5-108 MHz, 174-230 MHz, 470-862 MHz — -60 25-1000 MHz — 1-12 GHz — silabs.com | Smart. Connected. Energy-friendly. l — [2400-2BW to 2400-BW] MHz, [2483.5+BW to 2483.5+2BW] MHz per ETSI 300.328 Spurious emissions per ETSI SPURETSI440 EN300.440 tia SPURETSI328 en Spurious emissions out-ofband; per ETSI 300.328 fid In-band spurious emissions at 20 dBm, with allowed exceptions1 2 SPURINB — dBm -42 — dBm -36 — dBm Preliminary Rev. 1.1 | 26 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Per Bluetooth Core_4.2, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less. 2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value. 3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value. tia en fid on C l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 27 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.14. RF Receiver Characteristics for Bluetooth Smart in the 2.4GHz Band Symbol Test Condition Min Typ Max Unit Max usable receiver input level, 0.1% BER SAT Signal is reference signal1. Packet length is 20 bytes. — 10 — dBm Sensitivity, 0.1% BER2 SENS Signal is reference signal1. Using DC-DC converter — -91 — dBm With non-ideal signals as specified in RF-PHY.TS.4.2.2, section 4.6.1 — -90.2 — dBm Signal to co-channel interfer- C/ICC er, 0.1% BER Desired signal 3 dB above reference sensitivity — 8.3 — dB N+1 adjacent channel (1 C/I1+ MHz) selectivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm Interferer is reference signal at +1 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz — -3.3 — dB Interferer is reference signal at -1 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz — 1.3 — dB Interferer is reference signal at ± 2 MHz offset. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz — -39.5 — dB Alternate (3 MHz) selectivity, C/I3 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm Interferer is reference signal at ±3 MHz offset. Desired frequency 2404 MHz ≤ Fc ≤ 2480 MHz — -43.8 — dB Selectivity to image frequen- C/IIM cy, 0.1% BER. Desired is reference signal at -67 dBm Interferer is reference signal at image frequency with 1 MHz precision — -29 — dB Selectivity to image frequency +1 MHz, 0.1% BER. Desired is reference signal at -67 dBm Interferer is reference signal at image frequency +1 MHz with 1 MHz precision — -43.6 — dB — -27 — dBm Interferer frequency 2003 MHz ≤ f ≤ 2399 MHz — -32 — dBm Interferer frequency 2484 MHz ≤ f ≤ 2997 MHz — -32 — dBm Interferer frequency 3 GHz ≤ f ≤ 12.75 GHz — -27 — dBm N-1 adjacent channel (1 C/I1MHz) selectivity, 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm silabs.com | Smart. Connected. Energy-friendly. Interferer frequency 30 MHz ≤ f ≤ 2000 MHz l Blocking, 0.1% BER, Desired BLOCKOOB is reference signal at -67 dBm. Interferer is CW in OOB range. tia C/IIM+1 en Alternate (2 MHz) selectivity, C/I2 0.1% BER, with allowable exceptions. Desired is reference signal at -67 dBm fid on C Parameter Preliminary Rev. 1.1 | 28 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Min Typ Max Unit — -25.8 — dBm Upper limit of input power RSSIMAX range over which RSSI resolution is maintained 4 — — dBm Lower limit of input power RSSIMIN range over which RSSI resolution is maintained — — -101 dBm — — 0.5 dB Intermodulation performance IM Per Core_4.1, Vol 6, Part A, Section 4.4 with n = 3 RSSIRES C RSSI resolution Test Condition Over RSSIMIN to RSSIMAX Note: 1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9; interferer data = PRBS15; frequency accuracy better than 1 ppm 2. Receive sensitivity on Bluetooth Smart channel 26 is -86 dBm tia en fid on l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 29 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.15. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band Symbol Test Condition Min Typ Max Unit Error vector magnitude (offset EVM), per 802.15.4-2011, not including 2415 MHz channel1 EVM Average across frequency. Signal is DSSS-OQPSK reference packet2 — 5.5 — % rms Power spectral density limit PSDLIMIT Relative, at carrier ±3.5 MHz — -26 — dBc Absolute, at carrier ±3.5 MHz3 — -36 — dBm Per FCC part 15.247 — -4.2 — dBm/ 3kHz Output power level which meets 10dBm/MHz ETSI 300.328 specification — 12 — dBm Occupied channel bandwidth OCPETSI328 per ETSI EN300.328 99% BW at highest and lowest channels in band — 2.25 — MHz Spurious emissions of harSPURHRM_FCC_ monics in restricted bands R per FCC Part 15.205/15.209, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency is 2450 MHz Continuous transmission of modulated carrier — -45.8 — dBm — dBc SPURHRM_FCC_ NRR — -26 tia Spurious emissions of harmonics in harmonics in nonrestricted bands per FCC Part 15.247/15.35, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency is 2450 MHz en fid on C Parameter l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 30 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Spurious emissions out-ofband in restricted bands (30-88 MHz), per FCC part 15.205/15.209, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz SPUROOB_FCC_ Above 2.483 GHz or below 2.4 GHz; continuous transmission of modulated carrier4 — -52 — dBm Spurious emissions out-ofband in restricted bands (88-216 MHz), per FCC part 15.205/15.209, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz — -62 — dBm Spurious emissions out-ofband in restricted bands (216-960 MHz), per FCC part 15.205/15.209, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz — -57 — dBm — -48 — dBm — dBc R en fid on C Spurious emissions out-ofband in restricted bands (>960 MHz), per FCC part 15.205/15.209, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz Above 2.483 GHz or below 2.4 GHz; continuous transmission of modulated carrier Spurious emissions out-ofband; per ETSI 300.3285 [2400-BW to 2400], [2483.5 to 2483.5+BW]; SPURETSI328 -16 — dBm — -26 — dBm 47-74 MHz,87.5-108 MHz, 174-230 MHz, 470-862 MHz — -60 — dBm 25-1000 MHz, excluding above frequencies — -42 — dBm 1G-14G — -36 — dBm l silabs.com | Smart. Connected. Energy-friendly. -26 — [2400-2BW to 2400-BW], [2483.5+BW to 2483.5+2BW]; per ETSI 300.328 Spurious emissions per ETSI SPURETSI440 EN300.4405 — tia Spurious emissions out-ofSPUROOB_FCC_ band in non-restricted bands NR per FCC Part 15.247, Emissions taken at Pout_Max power level of 19.5 dBm, PAVDD connected to external 3.3 V supply, Test Frequency = 2450 MHz Preliminary Rev. 1.1 | 31 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Typical EVM for the 2415 MHz channel is 7.9% 2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with pseudo-random packet data content 3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this value. 4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value. 5. Specified at maximum power output level of 10 dBm tia en fid on C l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 32 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.8.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to Figure 5.2 EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65. Table 4.16. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band Symbol Test Condition Max usable receiver input level, 1% PER SAT Sensitivity, 1% PER2 SENS Min Typ Max Unit Signal is reference signal1. Packet length is 20 octets. — 10 — dBm Signal is reference signal. Packet length is 20 octets. Using DC-DC converter. — -101 — dBm Signal is reference signal. Packet length is 20 octets. Without DCDC converter. — -101 — dBm CCR Desired signal 10 dB above sensitivity limit — -2.6 — dB High-side adjacent channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 ACR+1 Interferer is reference signal at +1 channel-spacing. — 33.75 — dB Interferer is filtered reference signal4 at +1 channel-spacing. — 52.2 — dB Interferer is CW at +1 channelspacing.5 — 58.6 — dB Interferer is reference signal at -1 channel-spacing. — 35 — dB Interferer is filtered reference signal4 at -1 channel-spacing. — 54.7 — dB Interferer is CW at -1 channelspacing. — 60.1 — dB Interferer is reference signal at ±2 channel-spacing — 45.9 — dB Interferer is filtered reference signal4 at ±2 channel-spacing — 56.8 — dB Low-side adjacent channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 ACR2 Interferer is CW at ±2 channelspacing tia Alternate channel rejection, 1% PER. Desired is reference signal at 3dB above reference sensitivity level3 ACR-1 en Co-channel interferer rejection, 1% PER fid on C Parameter — 65.5 — dB — 40.8 — dB Interferer is CW in image band5 Blocking rejection of all other BLOCK channels. 1% PER, Desired is reference signal at 3dB above reference sensitivity level3. Interferer is reference signal. Interferer frequency < Desired frequency - 3 channel-spacing — 57.2 Interferer frequency > Desired frequency + 3 channel-spacing — Blocking rejection of 802.11g BLOCK80211G signal centered at +12MHz or -13MHz Desired is reference signal at 6dB above reference sensitivity level3 — silabs.com | Smart. Connected. Energy-friendly. l Image rejection, 1% PER, IR Desired is reference signal at 3dB above reference sensitivity level3 — dB 57.9 — dB 51.6 — dB Preliminary Rev. 1.1 | 33 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Min Typ Max Unit Upper limit of input power RSSIMAX range over which RSSI resolution is maintained 5 — — dBm Lower limit of input power RSSIMIN range over which RSSI resolution is maintained — — -98 dBm — 0.25 — dB — ±1 — dB RSSIRES RSSI accuracy in the linear region as defined by 802.15.4-2003 RSSILIN over RSSIMIN to RSSIMAX C RSSI resolution Test Condition fid on Note: 1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksymbols/s 2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm 3. Reference sensitivity level is -85 dBm 4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stopband rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier. 5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster. 4.1.9 Modem Features Table 4.17. Modem Features Symbol Test Condition Min Receive Bandwidth RXBandwidth Configurable range with 38.4 MHz crystal 0.1 IF Frequency IFFreq Configurable range with 38.4 MHz crystal. Selected steps available. 150 Typ Max Unit — 2530 kHz — 1371 kHz tia en Parameter l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 34 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.10 Oscillators 4.1.10.1 LFXO Table 4.18. LFXO Parameter Symbol Crystal frequency Test Condition Typ Max Unit fLFXO — 32.768 — kHz Supported crystal equivalent series resistance (ESR) ESRLFXO — — 70 kΩ Supported range of crystal load capacitance 1 CLFXO_CL 6 — 18 pF On-chip tuning cap range 2 CLFXO_T 8 — 40 pF — 0.25 — pF On each of LFXTAL_N and LFXTAL_P pins on C Min On-chip tuning cap step size SSLFXO Current consumption after startup 3 ILFXO ESR = 70 kΩ, CL = 7 pF, GAIN4 = 3, AGC4 = 1 — 273 — nA Start- up time tLFXO ESR=70 kΩ, CL = 7 pF, GAIN4 = 2 — 308 — ms fid Note: 1. Total load capacitance as seen by the crystal 2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal. 3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register 4. In CMU_LFXOCTRL register tia en l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 35 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.10.2 HFXO Table 4.19. HFXO Symbol Crystal Frequency fHFXO Supported crystal equivalent series resistance (ESR) ESRHFXO Supported range of crystal load capacitance 1 CHFXO_CL On-chip tuning cap range 2 CHFXO_T On-chip tuning capacitance step SSHFXO Startup time tHFXO FTHFXO Test Condition Min Typ Max Unit 38 38.4 40 MHz — — 60 Ω 6 — 12 pF 9 20 25 pF — 0.04 — pF 38.4 MHz, ESR = 50 Ω, CL = 10 pF — 300 — μs 38.4 MHz, ESR = 50 Ω, CL = 10 pF -40 — 40 ppm Crystal frequency 38.4 MHz On each of HFXTAL_N and HFXTAL_P pins on C Parameter Frequency Tolerance for the crystal 4.1.10.3 LFRCO fid Note: 1. Total load capacitance as seen by the crystal 2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal. en Table 4.20. LFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency fLFRCO ENVREF = 1 in CMU_LFRCOCTRL 26.2 32.768 34.5 kHz ENVREF = 0 in CMU_LFRCOCTRL 26.2 32.768 34.5 kHz tLFRCO Current consumption 1 ILFRCO ENVREF = 1 in CMU_LFRCOCTRL ENVREF = 0 in CMU_LFRCOCTRL tia Startup time — 500 — μs — 342 — nA — 494 — nA silabs.com | Smart. Connected. Energy-friendly. l Note: 1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register Preliminary Rev. 1.1 | 36 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.10.4 HFRCO and AUXHFRCO Table 4.21. HFRCO and AUXHFRCO Symbol Test Condition Min Typ Max Unit Frequency Accuracy fHFRCO_ACC Any frequency band, across supply voltage and temperature -10 — 3 % Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns 4 < fHFRCO < 19 MHz — 1 — μs fHFRCO ≤ 4 MHz — 2.5 — μs fHFRCO = 38 MHz — 204 228 μA fHFRCO = 32 MHz — 171 190 μA fHFRCO = 26 MHz — 147 164 μA fHFRCO = 19 MHz — 126 138 μA fHFRCO = 16 MHz — 110 120 μA fHFRCO = 13 MHz — 100 110 μA fHFRCO = 7 MHz — 81 91 μA fHFRCO = 4 MHz — 33 35 μA fHFRCO = 2 MHz — 31 35 μA fHFRCO = 1 MHz — 30 35 μA Coarse (% of period) — 0.8 — % Fine (% of period) — 0.1 — % — 0.2 — % RMS C Parameter Current consumption on all supplies IHFRCO SSHFRCO PJHFRCO 4.1.10.5 ULFRCO en Period Jitter fid on Step size Table 4.22. ULFRCO Symbol Oscillation frequency fULFRCO Test Condition tia Parameter Min Typ Max Unit 0.8 1 1.05 kHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 37 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.11 Flash Memory Characteristics Table 4.23. Flash Memory Characteristics1 Parameter Symbol Flash erase cycles before failure ECFLASH Flash data retention Test Condition Typ Max Unit 10000 — — cycles RETFLASH 10 — — years Word (32-bit) programming time tW_PROG 20 26 40 μs Page erase time tPERASE 20 27 40 ms Mass erase time tMERASE 20 27 40 ms Device erase time2 tDERASE — 60 74 ms Page erase current3 IERASE — — 3 mA — — 5 mA — — 3 mA on C Min Mass or Device erase current3 Write current3 IWRITE tia en fid Note: 1. Flash data retention information is published in the Quarterly Quality and Reliability Report. 2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock Word (ULW) 3. Measured at 25°C l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 38 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.12 GPIO Table 4.24. GPIO Parameter Symbol Input low voltage Test Condition Min Typ Max Unit VIOIL — — IOVDD*0.3 V Input high voltage VIOIH IOVDD*0.7 — — V Output high voltage relative to IOVDD VIOOH IOVDD*0.8 — — V IOVDD*0.6 — — V IOVDD*0.8 — — V IOVDD*0.6 — — V — — IOVDD*0.2 V — — IOVDD*0.4 V — — IOVDD*0.2 V Sourcing 3 mA, IOVDD ≥ 3 V, C DRIVESTRENGTH1 = WEAK Sourcing 1.2 mA, IOVDD ≥ 1.62 V, DRIVESTRENGTH1 = WEAK on Sourcing 20 mA, IOVDD ≥ 3 V, DRIVESTRENGTH1 = STRONG Sourcing 8 mA, IOVDD ≥ 1.62 V, DRIVESTRENGTH1 = STRONG Sinking 3 mA, IOVDD ≥ 3 V, fid Output low voltage relative to VIOOL IOVDD DRIVESTRENGTH1 = WEAK Sinking 1.2 mA, IOVDD ≥ 1.62 V, DRIVESTRENGTH1 = WEAK Sinking 20 mA, IOVDD ≥ 3 V, DRIVESTRENGTH1 = STRONG en Sinking 8 mA, IOVDD ≥ 1.62 V, — — IOVDD*0.4 V All GPIO except LFXO pins, GPIO ≤ IOVDD — 0.1 30 nA LFXO Pins, GPIO ≤ IOVDD — 0.1 50 nA IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 15 μA 30 43 65 kΩ 30 43 65 kΩ 20 25 35 ns — 1.8 — 4.5 DRIVESTRENGTH1 = STRONG Input leakage current IIOLEAK I5VTOLLEAK I/O pin pull-up resistor RPU I/O pin pull-down resistor RPD Output fall time, From 70% to 30% of VIO tIOOF CL = 50 pF, l Pulse width of pulses retIOGLITCH moved by the glitch suppression filter tia Input leakage current on 5VTOL pads above IOVDD — ns — ns DRIVESTRENGTH1 = STRONG, SLEWRATE1 = 0x6 CL = 50 pF, DRIVESTRENGTH1 = WEAK, SLEWRATE1 = 0x6 silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 39 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Output rise time, From 30% to 70% of VIO tIOOR CL = 50 pF, — 2.2 — ns — 7.4 — ns Min Typ Max Unit — 5.8 8.26 μA In EM0 or EM1, 4 supplies monitored — 11.8 16.8 μA In EM2, EM3 or EM4, 1 supply monitored — 62 — nA In EM2, EM3 or EM4, 4 supplies monitored — 99 — nA DRIVESTRENGTH1 = STRONG, SLEWRATE = 0x61 CL = 50 pF, DRIVESTRENGTH1 = WEAK, SLEWRATE1 = 0x6 C Note: 1. In GPIO_Pn_CTRL register on 4.1.13 VMON Table 4.25. VMON Parameter VMON Supply Current Symbol Test Condition IVMON In EM0 or EM1, 1 supply monitored Threshold range VVMON_RANGE Threshold step size NVMON_STESP — 2 — μA In EM2, EM3 or EM4 — 2 — nA 1.62 — 3.4 V — 200 — mV — 20 — mV — 460 — ns — 26 — mV Coarse tVMON_RES Hysteresis VVMON_HYST Supply drops at 1V/μs rate tia In EM0 or EM1 Fine Response time en fid VMON Loading of Monitored ISENSE Supply l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 40 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.14 ADC Table 4.26. ADC Parameter Symbol Resolution VRESOLUTION Input voltage range VADCIN Test Condition Single ended Differential C Input range of external refer- VADCREFIN_P ence voltage, single ended and differential Min Typ Max Unit 6 — 12 Bits 0 — 2*VREF V -VREF — VREF V 1 — VAVDD V PSRRADC At DC — 80 — dB Analog input common mode rejection ratio CMRRADC At DC — 80 — dB 1 Msps / 16 MHz ADCCLK, — 301 350 μA 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 3 — 149 — μA 62.5 ksps / 1 MHz ADCCLK, — 91 — μA — 51 — μA on Power supply rejection1 Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_LP Continous operation. WARMUPMODE2 = KEEPADCWARM BIASPROG = 0, GPBIASACC = 1 3 fid BIASPROG = 15, GPBIASACC = 13 en Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, ing internal reference buffer. BIASPROG = 0, GPBIASACC = 1 Duty-cycled operation. WAR3 2 MUPMODE = NORMAL 5 ksps / 16 MHz ADCCLK — 9 — μA — 117 — μA BIASPROG = 0, GPBIASACC = 1 3 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 3 35 ksps / 16 MHz ADCCLK, 79 — μA — 345 — μA 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 3 — 191 — μA 62.5 ksps / 1 MHz ADCCLK, — 132 — μA BIASPROG = 0, GPBIASACC = 1 1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 l — 3 Current from all supplies, us- IADC_CONTIing internal reference buffer. NOUS_HP Continous operation. WARMUPMODE2 = KEEPADCWARM tia Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP Duty-cycled operation. AWARMUPMODE2 = KEEPINSTANDBY or KEEPINSLOWACC 3 BIASPROG = 15, GPBIASACC = 03 silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 41 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, ing internal reference buffer. BIASPROG = 0, GPBIASACC = 0 Duty-cycled operation. WAR3 2 MUPMODE = NORMAL 5 ksps / 16 MHz ADCCLK Min Typ Max Unit — 102 — μA — 17 — μA — 162 — μA — 123 — μA — 140 — μA BIASPROG = 0, GPBIASACC = 0 3 C Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP Duty-cycled operation. AWARMUPMODE2 = KEEPINSTANDBY or KEEPINSLOWACC 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 3 35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 on 3 IADC_CLK ADC Clock Frequency fADCCLK — — 16 MHz Throughput rate fADCRATE — — 1 Msps Conversion time4 tADCCONV 6 bit — 7 — cycles 8 bit — 9 — cycles 12 bit — 13 — cycles WARMUPMODE2 = NORMAL — — 5 μs WARMUPMODE2 = KEEPINSTANDBY — — 2 μs WARMUPMODE2 = KEEPINSLOWACC — — 1 μs Internal reference, 2.5 V full-scale, differential (-1.25, 1.25) 58 67 — dB vrefp_in = 1.25 V direct mode with 2.5 V full-scale, differential — 68 — dB — 75 — dB Startup time of reference generator and ADC core tADCSTART SNDRADC Spurious-Free Dynamic Range (SFDR) SFDRADC 1 MSamples/s, 10 kHz full-scale sine wave Input referred ADC noise, rms VREF_NOISE Including quantization noise and distortion Offset Error VADCOFFSETERR Gain error in ADC VADC_GAIN Using internal reference Using external reference tia en SNDR at 1Msps and fin = 10kHz HFPERCLK = 16 MHz fid Current from HFPERCLK — 380 — μV -3 0.25 3 LSB — -0.2 5 % — -1 — % DNLADC 12 bit resolution, No Missing Codes -1 — Integral non-linearity (INL), End point method INLADC 12 bit resolution -6 Temperature Sensor Slope VTS_SLOPE — silabs.com | Smart. Connected. Energy-friendly. l Differential non-linearity (DNL) 2 LSB — 6 LSB -1.84 — mV/°C Preliminary Rev. 1.1 | 42 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL 2. In ADCn_CNTL register 3. In ADCn_BIASPROG register 4. Derived from ADCCLK tia en fid on C l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 43 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.15 IDAC Table 4.27. IDAC Parameter Symbol Number of Ranges NIDAC_RANGES Output Current IIDAC_OUT C Linear steps within each range Min Typ Max Unit — 4 — - RANGSEL1 = RANGE0 0.05 — 1.6 μA RANGSEL1 = RANGE1 1.6 — 4.7 μA RANGSEL1 = RANGE2 0.5 — 16 μA RANGSEL1 = RANGE3 2 — 64 μA — 32 — RANGSEL1 = RANGE0 — 50 — nA RANGSEL1 = RANGE1 — 100 — nA RANGSEL1 = RANGE2 — 500 — nA RANGSEL1 = RANGE3 — 2 — μA EM0 or EM1, AVDD=3.3 V, T = 25 °C -5 — 2 % EM0 or EM1 -18 — 22 % EM2 or EM3, Source mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T = 25 °C — -2 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T = 25 °C — -1.7 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T = 25 °C — -0.8 — % EM2 or EM3, Source mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T = 25 °C — -0.5 — % NIDAC_STEPS on Step size Test Condition SSIDAC EM2 or EM3, Sink mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T = 25 °C -0.7 — % — -0.6 — % EM2 or EM3, Sink mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T = 25 °C — -0.5 EM2 or EM3, Sink mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T = 25 °C — tIDAC_SU Output within 1% of steady state value — silabs.com | Smart. Connected. Energy-friendly. l — EM2 or EM3, Sink mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T = 25 °C Start up time tia en fid Total Accuracy, STEPSEL1 = ACCIDAC 0x10 — % -0.5 — % 5 — μs Preliminary Rev. 1.1 | 44 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Settling time, (output settled tIDAC_SETTLE within 1% of steady state value) Range setting is changed — 5 — μs Step value is changed — 1 — μs Current consumption in EM0 IIDAC or EM1 2 Source mode, excluding output current — 8.9 13 μA Sink mode, excluding output current — 12 16 μA Source mode, excluding output current, duty cycle mode, T = 25 °C — 1.04 — μA Sink mode, excluding output current, duty cycle mode, T = 25 °C — 1.08 — μA Source mode, excluding output current, duty cycle mode, T ≥ 85 °C — 8.9 — μA Sink mode, excluding output current, duty cycle mode, T ≥ 85 °C — 12 — μA RANGESEL1=0, output voltage = min(VIOVDD, VAVDD2-100 mv) — 0.04 — % RANGESEL1=1, output voltage = min(VIOVDD, VAVDD2-100 mV) — 0.02 — % RANGESEL1=2, output voltage = min(VIOVDD, VAVDD2-150 mV) — 0.02 — % RANGESEL1=3, output voltage = min(VIOVDD, VAVDD2-250 mV) — 0.02 — % RANGESEL1=0, output voltage = 100 mV — 0.18 — % RANGESEL1=1, output voltage = 100 mV — 0.12 — % RANGESEL1=2, output voltage = 150 mV — 0.08 — % RANGESEL1=3, output voltage = 250 mV — 0.02 — % on C Current consumption in EM2 or EM32 Output voltage compliance in ICOMP_SINK sink mode, sink current change relative to current sunk at IOVDD tia en fid Output voltage compliance in ICOMP_SRC source mode, source current change relative to current sourced at 0 V Note: 1. In IDAC_CURPROG register 2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1). l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 45 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.16 Analog Comparator (ACMP) Table 4.28. ACMP Parameter Symbol Test Condition Input voltage range VACMPIN ACMPVDD = ACMPn_CTRL_PWRSEL 1 Supply Voltage VACMPVDD C Active current not including voltage reference IACMP Typ Max Unit 0 — VACMPVDD V BIASPROG2 ≤ 0x10 or FULLBIAS2 = 0 1.85 — VVREGVDD_ V 0x10 < BIASPROG2 ≤ 0x20 and FULLBIAS2 = 1 2.1 BIASPROG2 = 1, FULLBIAS2 = 0 — 50 — nA BIASPROG2 = 0x10, FULLBIAS2 =0 — 306 — nA BIASPROG2 = 0x20, FULLBIAS2 =1 — 74 95 μA VLP selected as input using 2.5 V Reference / 4 (0.625 V) — 50 — nA VLP selected as input using VDD — 20 — nA VBDIV selected as input using 1.25 V reference / 1 — 4.1 — μA VADIV selected as input using VDD/1 — 2.4 — μA HYSTSEL3 = HYST0 -1.75 0 1.75 mV HYSTSEL3 = HYST1 10 18 26 mV HYSTSEL3 = HYST2 21 32 46 mV HYSTSEL3 = HYST3 27 44 63 mV HYSTSEL3 = HYST4 32 55 80 mV HYSTSEL3 = HYST5 38 65 100 mV HYSTSEL3 = HYST6 43 77 121 mV 47 86 148 mV -4 0 4 mV -27 -18 -10 mV -47 -32 -18 mV -64 -43 -27 mV HYSTSEL3 = HYST12 -78 -54 -32 mV HYSTSEL3 = HYST13 -93 -64 -37 mV HYSTSEL3 = HYST14 -113 -74 -42 mV HYSTSEL3 = HYST15 -135 -85 -47 mV on Min Current consumption of inter- IACMPREF nal voltage reference VACMPHYST HYSTSEL3 = HYST8 HYSTSEL3 = HYST9 HYSTSEL3 = HYST10 V MAX l HYSTSEL3 = HYST11 VVREGVDD_ tia HYSTSEL3 = HYST7 silabs.com | Smart. Connected. Energy-friendly. — en fid Hysteresis (VCM = 1.25 V, BIASPROG2 = 0x10, FULLBIAS2 = 1) MAX Preliminary Rev. 1.1 | 46 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Comparator delay4 tACMPDELAY BIASPROG2 = 1, FULLBIAS2 = 0 — 30 — μs BIASPROG2 = 0x10, FULLBIAS2 =0 — 3.7 — μs BIASPROG2 = 0x20, FULLBIAS2 =1 — 35 — ns -35 — 35 mV VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2 =1 Reference Voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V Internal 2.5 V reference 2 2.5 2.8 V CSRESSEL5 = 0 — inf — kΩ CSRESSEL5 = 1 — 15 — kΩ CSRESSEL5 = 2 — 27 — kΩ CSRESSEL5 = 3 — 39 — kΩ CSRESSEL5 = 4 — 51 — kΩ CSRESSEL5 = 5 — 102 — kΩ CSRESSEL5 = 6 — 164 — kΩ CSRESSEL5 = 7 — 239 — kΩ C Offset voltage Capacitive Sense Internal Resistance RCSRES fid on en Note: 1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD 2. In ACMPn_CTRL register 3. In ACMPn_HYSTERESIS register 4. ±100 mV differential drive 5. In ACMPn_INPUTSEL register The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as: IACMPTOTAL = IACMP + IACMPREF IACMPREF is zero if an external voltage reference is used. tia l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 47 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.17 I2C I2C Standard-mode (Sm) Table 4.29. I2C Standard-mode (Sm)1 Parameter Symbol SCL clock frequency2 Test Condition Typ Max Unit fSCL 0 — 100 kHz SCL clock low time tLOW 4.7 — — μs SCL clock high time tHIGH 4 — — μs SDA set-up time tSU,DAT 250 — — ns SDA hold time3 tHD,DAT 100 — 3450 ns 4.7 — — μs (Repeated) START condition tHD,STA hold time 4 — — μs STOP condition set-up time tSU,STO 4 — — μs Bus free time between a STOP and START condition tBUF 4.7 — — μs on C Min Repeated START condition set-up time tSU,STA fid Note: 1. For CLHR set to 0 in the I2Cn_CTRL register 2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual 3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW) tia en l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 48 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications I2C Fast-mode (Fm) Table 4.30. I2C Fast-mode (Fm)1 Parameter Symbol SCL clock frequency2 Test Condition Min Typ Max Unit fSCL 0 — 400 kHz SCL clock low time tLOW 1.3 — — μs SCL clock high time tHIGH 0.6 — — μs C tSU,DAT 100 — — ns SDA hold time3 tHD,DAT 100 — 900 ns Repeated START condition set-up time tSU,STA 0.6 — — μs (Repeated) START condition tHD,STA hold time 0.6 — — μs STOP condition set-up time tSU,STO 0.6 — — μs Bus free time between a STOP and START condition tBUF 1.3 — — μs on SDA set-up time I2C Fast-mode Plus (Fm+) en fid Note: 1. For CLHR set to 1 in the I2Cn_CTRL register 2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual 3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW) Table 4.31. I2C Fast-mode Plus (Fm+)1 Symbol SCL clock frequency2 fSCL SCL clock low time tLOW SCL clock high time tHIGH SDA set-up time tSU,DAT SDA hold time tHD,DAT Repeated START condition set-up time tSU,STA Min Typ Max Unit 0 — 1000 kHz 0.5 — — μs 0.26 — — μs 50 — — ns 100 — — ns 0.26 — — μs 0.26 — — μs l (Repeated) START condition tHD,STA hold time Test Condition tia Parameter STOP condition set-up time tSU,STO 0.26 — — μs Bus free time between a STOP and START condition tBUF 0.5 — — μs Note: 1. For CLHR set to 0 or 1 in the I2Cn_CTRL register 2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 49 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.1.18 USART SPI SPI Master Timing Table 4.32. SPI Master Timing Parameter Symbol SCLK period 1 2 tSCLK Test Condition Min Typ Max Unit 2* tHFPERCLK — — ns C tCS_MO 0 — 8 ns SCLK to MOSI 1 2 tSCLK_MO 3 — 20 ns MISO setup time 1 2 tSU_MI IOVDD = 1.62 V 56 — — ns IOVDD = 3.0 V 37 — — ns 6 — — ns on CS to MOSI 1 2 tH_MI MISO hold time 1 2 Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD) fid CS tCS_MO tSCKL_MO SCLK CLKPOL = 0 tSCLK CLKPOL = 1 MOSI tSU_MI MISO en SCLK tH_MI tia Figure 4.1. SPI Master Timing Diagram l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 50 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications SPI Slave Timing Table 4.33. SPI Slave Timing Parameter Symbol SCKL period 1 2 SCLK high period1 2 Test Condition Typ Max Unit tSCLK_sl 2* tHFPERCLK — — ns tSCLK_hi 3* tHFPERCLK — — ns 3* tHFPERCLK — — ns C Min tSCLK_lo CS active to MISO 1 2 tCS_ACT_MI 4 — 50 ns CS disable to MISO 1 2 tCS_DIS_MI 4 — 50 ns MOSI setup time 1 2 tSU_MO 4 — — ns MOSI hold time 1 2 tH_MO 3+2* tHFPERCLK — — ns SCLK to MISO 1 2 tSCLK_MI 16 + tHFPERCLK — 66 + 2 * tHFPERCLK ns on SCLK low period 1 2 tCS_ACT_MI en CS fid Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD) tCS_DIS_MI SCLK CLKPOL = 0 SCLK CLKPOL = 1 tSCLK_HI tSU_MO MOSI tH_MO tSCLK tia tSCLK_MI MISO tSCLK_LO Figure 4.2. SPI Slave Timing Diagram Typical performance curves indicate typical characterized performance under the stated conditions. silabs.com | Smart. Connected. Energy-friendly. l 4.2 Typical Performance Curves Preliminary Rev. 1.1 | 51 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.2.1 Supply Current on C Figure 4.3. EM0 Active Mode Typical Supply Current tia en fid Figure 4.4. EM1 Sleep Mode Typical Supply Current l Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 52 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications tia en fid on C Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 53 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.2.2 DC-DC Converter Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz tia en fid on C l Figure 4.6. DC-DC Converter Typical Performance Characteristics silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 54 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications Load Step Response in LN (CCM) mode (Heavy Drive) LN (CCM) and LP mode transition (load: 5mA) DVDD DVDD 60mV/div offset:1.8V 50mV/div offset:1.8V 100mA C VSW ILOAD 2V/div offset:1.8V 1mA 10μs/div 100μs/div on Figure 4.7. DC-DC Converter Transition Waveforms tia en fid l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 55 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.2.3 Internal Oscillators on C Figure 4.8. HFRCO and AUXHFRCO Typical Performance at 38 MHz tia en fid Figure 4.9. HFRCO and AUXHFRCO Typical Performance at 32 MHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 56 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.10. HFRCO and AUXHFRCO Typical Performance at 26 MHz tia en fid Figure 4.11. HFRCO and AUXHFRCO Typical Performance at 19 MHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 57 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.12. HFRCO and AUXHFRCO Typical Performance at 16 MHz tia en fid Figure 4.13. HFRCO and AUXHFRCO Typical Performance at 13 MHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 58 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.14. HFRCO and AUXHFRCO Typical Performance at 7 MHz tia en fid Figure 4.15. HFRCO and AUXHFRCO Typical Performance at 4 MHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 59 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.16. HFRCO and AUXHFRCO Typical Performance at 2 MHz tia en fid Figure 4.17. HFRCO and AUXHFRCO Typical Performance at 1 MHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 60 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.18. LFRCO Typical Performance at 32.768 kHz tia en fid Figure 4.19. ULFRCO Typical Performance at 1 kHz l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 61 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications 4.2.4 2.4 GHz Radio tia en fid on C silabs.com | Smart. Connected. Energy-friendly. l Figure 4.20. 2.4 GHz RF Transmitter Output Power Preliminary Rev. 1.1 | 62 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Electrical Specifications on C Figure 4.21. 2.4 GHz RF Receiver Sensitivity tia en fid l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 63 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Typical Connection Diagrams 5. Typical Connection Diagrams 5.1 Power Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure. VDD Main Supply + – VREGVDD AVDD C VREGSW IOVDD HFXTAL_N VREGVSS HFXTAL_P DVDD LFXTAL_N LFXTAL_P on DECOUPLE RFVDD PAVDD Figure 5.1. EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter fid Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter supply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs supporting high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm. VDD + – en Main Supply VREGVDD VDCDC AVDD VREGSW HFXTAL_N VREGVSS HFXTAL_P LFXTAL_N tia DVDD IOVDD LFXTAL_P DECOUPLE RFVDD PAVDD l Figure 5.2. EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 64 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Typical Connection Diagrams VDD Main Supply + – VREGVDD VDCDC AVDD VREGSW IOVDD HFXTAL_N VREGVSS HFXTAL_P DVDD LFXTAL_N LFXTAL_P C DECOUPLE RFVDD PAVDD on Figure 5.3. EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD) 5.2 RF Matching Networks fid Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65 for applications in the 2.4GHz band. Application-specific component values can be found in the EFR32 Reference Manual. For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm). 4-Element Match for 2.4GHz Band 2-Element Match for 2.4GHz Band PAVDD PAVDD PAVDD L0 2G4RF_IOP 2G4RF_ION en PAVDD 50Ω C0 L0 L1 2G4RF_IOP 2G4RF_ION C0 50Ω C1 tia Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits 5.3 Other Connections Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware Design Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes). l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 65 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions 6. Pin Definitions 6.1 EFR32BG1 CSP43 2.4 GHz Definition en fid on C Figure 6.1. EFR32BG1 CSP43 2.4 GHz Pinout tia l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 66 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Table 6.1. CSP43 2.4 GHz Device Pinout CSP Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name A1 VREGSW DCDC regulator switching node A2 VREGVDD Voltage regulator VDD input A3 DECOUPLE Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin. A4 IOVDD Analog C Communication PF0 US0_TX #24 US0_RX #23 US0_CLK #22 US0_CS #21 US0_CTS #20 US0_RTS #19 US1_TX #24 US1_RX #23 US1_CLK #22 US1_CS #21 US1_CTS #20 US1_RTS #19 LEU0_TX #24 LEU0_RX #23 I2C0_SDA #24 I2C0_SCL #23 FRC_DCLK #24 FRC_DOUT #23 FRC_DFRAME #22 MODEM_DCLK #24 MODEM_DIN #23 MODEM_DOUT #22 MODEM_ANT0 #21 MODEM_ANT1 #20 PRS_CH0 #0 PRS_CH1 #7 PRS_CH2 #6 PRS_CH3 #5 ACMP0_O #24 ACMP1_O #24 DBG_SWCLKTCK #0 BUSAX BUSBY TIM0_CC0 #25 TIM0_CC1 #24 TIM0_CC2 #23 TIM0_CDTI0 #22 TIM0_CDTI1 #21 TIM0_CDTI2 #20 TIM1_CC0 #25 TIM1_CC1 #24 TIM1_CC2 #23 TIM1_CC3 #22 LETIM0_OUT0 #25 LETIM0_OUT1 #24 PCNT0_S0IN #25 PCNT0_S1IN #24 US0_TX #25 US0_RX #24 US0_CLK #23 US0_CS #22 US0_CTS #21 US0_RTS #20 US1_TX #25 US1_RX #24 US1_CLK #23 US1_CS #22 US1_CTS #21 US1_RTS #20 LEU0_TX #25 LEU0_RX #24 I2C0_SDA #25 I2C0_SCL #24 FRC_DCLK #25 FRC_DOUT #24 FRC_DFRAME #23 MODEM_DCLK #25 MODEM_DIN #24 MODEM_DOUT #23 MODEM_ANT0 #22 MODEM_ANT1 #21 PRS_CH0 #1 PRS_CH1 #0 PRS_CH2 #7 PRS_CH3 #6 ACMP0_O #25 ACMP1_O #25 DBG_SWDIOTMS #0 VREGVSS BUSBX Voltage regulator VSS tia B1 BUSAY en PF1 Other TIM0_CC0 #24 TIM0_CC1 #23 TIM0_CC2 #22 TIM0_CDTI0 #21 TIM0_CDTI1 #20 TIM0_CDTI2 #19 TIM1_CC0 #24 TIM1_CC1 #23 TIM1_CC2 #22 TIM1_CC3 #21 LETIM0_OUT0 #24 LETIM0_OUT1 #23 PCNT0_S0IN #24 PCNT0_S1IN #23 fid A7 Radio Digital IO power supply. on A6 Timers l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 67 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # Pin Name Pin Alternate Functionality / Description Analog LFXTAL_P PB15 BUSCY C B2 BUSDX Radio Other TIM0_CC0 #10 TIM0_CC1 #9 TIM0_CC2 #8 TIM0_CDTI0 #7 TIM0_CDTI1 #6 TIM0_CDTI2 #5 TIM1_CC0 #10 TIM1_CC1 #9 TIM1_CC2 #8 TIM1_CC3 #7 LETIM0_OUT0 #10 LETIM0_OUT1 #9 PCNT0_S0IN #10 PCNT0_S1IN #9 US0_TX #10 US0_RX #9 US0_CLK #8 US0_CS #7 US0_CTS #6 US0_RTS #5 US1_TX #10 US1_RX #9 US1_CLK #8 US1_CS #7 US1_CTS #6 US1_RTS #5 LEU0_TX #10 LEU0_RX #9 I2C0_SDA #10 I2C0_SCL #9 FRC_DCLK #10 FRC_DOUT #9 FRC_DFRAME #8 MODEM_DCLK #10 MODEM_DIN #9 MODEM_DOUT #8 MODEM_ANT0 #7 MODEM_ANT1 #6 CMU_CLK0 #1 PRS_CH6 #10 PRS_CH7 #9 PRS_CH8 #8 PRS_CH9 #7 ACMP0_O #10 ACMP1_O #10 DVDD TIM0_CC0 #11 TIM0_CC1 #10 TIM0_CC2 #9 TIM0_CDTI0 #8 TIM0_CDTI1 #7 TIM0_CDTI2 #6 TIM1_CC0 #11 TIM1_CC1 #10 TIM1_CC2 #9 TIM1_CC3 #8 LETIM0_OUT0 #11 LETIM0_OUT1 #10 PCNT0_S0IN #11 PCNT0_S1IN #10 US0_TX #11 US0_RX #10 US0_CLK #9 US0_CS #8 US0_CTS #7 US0_RTS #6 US1_TX #11 US1_RX #10 US1_CLK #9 US1_CS #8 US1_CTS #7 US1_RTS #6 LEU0_TX #11 LEU0_RX #10 I2C0_SDA #11 I2C0_SCL #10 FRC_DCLK #11 FRC_DOUT #10 FRC_DFRAME #9 MODEM_DCLK #11 MODEM_DIN #10 MODEM_DOUT #9 MODEM_ANT0 #8 MODEM_ANT1 #7 CMU_CLK0 #2 PRS_CH0 #8 PRS_CH9 #11 PRS_CH10 #0 PRS_CH11 #5 ACMP0_O #11 ACMP1_O #11 PC6 TIM0_CC0 #14 TIM0_CC1 #13 TIM0_CC2 #12 TIM0_CDTI0 #11 TIM0_CDTI1 #10 TIM0_CDTI2 #9 TIM1_CC0 #14 TIM1_CC1 #13 TIM1_CC2 #12 TIM1_CC3 #11 LETIM0_OUT0 #14 LETIM0_OUT1 #13 PCNT0_S0IN #14 PCNT0_S1IN #13 US0_TX #14 US0_RX #13 US0_CLK #12 US0_CS #11 US0_CTS #10 US0_RTS #9 US1_TX #14 US1_RX #13 US1_CLK #12 US1_CS #11 US1_CTS #10 US1_RTS #9 LEU0_TX #14 LEU0_RX #13 I2C0_SDA #14 I2C0_SCL #13 FRC_DCLK #14 FRC_DOUT #13 FRC_DFRAME #12 MODEM_DCLK #14 MODEM_DIN #13 MODEM_DOUT #12 MODEM_ANT0 #11 MODEM_ANT1 #10 Digital power supply. fid B4 Communication on B3 Timers BUSAX BUSBY PC9 BUSAY BUSBX l silabs.com | Smart. Connected. Energy-friendly. tia en B5 PRS_CH0 #11 PRS_CH9 #14 PRS_CH10 #3 PRS_CH11 #2 ACMP0_O #14 ACMP1_O #14 Preliminary Rev. 1.1 | 68 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # PF2 Analog BUSAX C B6 Pin Name Pin Alternate Functionality / Description BUSBY Communication Radio Other TIM0_CC0 #26 TIM0_CC1 #25 TIM0_CC2 #24 TIM0_CDTI0 #23 TIM0_CDTI1 #22 TIM0_CDTI2 #21 TIM1_CC0 #26 TIM1_CC1 #25 TIM1_CC2 #24 TIM1_CC3 #23 LETIM0_OUT0 #26 LETIM0_OUT1 #25 PCNT0_S0IN #26 PCNT0_S1IN #25 US0_TX #26 US0_RX #25 US0_CLK #24 US0_CS #23 US0_CTS #22 US0_RTS #21 US1_TX #26 US1_RX #25 US1_CLK #24 US1_CS #23 US1_CTS #22 US1_RTS #21 LEU0_TX #26 LEU0_RX #25 I2C0_SDA #26 I2C0_SCL #25 FRC_DCLK #26 FRC_DOUT #25 FRC_DFRAME #24 MODEM_DCLK #26 MODEM_DIN #25 MODEM_DOUT #24 MODEM_ANT0 #23 MODEM_ANT1 #22 CMU_CLK0 #6 PRS_CH0 #2 PRS_CH1 #1 PRS_CH2 #0 PRS_CH3 #7 ACMP0_O #26 ACMP1_O #26 DBG_TDO #0 DBG_SWO #0 GPIO_EM4WU0 TIM0_CC0 #27 TIM0_CC1 #26 TIM0_CC2 #25 TIM0_CDTI0 #24 TIM0_CDTI1 #23 TIM0_CDTI2 #22 TIM1_CC0 #27 TIM1_CC1 #26 TIM1_CC2 #25 TIM1_CC3 #24 LETIM0_OUT0 #27 LETIM0_OUT1 #26 PCNT0_S0IN #27 PCNT0_S1IN #26 US0_TX #27 US0_RX #26 US0_CLK #25 US0_CS #24 US0_CTS #23 US0_RTS #22 US1_TX #27 US1_RX #26 US1_CLK #25 US1_CS #24 US1_CTS #23 US1_RTS #22 LEU0_TX #27 LEU0_RX #26 I2C0_SDA #27 I2C0_SCL #26 FRC_DCLK #27 FRC_DOUT #26 FRC_DFRAME #25 MODEM_DCLK #27 MODEM_DIN #26 MODEM_DOUT #25 MODEM_ANT0 #24 MODEM_ANT1 #23 CMU_CLK1 #6 PRS_CH0 #3 PRS_CH1 #2 PRS_CH2 #1 PRS_CH3 #0 ACMP0_O #27 ACMP1_O #27 DBG_TDI #0 TIM0_CC0 #9 TIM0_CC1 #8 TIM0_CC2 #7 TIM0_CDTI0 #6 TIM0_CDTI1 #5 TIM0_CDTI2 #4 TIM1_CC0 #9 TIM1_CC1 #8 TIM1_CC2 #7 TIM1_CC3 #6 LETIM0_OUT0 #9 LETIM0_OUT1 #8 PCNT0_S0IN #9 PCNT0_S1IN #8 US0_TX #9 US0_RX #8 US0_CLK #7 US0_CS #6 US0_CTS #5 US0_RTS #4 US1_TX #9 US1_RX #8 US1_CLK #7 US1_CS #6 US1_CTS #5 US1_RTS #4 LEU0_TX #9 LEU0_RX #8 I2C0_SDA #9 I2C0_SCL #8 FRC_DCLK #9 FRC_DOUT #8 FRC_DFRAME #7 MODEM_DCLK #9 MODEM_DIN #8 MODEM_DOUT #7 MODEM_ANT0 #6 MODEM_ANT1 #5 PF3 C1 AVDD BUSAY BUSBX Analog power supply. C2 PB14 BUSCX BUSDY l silabs.com | Smart. Connected. Energy-friendly. CMU_CLK1 #1 PRS_CH6 #9 PRS_CH7 #8 PRS_CH8 #7 PRS_CH9 #6 ACMP0_O #9 ACMP1_O #9 tia LFXTAL_N en B7 fid on Timers Preliminary Rev. 1.1 | 69 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # PB13 Analog BUSCY C C3 Pin Name Pin Alternate Functionality / Description BUSDX Communication Radio Other TIM0_CC0 #8 TIM0_CC1 #7 TIM0_CC2 #6 TIM0_CDTI0 #5 TIM0_CDTI1 #4 TIM0_CDTI2 #3 TIM1_CC0 #8 TIM1_CC1 #7 TIM1_CC2 #6 TIM1_CC3 #5 LETIM0_OUT0 #8 LETIM0_OUT1 #7 PCNT0_S0IN #8 PCNT0_S1IN #7 US0_TX #8 US0_RX #7 US0_CLK #6 US0_CS #5 US0_CTS #4 US0_RTS #3 US1_TX #8 US1_RX #7 US1_CLK #6 US1_CS #5 US1_CTS #4 US1_RTS #3 LEU0_TX #8 LEU0_RX #7 I2C0_SDA #8 I2C0_SCL #7 FRC_DCLK #8 FRC_DOUT #7 FRC_DFRAME #6 MODEM_DCLK #8 MODEM_DIN #7 MODEM_DOUT #6 MODEM_ANT0 #5 MODEM_ANT1 #4 PRS_CH6 #8 PRS_CH7 #7 PRS_CH8 #6 PRS_CH9 #5 ACMP0_O #8 ACMP1_O #8 DBG_SWO #1 GPIO_EM4WU9 TIM0_CC0 #12 TIM0_CC1 #11 TIM0_CC2 #10 TIM0_CDTI0 #9 TIM0_CDTI1 #8 TIM0_CDTI2 #7 TIM1_CC0 #12 TIM1_CC1 #11 TIM1_CC2 #10 TIM1_CC3 #9 LETIM0_OUT0 #12 LETIM0_OUT1 #11 PCNT0_S0IN #12 PCNT0_S1IN #11 US0_TX #12 US0_RX #11 US0_CLK #10 US0_CS #9 US0_CTS #8 US0_RTS #7 US1_TX #12 US1_RX #11 US1_CLK #10 US1_CS #9 US1_CTS #8 US1_RTS #7 LEU0_TX #12 LEU0_RX #11 I2C0_SDA #12 I2C0_SCL #11 FRC_DCLK #12 FRC_DOUT #11 FRC_DFRAME #10 MODEM_DCLK #12 MODEM_DIN #11 MODEM_DOUT #10 MODEM_ANT0 #9 MODEM_ANT1 #8 CMU_CLK1 #2 PRS_CH0 #9 PRS_CH9 #12 PRS_CH10 #1 PRS_CH11 #0 ACMP0_O #12 ACMP1_O #12 TIM0_CC0 #13 TIM0_CC1 #12 TIM0_CC2 #11 TIM0_CDTI0 #10 TIM0_CDTI1 #9 TIM0_CDTI2 #8 TIM1_CC0 #13 TIM1_CC1 #12 TIM1_CC2 #11 TIM1_CC3 #10 LETIM0_OUT0 #13 LETIM0_OUT1 #12 PCNT0_S0IN #13 PCNT0_S1IN #12 US0_TX #13 US0_RX #12 US0_CLK #11 US0_CS #10 US0_CTS #9 US0_RTS #8 US1_TX #13 US1_RX #12 US1_CLK #11 US1_CS #10 US1_CTS #9 US1_RTS #8 LEU0_TX #13 LEU0_RX #12 I2C0_SDA #13 I2C0_SCL #12 FRC_DCLK #13 FRC_DOUT #12 FRC_DFRAME #11 MODEM_DCLK #13 MODEM_DIN #12 MODEM_DOUT #11 MODEM_ANT0 #10 MODEM_ANT1 #9 C4 BUSBX BUSAX BUSBY PRS_CH0 #10 PRS_CH9 #13 PRS_CH10 #2 PRS_CH11 #1 ACMP0_O #13 ACMP1_O #13 tia PC8 BUSAY en C5 PC7 fid on Timers l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 70 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # PF4 Analog BUSAX C C6 Pin Name Pin Alternate Functionality / Description BUSBY Communication Radio Other TIM0_CC0 #28 TIM0_CC1 #27 TIM0_CC2 #26 TIM0_CDTI0 #25 TIM0_CDTI1 #24 TIM0_CDTI2 #23 TIM1_CC0 #28 TIM1_CC1 #27 TIM1_CC2 #26 TIM1_CC3 #25 LETIM0_OUT0 #28 LETIM0_OUT1 #27 PCNT0_S0IN #28 PCNT0_S1IN #27 US0_TX #28 US0_RX #27 US0_CLK #26 US0_CS #25 US0_CTS #24 US0_RTS #23 US1_TX #28 US1_RX #27 US1_CLK #26 US1_CS #25 US1_CTS #24 US1_RTS #23 LEU0_TX #28 LEU0_RX #27 I2C0_SDA #28 I2C0_SCL #27 FRC_DCLK #28 FRC_DOUT #27 FRC_DFRAME #26 MODEM_DCLK #28 MODEM_DIN #27 MODEM_DOUT #26 MODEM_ANT0 #25 MODEM_ANT1 #24 PRS_CH0 #4 PRS_CH1 #3 PRS_CH2 #2 PRS_CH3 #1 ACMP0_O #28 ACMP1_O #28 TIM0_CC0 #29 TIM0_CC1 #28 TIM0_CC2 #27 TIM0_CDTI0 #26 TIM0_CDTI1 #25 TIM0_CDTI2 #24 TIM1_CC0 #29 TIM1_CC1 #28 TIM1_CC2 #27 TIM1_CC3 #26 LETIM0_OUT0 #29 LETIM0_OUT1 #28 PCNT0_S0IN #29 PCNT0_S1IN #28 US0_TX #29 US0_RX #28 US0_CLK #27 US0_CS #26 US0_CTS #25 US0_RTS #24 US1_TX #29 US1_RX #28 US1_CLK #27 US1_CS #26 US1_CTS #25 US1_RTS #24 LEU0_TX #29 LEU0_RX #28 I2C0_SDA #29 I2C0_SCL #28 FRC_DCLK #29 FRC_DOUT #28 FRC_DFRAME #27 MODEM_DCLK #29 MODEM_DIN #28 MODEM_DOUT #27 MODEM_ANT0 #26 MODEM_ANT1 #25 PRS_CH0 #5 PRS_CH1 #4 PRS_CH2 #3 PRS_CH3 #2 ACMP0_O #29 ACMP1_O #29 TIM0_CC0 #7 TIM0_CC1 #6 TIM0_CC2 #5 TIM0_CDTI0 #4 TIM0_CDTI1 #3 TIM0_CDTI2 #2 TIM1_CC0 #7 TIM1_CC1 #6 TIM1_CC2 #5 TIM1_CC3 #4 LETIM0_OUT0 #7 LETIM0_OUT1 #6 PCNT0_S0IN #7 PCNT0_S1IN #6 US0_TX #7 US0_RX #6 US0_CLK #5 US0_CS #4 US0_CTS #3 US0_RTS #2 US1_TX #7 US1_RX #6 US1_CLK #5 US1_CS #4 US1_CTS #3 US1_RTS #2 LEU0_TX #7 LEU0_RX #6 I2C0_SDA #7 I2C0_SCL #6 FRC_DCLK #7 FRC_DOUT #6 FRC_DFRAME #5 MODEM_DCLK #7 MODEM_DIN #6 MODEM_DOUT #5 MODEM_ANT0 #4 MODEM_ANT1 #3 C7 BUSBX BUSCX BUSDY PRS_CH6 #7 PRS_CH7 #6 PRS_CH8 #5 PRS_CH9 #4 ACMP0_O #7 ACMP1_O #7 tia PB12 BUSAY en D1 PF5 fid on Timers l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 71 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # PB11 Analog BUSCY C D2 Pin Name Pin Alternate Functionality / Description BUSDX Communication Radio Other TIM0_CC0 #6 TIM0_CC1 #5 TIM0_CC2 #4 TIM0_CDTI0 #3 TIM0_CDTI1 #2 TIM0_CDTI2 #1 TIM1_CC0 #6 TIM1_CC1 #5 TIM1_CC2 #4 TIM1_CC3 #3 LETIM0_OUT0 #6 LETIM0_OUT1 #5 PCNT0_S0IN #6 PCNT0_S1IN #5 US0_TX #6 US0_RX #5 US0_CLK #4 US0_CS #3 US0_CTS #2 US0_RTS #1 US1_TX #6 US1_RX #5 US1_CLK #4 US1_CS #3 US1_CTS #2 US1_RTS #1 LEU0_TX #6 LEU0_RX #5 I2C0_SDA #6 I2C0_SCL #5 FRC_DCLK #6 FRC_DOUT #5 FRC_DFRAME #4 MODEM_DCLK #6 MODEM_DIN #5 MODEM_DOUT #4 MODEM_ANT0 #3 MODEM_ANT1 #2 PRS_CH6 #6 PRS_CH7 #5 PRS_CH8 #4 PRS_CH9 #3 ACMP0_O #6 ACMP1_O #6 TIM0_CC0 #1 TIM0_CC1 #0 TIM0_CC2 #31 TIM0_CDTI0 #30 TIM0_CDTI1 #29 TIM0_CDTI2 #28 TIM1_CC0 #1 TIM1_CC1 #0 TIM1_CC2 #31 TIM1_CC3 #30 LETIM0_OUT0 #1 LETIM0_OUT1 #0 PCNT0_S0IN #1 PCNT0_S1IN #0 US0_TX #1 US0_RX #0 US0_CLK #31 US0_CS #30 US0_CTS #29 US0_RTS #28 US1_TX #1 US1_RX #0 US1_CLK #31 US1_CS #30 US1_CTS #29 US1_RTS #28 LEU0_TX #1 LEU0_RX #0 I2C0_SDA #1 I2C0_SCL #0 FRC_DCLK #1 FRC_DOUT #0 FRC_DFRAME #31 MODEM_DCLK #1 MODEM_DIN #0 MODEM_DOUT #31 MODEM_ANT0 #30 MODEM_ANT1 #29 CMU_CLK0 #0 PRS_CH6 #1 PRS_CH7 #0 PRS_CH8 #10 PRS_CH9 #9 ACMP0_O #1 ACMP1_O #1 TIM0_CC0 #15 TIM0_CC1 #14 TIM0_CC2 #13 TIM0_CDTI0 #12 TIM0_CDTI1 #11 TIM0_CDTI2 #10 TIM1_CC0 #15 TIM1_CC1 #14 TIM1_CC2 #13 TIM1_CC3 #12 LETIM0_OUT0 #15 LETIM0_OUT1 #14 PCNT0_S0IN #15 PCNT0_S1IN #14 US0_TX #15 US0_RX #14 US0_CLK #13 US0_CS #12 US0_CTS #11 US0_RTS #10 US1_TX #15 US1_RX #14 US1_CLK #13 US1_CS #12 US1_CTS #11 US1_RTS #10 LEU0_TX #15 LEU0_RX #14 I2C0_SDA #15 I2C0_SCL #14 FRC_DCLK #15 FRC_DOUT #14 FRC_DFRAME #13 MODEM_DCLK #15 MODEM_DIN #14 MODEM_DOUT #13 MODEM_ANT0 #12 MODEM_ANT1 #11 on Timers D3 PA1 BUSCY BUSDX D4 PC10 Ground BUSAX BUSBY l silabs.com | Smart. Connected. Energy-friendly. CMU_CLK1 #3 PRS_CH0 #12 PRS_CH9 #15 PRS_CH10 #4 PRS_CH11 #3 ACMP0_O #15 ACMP1_O #15 GPIO_EM4WU12 tia D5 VSS en fid ADC0_EXTP Preliminary Rev. 1.1 | 72 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions CSP Pin# and Name Pin # Pin Name PC11 D7 RFVDD Analog BUSAY C D6 Pin Alternate Functionality / Description BUSBX Radio Other TIM0_CC0 #16 TIM0_CC1 #15 TIM0_CC2 #14 TIM0_CDTI0 #13 TIM0_CDTI1 #12 TIM0_CDTI2 #11 TIM1_CC0 #16 TIM1_CC1 #15 TIM1_CC2 #14 TIM1_CC3 #13 LETIM0_OUT0 #16 LETIM0_OUT1 #15 PCNT0_S0IN #16 PCNT0_S1IN #15 US0_TX #16 US0_RX #15 US0_CLK #14 US0_CS #13 US0_CTS #12 US0_RTS #11 US1_TX #16 US1_RX #15 US1_CLK #14 US1_CS #13 US1_CTS #12 US1_RTS #11 LEU0_TX #16 LEU0_RX #15 I2C0_SDA #16 I2C0_SCL #15 FRC_DCLK #16 FRC_DOUT #15 FRC_DFRAME #14 MODEM_DCLK #16 MODEM_DIN #15 MODEM_DOUT #14 MODEM_ANT0 #13 MODEM_ANT1 #12 CMU_CLK0 #3 PRS_CH0 #13 PRS_CH9 #16 PRS_CH10 #5 PRS_CH11 #4 ACMP0_O #16 ACMP1_O #16 DBG_SWO #3 TIM0_CC0 #0 TIM0_CC1 #31 TIM0_CC2 #30 TIM0_CDTI0 #29 TIM0_CDTI1 #28 TIM0_CDTI2 #27 TIM1_CC0 #0 TIM1_CC1 #31 TIM1_CC2 #30 TIM1_CC3 #29 LETIM0_OUT0 #0 LETIM0_OUT1 #31 PCNT0_S0IN #0 PCNT0_S1IN #31 US0_TX #0 US0_RX #31 US0_CLK #30 US0_CS #29 US0_CTS #28 US0_RTS #27 US1_TX #0 US1_RX #31 US1_CLK #30 US1_CS #29 US1_CTS #28 US1_RTS #27 LEU0_TX #0 LEU0_RX #31 I2C0_SDA #0 I2C0_SCL #31 FRC_DCLK #0 FRC_DOUT #31 FRC_DFRAME #30 MODEM_DCLK #0 MODEM_DIN #31 MODEM_DOUT #30 MODEM_ANT0 #29 MODEM_ANT1 #28 CMU_CLK1 #0 PRS_CH6 #0 PRS_CH7 #10 PRS_CH8 #9 PRS_CH9 #8 ACMP0_O #0 ACMP1_O #0 on Communication Radio power supply PA0 BUSCX BUSDY en fid ADC0_EXTN E1 Timers VSS Ground E3 VSS Ground E4 VSS Ground E5 VSS Ground E6 VSS Ground E7 HFXTAL_N F1 VSS F2 2G4RF_IOP 2.4 GHz Differential RF input/output, positive path. F3 2G4RF_ION 2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded. F4 PAVSS Power Amplifier (PA) voltage regulator VSS F5 RFVSS Radio Ground F6 VSS F7 HFXTAL_P G1 PAVDD Power Amplifier (PA) voltage regulator VDD input G7 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. High Frequency Crystal input pin. Ground tia E2 l Ground High Frequency Crystal output pin. silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 73 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions 6.1.1 EFR32BG1 CSP43 2.4 GHz GPIO Overview The GPIO pins are organized as 16-bit ports indicated by letters (A, B, C...), and the individual pins on each port are indicated by a number from 15 down to 0. Table 6.2. CSP43 2.4 GHz GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A - - - - - - - - - - - - - - PA1 PA0 - - - - - - - - - - - PC9 (5V) PC8 (5V) PC7 (5V) PC6 (5V) - - - - - - - - - - PF5 (5V) PF4 (5V) PF3 (5V) PF2 (5V) PF1 (5V) PF0 (5V) PB15 PB14 PB13 PB12 PB11 (5V) (5V) (5V) C Port B - - - - Port F - - - - PC11 PC10 (5V) (5V) - - on Port C Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Note: 1. GPIO with 5V tolerance are indicated by (5V). 2. The pins PB13, PB12, and PB11 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains. tia en fid l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 74 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions 6.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 6.3. Alternate functionality overview C Alternate Functionality 4-7 8 - 11 12 - 15 16 - 19 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 0: PA0 1: PA1 ACMP0_O on ACMP1_O 0-3 LOCATION 0: PA0 1: PA1 20 - 23 24 - 27 28 - 31 0: PA0 CMU_CLK1 0: PA0 1: PB14 2: PC7 3: PC10 6: PF2 6: PF3 DBG_SWCLKTCK Clock Management Unit, clock output number 0. Clock Management Unit, clock output number 1. Debug-interface Serial Wire clock input and JTAG Test Clock. tia 0: PF0 Analog comparator ACMP1, digital output. Analog to digital converter ADC0 external reference input positive pin en CMU_CLK0 0: PA1 1: PB15 2: PC6 3: PC11 fid ADC0_EXTP Analog comparator ACMP0, digital output. Analog to digital converter ADC0 external reference input negative pin ADC0_EXTN 0: PA1 Description Note that this function is enabled to the pin out of reset, and has a built-in pull down. l 0: PF1 DBG_SWDIOTMS silabs.com | Smart. Connected. Energy-friendly. Debug-interface Serial Wire data input / output and JTAG Test Mode Select. Note that this function is enabled to the pin out of reset, and has a built-in pull up. Preliminary Rev. 1.1 | 75 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Debug-interface Serial Wire viewer Output. 0: PF2 1: PB13 DBG_SWO Note that this function is not enabled after reset, and must be enabled by software to be used. 3: PC11 C Debug-interface JTAG Test Data In. 0: PF3 Note that this function is enabled to pin out of reset, and has a built-in pull up. DBG_TDI on Debug-interface JTAG Test Data Out. 0: PF2 DBG_TDO 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 0: PA1 FRC_DOUT 0: PF2 16: PC11 24: PF0 25: PF1 26: PF2 27: PF3 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 30: PA0 31: PA1 28: PF5 31: PA0 Frame Controller, Data Sniffer Clock. Frame Controller, Data Sniffer Frame active Frame Controller, Data Sniffer Output. Pin can be used to wake the system up from EM4 tia GPIO_EM4WU0 0: PB13 Pin can be used to wake the system up from EM4 GPIO_EM4WU9 l 0: PC10 Pin can be used to wake the system up from EM4 GPIO_EM4WU12 0: PA1 I2C0_SCL 28: PF4 29: PF5 en FRC_DFRAME Note that this function is enabled to pin out of reset. fid FRC_DCLK 0: PA0 1: PA1 Description 5: PB11 6: PB12 7: PB13 silabs.com | Smart. Connected. Energy-friendly. 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 I2C0 Serial Clock Line input / output. 31: PA0 Preliminary Rev. 1.1 | 76 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 12 - 15 16 - 19 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 0: PA0 1: PA1 I2C0_SDA LETIM0_OUT0 0: PA0 1: PA1 C 0: PA1 LETIM0_OUT1 LEU0_RX LEU0_TX on 0: PA1 0: PA0 1: PA1 LFXTAL_N LFXTAL_P MODEM_ANT1 MODEM_DCLK MODEM_DOUT 28: PF4 29: PF5 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 28: PF5 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 16: PC11 31: PA0 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 0: PA0 1: PA1 silabs.com | Smart. Connected. Energy-friendly. Low Energy Timer LETIM0, output channel 0. Low Energy Timer LETIM0, output channel 1. LEUART0 Receive input. 31: PA0 LEUART0 Transmit output. Also used as receive input in half duplex communication. Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. Low Frequency Crystal (typically 32.768 kHz) positive pin. 24: PF3 25: PF4 26: PF5 29: PA0 30: PA1 24: PF4 25: PF5 28: PA0 29: PA1 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 28: PF5 23: PF0 24: PF1 25: PF2 26: PF3 27: PF4 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 21: PF0 22: PF1 23: PF2 20: PF0 21: PF1 22: PF2 23: PF3 16: PC11 I2C0 Serial Data input / output. MODEM antenna control output 0, used for antenna diversity. MODEM antenna control output 1, used for antenna diversity. MODEM data clock out. l 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 0: PA1 MODEM_DIN 24: PF0 25: PF1 26: PF2 27: PF3 Description tia 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 MODEM_ANT0 28 - 31 en 0: PB15 24 - 27 fid 0: PB14 20 - 23 MODEM data in. 31: PA0 30: PA0 31: PA1 MODEM data out. Preliminary Rev. 1.1 | 77 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Alternate LOCATION Functionality PCNT0_S0IN 0-3 4-7 8 - 11 12 - 15 16 - 19 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 0: PA0 1: PA1 0: PA1 PCNT0_S1IN C 4: PF4 5: PF5 4: PF5 PRS_CH1 0: PF1 1: PF2 2: PF3 3: PF4 PRS_CH2 PRS_CH6 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 31: PA0 0: PF2 1: PF3 2: PF4 3: PF5 0: PF3 1: PF4 2: PF5 0: PA0 1: PA1 8: PB15 9: PA0 10: PA1 PRS_CH9 4: PB12 5: PB13 6: PB14 7: PB15 8: PA0 9: PA1 3: PB11 4: PC10 5: PC11 PRS_CH11 0: PC7 1: PC8 2: PC9 3: PC10 4: PC11 5: PC6 0: PA0 1: PA1 6: PB11 7: PB12 silabs.com | Smart. Connected. Energy-friendly. 16: PC11 Peripheral Reflex System PRS, channel 8. Peripheral Reflex System PRS, channel 9. Peripheral Reflex System PRS, channel 10. l PRS_CH10 0: PC6 1: PC7 2: PC8 3: PC9 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 Peripheral Reflex System PRS, channel 7. tia PRS_CH8 4: PB11 5: PB12 6: PB13 7: PB14 Peripheral Reflex System PRS, channel 6. en PRS_CH7 Peripheral Reflex System PRS, channel 3. 8: PB13 9: PB14 10: PB15 8: PB14 9: PB15 10: PA0 Pulse Counter PCNT0 input number 1. Peripheral Reflex System PRS, channel 2. 5: PF0 6: PF1 7: PF2 5: PB11 6: PB12 7: PB13 Pulse Counter PCNT0 input number 0. Peripheral Reflex System PRS, channel 1. 6: PF0 7: PF1 6: PB11 7: PB12 Description Peripheral Reflex System PRS, channel 0. 7: PF0 0: PA1 TIM0_CC0 28 - 31 fid PRS_CH3 23: PF0 24 - 27 on PRS_CH0 0: PF0 1: PF1 2: PF2 3: PF3 20 - 23 Peripheral Reflex System PRS, channel 11. 8: PB13 9: PB14 10: PB15 11: PC6 12: PC7 13: PC8 14: PC9 15: PC10 16: PC11 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 Timer 0 Capture Compare input / output channel 0. Preliminary Rev. 1.1 | 78 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 0: PA1 TIM0_CC1 TIM0_CC2 C TIM0_CDTI0 3: PB11 12 - 15 on TIM0_CDTI1 TIM0_CDTI2 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 12: PC8 13: PC9 14: PC10 15: PC11 TIM1_CC2 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 TIM1_CC3 4: PB12 5: PB13 6: PB14 7: PB15 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 US0_CLK 4: PB11 5: PB12 6: PB13 7: PB14 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 US0_CS 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 0: PA1 TIM1_CC1 22: PF0 23: PF1 24: PF2 25: PF3 26: PF4 27: PF5 30: PA0 31: PA1 24: PF3 25: PF4 26: PF5 29: PA0 30: PA1 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 28: PA0 29: PA1 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 28: PA1 silabs.com | Smart. Connected. Energy-friendly. 23: PF0 31: PA0 27: PA0 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 24: PF1 25: PF2 26: PF3 27: PF4 28: PF5 31: PA0 22: PF0 23: PF1 21: PF0 22: PF1 23: PF2 24: PF2 25: PF3 26: PF4 27: PF5 30: PA0 31: PA1 24: PF3 25: PF4 26: PF5 29: PA0 30: PA1 Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Dead Time Insertion channel 0. Timer 0 Complimentary Dead Time Insertion channel 1. Timer 0 Complimentary Dead Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 1 Capture Compare input / output channel 3. 24: PF2 25: PF3 26: PF4 27: PF5 30: PA0 31: PA1 24: PF3 25: PF4 26: PF5 29: PA0 30: PA1 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 28: PA0 29: PA1 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 28: PA1 22: PF0 23: PF1 21: PF0 22: PF1 23: PF2 19: PF0 27: PA0 USART0 clock input / output. USART0 chip select input / output. l US0_RTS 23: PF0 16: PC11 28: PF5 Description tia US0_CTS 28 - 31 en 3: PB11 24 - 27 24: PF1 25: PF2 26: PF3 27: PF4 fid 6: PB11 7: PB12 12: PC7 13: PC8 14: PC9 15: PC10 20 - 23 21: PF0 22: PF1 23: PF2 19: PF0 8: PB13 9: PB14 10: PB15 11: PC6 TIM1_CC0 0: PA0 1: PA1 16 - 19 USART0 Clear To Send hardware flow control input. USART0 Request To Send hardware flow control output. Preliminary Rev. 1.1 | 79 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Alternate LOCATION Functionality 0-3 4-7 8 - 11 5: PB11 6: PB12 7: PB13 8: PB14 9: PB15 10: PC6 11: PC7 0: PA1 US0_RX C US0_TX 8: PB15 9: PC6 10: PC7 11: PC8 12: PC9 13: PC10 14: PC11 8: PC6 9: PC7 10: PC8 11: PC9 12: PC10 13: PC11 3: PB11 4: PB12 5: PB13 6: PB14 7: PB15 8: PC7 9: PC8 10: PC9 11: PC10 12: PC11 2: PB11 3: PB12 4: PB13 5: PB14 6: PB15 7: PC6 1: PB11 2: PB12 3: PB13 4: PB14 5: PB15 6: PC6 7: PC7 8: PC8 9: PC9 10: PC10 11: PC11 23: PF0 16: PC11 US1_RX 0: PA0 1: PA1 24: PF0 25: PF1 26: PF2 27: PF3 silabs.com | Smart. Connected. Energy-friendly. 8: PB13 9: PB14 10: PB15 11: PC6 28: PF5 31: PA0 28: PF4 29: PF5 30: PA0 31: PA1 24: PF3 25: PF4 26: PF5 29: PA0 30: PA1 20: PF0 21: PF1 22: PF2 23: PF3 24: PF4 25: PF5 28: PA0 29: PA1 20: PF1 21: PF2 22: PF3 23: PF4 24: PF5 28: PA1 21: PF0 22: PF1 23: PF2 19: PF0 12: PC8 13: PC9 14: PC10 15: PC11 12: PC7 13: PC8 14: PC9 15: PC10 23: PF0 16: PC11 27: PA0 24: PF1 25: PF2 26: PF3 27: PF4 USART0 Asynchronous Receive. USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit. Also used as receive input in half duplex communication. USART0 Synchronous mode Master Output / Slave Input (MOSI). 24: PF2 25: PF3 26: PF4 27: PF5 22: PF0 23: PF1 Description 28: PF5 31: PA0 USART1 clock input / output. USART1 chip select input / output. USART1 Clear To Send hardware flow control input. USART1 Request To Send hardware flow control output. USART1 Asynchronous Receive. USART1 Synchronous mode Master Input / Slave Output (MISO). 24: PF0 25: PF1 26: PF2 27: PF3 28: PF4 29: PF5 USART1 Asynchronous Transmit. Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). l 6: PB11 7: PB12 8: PB14 9: PB15 10: PC6 11: PC7 24: PF1 25: PF2 26: PF3 27: PF4 28 - 31 tia 5: PB11 6: PB12 7: PB13 24 - 27 en 0: PA1 US1_TX 12: PC7 13: PC8 14: PC9 15: PC10 20 - 23 fid US1_RTS 12: PC8 13: PC9 14: PC10 15: PC11 4: PB11 5: PB12 6: PB13 7: PB14 US1_CS US1_CTS 6: PB11 7: PB12 8: PB13 9: PB14 10: PB15 11: PC6 16 - 19 on US1_CLK 0: PA0 1: PA1 12 - 15 Preliminary Rev. 1.1 | 80 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions 6.3 Analog Port (APORT) Client Maps The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs, DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. A complete description of APORT functionality can be found in the Reference Manual. Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins. In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared bus used by this connection is indicated in the Bus column. CH0 CH1 CH2 CH3 CH4 PD10 PD9 PD11 PD13 PD12 PC6 PD14 PD15 PA0 PA1 PA2 PA3 PD10 PD9 PD11 PD12 PD13 PD14 PD15 PA0 PA1 PA2 PA3 PA5 PA5 CH5 CH6 PC6 CH7 PC8 PC7 PC7 PC8 PC9 PC10 PC9 PC11 PF0 CH8 CH9 CH10 PC10 PC11 PF1 PF2 PF3 PF4 PF1 PA4 PB12 PB11 PB11 PA4 PB12 PB13 PB13 PB15 PB15 PB14 BUSCX PF6 PF5 PF7 BUSBY PB14 l silabs.com | Smart. Connected. Energy-friendly. tia BUSCY en BUSDX CH11 CH12 CH13 CH14 CH15 CH16 PF0 PF2 PF3 PF5 PF4 PF6 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 PF7 BUSAY BUSBX fid BUSDY CH26 CH27 CH28 CH29 CH30 CH31 Bus BUSAX on APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port C Table 6.4. ACMP0 Bus and Pin Mapping Preliminary Rev. 1.1 | 81 C tia l silabs.com | Smart. Connected. Energy-friendly. PB12 PB14 BUSCY PB15 PB13 PB11 PB15 PB13 PB11 PD10 PD12 PD14 PA0 PA2 PA4 PD9 PD11 PD13 PD15 PA1 PA3 PA5 en PB12 PB14 BUSCX PD9 PD11 PD13 PD15 PA1 PA3 PA5 PD10 PD12 PD14 PA0 PA2 PA4 fid BUSDX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY BUSBX PC7 PC9 PC11 PF1 PF3 PF5 PF7 on BUSDY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Table 6.5. ACMP1 Bus and Pin Mapping Preliminary Rev. 1.1 | 82 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 l silabs.com | Smart. Connected. Energy-friendly. PA4 PB12 PB14 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 PD10 PD12 PD14 PA0 PA2 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 tia PB15 Bus Table 6.7. IDAC0 Bus and Pin Mapping PA4 PB12 PB14 BUSDY PD10 PD12 PD14 PA0 PA2 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX en PB12 PB14 BUSCX PD10 PD12 PD14 PA0 PA2 PA4 fid BUSCX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY BUSBX PC7 PC9 PC11 PF1 PF3 PF5 PF7 on BUSCY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port C APORT1Y APORT1X Port EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Pin Definitions Table 6.6. ADC0 Bus and Pin Mapping Preliminary Rev. 1.1 | 83 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet CSP Package Specifications 7. CSP Package Specifications 7.1 CSP Package Dimensions tia en fid on C Figure 7.1. CSP Package Drawing l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 84 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet CSP Package Specifications Table 7.1. CSP Package Dimensions Dimension Typ Max A 0.480 0.510 0.540 A1 0.175 0.190 0.205 c 0.270 0.295 0.320 c1 0.022 0.025 0.028 D 3.260 3.295 3.320 E 3.108 3.143 3.168 b 0.240 0.270 0.300 — 2.400 — — 2.400 — — 0.447 — — 0.302 — — 0.448 — — 0.441 — C Min D1 D2 E2 D3 E3 aaa bbb ccc ddd fid e on E1 0.400 — 0.10 0.10 0.03 0.15 en eee — 0.05 tia Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls. 4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”. 5. Minimum bump pitch 0.4mm. 6. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 85 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet CSP Package Specifications 7.2 CSP PCB Land Pattern en fid on C Figure 7.2. CSP PCB Land Pattern Drawing tia l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 86 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet CSP Package Specifications Table 7.2. CSP PCB Land Pattern Dimensions Typ X 0.20 C1 2.40 C2 2.40 E1 0.40 E2 0.40 C Dimension tia en fid on Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.075 mm (3 mils). 7. A stencil of square aperture (0.22 x 0.22 mm) is recommended. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 87 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet CSP Package Specifications 7.3 CSP Package Marking on C PPPPPPPPP TTTTTT YYWW # Figure 7.3. CSP Package Marking fid tia en The package marking consists of: • PPPPPPPPP – The part number designation. 1. Family Code (B | M | F) 2. G (Gecko) 3. Series (1, 2,...) 4. Performance Grade (P | B | V) 5. Feature Code (1 to 7) 6. TRX Code (3 = TXRX | 2= RX | 1 = TX) 7. Band (2 = 2.4 GHz) 8. Flash (G = 256K | F = 128K | E = 64K | D = 32K) 9. Temperature Grade (G = -40 to 85) • TTTTTT – A trace or manufacturing code. The first letter is the device revision. • YY – The last 2 digits of the assembly year. • WW – The 2-digit workweek when the device was assembled. • # – Bootloader revision number. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 88 EFR32BG1 Blue Gecko Bluetooth® Smart SoC CSP Family Data Sheet Revision History 8. Revision History 8.1 Revision 1.1 2016-Oct-26 C • Ordering Information: Removed Encryption column. All products in family include full encryption capabilites. Previously EFR32BG1V devices listed as "AES only". • System Overview Sections: Minor wording and typographical error fixes. • Electrical Characteristics: Minor wording and typographical error fixes. • "Current Consumption 3.3V with DC-DC" table in Electrical Characteristics: Typical values for EM2 and EM3 current updated with correct values from silicon characterization. • Pinout tables: APORT channel details removed from "Analog" column. This information is now found in the APORT client map sections. • Updated APORT client map sections. on 8.2 Revision 0.98 8.3 Revision 0.3 2015-11-2 Initial release of CSP package document. tia en fid 2016-July-6 • All OPNs changed to rev C0. Note the following: • All OPNs ending in -B0 are Engineering Samples based on an older revision of silicon and are being removed from the OPN table. These older revisions should be used for evaluation only and will not be supported for production. • OPNs ending in -C0 are the Current Revision of Silicon and are intended for production. • Updated OPN table to new format. • Updated OPN decoder figure to include extended family options. • Added supported modulation formats and protocols to feature list for P-grade devices. • Electrical specification tables updated with latest characterization data and production test limits. • Added graphs in typical performance curves for supply current, oscillator frequency and RF. • Updated DC-DC graphs in typical performance section. • Typical connection diagram formatting updated. • Pinout diagram formatting updated. • Removed BOOT_TX and BOOT_RX alternate functions from pin function tables. • Updated package marking diagram with latest inclusive version. l silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 1.1 | 89 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Radio. . . . . . . . . . . . 3.2.1 Antenna Interface . . . . . . . 3.2.2 Fractional-N Frequency Synthesizer. 3.2.3 Receiver Architecture. . . . . . 3.2.4 Transmitter Architecture . . . . . 3.2.5 Wake on Radio . . . . . . . . 3.2.6 RFSENSE . . . . . . . . . 3.2.7 Flexible Frame Handling. . . . . 3.2.8 Packet and State Trace . . . . . 3.2.9 Data Buffering . . . . . . . . 3.2.10 Radio Controller (RAC). . . . . 3.2.11 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Power . . . . . . . . . . 3.3.1 Energy Management Unit (EMU) . 3.3.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . 6 . 6 3.4 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . 6 3.5 Clocking . . . . . . . . . . 3.5.1 Clock Management Unit (CMU) . 3.5.2 Internal and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . 6 . 6 3.6 Counters/Timers and PWM . . . . . . . . 3.6.1 Timer/Counter (TIMER) . . . . . . . . . 3.6.2 Real Time Counter and Calendar (RTCC) . . . 3.6.3 Low Energy Timer (LETIMER). . . . . . . 3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) 3.6.5 Pulse Counter (PCNT) . . . . . . . . . 3.6.6 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 7 7 7 7 7 3.7 Communications and Other Digital Peripherals . . . . . . . . . 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) 3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . 3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 8 8 8 3.8 Security Features. . . . . . . . . . . . . . . 3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) . 3.8.2 Crypto Accelerator (CRYPTO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 8 . 8 3.9 Analog . . . . . . . . . . . . . 3.9.1 Analog Port (APORT) . . . . . . . 3.9.2 Analog Comparator (ACMP) . . . . . 3.9.3 Analog to Digital Converter (ADC) . . . 3.9.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table of Contents 3 3 4 4 4 4 4 5 5 5 5 5 8 8 8 9 9 90 3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . 9 3.11 Core and Memory . . . . . . . . . . . 3.11.1 Processor Core . . . . . . . . . . . 3.11.2 Memory System Controller (MSC) . . . . . 3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Memory Map . . . . . . . . . . 9 9 9 9 . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .11 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . 4.1.2.1 General Operating Conditions . . . . . . . . . . . . . . . . . . 4.1.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 Current Consumption. . . . . . . . . . . . . . . . . . . . . . 4.1.4.1 Current Consumption 3.3 V without DC-DC Converter . . . . . . . . . . 4.1.4.2 Current Consumption 3.3 V using DC-DC Converter . . . . . . . . . . 4.1.4.3 Current Consumption 1.85 V without DC-DC Converter . . . . . . . . . 4.1.4.4 Current Consumption Using Radio . . . . . . . . . . . . . . . . 4.1.5 Wake up times . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 Brown Out Detector . . . . . . . . . . . . . . . . . . . . . . 4.1.7 Frequency Synthesizer Characteristics . . . . . . . . . . . . . . . . 4.1.8 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . 4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band . . . . . . . 4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band . . . . . . . . 4.1.8.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band . . . . 4.1.8.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band. . . . . 4.1.8.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band . 4.1.8.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band. . 4.1.9 Modem Features . . . . . . . . . . . . . . . . . . . . . . . 4.1.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.4 HFRCO and AUXHFRCO . . . . . . . . . . . . . . . . . . . 4.1.10.5 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.11 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . 4.1.12 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13 VMON . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.14 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.15 IDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.16 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . 4.1.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.18 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .13 .14 .14 .15 .17 .17 .18 .20 .21 .22 .22 .23 .24 .24 .25 .26 .28 .30 .33 .34 .35 .35 .36 .36 .37 .37 .38 .39 .40 .41 .44 .46 .48 .50 4.2 Typical Performance Curves 4.2.1 Supply Current . . . . 4.2.2 DC-DC Converter . . . 4.2.3 Internal Oscillators. . . 4.2.4 2.4 GHz Radio . . . . . . . . . . . . . . . . . . . . . . . . .51 .52 .54 .56 .62 Table of Contents 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Power . . . . . 64 . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .65 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 . 6.1 EFR32BG1 CSP43 2.4 GHz Definition . . . 6.1.1 EFR32BG1 CSP43 2.4 GHz GPIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 .74 6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . .75 6.3 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . .81 . . . . . . . . . . . . . . . . . . . . . . . . 84 7.1 CSP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .84 7.2 CSP PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.3 CSP Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .88 8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7. CSP Package Specifications 8.1 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 8.2 Revision 0.98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 8.3 Revision 0.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table of Contents 92 . Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/IoT SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. 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