ETC2 DV2004L1 Fast charge development system control of pnp power transistor Datasheet

DV2004L1
Fast Charge Development System
Control of PNP Power Transistor
Features
➤ bq2004 fast-charge control evaluation and
development
➤ Charge current sourced from an on-board
frequency-modulated linear regulator (up to 3.0A)
➤ Fast charge of 4 to 10 NiCd or NiMH cells and one
user-defined selection
➤ Fast-charge termination by delta temperature/delta
time (∆T/∆t), negative delta voltage (-∆V) or peak
voltage detect, maximum temperature, maximum
time, and maximum voltage
➤ -∆V/peak voltage detect, hold-off, top-off, maximum
time, and number of cells are jumper-configurable
➤ Programmable charge status display
➤ Discharge-before-charge control with push-button
switch or auto discharge-before-charge with jumper
➤ Inhibit fast charge by logic-level input
General Description
The DV2004L1 Development System provides a development environment for the bq2004 Fast-Charge IC. The
DV2004L1 incorporates a bq2004 and a frequencymodulated linear regulator to provide fast charge control
for 4 to 10 NiCd or NiMH cells.
The fast charge is terminated by any of the following:
∆T/∆t, -∆V or peak voltage detect, maximum temperature, maximum time, maximum voltage, or an inhibit
command. Jumper settings select the voltage termination mode, the hold-off, top-off, and maximum time limits, and automatic discharge-before-charge.
Connection Descriptions
J1
The user provides a power supply and batteries. The
user configures the DV2004L1 for the number of cells,
voltage, charge termination mode, and maximum charge
time (with or without top-off), and commands the
discharge-before-charge option with the push-button
switch S1.
THERM
Thermistor connection
SNS
tor
Negative battery terminal and thermisconnection
Please review the bq2004 data sheet before using the
DV2004L1 board.
BAT
Positive battery terminal and high side
of discharge load
LOAD
Low side of discharge load
GND
Ground from charger supply
DC
JP1 INH
3/98
DC input from charger supply
Inhibit input
Rev. B Board
1
DV2004L1
JP2 DSEL
Display select
JP3 VSEL
Voltage termination select
JP4 TM1
TM1 setting
JP5 TM2
TM2 setting
JP6 NOC
Select number of cells
JP7
Auto discharge-before-charge select
With the provided NTC thermistor connected between
THERM and SNS, values are: LTF = 10°C, HTF = 49°C,
and TCO = 50°C. The ∆T/∆t settings at 30°C (T∆T) are:
minimum = 0.82°C/minute, typical = 1.10°C/minute.
The thermistor is identified by the serial number suffix
as follows:
Fixed Configuration
The DV2004L1 board has the following fixed characteristics :
■
VCC (4.75–5.25V) is regulated on-board from the supply at connector J1 (DC: GND).
■
LEDs indicate charge status.
■
Charge initiates on the later application of the battery or DC, which provides VCC to the bq2004.
Thermistor
K1
Keystone RL0703-5744-103-S1
(blank)
Philips 2322-640-63103
F1
Fenwal Type 16, 197-103LA6-A01
O1
Ozhumi 150-108-00(4)
S1
Semetic 103AT-2
Jumper-Selectable Configuration
The DV2004L1 must be configured as described below.
Pin DCMD may be tied to ground through JP7 for automatic discharge-before-charge. With JP7 open, a toggle
of switch S1 momentarily pulls DCMD low and initiates
a discharge-before-charge. The bq2004 output activates
FET Q1, allowing current to flow through an external
current-limiting load between BAT and LOAD on connector J1.
INH (JP1): Enables/disables charge inhibit (see bq2004
data sheet).
As shipped from Benchmarq, the DV2004L1 frequencymodulated linear regulator is configured to a charging
current of 1.13A. This current level is controlled by the
value of sense resistor RSNS by the relationship:
I CHG =
Identifier
Jumper Setting
Pin State
[12]3
Disabled (high)
1[23]
Enabled (low)
TM1 and TM2 (JP4 and JP5): Select fast charge
safety time/hold-off/top-off (see bq2004 data sheet).
0.225V
R SNS
The value of RSNS at shipment is 0.200Ω. This resistor
can be changed depending on the application.
The suggested maximum ICHG for the DV2004L1 board
is 3A. Q4 must be mounted to an appropriate heat
sink.
Jumper Setting
Pin State
[12]3
High
1[23]
Low
123
Float
Number of Cells (JP6): A resistor-divider network is
provided to select 4 to 10 cells (the resulting resistor
The maximum cell voltage (MCV) is scaled to 1.8V/cell.
Note: Use the bqCharge diskette to calculate the
RB1/RB2 resistors to adjust MCV.
Rev. B Board
2
Closed Jumper
Number of Cells
RB25
User-selectable
RB24
10
RB23
8
RB22
6
RB21
5
DV2004L1
value equals N 2 – 1 cells). RB1 is a 150KΩ resistor, and
RB2 (RB20–RB25) is jumper-selected.
Setup Procedure
Temperature Disable: Connecting a 10KΩ resistor between THERM and SNS disables temperature control.
1.
Configure VSEL, TM1, TM2, DSEL, INH, and
number-of-cells (NOC) jumpers.
DSEL (JP2): Selects LED1 and LED2 display state (see
bq2004 data sheet, Table 2).
2.
Connect the provided thermistor or a 10KΩ resistor
between THERM and SNS.
VSEL (JP3): Selects -∆V or peak-voltage detection, or
disables voltage-based termination (see bq2004 data
sheet).
3.
If using the discharge-before-charge option, connect
a current-limiting discharge load between BAT and
LOAD.
AUTO DIS SELECT (JP7): Jumping JP7 enables automatic discharge-before-charge.
4.
Attach the battery pack to BAT and SNS. For temperature control, the thermistor must contact the
cells.
5.
Attach DC current source to DC (+) and GND (-)
connections in J1. (Note: Capacitors C2 and C3
must be changed from those shipped with the board
for input voltage in excess of 25V.)
Recommended DC Operating Conditions
Symbol
Description
Minimum
Typical
Maximum
Unit
IDC
Maximum input current
-
-
3
A
VDC
Maximum input voltage
2.0 + VBAT
or 8.5
-
18 + VBAT
or 35
V
VBAT
BAT input voltage
-
-
24
V
VTHERM
THERM input voltage
0
-
5
V
IDSCHG
Discharge load current
-
-
2
A
Note:
Notes
Note 1
1. The voltage at R14 is application-specific and limits the dissipation of Q2 to a safe limit during Q4
conduction. See Table 1 for recommended R14 selections per VDC+ and ICHARGE.
Rev. B Board
3
DV2004L1
DV2004L1 Board Schematic
J1
1
2
3
4
5
6
THERM
SNS
BAT+
LOAD
GND
DC
D1
R13
+5V
1N5400
C1
1000UF
35V
Optional
D2
1N4148
U2
78L05ACZ
IN
C2
1000UF
35V
2K
RB1
200K
1%
R27
1M
Q3
JP6
Number of Cells
TIP42
+5V
+5V
OUT
GND
C3
100UF
25V
1
JP1
2
3
INH
C5
JP7
100UF AUTO_DIS.
6.3V
1
JP2
2
3
DSEL
JP3
VSEL
+5V
JP4
TM1
RT1
4.53K
1%
S1
+5V
0.1UF
R9
Q1
100K
4
5
6
8
RB20
200K
1%
RB21
133K
1%
RB22
100K
1%
RB23
66.5K
1%
300K
R5
27.4K
1%
10
RB24
49.9K
1%
RB25
USER_DEF.
1%
MTP3055VL
1
2
3
R4
73.2K
1%
1
2
3
4
5
6
7
8
1
2
3
R2
C9
2K
DISCHARGE_CMD
1
2
R8
2K
1
2
3
JP5
TM2
RT2
3.57K
1%
R12
C7
0.1UF
C6
1UF
DCMD
DSEL
VSEL
TM1
TM2
TCO
TS
BAT
INH
DIS
MOD
VCC
VSS
LED2
LED1
SNS
R10
16
15
14
13
12
11
10
9
+5V
Q2
2N3904
2K
R26
100K
C4
R11
220
0.1UF
U1
BQ2004
C10
0.1UF
R1
510K
Q4
2N3904
D3
Q5
2N3904
D4
GREEN
RSNS
0.2
1%
R7
RED R6
120
120
DV2004L1, Rev B, 5-19-97
Rev. B Board
4
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