ON MC10E142FNR2 5v ecl 9-bit shift register Datasheet

MC10E142, MC100E142
5VECL 9-Bit Shift Register
Description
The MC10E/100E142 is a 9-bit shift register, designed with
byte-parity applications in mind. The E142 performs serial/parallel in
and serial/parallel out, shifting in one direction. The nine inputs
D0 − D8 accept parallel input data, while S-IN accepts serial input
data. The Qn outputs do not need to be terminated for the shift
operation to function. To minimize noise and power, any Q output not
used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes
of operation − SHIFT and LOAD. The shift direction is from bit 0 to
bit 8. Input data is accepted by the registers a set-up time before the
positive going edge of CLK1 or CLK2; shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
700 MHz Min. Shift Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 405 devices
Pb−Free Packages are Available*
MARKING DIAGRAM*
1
MCxxxE142G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1
Publication Order Number:
MC10E142/D
MC10E142, MC100E142
SEL
D8
D7
D6
D5
25
24
23
22
21
S-IN
VCCO Q8
20
19
MR
26
18
Q7
CLK1
27
17
Q6
CLK2
28
16
VC
VEE
1
15
Q5
14
VC
S-IN
MC10E142/MC100E142
2
D0
3
13
Q4
D1
4
12
Q3
5
6
7
8
D2
D3
D4 VCCO
9
10
11
Q0
Q1
Q2
* All VCC and VCCO pins are tied together on the die.
D0
1
0
D
D1
1
0
D
D2
1
0
D
D3
1
0
D
D8
1
0
D
Q
Q0
Q
Q1
Q
Q2
Q
Q3
Q
Q8
SEL
Warning: All VCC, VfCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
CLK1
CLK2
Figure 1. Pinout: PLCC−28 (Top View)
MR
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Function
D0 − D8
ECL Parallel Data Inputs
S-IN
ECL Serial Data Input
SEL
ECL Mode Select Input
CLK1, CLK2
ECL Clock Inputs
MR
ECL Master Reset
Q0 − Q8
ECL Data Outputs
VCC, VCCO
Positive Supply*
VEE
Negative Supply
Table 2. FUNCTIONS
SEL
L
H
*From VCC pin to each VCCO pin is an internal 100 W resistor.
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2
Mode
Load
Shift
MC10E142, MC100E142
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
VEE
PECL Operating Range
NECL Operating Range
Tsol
Wave Solder
VI VCC
VI VEE
0 to +85
°C
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
4.2 to 5.7
−5.7 to −4.2
V
V
265
265
°C
Pb
Pb−Free
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
120
145
Min
85°C
Typ
Max
120
145
Min
Typ
Max
Unit
120
145
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E142, MC100E142
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
120
145
Min
85°C
Typ
Max
120
145
Min
Typ
Max
Unit
120
145
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 4)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
120
145
Min
85°C
Typ
Max
120
145
Min
Typ
Max
Unit
138
165
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 6)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
120
145
Min
85°C
Typ
Max
120
145
Min
Typ
Max
Unit
138
165
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 8)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E142, MC100E142
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
−40°C
Characteristic
Min
Typ
fSHIFT
Maximum Toggle Frequency
700
900
tPLH
tPHL
Propagation Delay to Output
CLK
MR
600
600
800
800
tS
Setup Time
D
SEL
50
300
tH
Hold Time
D
SEL
300
75
tSKEW
Within-Device Skew (Note 10)
tRR
Reset Recovery Time
tSKEW
Within-Device Skew (Note 10)
75
tJITTER
Random Clock Jitter (RMS)
<1
tr, tf
Rise/Fall Times
(20 - 80%)
Symbol
D to Q
25°C
Max
Min
Typ
700
900
600
600
800
800
−100
150
50
300
100
150
300
75
1000
1000
75
900
300
Max
Min
Typ
700
900
600
600
800
800
−100
150
50
300
−100
150
100
150
300
75
100
150
1000
1000
75
700
525
85°C
900
800
300
Max
MHz
1000
1000
900
ps
ps
ps
ps
75
700
Unit
700
ps
75
75
ps
<1
<1
ps
525
800
300
525
800
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
10. Within-device skew is defined as identical transitions on similar paths through a device.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC10E142, MC100E142
ORDERING INFORMATION
Package
Shipping †
MC10E142FN
PLCC−28
37 Units / Rail
MC10E142FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E142FNR2
PLCC−28
500 / Tape & Reel
MC10E142FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E142FN
PLCC−28
37 Units / Rail
MC100E142FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E142FNR2
PLCC−28
500 / Tape & Reel
MC100E142FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E142, MC100E142
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
T L −M
S
N
S
M
T L −M
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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7
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
−
0.025
−
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
−
0.020
2°
10°
0.410 0.430
0.040
−
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
−
0.64
−
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
−
0.50
2°
10°
10.42 10.92
1.02
−
M
T L −M
S
N
S
S
MC10E142, MC100E142
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
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