TI1 CDC2510BPWRG4 3.3v phase-lock loop clock driver Datasheet

SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
D Use CDCVF2510A as a Replacement for
D
D
D
D
D
D
D
D
D
D
D
D
D
D
this Device
Designed to Meet PC SDRAM Registered
DIMM Specification
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 125 MHz
tPhase Error Minus Jitter at 66 MHz to
100 MHz Is ±150 ps
Jitter (pk − pk) at 66 MHz to 100 MHz is
±80ps
Jitter (cyc − cyc) at 66 MHz to 100 MHz is
|100 ps|
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Ten Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3-V
PW PACKAGE
(TOP VIEW)
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
description
The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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1
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
description (continued)
The CDC2510B is characterized for operation from 0°C to 70°C.
For application information, see the High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039) application reports.
FUNCTION TABLE
INPUTS
OUTPUTS
CLK
1Y
(0:9)
X
L
L
L
L
H
L
H
H
H
H
H
G
FBOUT
functional block diagram
G
11
3
4
5
8
9
15
CLK
24
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
PLL
FBIN
AVCC
13
23
16
17
20
21
12
AVAILABLE OPTIONS
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
FBOUT
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
PACKAGE
TA
SMALL OUTLINE
(PW)
0°C to 70°C
CDC2510BPWR
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDC2510B clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
GND
2, 10, 14, 22
Power
Power supply
6, 7, 18, 19
Ground
Ground
POST OFFICE BOX 655303
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3
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V
Supply voltage range, VCC, AVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high
or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
MAX
Supply voltage, VCC, AVCC
3
3.6
High-level input voltage, VIH
2
Low-level input voltage, VIL
0
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
0.8
Input voltage, VI
UNIT
V
VCC
−12
mA
V
12
mA
70
°C
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II = −18 mA
IOH = −100 µA
VOH
IOH = −12 mA
IOH = − 6 mA
VOL
II
ICC§
∆ICC
Ci
Co
AVCC, VCC
3V
MIN
MIN to MAX
3V
VCC −0.2
2.1
3V
2.4
IOL = 100 µA
IOL = 12 mA
IO = 0, Outputs: low or high
Other inputs at VCC or GND
MAX
UNIT
−1.2
V
V
MIN to MAX
0.2
3V
0.8
3V
0.55
IOL = 6 mA
VI = VCC or GND
VI = VCC or GND,
One input at VCC − 0.6 V,
TYP‡
3.6 V
±5
µA
3.6 V
10
µA
500
µA
3.3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
V
3.3 V
4
pF
3.3 V
6
pF
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ For ICC of AVCC and ICC vs Frequency (see Figures 7 and 8).
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fclk
Clock frequency
Input clock duty cycle
Stabilization time†
MIN
MAX
UNIT
25
125
MHz
40%
60%
1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)‡
PARAMETER
tphase error, − jitter
(see Notes 7 and 8,
Figures 3, 4, and 5)
tsk(o)§
Jitter(pk-pk) (see Figure 6)
Jitter(cycle-cycle)
(See Figure 6)
Duty cycle reference
(see Figure 4)
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
CLKIN↑ = 66 MHz to 100 MHz
FBIN↑
Any Y or FBOUT
Any Y or FBOUT
VCC, AVCC = 3.3 V
± 0.165 V
VCC, AVCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
150
−200
−150
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
F(clkin > 60 MHz)
TYP
−80
Any Y or FBOUT
Any Y or FBOUT
TYP
200
ps
200
ps
80
|100|
45%
• DALLAS, TEXAS 75265
ps
55%
tr
Any Y or FBOUT
1.3
1.9
0.8
2.1
tf
Any Y or FBOUT
1.7
2.5
1.2
2.7
‡ These parameters are not production tested.
§ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is − 230 ps to 230 ps for the 5% VCC range.
POST OFFICE BOX 655303
UNIT
MAX
ns
ns
5
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 W
Output
30 pF
2V
0.4 V
tr
LOAD CIRCUIT FOR OUTPUTS
50% VCC
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
6
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SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
250
50
VCC = 3.3 V
fc = 100 MHz
CLY = 30pF
TA = 25°C
Phase Error Measured
from CLK to Y
30
20
200
150
Phase Error
100
50
10
0
0
−10
−50
−20
−100
−30
Phase Error − ps
Phase Adjustment Slope − ps/pF
40
−150
Phase Adjustment Slope
−200
−40
−250
−50
0
5
10
15
20
25
30
35
40
45
50
CLF − Lumped Feedback Capacitance at FBIN − pF
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
400
VCC = 3.3 V
CLY = CLF = 30 pF
TA = 25°C
Phase Error Measured
from CLK to FBIN
Phase Error − ps
300
200
100
0
−100
35
45
55
65
75
85
95
105
115 125
fc − Clock Frequency − MHz
Figure 4
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
POST OFFICE BOX 655303
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7
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
SUPPLY VOLTAGE
JITTER
vs
CLOCK FREQUENCY
400
400
350
300
fc = 100 MHz
CLY = CLF = 30 pF
TA = 25°C
Phase Error Measured
from CLK to FBIN
VCC = 3.3 V
TA = 25°C
350
300
Jitter − ps
Phase Error − ps
250
200
150
100
250
200
150
Peak to Peak
50
100
0
50
−50
−100
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Cycle to Cycle
0
35
3.7
45
Figure 5
95
105 115 125
250
VCC = 3.6 V
TA = 25°C
CLY = CLF = 30 pF
AVCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
TA = 25°C
200
I CC − Supply Current − mA
AI CC − Analog Supply Current − mA
85
SUPPLY CURRENT
vs
CLOCK FREQUENCY
16
10
8
6
4
150
100
50
2
0
10
0
20
40
60
80
100
120
140
20
40
fc − Clock Frequency − MHz
Figure 7
60
80
100
120
fclk − Clock Frequency − MHz
Figure 8
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
8
75
Figure 6
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
12
65
fc − Clock Frequency − MHz
VCC − Supply Voltage − V
14
55
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• DALLAS, TEXAS 75265
140
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDC2510BPWR
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CK2510B
CDC2510BPWRG4
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CK2510B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDC2510BPWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDC2510BPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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