2-Wire Communication Flash MCU HT45F2002 Revision: V1.00 Date: ������������� July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Table of Contents Features............................................................................................................. 3 MCU CPU Features................................................................................................................. 3 MCU Peripheral Features........................................................................................................ 3 Two Line Type Power Line Data Transmitter Features............................................................ 3 General Description.......................................................................................... 4 Block Diagram................................................................................................... 5 Pin Assignment................................................................................................. 6 Pin Descriptions............................................................................................... 6 Internally Connected Pins........................................................................................................ 8 Absolute Maximum Ratings............................................................................. 8 MCU D.C. Characteristics................................................................................ 9 MCU A.C. Characteristics............................................................................... 10 ADC Electrical Characteristics ......................................................................11 LVR Electrical Characteristics....................................................................... 12 LCD Electrical Characteristics...................................................................... 12 Power on Reset Electrical Characteristics................................................... 12 Two Line Type Power Line Data Transmitter D.C. Characteristics............. 13 LDO Characteristics....................................................................................... 13 LVD Characteristics........................................................................................ 14 Comparator Characteristics.......................................................................... 14 Constant Current Modulator Characteristics............................................... 14 Functional Description................................................................................... 14 Multi-chip Hardware Considerations...................................................................................... 15 Multi-chip Programming Considerations................................................................................ 15 Instruction Set................................................................................................. 16 Introduction............................................................................................................................ 16 Instruction Timing................................................................................................................... 16 Moving and Transferring Data................................................................................................ 16 Arithmetic Operations............................................................................................................. 16 Logical and Rotate Operation................................................................................................ 17 Branches and Control Transfer.............................................................................................. 17 Bit Operations........................................................................................................................ 17 Table Read Operations.......................................................................................................... 17 Other Operations.................................................................................................................... 17 Instruction Set Summary............................................................................... 18 Table Conventions.................................................................................................................. 18 Instruction Definition...................................................................................... 20 Package Information...................................................................................... 29 20-pin SSOP (150mil) Outline Dimensions............................................................................ 30 Rev. 1.00 2 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Features MCU CPU Features • Operating voltage ♦♦ fSYS =8MHz: 2.2V~5.5V ♦♦ fSYS =12MHz: 2.7V~5.5V ♦♦ fSYS =16MHz: 3.3V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Two oscillators ♦♦ Internal RC − HIRC ♦♦ Internal 32kHz RC − LIRC • Fully intergrated internal 8/12/16MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 6-level subroutine nesting • Bit manipulation instruction MCU Peripheral Features • Flash Program Memory: 2K×15 • RAM Data Memory: 96×8 • EEPROM Memory: 32×8 • Watchdog Timer function • Up to 11 bidirectional I/O lines • Software controlled SCOM lines LCD driver with 1/2 bias • Multiple Timer Modules for time measure, compare match output, capture input, PWM output, single pulse output functions • Dual Time-Base functions for generation of fixed time interrupt signals • 5-channel 12-bit resolution A/D converter • Serial Interface Module − SPI or I2C • Programmable I/O port source current for LED driving applications • Low voltage reset function • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years • Package type: 20-pin SSOP Two Line Type Power Line Data Transmitter Features • Complete data transmission on power line functions Rev. 1.00 3 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU • High maximum input voltage: 42V • Build-in 5V LDO output • Integrated low dropout voltage regulator with soft-start and short circuit protection • Integrated voltage detector for power supply monitoring • Integrated comparator • Open drain NMOS driver for flexible interfacing • Power and reset protection features • Minimal external component requirements General Description This device is Flash Memory type 8-bit high performance RISC architecture microcontroller. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter function. Multiple and extremely flexible Timer Modules provide timing, pulse generation, capture input, compare match output, single pulse output and PWM generation functions. Communication with the outside world is managed by including fully integrated SPI and I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer and Low Voltage Reset coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. This device also contains a two line type power line data transceiver. In systems where a master controller controls a number of individual interconnected subsystems such as found in smoke detector systems, water metering systems, solar energy system, etc., the cost of the extensive interconnecting cabling can be a major factor. By sending data along the power supply lines, the interconnecting cables can be reduced to a simple two line type, thus greatly reducing both cable and installation costs. With the addition of a few external components, this power line data transceiver device contains all the internal components required to provide users with a system for power line data transmission and reception. Data is modulated onto the power line by the simple reduction of the power line voltage for a specific period of time. Power supply voltage changes can be initiated by the master controller for data reception or initiated by the power line data transceiver for data transmission. An internal voltage regulator with Soft-Start and short circuit protection function within the device ensures that a constant voltage power supply is provided to the interconnected subsystem units while an internal voltage detector monitors the power line voltage level. An internal comparator is used to translate the differential signal into a logic signal for the MCU. A full choice of internal low and high speed, oscillator functions are provided including fully integrated system oscillators which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The SPI and I 2 C interfaces offer possibilities for data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery Rev. 1.00 4 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU operated device communication, etc. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the device will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Block Diagram The following block diagram illustrates the dual-chip structure of the device, where an individual MCU and a two-line type power line data transceiver chip are combined into a single package. VDD LDO VDD VDD I/O Ports VCC CN CN IS IS RX RX TX TX LCD pins HT66F0042 A/D pins HT45B0005 OSC pins TM pins VCC VSS VSS TRX TRX VSS Watchdog Timer Flash/EEPROM Programming Circuitry EEPROM Data Memory Internal RC Oscillators Low Voltage Reset Flash Program Memory RAM Data Memory Time Base Reset Circuit 8-bit RISC MCU Core Interrupt Controller 12-bit A/D Converter LCD Driver SIM (I2C/SPI) I/O Timer Modules LED Driver Power Line Data Transceiver Note: The Power Line Data Transceicer is the IC of the dual-chip in one device. Rev. 1.00 5 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Pin Assignment TRX 1 �0 VSS CN � 19 IS VCC 3 18 TX PA0/PTP0I_0/AN�/ICPDA � 17 RX PA1/PTP0/AN7 5 1� LDO PA�/CTCK0_0/ICPCK � 15 VDD PA3/CTP1/SCOM0 7 1� PA�/SDI/SDA/AN3 PC0/PTP1 8 13 PA5/PTCK�_0/SDO/AN� PC�/CTP0/RES PB5/PTP3/SCOM3 9 1� PA�/SCK/SCL/AN5 10 11 PA7/PTP�I_0 HT45F2002 20 SSOP-A Note: The PB0~PB4, PB5, PC, PC3~PC6 and their pin-shared functions are not connected to external package pins, care must therefore be taken to manage them properly with the application program. Pin Descriptions With the exception of the power pins and some relevant power line data transceiver pins, all pins on this device can be referenced by its Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name Function OPT I/T O/T PAWU PAPU PAS0 ST CMOS PAS0 PTM0C0 ST — PTM0 input PAS0 AN — A/D Converter input channel 6 — ST CMOS ICP Data Line PA1 PAWU PAPU PAS0 ST CMOS PTP0 PAS0 — CMOS PTM0 output AN7 PAS0 AN — PA2 PAWU PAPU ST CMOS CTCK0_0 CTM0C0 ST — CTM0 clock input ICPCK — ST — ICP Clock Line PA3 PAWU PAPU PAS0 ST CMOS CTP1 PAS0 — CMOS CTM1output SCOM0 PAS0 — PA0 PA0/PTP0I_0/AN6/ PTP0I_0 ICPDA AN6 ICPDA PA1/PTP0/AN7 PA2/CTCK0_0/ ICPCK PA3/CTP1/SCOM0 Rev. 1.00 6 AN Description General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up A/D Converter input channel 7 General purpose I/O. Register enabled pull-up and wake-up General purpose I/O. Register enabled pull-up and wake-up LCD driver output for LCD panel common July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Pin Name Function OPT I/T O/T PA4 PAWU PAPU PAS1 ST CMOS PA4/SDI/SDA/AN3 SDI PAS1 SIMC0 ST ─ PAS1 SIMC0 ST AN3 PAS1 AN — PA5 PAWU PAPU PAS1 ST CMOS ST — SDA PA5/PTCK2_0/ SDO/AN4 PAS1 PTCK2_0 PTM2C0 IFS General purpose I/O. Register enabled pull-up and wake-up SPI serial data input NMOS I2C data line A/D Converter input channel 3 General purpose I/O. Register enabled pull-up and wake-up PTM2 clock input SDO PAS1 ─ AN4 PAS1 AN — PA6 PAWU PAPU PAS1 ST CMOS PA6/SCK/SCL/AN5 SCK PAS1 SIMC0 ST CMOS SPI serial clock SCL PAS1 SIMC0 ST NMOS I2C clock line AN5 PAS1 AN — PA7 PAWU PAPU ST CMOS PTM2C0 IFS ST — PB5 PBPU PBS1 ST CMOS PTP3 PBS1 — CMOS PTM3 output SCOM3 PBS1 — AN PC0 PCPU PCS0 ST CMOS PTP1 PCS0 — CMOS PTM1 output PC2 PCPU PCS0 RSTC ST CMOS CTP0 PCS0 RSTC — CMOS CTM0 output PA7/PTP2I_0 PTP2I_0 PB5/PTP3/SCOM3 PC0/PTP1 PC2/CTP0/RES Rev. 1.00 Description CMOS SPI serial data output A/D Converter input channel 4 General purpose I/O. Register enabled pull-up and wake-up A/D Converter input channel 5 General purpose I/O. Register enabled pull-up and wake-up PTM2 iutput General purpose I/O. Register enabled pull-up LCD driver output for LCD panel common General purpose I/O. Register enabled pull-up General purpose I/O. Register enabled pull-up RES RSTC ST — External reset input CN CN — ST — Comparator Negative Input TRX TRX — ST CMOS Transceiver signal detect/modulate IS IS — — CMOS TX TX — ST — RX RX — — CMOS LDO LDO — — CMOS LDO Voltage output 7 Source terminal of constant current NMOS driver Input pin for constant current modulate Comparator output, transmitter signal detect output July 14, 2016 HT45F2002 2-Wire Communication Flash MCU OPT I/T O/T VCC Pin Name VCC Function — PWR — Input voltage Description VDD VDD — PWR — Digital positive power supply. Could connect to LDO pin externally VSS VSS — PWR — Digital negative power supply. Ground pin - VSS Legend: I/T: Input type O/T: Output type OPT: Optional by register option PWR: Power ST: Schmitt Trigger input AN: Analog signal CMOS: CMOS output NMOS: NMOS output Note: The PB0~PB4, PB5, PC1, PC3~PC6 and their pin-shared functions are not connected to external package pins. Internally Connected Pins Except the pins mentioned in the table above several pins are not connected to external package pins. These pins are interconnection pins between the MCU and the power line data transceiver chips and are listed in the following table. The description is provided from the power line data transceiver chip standpoint. Power Line Data Transceiver Pin Name VSS Type PWR Description Ground Pin. Connected to MCU negative power supply, VSS Absolute Maximum Ratings Supply Voltage.....................................................................................................VSS-0.3V to VSS+50V Input Voltage.......................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature...................................................................................................... -50°C to 125°C Operating Temperature..................................................................................................... -40°C to 85°C IOL Total.........................................................................................................................................80mA IOH Total........................................................................................................................................-80mA Total Power Dissipation............................................................................................................. 500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 8 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU MCU D.C. Characteristics Ta = 25°C Symbol Parameter Test Conditions Conditions VDD fSYS=fHIRC=8MHz VDD Operating Voltage (HIRC) Operating Voltage (LIRC) Operating Current (HIRC) IDD — 5.5 V — 5.5 V fSYS=fHIRC=16MHz 3.3 — 5.5 V — fSYS=fLIRC=32kHz 2.2 — 5.5 V 3V No load, fSYS=fHIRC=8MHz, ADC off, 5V WDT enable, LVR enable — 1.0 2.0 mA — 2.5 4.0 mA — 1.5 2.5 mA 3V No load, fSYS=fHIRC=12MHz, ADC off, 5V WDT enable, LVR enable 3V No load, fSYS=fLICRC=32kHz, ADC off, 5V WDT enable, LVR enable Rev. 1.00 — 3.5 5.5 mA — 2.0 3.0 mA — 4.5 7.0 mA — 15 30 μA — 30 60 μA — 2.0 3.0 mA — 3.0 4.0 mA — 1.0 1.6 mA — 1.6 2.2 mA — 1.5 2.2 mA — 2.2 3.0 mA — 0.7 1.2 mA — 1.2 1.6 mA 3V No load, fSYS=fH/2, ADC off, 5V WDT enable, LVR enable — 1.0 1.5 mA — 1.5 2.0 mA 3V No load, fSYS=fH/64, ADC off, 5V WDT enable, LVR enable — 0.5 0.8 mA — 0.8 1.1 mA SLEEP0 Mode Standby Current (LIRC Off) 3V — 0.2 0.8 μA — 0.5 1.0 μA SLEEP1 Mode Standby Current (LIRC On) 3V No load, ADC off, WDT enable, 5V LVR disable — 1.3 3.0 μA — 5.0 10 μA IDLE0 Mode Standby Current (LIRC On) 3V No load, ADC off, WDT enable, 5V LVR disable — 1.3 3.0 μA — 5.0 10 μA 3V No load, ADC off, WDT enable, 5V fSYS=fHIRC=8MHz on — 0.8 1.6 mA 5V No load, all peripherals off, WDT off — 1.0 2.0 mA 3V No load, ADC off, WDT enable, 5V fSYS=fHIRC=12MHz on — 1.2 2.4 mA — 1.5 3.0 mA 3V No load, ADC off, WDT enable, 5V fSYS=fHIRC=16MHz on — 1.6 3.2 mA — 2.0 4.0 mA Input Low Voltage for I/O Ports or Input Pins except RES Pin 5V — 0 — 1.5 V — — 0 — 0.2VDD V Input Low Voltage for RES Pin — — 0 — 0.4VDD V Input High Voltage for I/O Ports or 5V Input Pins except RES Pin — — 3.5 — 5.0 V — 0.8VDD — VDD V Input High Voltage for RES Pin — 0.9VDD — VDD V IDLE1 Mode Standby Current (HIRC On) VIH Unit 2.7 3V No load, fSYS=fH/2, ADC off, Operating Current, Normal Mode, 5V WDT enable, LVR enable fH=16MHz (HIRC) 3V No load, fSYS=fH/64, ADC off, 5V WDT enable, LVR enable Operating Current, Normal Mode, fH=8MHz (HIRC) VIL Max. 2.2 3V No load, fSYS=fH/2, ADC off, Operating Current, Normal Mode, 5V WDT enable, LVR enable fH=12MHz (HIRC) 3V No load, fSYS=fH/64, ADC off, 5V WDT enable, LVR enable ISTB Typ. — fSYS=fHIRC=12MHz 3V No load, fSYS=fHIRC=16MHz, ADC off, 5V WDT enable, LVR enable Operating Current (LIRC) Min. — 9 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Symbol IOL Parameter I/O Port Sink Current Test Conditions Min. Typ. Max. Unit 3V VOL=0.1VDD 18 36 — mA 5V VOL=0.1VDD 40 80 — mA -1.0 -2.0 — mA 5V VOH=0.9VDD, PxPS=00 -2.0 -4.0 — mA 3V VOH=0.9VDD, PxPS=01 -1.75 -3.5 — mA 5V VOH=0.9VDD, PxPS=01 -3.5 -7.0 — mA mA Conditions VDD 3V VOH=0.9VDD, PxPS=00 IOH RPH I/O Port, Source Current Pull-high Resistance for I/O Ports 3V VOH=0.9VDD, PxPS=10 -2.5 -5.0 — 5V VOH=0.9VDD, PxPS=10 -5.0 -10 — mA 3V VOH=0.9VDD, PxPS=11 -5.5 -11 — mA 5V VOH=0.9VDD, PxPS=11 -11 -22 — mA 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ MCU A.C. Characteristics Ta=25°C Symbol Parameter System Clock (HIRC) fSYS System Clock (LIRC) Test Conditions Min. Typ. 2.2V~ fSYS=fHIRC=8MHz 5.5V — 8 — MHz 2.7V~ fSYS=fHIRC=12MHz 5.5V — 12 — MHz 3.3V~ fSYS=fHIRC=16MHz 5.5V — 16 — MHz 2.2V~ fSYS=fLIRC=32kHz 5.5V — 32 — kHz VDD High Speed Internal RC Oscillator (HIRC Trim @ VDD=3V/5V, Ta=25°C) fLIRC System Clock (32kHz RC Oscillator) Max. Unit -2% 8 +2% MHz -2% 12 +2% MHz -2% 16 +2% MHz 2.2V~ 5.5V -3% 8 +3% MHz 2.7V~ Ta= -40°C to 85°C 5.5V -3% 12 +3% MHz 3.3V~ 5.5V -3% 16 +3% MHz 8 32 5V fHIRC Condition Ta= -20°C to 50°C 2.2V~ Ta= -40°C to 85°C 5.5V 50 kHz tTCK xTCKn, PTPnI Input Pulse Width — — 0.3 — — μs tRES External Reset Low Pulse Width — — 10 — — μs tINT Interrupt Pulse Width — — 0.3 — — μs tEERD EEPROM Read Time — — — 2 4 tSYS tEEWR EEPROM Write Time — — — 2 6.5 ms Rev. 1.00 10 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Symbol tSST tRSTD Test Conditions Parameter Min. Typ. fSYS=HIRC 16 — — fSYS=LIRC 2 — — Condition VDD Max. Unit System Start-up Timer Period (Wake-up from HALT, fSYS Off at HALT State, Reset Pin Reset) — System Start-up Timer Period (Wake-up from HALT, fSYS on at HALT State) — — 2 — — tSYS System Reset Delay Time (Power On Reset, LVR Reset, WDT S/W Reset (WDTC) — — 6.25 50 125 ms System Reset Delay Time (RES Pin Reset, WDT Normal Reset) — — 2.08 16.7 47.9 ms — No clock debounce 2 — — MHz I2C Standard Mode (100kHz) fSYS Frequency — 2 system clock debounce 4 — — MHz — 4 system clock debounce 8 — — MHz fI2C I2C Fast Mode (400kHz) fSYS Frequency tSYS — No clock debounce 5 — — MHz — 2 system clock debounce 10 — — MHz — 4 system clock debounce 20 — — MHz Note: 1. tSYS= 1/fSYS 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. ADC Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit AVDD A/D Converter Operating Voltage — — 2.7 — 5.5 V VADI A/D Converter Input Voltage — — 0 — AVDD /VREF V VREF A/D Converter Reference Voltage — 2 — AVDD V DNL Differential Non-linearity VREF=AVDD=VDD tADCK =0.5μs -3 — +3 LSB VREF=AVDD=VDD tADCK =0.5μs -4 — +4 LSB 3V 5V 2.7V 3V 5V 2.7V INL Integral Non-linearity 3V IADC Additional Power Consumption if A/D Converter is used 3V No load (tADCK =0.5μs ) — 1.0 2.0 mA 5V No load (tADCK =0.5μs ) — 1.5 3.0 mA 0.5 — 10 μs 16 — 20 tADCK 5V tADCK A/D Converter Clock Period 2.7V~ 5.5V tADC A/D Conversion Time (Include Sample and Hold Time) 2.7~ 5.5V tADS A/D Converter Sampling Time 2.7V~ 5.5V — — 4 — tADCK tON2ST A/D Converter On-to-Start Time 2.7V~ 5.5V — 4 — — μs Rev. 1.00 — 12-bit ADC 11 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU LVR Electrical Characteristics Symbol Parameter Test Conditions Min. Conditions VDD Typ. Max. Unit VDD Operating Voltage — — 1.9 — 5.5 V VLVR Low Voltage Reset Voltage — LVR Enable, 2.1V option -5% 2.1 +5% V BUFO Reference Output with Buffer — TJ = +25°[email protected] -5% 1.04 +5% V tLVR Low Voltage Width to Reset — 160 320 640 μs Min. Typ. Max. Unit ISEL[1:0]=00 17.5 25.0 32.5 μA ISEL[1:0]=01 35 50 65 μA ISEL[1:0]=10 70 100 130 μA ISEL[1:0]=11 140 200 260 μA 0.475 0.500 0.525 VDD — LCD Electrical Characteristics Symbol IBIAS VSCOM Test Conditions Parameter VDD/2 Bias Current for LCD VDD/2 Voltage for LCD COM Port Conditions VDD 5V 2.2V~5.5V No load Power on Reset Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Rev. 1.00 12 Time July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Two Line Type Power Line Data Transmitter D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions — Min. Typ. Max. Unit 7 — 42 V VCC Operating Voltage — ICC Operating Current — VCC=42V, VDD No Load, — 20 40 μA Vcc=42V, VDD No Load, TRX=0V — 10 20 μA IOFF Offline Current — VOFF TRX Offline Voltage — — — — 0.5 V VON TRX Online Voltage — — 4 — — V VT Threshold Voltage — — — VMARK-5.6 — V — 15 — mA — RS=100Ω — RS=47Ω IMC Modulate Current — 32 — mA VIL Input low voltage for TX pin 5V — 0 — 1.5 V VIH Input high voltage for TX pin 5V — 3.5 — 5 V IOL Sink current for RX pin 5V VOL=0.1VDD 10 20 — mA IOH Source current for RX pin 5V VOH=0.9VDD -5 -10 — mA RPH Pull-high Resistance for TX — -30% 50 30% kΩ — LDO Characteristics Ta=25°C Symbol VOUT Parameter Output Voltage Test Conditions Conditions VDD 5V Min. Typ. Max. Unit VCC=7V, ILOAD=10mA 4.85 5 5.15 V VCC=10V, ΔVOUT=-3% 60 — — mA IOUT Output Current — VCC=7V, ΔVOUT=-3% 30 — — mA ΔVLINE Line Regulation — 7V ≤ VIN ≤ 42V, ILOAD=1mA — — 0.2 %/V TC Temperature Coefficient 5V Ta=-40°C ~ 85°C, VCC=7V, ILOAD=10mA — ±0.75 ±1.5 mV/°C ΔVOUT_RIPPLE Output Voltage Ripple — VCC=7V, ILOAD=10mA — — 40 mV — — 10 ms 0.8 — — mA tSTART LDO Startup Time 5V VCC=7V, ILOAD=1mA, VOUT=5V ± 3% IOL Sink current for VDD — VCC=5V, VOL=0.5V Rev. 1.00 13 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU LVD Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit V VLVD Low voltage detection voltage — — 5.7 6.0 6.3 VHYS Hysteresis Voltage — — — 0.5 — V TC Temperature coefficient (ΔVLVD/ΔTa) — — ±0.9 — mV/°C Ta=-40°C ~ 85°C Comparator Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit dB AOL Open loop gain — — 60 80 — VHYS Hysteresis — — — 0.15 — V tRP Response time — — — — 5 μs Constant Current Modulator Characteristics Ta=25°C Symbol tRP Parameter Response Time Test Conditions Conditions VDD — No Load Min. Typ. Max. Unit — — 5 μs Functional Description As this device package contains multiple internal chips, for a detailed functional description, users must refer to the relevant individual datasheets for both the MCU and the power line data transceiver chip. The following table shows what devices are inside for this package. Device MCU Power Line Data Transceiver HT45F2002 HT66F0042 HT45B0005 Multi-chip Internal Device Although most of the functional description material will be located in the individual datasheets, there are some special considerations which need to be taken into account when using multi-chip device. These points will be mentioned in the following sections Rev. 1.00 14 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Multi-chip Hardware Considerations As the single-package-multi-chip device is composed of an individual MCU and the power line data transceiver chip, using them together requires the user to take care of some special points. Absolute Maximum Rating The Absolute Maximum Ratings for the two individual chips must be checked for discrepancies and the necessary care taken in device handling and usage. Power Supply and Consumption Examination of the block diagram will reveal that the power line data transceiver chip Ground pin, VSS, has internal connection to the MCU Ground pin, VSS. For this reason these two pins do not need to be connected externally. The single-package-multi-chip device LDO pin is the power line data transceiver chip LDO output pin, VDD, while the single-package-multi-chip device VDD pin is the MCU power supply VDD pin. To calculate the power consumption for the device, the total operating current is the sum of the operating current for the MCU specified in the MCU datasheet and the operating current for the power line data transceiver chip listed in its datasheet. Similarly, the standby current is the sum of the two individual chip standby currents. Power Down and Wake up The MCU power-down and wake-up functions are covered in the relevant MCU datasheet. However, the power line data transceiver chip is always operating after a power-up. Therefore, no power-down issue for the power line data transceiver chip is controlled by the relevant MCU device. Unbonded MCU Pins Examination of the relevant MCU datasheet will reveal that not all of the MCU I/O port lines are bonded out to external pins. As a result special attention regarding initialisation procedures should be paid to these port lines. Users should ensure that these pins are setup in input states with pull high resistors or in output states with either a high or low levels to avoid additional power consumption resulting from floating input pins. Multi-chip Programming Considerations To use the power line data transceiver function, several important steps must be implemented to ensure that the power line data transceiver chip operates normally: The MCU power line, VSS, is internally connected to the power line data transceiver VSS pin. For this reason, these two pins no need to be connected externally. Other corresponding programming considerations may be covered in the MCU and power line data transceiver datasheets respectively. Refer to all information in the individual datasheet for desired applications. Rev. 1.00 15 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 16 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 17 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 18 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 19 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 20 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Rev. 1.00 Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z 21 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z DAA [m] Description Operation Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Rev. 1.00 22 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z JMP addr Description Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) Rev. 1.00 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None 23 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) Rev. 1.00 Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None 24 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) Rev. 1.00 Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None 25 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SDZA [m] Description Operation Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.00 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C 26 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.00 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 27 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU TABRD [m] Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.00 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 28 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.00 29 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU 20-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.0098 G 0.016 — 0.05 H 0.004 — 0.01 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. — A — 6.000 BSC B — 3.900 BSC — C 0.20 — 0.30 C’ — 8.660 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 30 July 14, 2016 HT45F2002 2-Wire Communication Flash MCU Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 31 July 14, 2016