Maxim MAX17232 Eliminates external components and reduces total cost Datasheet

EVALUATION KIT AVAILABLE
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
General Description
Benefits and Features
These devices use a current-mode-control architecture.
The devices can be operated in pulse-width modulation
(PWM) or pulse-frequency modulation (PFM) control
schemes. PWM operation provides constant frequency
operation at all loads, and is useful in applications
sensitive to switching frequency. PFM operation disables
negative inductor current and additionally skips pulses at
light loads for high efficiency. The low-resistance, on-chip
MOSFETs ensure high efficiency at full load and simplify
the layout.
●● Reduces Number of DC-DC Controllers to Stock
• Fixed Output Voltage with ±1% Accuracy (5V/3.3V)
or Externally Resistor Adjustable (1V to 10V)
• 220kHz to 2.2MHz Adjustable Frequency with
External Synchronization
• Frequency Synchronization Input
The devices are available in a 28-pin TQFN-EP package
with exposed pad, and are specified for operation over
-40°C to +85°C.
●● Operates Reliably
• 42V Input Voltage Transient Protection
• Cycle-by-Cycle Current Limit, Thermal Shutdown
• Supply Overvoltage and Undervoltage Lockout
• Power-OK Monitor
• Reduced EMI Emission with Spread-Spectrum Control
• 50ns (typ) Minimum On-Time Guarantees PWM
Operation at Low Duty Cycle at 2.2MHz
The MAX17232/MAX17233 offers dual synchronous stepdown DC-DC controllers with integrated MOSFETs. They
operates over a 3.5V to 36V input voltage range with 42V
input transient protection, and can operate in dropout
condition by running at 95% duty cycle. The controllers
can generate fixed output voltages of 3.3V/5V, along with
the capability to program the output voltage between
1V to 10V.
Applications
●● Distributed Supply Regulation
●● Wall Transformer Regulation
●● General-Purpose Point-of-Load
●● Eliminates External Components and Reduces Total Cost
• No Schottky-Synchronous Operation for High
Efficiency and Reduced Cost
• Simple External RC Compensation for Stable
Operation at Any Output Voltage
• All-Ceramic Capacitor Solution: Ultra-Compact Layout
• 180° Out-of-Phase Operation Reduces Output
Ripple and Enables Cascaded Power Supplies
●● Reduces Power Dissipation
• 92% Peak Efficiency
• 8μA (typ) in Shutdown
• 20μA (typ) Quiescent Current in PFM Mode
Ordering Information and Selector Guide appears at end of
data sheet.
19-8366; Rev 0; 2/16
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Typical Application Circuit
RPGOOD1
FB1
OUT1
OUT1
CS1
CS1
PGOOD1
DL1
COMP1
AGND
COMP2
OUT1
DH1
MAX17233
BIAS
PGND1
EXTVCC
IN
OUT1
VBAT
CIN
DH2
EN2
BST2
CS2
CS2
LX2
OUT2
OUT2
FB2
COUT1
L1
BST1
PGND2 MAX17232
FOSC
RCS1*
LX1
EN1
FSYNC
CS1
DL2
PGOOD2
RCS2*
L2
CS2
OUT2
COUT2
PGND2
*DCR SENSE IS ALSO AN OPTION.
www.maximintegrated.com
Maxim Integrated │ 2
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Absolute Maximum Ratings
LX_ to PGND_.......................................................-0.3V to +42V
PGND_ to AGND...................................................-0.3V to +0.3V
PGOOD1, PGOOD2 to AGND..............................-0.3V to +6.0V
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 28.6mW/NC above +70°C)..............2285.7mW
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature Range...........................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................ +260°C
IN, EN1, EN2, TERM to PGND_............................-0.3V to +42V
CS1, CS2, OUT1, OUT2 to AGND......................... -0.3V to +11V
CS1 to OUT1.........................................................-0.2V to +0.2V
CS2 to OUT2.........................................................-0.2V to +0.2V
BIAS, FSYNC, FOSC to AGND............................-0.3V to +6.0V
COMP1, COMP2 to AGND...................................-0.3V to +6.0V
FB1, FB2, EXTVCC to AGND...............................-0.3V to +6.0V
DL_ to PGND_......................................................-0.3V to +6.0V
BST_, to LX_........................................................-0.3V to + 6.0V
DH_ to LX_...........................................................-0.3V to + 6.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........35°C/W
Junction-to-Case Thermal Resistance (θJC)..................3°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C under
normal conditions, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
SYNCHRONOUS STEP-DOWN DC-DC CONTROLLERS
Supply Voltage Range
VIN
Output Overvoltage Threshold
Supply Current
IIN
Buck 1 Fixed Output Voltage
VOUT1
Buck 2 Fixed Output Voltage
VOUT2
Output Voltage Adjustable Range
www.maximintegrated.com
Normal operation
3.5
36
t < 1s
42
FB rising (Note 3)
+10
+15
+20
FB falling
+5
+10
+15
VEN1 = VEN2 = 0V, TA = +25°C
8
20
VEN1 = VEN2 = 0V, TA = +125°C
20
VEN1 = 5V, VOUT1 = 5V, VEN2 = 0V;
VEXTVCC = 5V, no switching
30
VEN2 = 5V, VOUT2 = 3.3V; VEN1 = 0V,
VEXTVCC = 3.3V, no switching
20
30
VEN1 = VEN2 = 5V, VOUT1 = 5V, VOUT2 = 3.3V,
VEXTVCC = 3.3V, no switching
25
40
%
40
µA
VFB1 = VBIAS, PWM mode
4.95
5
5.05
VFB1 = VBIAS, skip mode
4.95
5
5.075
VFB2 = VBIAS, PWM mode
3.234
3.3
3.366
VFB2 = VBIAS, skip mode
3.234
3.3
3.4
Buck 1, buck 2
V
1
10
V
V
V
Maxim Integrated │ 3
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Electrical Characteristics (continued)
(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C under
normal conditions, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
Regulated Feedback Voltage
VFB1,2
Feedback Leakage Current
IFB1,2
Feedback Line Regulation Error
Transconductance
(from FB_ to COMP_)
gm
Dead Time
Maximum Duty Cycle
Minimum On-Time
PWM Switching Frequency
CONDITIONS
0.99
fSW
Buck 2 Switching Frequency
Spread-Spectrum Range
MAX
UNIT
1.0
1.01
V
0.01
1
µA
VIN = 3.5V to 36V, VFB = 1V
0.001
VFB = 1V, VBIAS = 5V
1200
MAX17233: DL_ low to DH_ high
35
MAX17233: DH_ low to DL_ high
60
MAX17232: DL_ low to DH_ high
60
MAX17232: DH_ low to DL_ high
100
95
Buck 1, buck 2
%/V
2400
µS
ns
98.5
%
50
ns
MAX17233
1
2.2
MAX17232
0.2
1
MAX17233ATIT+, MAX17233BATIU+ only
Switching Frequency Accuracy
TYP
TA = +25°C
Buck 1, buck 2
tON(MIN)
MIN
1/2fSW
MHz
MHz
MAX17233: RFOSC = 13.7kΩ, VBIAS = 5V
1.98
2.2
2.42
MHz
MAX17232: RFOSC = 80.6kΩ, VBIAS = 5V
360
400
440
kHz
Spread spectrum enabled
±6
%
FSYNC INPUT
FSYNC Frequency Range
FSYNC Switching Thresholds
CS Current-Limit Voltage Threshold
MAX17233: Minimum sync pulse of 100ns
1.2
2.4
MHz
MAX17232: Minimum sync pulse of 400ns
240
1200
kHz
High threshold
1.5
Low threshold
VLIMIT1,2
VCS – VOUT, VBIAS = 5V, VOUT ≥ 2.5V
0.6
64
Skip Mode Threshold
Soft-Start Ramp Time
80
96
15
Buck 1 and buck 2, fixed soft-start time
regardless of frequency
Phase Shift Between Buck1 and
Buck 2
2
6
V
mV
mV
10
180
ms
°
LX1, LX2 Leakage Current
VIN = 6V, VLX_ = VIN, TA = +25°C
DH1, DH2 Pullup Resistance
VBIAS = 5V, IDH_ = -100mA
10
20
Ω
DH1, DH2 Pulldown Resistance
VBIAS = 5V, IDH_ = +100mA
2
4
Ω
DL1, DL2 Pullup Resistance
VBIAS = 5V, IDL_ = -100mA
4
8
Ω
DL1, DL2 Pulldown Resistance
VBIAS = 5V, IDL_ = +100mA
1.5
3
Ω
www.maximintegrated.com
0.01
µA
Maxim Integrated │ 4
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Electrical Characteristics (continued)
(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C under
normal conditions, unless otherwise noted.) (Note 2)
PARAMETER
PGOOD1, PGOOD2 Threshold
SYMBOL
CONDITIONS
MIN
TYP
MAX
PGOOD_H
% of VOUT_, rising
85
90
95
PGOOD_F
% of VOUT_, falling
80
85
90
0.01
1
PGOOD1, PGOOD2 Leakage
Current
VPGOOD1,2 = 5V, TA = +25°C
PGOOD1, PGOOD2 Startup
Delay Time
Buck 1 and buck 2 after soft-start is
complete
PGOOD1, PGOOD2 Debounce
Time
Fault detection
64
UNIT
%
µA
Cycles
8
20
50
µs
4.75
5
5.25
V
3.1
3.4
INTERNAL LDO: BIAS
VIN > 6V
Internal BIAS Voltage
VBIAS rising
BIAS UVLO Threshold
VBIAS falling
2.7
Hysteresis
External VCC
2.9
0.2
VTH,EXTVCC
EXTVCC rising, HYST = 110mV
3.0
V
V
3.2
V
THERMAL OVERLOAD
Thermal-Shutdown Temperature
(Note 4)
+170
°C
Thermal-Shutdown Hysteresis
(Note 4)
20
°C
EN LOGIC INPUT
High Threshold
1.8
Low Threshold
Input Current
TA = +25°C
V
0.8
V
1
µA
Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage
range are guaranteed by design and characterization. Typical values are at TA = +25°C.
Note 3: Overvoltage protection is detected at the FB1/FB2 pins. If the feedback voltage reaches overvoltage threshold of FB1/FB2 +
15% (typ), the corresponding controller stops switching. The controllers resume switching once the output drops below FB1/FB2
+ 10% (typ).
Note 4: Guaranteed by design; not production tested.
www.maximintegrated.com
Maxim Integrated │ 5
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
NO LOAD STARTUP SEQUENCE
(VFSYNC = 0V)
FULL LOAD STARTUP SEQUENCE
(VFSYNC = 0V)
toc01
toc02
VBAT
5V/div
VBAT
5V/div
VOUT1
2V/div
IOUT1
2A/div
VPGOOD1
5V/div
VOUT1
2V/div
VOUT2
2V/div
VOUT2
2V/div
IOUT2
2A/div
VPGOOD2
5V/div
VPGOOD1
5V/div
VPGOOD2
5V/div
QUIESCIENT CURRENT
vs. SUPPLY VOLTAGE
VEN1 = 0V
VEN2 = VBAT
EXTVCC = VOUT2
90
EFFICIENCY (%)
80
70
60
50
30
20
0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
BUCK1 EFFICIENCY
fSW = 2.2MHz EXTVCC = VOUT1
L = 2.2µH
VBAT = 14V
VOUT1 = 5V
EXTVCC
= GND
SKIP MODE
50
40
30
20
EXTVCC
= VOUT2
100
90
80
EXTVCC
= GND
PWM MODE
10
0
1.0E-04
1.0E-02
1.0E+00
1.0E-06
1.0E-05
1.0E-03
1.0E-01
1.0E+01
IOUT1 (A)
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BUCK 1
EXTVCC = VOUT1
40
BUCK 2
EXTVCC = VOUT2
10
toc05
100
60
70
60
0
5
10 15 20 25 30
SUPPLY VOLTAGE (V)
30
20
40
BUCK2 EFFICIENCY
fSW = 2.2MHz EXTVCC = VOUT2
L = 2.2µH
VBAT = 14V
VOUT2 = 3.3V
EXTVCC
= GND
SKIP MODE
50
40
35
toc06
20
10
toc04
70
VEN1 = VBAT
VEN2 = 0V
EXTVCC = VOUT1
30
0
80
SUPPLY CURRENT (µA)
40
QUIESCIENT CURRENT
vs. TEMPERATURE
EFFICIENCY (%)
SUPPLY CURRENT (µA)
50
4ms/div
toc03
60
2ms/div
EXTVCC
= GND
EXTVCC
= VOUT2
PWM MODE
10
0
1.0E-04
1.0E-02
1.0E+00
1.0E-06
1.0E-05
1.0E-03
1.0E-01
1.0E+01
IOUT2 (A)
Maxim Integrated │ 6
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
SWITCHING FREQUENCY (MHz)
BUCK 2
2.26
2.24
2.22
BUCK 1
2.20
2.18
2.16
2.14
2.12
2.10
0
1
2
3
4
5
6
2.2
2.0
1.8
VBIAS = 5V
1.6
1.4
VBIAS = 3.3V
1.2
0
15
0
SWITCHING FREQUENCY (MHz)
20
RFOSC (kΩ)
1.0
0.9
0.8
0.7
0.6
VBIAS = 5V
0.5
0.4
VBIAS = 3.3V
25
30
0.2
30
40
50
60
RFOSC = 13.7kΩ
70
90 110 130 150 170
80 100 120 140 160
RFOSC (kΩ)
LOAD TRANSIENT RESPONSE
toc10
SWITCHING FREQUENCY vs. TEMPERATURE
2.35
1.1
0.3
LOAD CURRENT (A)
2.40
SWITCHING FREQUENCY
vs. RFOSC (MAX17232)
toc09
2.4
SWITCHING FREQUENCY (MHz)
2.28
toc08
toc07
2.30
SWITCHING FREQUENCY (MHz)
SWITCHING FREQUENCY
vs. RFOSC (MAX17233)
SWITCHING FREQUENCY
vs. LOAD CURRENT
toc11
2.30
VOUT1
100mV/div
2.25
2.20
2.15
2.10
IOUT1
1A/div
2.05
2.00
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
400µs/div
EXTERNAL SYNC TRANSITION
DIPS AND DROPS
toc12
VLX1
10V/div
VBAT
10V/div
VLX2
10V/div
VPGOOD1
5V/div
VSYNC
2V/div
400ns/div
www.maximintegrated.com
toc13
VOUT1
5V/div
40ms/div
Maxim Integrated │ 7
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LINE TRANSIENT
SLOW VIN RAMP
toc14
toc15
VBAT
5V/div
VBAT
10V/div
VOUT2
1V/div
VOUT1
2V/div
VPGOOD1
5V/div
VOUT2
2V/div
VPGOOD2
5V/div
VPGOOD2
5V/div
100ms/div
10s/div
SHORT CIRCUIT RESPONSE
OUTPUT OVERVOLTAGE RESPONSE
toc17
toc16
VOUT1
1V/div
VPGOOD1
2V/div
IOUT1
2A/div
VOUT1
1V/div
VPGOOD1
2V/div
200µs/div
1s/div
4.996
100.00
4.994
4.993
4.992
4.991
4.990
VSYNC = VBIAS
0
1
2
3
IOUT (A)
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4
5
6
VOUT (%NOMINAL)
VOUT (V)
VOUT (V)
100.05
3.295
4.995
4.989
VSYNC = VBIAS
3.296
100.10
3.294
3.293
3.292
99.95
3.290
99.75
1
2
3
IOUT (A)
4
5
6
VOUT1
99.85
99.80
0
VOUT2
99.90
3.291
3.289
toc20
toc18
VSYNC = VBIAS
4.997
VOUT vs. TEMPERATURE
BUCK 2 LOAD REGULATION
3.297
toc19
BUCK 1 LOAD REGULATION
4.998
99.70
EXTVCC = VGND
VSYNC = VBIAS
IOUT_ = 0A
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Maxim Integrated │ 8
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
toc21
VOUT1 = 1.8V
VOUT2 = 1.8V
1.005
VOUT (V)
1.000
0.995
1.000
0.995
0
10
5
15 20 25
VSUP (V)
30
35
0.990
40
MINIMUM ON-TIME (BUCK 1)
0
10
5
15 20 25
VSUP (V)
VBAT
5V/div
VBAT
5V/div
VOUT1
1V/div
VOUT1
1V/div
30
20
10
0
30
MEASURED AT VOUT2 ON THE
MAX17233ETIU+
30
25
20
15
10
5
0
500,000
-10
800k
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
MEASURED ON THE
MAX17233ETIS+
25
20
15
10
5
0
-5
-5
350,000 400,000 450,000
FREQUENCY (Hz)
35
OUTPUT SPECTRUM (dBµV)
40
35
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
toc26
40
toc25
MEASURED ON THE MAX17232ETIS+
OUTPUT SPECTRUM (dBµV)
OUTPUT SPECTRUM (dBµV)
toc24
200ns/div
SPECTRAL ENERGY DENSITY
vs. FREQUENCY
www.maximintegrated.com
40
IOUT2 = 300mA
200ns/div
-10
300,000
35
MINIMUM ON-TIME (BUCK 2)
toc23
IOUT1 = 300mA
50
30
toc27
VOUT (V)
1.005
0.990
FB2 LINE REGULATION
1.010
toc22
FB1 LINE REGULATION
1.010
900k
1000k
1100k
FREQUENCY (Hz)
1200k
-10
1800k
2200k
2400k
2000k
FREQUENCY (Hz)
2600k
Maxim Integrated │ 9
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
FB2
COMP2
FOSC
20
CS2
21
OUT2
PGND2
TOP VIEW
DL2
Pin Configuration
19
18
17
16
15
LX2 22
14
FSYNC
DH2 23
13
PGOOD2
12
PGOOD1
11
IN
EN1 26
10
EXTVCC
BST1 27
9
AGND
8
BIAS
MAX17232
MAX17233
BST2 24
EN2 25
EP
5
6
7
COMP1
4
FB1
LX1
DL1
3
OUT1
2
CS1
1
PGND1
+
DH1 28
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
1
LX1
Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the
lower supply rail for the DH1 high-side gate drive.
2
DL1
Low-Side Gate Drive Output for Buck 1. DL1 output voltage swings from VPGND1 to VBIAS.
3
PGND1
4
CS1
Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense
resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections.
5
OUT1
Output Sense and Negative Current-Sense Input for Buck 1. When using the internal preset 5V
feedback divider (FB1 = BIAS), the buck uses OUT1 to sense the output voltage. Connect OUT1 to
the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs
and Current-Sense Measurement sections.
6
FB1
7
COMP1
8
BIAS
9
AGND
10
EXTVCC
11
IN
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DESCRIPTION
Power Ground for Buck 1
Feedback Input for Buck 1. Connect FB1 to BIAS for the 5V fixed output or to a resistive divider
between OUT1 and GND to adjust the output voltage between 1V and 10V. In adjustable mode,
FB1 regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.
Buck 1 Error-Amplifier Output. Connect an RC network to COMP1 to compensate buck 1.
5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of 6.8µF
minimum value. BIAS provides the power to the internal circuitry and external loads. See the Fixed 5V
Linear Regulator (BIAS) section.
Signal Ground for IC
3.1V to 5.2V Input to the Switchover Comparator
Supply Input. Bypass IN with sufficient capacitance to supply the two out-of-phase buck converters.
Maxim Integrated │ 10
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Pin Description (continued)
PIN
12
NAME
PGOOD1
13
PGOOD2
14
FSYNC
15
FOSC
16
COMP2
17
FB2
DESCRIPTION
Open-Drain Power-Good Output for Buck 1. PGOOD1 is low if OUT1 is more than 15% (typ) below
the normal regulation point. PGOOD1 asserts low during soft-start and in shutdown. PGOOD1
becomes high impedance when OUT1 is in regulation. To obtain a logic signal, pullup PGOOD1
with an external resistor connected to a positive voltage lower than 5.5V. Place a minimum of 100Ω
(RPGOOD1) in series with PGOOD1. See the Voltage Monitoring section for details.
Open-Drain Power-Good Output for Buck 2. PGOOD2 is low if OUT2 is more than 15% (typ) below
the normal regulation point. PGOOD2 asserts low during soft-start and in shutdown. PGOOD2
becomes high impedance when OUT2 is in regulation. To obtain a logic signal, pullup PGOOD2 with
an external resistor connected to a positive voltage lower than 5.5V.
External Clock Synchronization Input. Synchronization to the controller operating frequency ratio is
1. Keep fSYNC a minimum of 10% greater than the maximum internal switching frequency for stable
operation. See the Switching Frequency/External Synchronization section.
Frequency Setting Input. Connect a resistor from FOSC to AGND to set the switching frequency of
the DC-DC converters.
Buck 2 Error Amplifier Output. Connect an RC network to COMP2 to compensate buck 2.
Feedback Input for Buck 2. Connect FB2 to BIAS for the 3.3V fixed output or to a resistive divider
between OUT2 and GND to adjust the output voltage between 1V and 10V. In adjustable mode, FB2
regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.
Output Sense and Negative Current-Sense Input for Buck 2. When using the internal preset 3.3V
feedback-divider (FB2 = BIAS), the buck uses OUT2 to sense the output voltage. Connect OUT2 to
the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs
and Current-Sense Measurement sections.
Positive Current-Sense Input for Buck 2. Connect CS2 to the positive terminal of the current-sense
resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement sections.
18
OUT2
19
CS2
20
PGND2
21
DL2
Low-Side Gate Drive Output for Buck 2. DL2 output voltage swings from VPGND2 to VBIAS.
22
LX2
Inductor Connection for Buck 2. Connect LX2 to the switched side of the inductor. LX2 serves as the
lower supply rail for the DH2 high-side gate drive.
23
DH2
High-Side Gate Drive Output for Buck 2. DH2 output voltage swings from VLX2 to VBST2.
24
BST2
Boost Capacitor Connection for High-Side Gate Voltage of Buck 2. Connect a high-voltage diode
between BIAS and BST2. Connect a ceramic capacitor between BST2 and LX2. See the High-Side
Gate-Driver Supply (BST_) section.
25
EN2
High-Voltage Tolerant, Active-High Digital Enable Input for Buck 2. Driving EN2 high enables buck 2.
26
EN1
High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables buck 1.
27
BST1
Boost Capacitor Connection for High-Side Gate Voltage of Buck 1. Connect a high-voltage diode
between BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side
Gate-Driver Supply (BST_) section.
28
DH1
High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from VLX1 to VBST1.
—
EP
www.maximintegrated.com
Power Ground for Buck 2
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to PGND1, PGND2, and AGND. The exposed
pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from
the IC.
Maxim Integrated │ 11
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Detailed Description
where ICC is the internal supply current, 5mA (typ), fSW
is the switching frequency, and QG_ is the MOSFET’s
total gate charge (specification limits at VGS = 5V). To
minimize the internal power dissipation, bypass BIAS to
an external 5V rail.
●● A buck controller with a fixed 5V output voltage or an
adjustable 1V to 10V output voltage.
EXTVCC Switchover
The MAX17232/MAX17233 are dual-output switching
power supplies. These devices integrate two synchronous
step-down controllers and can provide two independent
controlled power rails as follows:
●● A buck controller with a fixed 3.3V output voltage or
an adjustable 1V to 10V output voltage.
The two buck controllers can each provide up to 10A
output current and are independently controllable.
EN1 and EN2 enable the respective buck controllers.
Connect EN1 and EN2 directly to VBAT, or to powersupply sequencing logic.
In skip mode, with no load and only buck 2 active, the
total supply current is reduced to 20µA (typ). When both
controllers are disabled, the total current drawn is further
reduced to 8µA (typ).
Fixed 5V Linear Regulator (BIAS)
The internal circuitry of the devices requires a 5V bias
supply. An internal 5V linear regulator (BIAS) generates this
bias supply. Bypass BIAS with a 6.8µF or greater ceramic
capacitor to guarantee stability under the full-load condition.
The internal linear regulator can source up to 100mA
(150mA under EXTVCC switchover, see the EXTVCC
Switchover section). Use the following equation to estimate
the internal current requirements for the devices:
The internal linear regulator can be bypassed by connecting an external supply (3V to 5.2V) or the output of one of
the buck converters to EXTVCC. BIAS internally switches
to EXTVCC and the internal linear regulator turns off. This
configuration has several advantages:
●● It reduces the internal power dissipation of the devices.
●● The low-load efficiency improves as the internal supply
current gets scaled down proportionally to the duty cycle.
If VEXTVCC drops below VTH,EXTVCC = 3V (min), the
internal regulator enables and switches back to BIAS.
Undervoltage Lockout (UVLO)
The BIAS input undervoltage lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (BIAS) is below
its 2.9V (typ) UVLO falling threshold. Once the 5V bias
supply (BIAS) rises above its UVLO rising threshold and
EN1 and EN2 enable the buck controllers, the controllers
start switching and the output voltages begin to ramp up
using soft-start.
IBIAS = ICC + fSW(QG_DH1 + QG_DL1 +
QG_DH2 + QG_DL2) = 10mA to 50mA (typ)
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Maxim Integrated │ 12
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Buck Controllers
The devices provide two buck controllers with
synchronous rectification. The step-down controllers use
a PWM, current-mode control scheme. External logiclevel MOSFETs allow for optimized load-current design.
Fixed-frequency operation with optimal interleaving
minimizes input ripple current from the minimum to the
maximum input voltages. Output-current sensing provides
an accurate current limit with a sense resistor or power
dissipation can be reduced using lossless current sensing
across the inductor.
Soft-Start
Once a buck converter is enabled by driving the
corresponding EN_ high, the soft-start circuitry gradually
ramps up the reference voltage during soft-start time
(tSSTART = 6ms (typ)) to reduce the input surge currents
during startup. Before the device can begin the soft-start,
the following conditions must be met:
1) VBIAS exceeds the 3.4V (max) undervoltage-lockout
threshold.
2) VEN_ is logic-high.
Switching Frequency/External Synchronization
The MAX17232 provides an internal oscillator adjustable
from 1MHz to 2.2MHz. The MAX17233 provides an
internal oscillator adjustable from 200kHz to 1MHz. Highfrequency operation optimizes the application for the
smallest component size, trading off efficiency to higher
switching losses. Low-frequency operation offers the best
overall efficiency at the expense of component size and
board space. To set the switching frequency, connect a
resistor RFOSC from FOSC to AGND. See TOC8 and
TOC9 (Switching Frequency vs. RFOSC) in the Typical
Operating Characteristics to determine the relationship
between switching frequency and RFOSC.
Buck 1 is synchronized with the internal clock-signal rising
edge, while buck 2 is synchronized with the clock-signal
falling edge.
The devices can be synchronized to an external clock by
connecting the external clock signal to FSYNC. A rising edge
on FSYNC resets the internal clock. Keep the FSYNC
frequency between 110% and 150% of the internal
frequency. The FSYNC signal should have a 50% duty cycle.
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Light-Load Efficiency Skip Mode (VFSYNC = 0V)
Drive FSYNC low to enable skip mode. In skip mode, the
devices stop switching until the FB voltage drops below
the reference voltage. Once the FB voltage has dropped
below the reference voltage, the devices begin switching
until the inductor current reaches 20% (skip threshold)
of the maximum current defined by the inductor DCR or
output shunt resistor.
Forced-PWM Mode (VFSYNC = High)
Driving FSYNC high prevents the devices from entering
skip mode by disabling the zero-crossing detection of
the inductor current. This forces the low-side gate-driver
waveform to constantly be the complement of the highside gate-drive waveform, so the inductor current reverses
at light loads and discharges the output capacitor. The
benefit of forced PWM mode is to keep the switching
frequency constant under all load conditions. However,
forced-frequency operation diverts a considerable amount
of the output current to PGND, reducing the efficiency
under light-load conditions.
Forced-PWM mode is useful for improving load-transient
response and eliminating unknown frequency harmonics
that may interfere with AM radio bands.
Spread Spectrum
The
MAX17233ETIS,
MAX17233ETIU,
and
MAX17232ETIS feature enhanced EMI performance.
They perform ±6% dithering of the switching frequency
to reduce peak emission noise at the clock frequency
and its harmonics, making it easier to meet stringent
emission limits.
When using an external clock source (i.e., driving the FSYNC
input with an external clock), spread spectrum is disabled.
Buck 2 Switching Frequency
For the MAX17233ETIT and MAX17232BATIU, the
switching frequency of buck 2 is set to 1/2 of fSW (buck
1 switching frequency). When using these devices, the
external components of buck 2 should be sized to account
for the reduced switching frequency (see the Design
Procedure section).
Maxim Integrated │ 13
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
MOSFET Gate Drivers (DH_ and DL_)
The DH_ high-side nMOSFET drivers are powered from
capacitors at BST_ while the low-side drivers (DL_) are
powered by the 5V linear regulator (BIAS). On each channel,
a shoot-through protection circuit monitors the gate-tosource voltage of the external MOSFETs to prevent a
MOSFET from turning on until the complementary switch
is fully off. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET gates
for the protection circuits to work properly. Follow the
instructions listed to provide the necessary low-resistance
and low-inductance path:
●● Use very short, wide traces (50 mils to 100 mils wide
if the MOSFET is 1in from the driver).
It may be necessary to decrease the slew rate for the
gate drivers to reduce switching noise or to compensate
for low-gate charge capacitors. For the low-side drivers,
use gate capacitors in the range of 1nF to 5nF from DL_
to GND. For the high-side drivers, connect a small 5Ω to
10Ω resistor between BST_ and the bootstrap capacitor.
Note: Gate drivers must be protected during shutdown, at
the absence of the supply voltage (VBIAS = 0V) when the
gate is pulled high either capacitively or by the leakage path
on the PCB. Therefore, external gate pulldown resistors
are needed, to prevent making a direct path from VBAT
to GND.
High-Side Gate-Driver Supply (BST_)
The high-side MOSFET is turned on by closing an internal
switch between BST_ and DH_ and transferring the bootstrap capacitor’s (at BST_) charge to the gate of the highside MOSFET. This charge refreshes when the high-side
MOSFET turns off and the LX_ voltage drops down to ground
potential, taking the negative terminal of the capacitor to the
same potential. At this time the bootstrap diode recharges the
positive terminal of the bootstrap capacitor.
The selected high-side nMOSFET determines the appropriate
boost capacitance values (CBST_ in the Typical Application
Circuit) according to the following equation:
C BST_ =
QG
∆VBST_
where QG is the total gate charge of the high-side
MOSFET and ΔVBST_ is the voltage variation allowed
on the high-side MOSFET driver after turn-on. Choose
ΔVBST_ such that the available gate-drive voltage is not
significantly degraded (e.g., ΔVBST_ = 100mV to 300mV)
when determining CBST_.
The boost capacitor should be a low-ESR ceramic
capacitor. A minimum value of 100nF works in most cases.
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Current Limiting and Current-Sense Inputs
(OUT_ and CS_)
The current-limit circuit uses differential current-sense
inputs (OUT_ and CS_) to limit the peak inductor current.
If the magnitude of the current-sense signal exceeds the
current-limit threshold (VLIMIT1,2 = 80mV (typ)), the PWM
controller turns off the high-side MOSFET. The actual
maximum load current is less than the peak current-limit
threshold by an amount equal to half of the inductor ripple
current. Therefore, the maximum load capability is a
function of the current-sense resistance, inductor value,
switching frequency, and duty cycle (VOUT_/VIN).
For the most accurate current sensing, use a currentsense shunt resistor (RSH) between the inductor and the
output capacitor. Connect CS_ to the inductor side of RSH
and OUT_ to the capacitor side. Dimension RSH such that
the maximum inductor current (IL,MAX = ILOAD,MAX+1/2
IRIPPLE,PP) induces a voltage of VLIMIT1,2 across RSH
including all tolerances.
For higher efficiency, the current can also be measured
directly across the inductor. This method could cause
up to 30% error over the entire temperature range and
requires a filter network in the current-sense circuit. See
the Current-Sense Measurement section.
Voltage Monitoring (PGOOD_)
The devices include several power-monitoring
signals to facilitate power-supply sequencing and
supervision. PGOOD_ can be used to enable circuits that are
supplied by the corresponding voltage rail, or to turn on
subsequent supplies.
Each PGOOD_ goes high (high impedance) when the
corresponding regulator output voltage is in regulation.
Each PGOOD_ goes low when the corresponding regulator
output voltage drops below 15% (typ) or rises above 15%
(typ) of its nominal regulated voltage. Connect a 10kΩ
(typ) pullup resistor from PGOOD_ to the relevant logic
rail to level-shift the signal.
PGOOD_ asserts low during soft-start, soft-discharge,
and when either buck converter is disabled (either EN1
or EN2 is low).
To ensure latchup immunity on the PGOOD1 pin, a
minimum resistance of 100Ω should be placed
between the PGOOD1 pin and any other external
components.
Maxim Integrated │ 14
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Thermal-Overload, Overcurrent, and Overvoltage
and Undervoltage Behavior
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the devices. When the junction temperature exceeds
+170°C, an internal thermal sensor shuts down the devices,
allowing them to cool. The thermal sensor turns on the
devices again after the junction temperature cools by 20°C.
Overcurrent Protection
If the inductor current in the MAX17232/MAX17233
exceeds the maximum current limit programmed at CS_
and OUT_, the respective driver turns off. In an overcurrent
mode, this results in shorter and shorter high-side pulses.
A hard short results in a minimum on-time pulse every
clock cycle. Choose the components so they can withstand
the short-circuit current if required.
Overvoltage Protection
The devices limit the output voltage of the buck
converters by turning off the high-side gate driver at
approximately 115% of the regulated output voltage. The
output voltage needs to come back in regulation before
the high-side gate driver starts switching again.
Design Procedure
Buck Converter Design Procedure
Effective Input Voltage Range in Buck Converters
Although the MAX17232/MAX17233 can operate
from input supplies up to 36V (42V transients) and
regulate down to 1V, the minimum voltage conversion ratio
(VOUT/VIN) might be limited by the minimum controllable
on-time. For proper fixed-frequency PWM operation and
optimal efficiency, buck 1 and buck 2 should operate in
continuous conduction during normal operating conditions.
For continuous conduction, set the voltage conversion
ratio as follows:
VOUT
> t ON(MIN) × f SW
VIN
where tON(MIN) is 50ns (typ) and fSW is the switching
frequency in Hz. If the desired voltage conversion does
not meet the above condition, pulse skipping occurs to
decrease the effective duty cycle. Decrease the switching
frequency if constant switching frequency is required. The
same is true for the maximum voltage conversion ratio.
The maximum voltage conversion ratio is limited by the
maximum duty cycle (95%).
VOUT
< 0.95
VIN − VDROP
where VDROP = IOUT (RON,HS + RDCR) is the sum of
the parasitic voltage drops in the high-side path and fSW
is the programmed switching frequency. During low drop
operation, the devices reduce fSW to 25% (max) of the
programmed frequency. In practice, the above condition
should be met with adequate margin for good loadtransient response.
Setting the Output Voltage in Buck Converters
Connect FB1 and FB2 to BIAS to enable the fixed buck
controller output voltages (5V and 3.3V) set by a preset
internal resistive voltage-divider connected between
the output (OUT_) and AGND. To externally adjust the
output voltage between 1V and 10V, connect a resistive
divider from the output (OUT_) to FB_ to AGND (see
the Typical Application Circuit). Calculate RFB_1 and
RFB_2 with the following equation:
 VOUT_  
 − 1
=
R FB_1 R FB_2 
 VFB_  
where VFB_ = 1V (typ) (see the Electrical Characteristics
table).
DC output accuracy specifications in the Electrical
Characteristics table refer to the error comparator’s threshold,
VFB_ = 1V (typ). When the inductor conducts continuously, the
devices regulate the peak of the output ripple, so the actual DC
output voltage is lower than the slope-compensated trip level by
50% of the output ripple voltage.
In discontinuous conduction mode (skip or STDBY active
and IOUT < ILOAD(SKIP)), the devices regulate the
valley of the output ripple, so the output voltage has a DC
regulation level higher than the error-comparator threshold.
www.maximintegrated.com
Maxim Integrated │ 15
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Inductor Selection in Buck Converters
Three key inductor parameters must be specified for
operation with the MAX17232/MAX17233: inductance
value (L), inductor saturation current (ISAT), and DC
resistance (RDCR). To determine the optimum
inductance, knowing the typical duty cycle (D) is
important.
=
D
VOUT
VOUT
=
OR D
VIN
VIN − I OUT (R DS(ON) + R DCR )
if the RDCR of the inductor and RDS(ON) of the MOSFET
are available with VIN = (VBAT - VDIODE). All values should
be typical to optimize the design for normal operation.
Inductance
Peak Inductor Current
Inductors are rated for maximum saturation current. The
maximum inductor current equals the maximum load
current in addition to half of the peak-to-peak ripple
current:
=
IPEAK ILOAD(MAX) +
∆IINDUCTOR
2
For the selected inductance value, the actual peak-to-peak
inductor ripple current (ΔIINDUCTOR) is calculated as:
VOUT (VIN − VOUT )
∆IINDUCTOR =
VIN x f SW x L
where ΔIINDUCTOR is in mA, L is in µH, and fSW is in kHz.
The exact inductor value is not critical and can be
adjusted in order to make trade-offs among size, cost,
efficiency, and transient response requirements.
●● Lower inductor values increase LIR, which minimizes
size and cost and improves transient response at the
cost of reduced efficiency due to higher peak currents.
Once the peak current and the inductance are known, the
inductor can be selected. The saturation current should
be larger than IPEAK or at least in a range where the
inductance does not degrade significantly. The MOSFETs
are required to handle the same range of current without
dissipating too much power.
●● Higher inductance values decrease LIR, which
increases efficiency by reducing the RMS current at
the cost of requiring larger output capacitors to meet
load-transient specifications.
MOSFET Selection in Buck Converters
The ratio of the inductor peak-to-peak AC current to DC
average current (LIR) must be selected first. A good initial
value is a 30% peak-to-peak ripple current to averagecurrent ratio (LIR = 0.3). The switching frequency, input
voltage, output voltage, and selected LIR then determine
the inductor value as follows:
L[µH] =
(VIN − VOUT )x D
f SW [MHz]xI OUT x LIR
where VIN, VOUT, and IOUT are typical values (so that
efficiency is optimum for typical conditions).
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Each step-down controller drives two external logic-level
n-channel MOSFETs as the circuit switch elements. The
key selection parameters to choose these MOSFETs
include the items in the following sections.
Threshold Voltage
All four n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at VGS = 4.5V. If
the internal regulator is bypassed (for example: VEXTVCC
= 3.3V), then the nMOSFETS should be chosen to have
guaranteed on-resistance at that gate-to-source voltage.
Maximum Drain-to-Source Voltage (VDS(MAX))
All MOSFETs must be chosen with an appropriate VDS
rating to handle all VIN voltage conditions.
Maxim Integrated │ 16
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Current Capability
between the inductor and output as shown in Figure 1a.
This configuration constantly monitors the inductor current,
allowing accurate current-limit protection. Use low-inductance
current-sense resistors for accurate measurement.
The n-channel MOSFETs must deliver the average
current to the load and the peak current during switching.
Choose MOSFETs with the appropriate average current
at VGS = 4.5V or VGS = VEXTVCC when the internal
linear regulator is bypassed. For load currents below
approximately 3A, dual MOSFETs in a single package
can be an economical solution. To reduce switching noise
for smaller MOSFETs, use a series resistor in the BST_
path and additional gate capacitance.
Alternatively, high-power applications that do not require
highly accurate current-limit protection can reduce the
overall power dissipation by connecting a series RC
circuit across the inductor (Figure 1b) with an equivalent
time constant:
 R2 
R CSHL = 
 R DCR
 R1 + R2 
Current-Sense Measurement
For the best current-sense accuracy and overcurrent
protection, use a ±1% tolerance current-sense resistor
MAX17232
MAX17233
DH_
NH
RSENSE
L
LX_
DL_
INPUT (VIN)
CIN
COUT
NL
GND
CS_
OUT_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN)
MAX17232
MAX17233
DH_
CIN
NH
LX_
DL_
NL
GND
CS_
OUT_
INDUCTOR
L
DCR
R1
R2
CEQ
COUT
RCSHL =
RDCR =
( )
[ ]
R2
R
R1 + R2 DCR
L
1+ 1
CEQ R1 R2
B) LOSSLESS INDUCTOR SENSING
Figure 1. Current-Sense Configurations
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Maxim Integrated │ 17
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
and:
R DCR
=
L
1 
1
+

C EQ  R1 R2 
where RCSHL is the required current-sense resistor and
RDCR is the inductor’s series DC resistor. Use the
inductance and RDCR values provided by the inductor
manufacturer.
Carefully observe the PCB layout guidelines to ensure the
noise and DC errors do no corrupt the differential currentsense signals seen by CS_ and OUT_. Place the sense
resistor close to the devices with short, direct traces,
making a Kelvin-sense connection to the current-sense
resistor.
Input Capacitor in Buck Converters
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the input
capacitor must be carefully chosen to withstand the input
ripple current and keep the input voltage ripple within
design requirements. The 180° ripple phase operation
increases the frequency of the input capacitor ripple
current to twice the individual converter switching
frequency. When using ripple phasing, the worst-case
input capacitor ripple current is when the converter with
the highest output current is on.
The input voltage ripple is composed of ΔVQ (caused by
the capacitor discharge) and ΔVESR (caused by the ESR
of the input capacitor). The total voltage ripple is the sum
of ΔVQ and ΔVESR that peaks at the end of an on-cycle.
Calculate the input capacitance and ESR required for a
specific ripple using the following equation:
∆VESR
ESR[Ω] =
∆IP − P 

ILOAD(MAX) + 2 


V

ILOAD(MAX) x  OUT 
 VIN 
C IN[µF] =
∆
V
x
f
( Q SW )
where:
(VIN − VOUT ) x VOUT
∆IP−P =
VIN x f SW x L
ILOAD(MAX) is the maximum output current in A, ΔIP-P is
the peak-to-peak inductor current in A, fSW is the switching
frequency in MHz, and L is the inductor value in µH.
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The internal 5V linear regulator (BIAS) includes an output
UVLO with hysteresis to avoid unintentional chattering
during turn-on. Use additional bulk capacitance if the
input source impedance is high. At lower input voltage,
additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during
transient loading.
Output Capacitor in Buck Converters
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. The capacitor
is usually selected by ESR and the voltage rating rather
than by capacitance value.
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent VSAG and VSOAR from
causing problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the Transient Considerations
section). However, low-capacity filter capacitors typically
have high-ESR zeros that can affect the overall stability.
The total voltage sag (VSAG) can be calculated as follows:
VSAG =
L( ∆ILOAD(MAX) ) 2
2C OUT ((VIN × D MAX ) − VOUT )
+
∆ILOAD(MAX) (t − ∆t)
C OUT
The amount of overshoot (VSOAR) during a full-load to
no-load transient due to stored inductor energy can be
calculated as:
VSOAR ≈
( ∆ILOAD(MAX) ) 2 L
2C OUT VOUT
ESR Considerations
The output filter capacitor must have low enough
equivalent series resistance (ESR) to meet output
ripple and load-transient requirements, yet have high
enough ESR to satisfy stability requirements. When using
high-capacitance, low-ESR capacitors, the filter
capacitor’s ESR dominates the output voltage ripple. So
the output capacitor’s size depends on the maximum ESR
required to meet the output-voltage ripple (VRIPPLE(P-P))
specifications:
VRIPPLE(P−P) = ESR xILOAD(MAX) x LIR
Maxim Integrated │ 18
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
In standby mode, the inductor current becomes
discontinuous, with peak currents set by the idle-mode
current-sense threshold (VCS,SKIP = 26mV (typ)).
gmc = 1/(AVCS x RDC)
CS_
CURRENT MODE
POWER
MODULATION
Transient Considerations
The output capacitor must be large enough to absorb
the inductor energy while transitioning from no-load to
full-load condition without tripping the overvoltage fault
protection. The total output voltage sag is the sum of the
voltage sag while the inductor is ramping up and the voltage
sag before the next pulse can occur. Therefore:
(
)
2
L ∆ILOAD(MAX)
C OUT =
2VSAG (VIN x D MAX − VOUT )
+
OUT_
R1
RESR
COUT
gmea = 1200µS
FB_
COMP_
ERROR
AMP
R2
VREF
RC
30MΩ
CF
CC
∆ILOAD(MAX) (t − ∆t)
VSAG
where DMAX is the maximum duty factor (approximately
95%), L is the inductor value in µH, COUT is the output
capacitor value in µF, t is the switching period (1/fSW) in
µs, and Δt equals (VOUT/VIN) x t.
The MAX17232/MAX17233 use a peak current-mode
control scheme that regulates the output voltage by
forcing the required current through the external inductor,
so the controller uses the voltage drop across the DC
resistance of the inductor or the alternate series currentsense resistor to measure the inductor current. Currentmode control eliminates the double pole in the feedback
loop caused by the inductor and output capacitor resulting
in a smaller phase shift and requiring less elaborate
error-amplifier compensation than voltage-mode control.
A single series resistor (RC) and capacitor (CC) is all
that is required to have a stable, high-bandwidth loop in
applications where ceramic capacitors are used for output
filtering (see Figure 2). For other types of capacitors,
due to the higher capacitance and ESR, the frequency
of the zero created by the capacitance and ESR is lower
than the desired closed-loop crossover frequency. To
stabilize a non-ceramic output capacitor loop, add another
compensation capacitor (CF) from COMP to AGND to
cancel this ESR zero.
The basic regulator loop is modeled as a power
modulator, output feedback divider, and an error amplifier
as shown in Figure 2. The power modulator has a DC
gain set by gmc x RLOAD, with a pole and zero pair set
by RLOAD, the output capacitor (COUT), and its ESR. The
loop response is set by the following equations:
Figure 2. Compensation Network
where RLOAD = VOUT/ILOUT(MAX) in Ω and gmc =1/(AV_CS
x RDC) in S. AV_CS is the voltage gain of the current-sense
amplifier and is typically 11V/V. RDC is the DC resistance of
the inductor or the current-sense resistor in Ω.
In a current-mode step-down converter, the output
capacitor and the load resistance introduce a pole at the
following frequency:
f pMOD =
1
2π × C OUT × R LOAD
The unity gain frequency of the power stage is set by
COUT and gmc:
f UGAINpMOD =
g mc
2π × C OUT
The output capacitor and its ESR also introduce a zero at:
f zMOD =
1
2π × ESR × C OUT
When COUT is composed of “n” identical capacitors in
parallel, the resulting COUT = nxCOUT(EACH), and ESR =
ESR(EACH) /n. Note that the capacitor zero for a parallel
combination of alike capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAINFB =
VFB /VOUT, where VFB is 1V (typ).
GAINMOD(dc)
= g mc × R LOAD
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Maxim Integrated │ 19
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
The transconductance error amplifier has a DC gain
of GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is
the error amplifier transconductance, which is 1200µS
(typ), and ROUT,EA is the output resistance of the error
amplifier, which is 30MΩ (typ) (see the Electrical
Characteristics table.)
Set the error-amplifier compensation zero formed by RC
and CC at the fpMOD. Calculate the value of CC as follows:
A dominant pole (fdpEA) is set by the compensation
capacitor (CC) and the amplifier output resistance
(ROUT,EA). A zero (fZEA) is set by the compensation
resistor (RC) and the compensation capacitor (CC). There
is an optional pole (fPEA) set by CF and RC to cancel the
output capacitor ESR zero if it occurs near the crossover
frequency (fC, where the loop gain equals 1 (0dB)). Thus:
If fzMOD is less than 5 x fC, add a second capacitor CF
from COMP to AGND. The value of CF is:
f dpEA =
1
2π × C C × (R OUT,EA + R C )
1
f zEA =
2π × C C × R C
f pEA =
CF =
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases accordingly
and the crossover frequency remains the same.
Below is a numerical example to calculate the
compensation network component values of Figure 2:
VOUT = 5V
IOUT(MAX) = 5.33A
RLOAD = VOUT /IOUT(MAX) = 5V/5.33A = 0.9375Ω
COUT = 2x47µF = 94µF
VFB
× GAINEA(f ) =
1
C
VOUT
fSW = 26.4/65.5kΩ = 0.403MHz
GAINMOD(dc) =
6.06 × 0.9375 =
5.68
=
f pMOD
GAINEA(f
=
g m,EA × R C
C)
1
≈ 1.8kHz
2π × 94µF × 0.9375
f pMOD
f
f pMOD << f C ≤ SW
5
fC
1.8kHz << f C ≤ 80.6kHz
Therefore:
V
GAINMOD(f ) × FB × g m,EA × R C =
1
C
VOUT
RC =
2π × f zMOD × R C
ESR = 9mΩ/2 = 4.5mΩ
At the crossover frequency, the total loop gain must be
equal to 1. So:
Solving for RC:
1
gmc = 1/(AV_CS x RDC) = 1/(11 x 0.015) = 6.06
f
f pMOD << f C ≤ SW
5
C
2π × f pMOD × R C
RDCR = 15mΩ
1
2π × C F × R C
GAIN
=
MOD(f ) GAINMOD(dc) ×
1
AV_CS = 11V/V
The loop-gain crossover frequency (fC) should be set
below 1/5th of the switching frequency and much higher
than the power-modulator pole (fpMOD). Select a value for
fC in the range:
GAINMOD(f ) ×
C
CC =
VOUT
g m,EA × VFB × GAINMOD(f )
C
select fC = 40kHz
=
f zMOD
1
≈ 376kHz
2π × 4.5mΩ × 94µF
since fzMOD>fC:
RC ≈ 16kΩ
CC ≈ 5.6nF
CF ≈ 27pF
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Maxim Integrated │ 20
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Applications Information
Layout Recommendations
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention (Figure 3). If possible,
mount all the power components on the top side of the
board, with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
●● Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
●● Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full
load efficiency by 1% or more.
●● Minimize current-sensing errors by connecting CS_
and OUT_. Use kelvin sensing directly across the
current-sense resistor (RSENSE_).
●● Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (FB_,
CS_, and OUT_).
Layout Procedure
1) Place the power components first, with ground
terminals adjacent (low-side FET, CIN, COUT_, and
Schottky). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite NL_
and NH_ to keep LX_, GND, DH_, and the DL_ gate
drive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper adaptive
dead-time sensing.
3) Group the gate-drive components (BST_ diode and
capacitor and LDO bypass capacitor BIAS) together
near the controller IC. Be aware that gate currents of
up to 1A flow from the bootstrap capacitor to BST_,
from DH_ to the gate of the external HS switch and
from the LX_ pin to the inductor. Up to 100mA of
current flow from the BIAS capacitor through the
bootstrap diode to the bootstrap capacitor. Dimension
those traces accordingly.
4) Make the DC-DC controller ground connections as
shown in Figure 3. This diagram can be viewed as
having two separate ground planes: power ground,
where all the high-power components go; and an
analog ground plane for sensitive analog components.
The analog ground plane and power ground plane
must meet only at a single point directly under the IC.
5) Connect the output power planes directly to the output
filter capacitor positive and negative terminals with
multiple vias. Place the entire DC-DC converter circuit
as close to the load as is practical.
KELVIN-SENSE VIAS
UNDER THE SENSE RESISTOR
(REFER TO THE EVALUATION KIT)
INDUCTOR
LOW-SIDE
n-CHANNEL
MOSFET (NH)
COUT
CIN
COUT
HIGH-SIDE
n-CHANNEL
MOSFET (NL)
INPUT
OUTPUT
GROUND
Figure 3. Layout Example
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Maxim Integrated │ 21
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Block Diagram
PGOOD1 COMP1
DC-DC1
CONTROL LOGIC
PGOOD LOW LEVEL
PGOOD HIGH LEVEL PGOOD
COMP
FB1
FEEDBACK
SELECT LOGIC
MAX17232
MAX17233
EAMP1
INTERNAL
SOFT-START
EN1
REF = 1V
OUT1
80 mV(TYP) MAX
DIFFERENTIAL INPUT
PWM1
PWM1
CSA1
CLK1
CS1
ZX1
CL
SLOPE
COMP LOGIC
EN1
DH1
STEP-DOWN DC-DC1
GATE DRIVE
LOGIC
LX1
DL1
ZERO
CROSS
COMP
CURRENT-LIMIT
THRESHOLD
LX1
FOSC
BST1
PGND1
LX1
CLK1
OSCILLATOR
IN
SPREAD SPECTRUM
OPTION AVAILABLE WITH
INTERNAL CLOCK ONLY
FSYNC
FSYNC
SELECT LOGIC
EXTERNAL
CLOCK INPUT
BIAS
INTERNAL LINEAR
REGULATOR
TIED HIGH (PWM MODE)
TIED LOW (SKIP MODE)
SWITCHOVER
AGND
EN2
COMP2
EN2
BST2
PWM2
FB2
CS2
IF 3.1V <
VEXTVCC < 5.2V EXTVCC
CLK 180°
OUT-OF-PHASE
CLK2
OUT2
BIAS
CLK2
DC-DC2 CONTROL LOGIC
SAME AS DC-DC1 ABOVE
ZX2
PGOOD2
LX2
LX2
DH2
STEP-DOWN DC-DC2
GATE DRIVE
LOGIC
LX2
DL2
PGND2
EP
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Maxim Integrated │ 22
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Selector Guide
BUCK 1 SWITCHING
FREQUENCY (fSW1)
BUCK 2 SWITCHING
FREQUENCY (fSW2)
SPREAD
SPECTRUM (%)
MAX17233ETIR+
1MHz to 2.2MHz
fSW1
—
PART
MAX17233ETIS+
1MHz to 2.2MHz
fSW1
6
MAX17232ETIR+
200kHz to 1MHz
fSW1
—
MAX17232ETIS+
200kHz to 1MHz
fSW1
6
Package Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17233ETI_+
-40°C to +85°C
28 TQFN-EP*
MAX17232ETI_+
-40°C to +85°C
28 TQFN-EP*
Note: Insert the desired suffix letter (from Selector Guide) into
the blank to indicate buck 2 switching frequency and spread
spectrum.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855+5
21-0140
90-0025
Chip Information
PROCESS: BiCMOS
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Maxim Integrated │ 23
MAX17232/MAX17233
3.5V–36V, 2.2MHz, Synchronous Dual Buck
Controller with 20µA Quiescent Current
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/16
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 24