LINER LTC2979 16-channel pmbus low-voltage power system manager Datasheet

LTC2979
16-Channel PMBus
Low-Voltage Power System Manager
FEATURES
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DESCRIPTION
Sequence, Trim, Margin and Supervise 16
Power Supplies
Manage Faults, Monitor Telemetry and Create Fault Logs
PMBus Compliant Command Set
Supported by LTpowerPlay® GUI
Margin or Trim Supplies to within 0.5% of Target
Fast OV/UV Supervisors per Channel
Coordinate Sequencing and Fault Management
Across Multiple ADI PSM Devices
Automatic Fault Logging to Internal EEPROM
Operate Autonomously without Additional Software
Internal Temperature and Input Voltage Supervisors
Accurate Monitoring of 16 Output Voltages, Two
Input Voltages and Internal Die Temperature
I2C/SMBus Serial Interface
Powered from 3.13V to 3.47V
Programmable Watchdog Timer
Available in 144-Pin 12mm × 12mm BGA Package
APPLICATIONS
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Computers and Network Servers
Industrial Test and Measurement
High Reliability Systems
Medical Imaging
Video
The LTC®2979 is a 16-channel Power System Manager
used to sequence, trim (servo), margin, supervise,
manage faults, provide telemetry and create fault logs.
PMBus commands support power supply sequencing,
precision point-of-load voltage adjustment and margining. DACs use a proprietary soft-connect algorithm to
minimize supply disturbances. Supervisory functions
include overvoltage and undervoltage threshold limits
for sixteen power supply output channels and two power
supply input channels, as well as over and under temperature limits. Programmable fault responses can disable the
power supplies with optional retry after a fault is detected.
Faults that disable a power supply can automatically trigger black box EEPROM storage of fault status and associated telemetry. An internal 16-bit ADC monitors sixteen
output voltages, two input voltages and die temperature.
In addition, odd numbered channels can be configured
to measure the voltage across a current sense resistor. A
programmable watchdog timer monitors microprocessor
activity for a stalled condition and resets the microprocessor if necessary. A single wire bus synchronizes power
supplies across multiple ADI Power System Management
(PSM) devices. Configuration EEPROM with ECC supports autonomous operation without additional software.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 7382303, 7420359 and 7940091.
TYPICAL APPLICATION
LTC2979 Sequencing 16 Channels
16-Channel PMBus Power System Manager
48V
IN
IBC
OUT
EN
12V
VIN_SNS
VIN_EN
3.3V
REGULATOR
PMBus
INTERFACE
VDD33
LTC2979
VSENSEM0
SDA
SCL
ALERTB
CONTROL
FAULT
PWRGD
VOUT
VSENSEP0
VDAC
VIN
DC/DC
CONVERTER
LOAD
VFB
0.5V/DIV
RUN
R20
R30
R10
10ms/DIV
2979 TA01b
VOUT_EN
2979 TA01a
NOTE: SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF 16 CHANNELS SHOWN
2979f
For more information www.linear.com/LTC2979
1
LTC2979
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
Supply Voltages:
VIN_SNS .................................................. –0.3V to 15V
VDD33 .................................................... –0.3V to 3.6V
VDD25 .................................................. –0.3V to 2.75V
Digital Input/Output Voltages:
ALERTB, SDA, SCL, CONTROL0,
CONTROL1............................................ –0.3V to 5.5V
PWRGD, SHARE_CLK,
WDI/RESETB, WP ....................–0.3V to VDD33 + 0.3V
FAULTB00, FAULTB01, FAULTB10,
FAULTB11 ................................–0.3V to VDD33 + 0.3V
ASEL0, ASEL1 ..........................–0.3V to VDD33 + 0.3V
Analog Voltages:
REFP ................................................... –0.3V to 1.35V
REFM .................................................... –0.3V to 0.3V
VSENSEP[7:0] ............................................. –0.3V to 6V
VSENSEM[7:0] ............................................. –0.3V to 6V
VOUT_EN[7:0], VIN_EN ................................. –0.3V to 6V
VDACP[7:0]................................................. –0.3V to 6V
VDACM[7:0] ............................................ –0.3V to 0.3V
Operating Junction Temperature Range:
LTC2979C ................................................ 0°C to 70°C
LTC2979I ........................................... –40°C to 105°C
Storage Temperature Range ................ –55°C to 125°C*
Maximum Junction Temperature ........................ 125°C*
Maximum Solder Temperature .............................. 260°C
PIN 1
1
2
3
4
5
TOP VIEW
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
J
K
L
M
BGA PACKAGE
144-LEAD (12mm × 12mm × 1.29mm)
TJMAX = 125°C, θJA = 32°C/W, θJCtop = 11°C/W, θJCbottom = 15°C/W, θJB = 18°C/W,
WEIGHT = 1.6g, VALUES DETERMINED PER JEDEC 51-9, 51-12
*See OPERATION section of the LTC2977 data sheet for detailed EEPROM
derating information for junction temperatures in excess of 105°C.
ORDER INFORMATION
http://www.linear.com/product/LTC2979#orderinfo
PART MARKING*
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
SAC305 (RoHS)
LTC2979Y
e1
BGA
3
0°C to 70°C
SAC305 (RoHS)
LTC2979Y
e1
BGA
3
–40°C to 105°C
PART NUMBER
PAD OR BALL FINISH
LTC2979CY#PBF
LTC2979IY#PBF
OPERATING JUNCTION
TEMPERATURE RANGE
Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
2
2979f
For more information www.linear.com/LTC2979
LTC2979
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VDD33 = 3.3V, VIN_SNS = 12V, VDD25 and REF pins floating, unless
otherwise indicated. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
10
13
2.55
2.8
UNITS
Power Supply Characteristics
IVDD33
VDD33 Supply Current
3.13V ≤ VDD33 ≤ 3.47V
l
VUVLO_VDD33
VDD33 Undervoltage Lockout
VDD33 Ramping Up
l
2.35
VDD33 Undervoltage Lockout
Hysteresis
VDD33
Supply Input Operating Range
VDD25
Regulator Output Voltage
tINIT
Initialization Time
120
3.13V ≤ VDD33 ≤ 3.47V
Regulator Output Short-Circuit Current VDD33 = 3.47V, VDD25 = 0V
l
3.13
l
2.35
l
30
Time from VIN Applied Until the TON_DELAY
Timer Starts
mA
V
mV
3.47
V
2.5
2.6
V
55
80
mA
30
ms
Voltage Reference Characteristics
VREF
Output Voltage (Note 4)
VREF = VREFP – VREFM, 0 < IREFP < 100µA
1.232
Temperature Coefficient
Hysteresis
V
3
(Note 5)
ppm/°C
100
ppm
ADC Characteristics
VIN_ADC
Voltage Sense Input Range
Current Sense Input Range (Odd
Numbered Channels Only)
N_ADC
TUE_ADC_
VOLT_SNS
TUE_ADC_
CURR_SNS
Differential Voltage:
VIN_ADC = (VSENSEPn – VSENSEMn)
l
0
6
V
Single-Ended Voltage: VSENSEMn
l
–0.1
0.1
V
Single-Ended Voltage: VSENSEPn, VSENSEMn
l
–0.1
6
V
Differential Voltage: VIN_ADC
l
–170
170
mV
Voltage Sense Resolution (Uses L16
Format)
0V ≤ VIN_ADC ≤ 6V
Mfr_config_adc_hires = 0
Current Sense Resolution (Odd
Numbered Channels Only)
0mV ≤ |VIN_ADC| < 16mV (Note 6)
16mV ≤ |VIN_ADC| < 32mV
32mV ≤ |VIN_ADC| < 63.9mV
63.9mV ≤ |VIN_ADC| < 127.9mV
127.9mV ≤ |VIN_ADC|
Mfr_config_adc_hires = 1
Total Unadjusted Error (Note 4)
Voltage Sense Mode VIN_ADC ≥ 1V
l
±0.5
% of
Reading
Voltage Sense Mode 0 ≤ VIN_ADC ≤ 1V
l
±5.0
mV
Current Sense Mode, Odd Numbered
Channels Only, 20mV ≤ VIN_ADC ≤ 170mV
l
±0.7
% of
Reading
Current Sense Mode, Odd Numbered
Channels Only, VIN_ADC ≤ 20mV
l
±140
µV
l
±100
µV
Total Unadjusted Error (Note 4)
122
µV/LSB
15.625
31.25
62.5
125
250
µV/LSB
µV/LSB
µV/LSB
µV/LSB
µV/LSB
VOS_ADC
Offset Error
Current Sense Mode, Odd Numbered
Channels Only
tCONV_ADC
Conversion Time
Voltage Sense Mode (Note 7)
6.15
ms
Current Sense Mode (Note 7)
24.6
ms
Temperature Input (Note 7)
24.6
ms
Odd Numbered Channels in Current Sense
Mode (Note 7)
160
ms
1
pF
tUPDATE_ADC
Update Time
CIN_ADC
Input Sampling Capacitance
2979f
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3
LTC2979
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VDD33 = 3.3V, VIN_SNS = 12V, VDD25 and REF pins floating, unless
otherwise indicated. (Notes 2, 3)
SYMBOL
PARAMETER
fIN_ADC
Input Sampling Frequency
CONDITIONS
MIN
IIN_ADC
Input Leakage Current
VIN_ADC = 0V, 0V ≤ VCOMMONMODE ≤ 6V,
Current Sense Mode
l
Differential Input Current
VIN_ADC = 0.17V, Current Sense Mode
l
VIN_ADC = 6V, Voltage Sense Mode
l
TYP
MAX
62.5
UNITS
kHz
±0.5
µA
80
250
nA
10
15
µA
DAC Output Characteristics
N_VDACP
Resolution
VFS_VDACP
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF Buffer Gain Setting_0
DAC Polarity = 1
Buffer Gain Setting_1
l
l
10
INL_VDACP
Integral Nonlinearity
(Note 8)
l
±2
LSB
DNL_VDACP
Differential Nonlinearity
(Note 8)
l
±2.4
LSB
VOS_VDACP
Offset Voltage
(Note 8)
l
±20
mV
VDACP
Load Regulation (VDACPn – VDACMn)
VDACPn = 2.65V, IVDACPn Sourcing = 2mA
100
ppm/mA
VDACPn = 0.1V, IVDACPn Sinking = 2mA
100
ppm/mA
PSRR (VDACPn – VDACMn)
DC: 3.13V ≤ VDD33 ≤ 3.47V
60
dB
100mV Step in 20ns with 50pF Load
40
dB
1.32
2.53
1.38
2.65
Bits
1.44
2.77
60
V
V
DC CMRR (VDACPn – VDACMn)
–0.1V ≤ VDACMn ≤ 0.1V
Leakage Current
VDACPn Hi-Z, 0V ≤ VDACPn ≤ 6V
l
dB
Short-Circuit Current Low
VDACPn Shorted to GND
l
–10
–4
mA
Short-Circuit Current High
VDACPn Shorted to VDD33
l
4
10
mA
COUT
Output Capacitance
VDACPn Hi-Z
10
pF
tS_VDACP
DAC Output Update Rate
Fast Servo Mode
500
µs
±100
nA
DAC Soft-Connect Comparator Characteristics
VOS_CMP
Offset Voltage
VDACPn = 0.2V
l
±1
±18
mV
VDACPn = 1.3V
l
±2
±26
mV
VDACPn = 2.65V
l
±3
±52
mV
VIN_VS = (VSENSEPn Low Resolution Mode
– VSENSEMn)
High Resolution Mode
l
l
0
0
6
3.8
V
V
Single-Ended Voltage: VSENSEMn
l
–0.1
0.1
V
Voltage Supervisor Characteristics
VIN_VS
Input Voltage Range (Programmable)
N_VS
Voltage Sensing Resolution
TUE_VS
Total Unadjusted Error
0V to 3.8V Range: High Resolution Mode
4
0V to 6V Range: Low Resolution Mode
tS_VS
4
mV/LSB
8
mV/LSB
2V ≤ VIN_VS ≤ 6V, Low Resolution Mode
l
±1.25
% of
Reading
1.5V < VIN_VS ≤ 3.8V, High Resolution
Mode
l
±1.0
% of
Reading
0.8V ≤ VIN_VS ≤ 1.5V, High Resolution
Mode
l
±1.5
% of
Reading
Update Period
12.21
µs
2979f
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LTC2979
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VDD33 = 3.3V, VIN_SNS = 12V, VDD25 and REF pins floating, unless
otherwise indicated. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
15
V
90
110
kΩ
VIN_SNS Input Characteristics
VVIN_SNS
VIN_SNS Input Voltage Range
l
0
RVIN_SNS
VIN_SNS Input Resistance
l
70
TUEVIN_SNS
VIN_ON, VIN_OFF Threshold Total
Unadjusted Error
READ_VIN Total Unadjusted Error
3V ≤ VVIN_SNS ≤ 8V
l
±2.0
% of
Reading
VVIN_SNS > 8V
l
±1.0
% of
Reading
3V ≤ VVIN_SNS ≤ 8V
l
±1.5
% of
Reading
VVIN_SNS > 8V
l
±1.0
% of
Reading
Temperature Sensor Characteristics
TUE_TS
Total Unadjusted Error
±1
°C
VOUT Enable Output (VOUT_EN [3:0]) Characteristics
IVOUT_ENn
Output Sinking Current
Output Leakage Current
VVOUT_VALID
Strong Pull-Down Enabled,
VVOUT_ENn = 0.4V
l
3
5
Weak Pull-Down Enabled, VVOUT_ENn = 0.4V l
33
50
Internal Pull-Up Disabled,
0V ≤ VVOUT_ENn ≤ 6V
Minimum VDD33 when VVOUT_ENn Valid VVOUT_ENn ≤ 0.4V
8
mA
60
µA
l
±1
µA
l
1.1
V
VOUT Enable Output (VOUT_EN [7:4]) Characteristics
IVOUT_ENn
Output Sinking Current
Strong Pull-Down Enabled,
VOUT_ENn = 0.1V
l
3
6
9
mA
Output Leakage Current
0V ≤ VVOUT_ENn ≤ 6V
l
±1
µA
Output Sinking Current
VVIN_EN = 0.4V
l
Leakage Current
Internal Pull-Up Disabled,
0V ≤ VVIN_EN ≤ 6V
l
8
mA
±1
µA
l
1.1
V
VIN Enable Output (VIN_EN) Characteristics
IVIN_EN
VVOUT_VALID
Minimum VDD33 when VVOUT_ENn Valid VVOUT_ENn ≤ 0.4V
3
5
EEPROM Characteristics
Endurance
(Notes 10, 11)
0°C < TJ < 85°C During EEPROM Write
Operations
l
10,000
Retention
(Notes 10, 11)
TJ < 105°C
l
20
tMASS_WRITE
Mass Write Operation Time (Note 12)
STORE_USER_ALL, 0°C < TJ < 85°C During l
EEPROM Write Operations
Cycles
Years
440
4100
ms
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
VHYST
Input Hysteresis
ILEAK
Input Leakage Current
2.1
V
1.5
20
V
mV
0V ≤ VPIN ≤ 5.5V, SDA, SCL, CONTROLn
Pins Only
l
±2
µA
0V ≤ VPIN ≤ VDD33 + 0.3V, FAULTBzn,
WDI/RESETB, WP Pins Only
l
±2
µA
2979f
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5
LTC2979
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VDD33 = 3.3V, VIN_SNS = 12V, VDD25 and REF pins floating, unless
otherwise indicated. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
tSP
Pulse Width of Spike Suppressed
FAULTBzn, CONTROLn Pins Only
MIN
tFAULT_MIN
Minimum Low Pulse Width for
Externally Generated Faults
tRESETB
Pulse Width to Assert Reset
VWDI/RESETB ≤ 1.5V
l
300
tWDI
Pulse Width to Reset Watchdog Timer
VWDI/RESETB ≤ 1.5V
l
0.3
fWDI
Watchdog Interrupt Input Frequency
CIN
Digital Input Capacitance
TYP
MAX
10
SDA, SCL Pins Only
UNITS
µs
98
ns
110
ms
µs
200
1
l
10
µs
MHz
pF
Digital Input SHARE_CLK
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
fSHARE_CLK_IN Input Frequency Operating Range
1.6
V
0.8
V
l
90
110
kHz
tLOW
Assertion Low Time
VSHARE_CLK < 0.8V
l
0.825
1.1
µs
tRISE
Rise Time
VSHARE_CLK < 0.8V to VSHARE_CLK > 1.6V
l
450
ns
ILEAK
Input Leakage Current
0V ≤ VSHARE_CLK ≤ VDD33 + 0.3V
l
±1
µA
CIN
Input Capacitance
10
pF
Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11
VOL
Digital Output Low Voltage
fSHARE_CLK_OUT Output Frequency Operating Range
ISINK = 3mA
l
5.49kΩ Pull-Up to VDD33
l
90
VDD33 – 0.5
100
0.4
V
110
kHz
Digital Inputs ASEL0,ASEL1
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
0.5
V
l
±95
µA
l
±24
µA
IIH, IIL
High, Low Input Current
IHIZ
Hi-Z Input Current
CIN
Input Capacitance
ASEL[1:0] = 0, VDD33
V
10
pF
Serial Bus Timing Characteristics
fSCL
Serial Clock Frequency (Note 13)
l
10
400
kHz
tLOW
Serial Clock Low Period (Note 13)
l
1.3
µs
tHIGH
Serial Clock High Period (Note 13)
l
0.6
µs
tBUF
Bus Free Time Between Stop and Start
(Note 13)
l
1.3
µs
tHD,STA
Start Condition Hold Time (Note 13)
l
600
ns
tSU,STA
Start Condition Setup Time (Note 13)
l
600
ns
tSU,STO
Stop Condition Setup Time (Note 13)
l
600
ns
tHD,DAT
Data Hold Time (LTC2979 Receiving
Data) (Note 13)
l
0
ns
Data Hold Time (LTC2979 Transmitting
Data) (Note 13)
l
300
Data Setup Time (Note 13)
l
100
tSU,DAT
6
900
ns
ns
2979f
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LTC2979
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VDD33 = 3.3V, VIN_SNS = 12V, VDD25 and REF pins floating, unless
otherwise indicated. (Notes 2, 3)
SYMBOL
PARAMETER
tSP
Pulse Width of Spike Suppressed
(Note 13)
CONDITIONS
MIN
tTIMEOUT_BUS
Time Allowed to Complete any PMBus Mfr_config_all_longer_pmbus_timeout = 0
Command After Which Time SDA Will Mfr_config_all_longer_pmbus_timeout = 1
Be Released and Command Terminated
TYP
MAX
98
ns
25
200
l
l
UNITS
35
280
ms
ms
Additional Digital Timing Characteristics
Minimum Off Time for Any Channel
tOFF_MIN
100
ms
resolution for 1LSB in this range is 2–2 mV = 250µV. Each successively
lower range improves resolution by cutting the LSB size in half.
Note 7: The time between successive ADC conversions (latency of the
ADC) for any given channel is given as: 36.9ms + (6.15ms • number of
ADC channels configured in Low Resolution mode) + (24.6ms • number of
ADC channels configured in High Resolution mode).
Note 8: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 9: Output enable pins are charge pumped from VDD33.
Note 10: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 11: EEPROM endurance and retention will be degraded when
TJ > 105°C.
Note 12: The LTC2979 will not acknowledge any PMBus commands
while a mass write operation is being executed. This includes the
STORE_USER_ALL and MFR_FAULT_LOG_STORE commands or a
fault log store initiated by a channel faulting off.
Note 13: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data
and clock rise time (tr) and fall time (tf) are:
(20 + 0.1 • CB) (ns) < tr < 300ns and (20 + 0.1 • CB) (ns) < tf < 300ns.
CB = capacitance of one bus line in pF. SCL and SDA external pull-up
voltage, VIO, is 3.13V < VIO < 5.5V.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating for extended periods may affect device reliability and
lifetime.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: The LTC2979 electrical characteristics apply to each half of the
device, unless otherwise noted. The specifications and functions are the
same for both Device A pins and Device B pins.
Note 4: The ADC total unadjusted error includes all error sources. First,
a two-point analog trim is performed to achieve a flat reference voltage
(VREF) over temperature. This results in minimal temperature coefficient,
but the absolute voltage can still vary. To compensate for this, a highresolution, drift-free, and noiseless digital trim is applied at the output of
the ADC, resulting in a very high accuracy measurement.
Note 5: Hysteresis in the output voltage is created by package stress that
differs depending on whether the module was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but the
module is cycled to 105°C or –40°C before successive measurements.
Hysteresis is roughly proportional to the square of the temperature
change.
Note 6: The current sense resolution is determined by the L11 format and
the mV units of the returned value. For example a full scale value of 170mV
returns a L11 value of 0xF2A8 = 680 • 2–2 = 170. This is the lowest range
that can represent this value without overflowing the L11 mantissa and the
PMBUS TIMING DIAGRAM
SDA
tf
tLOW
tr
tSU(DAT)
tHD(STA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
START
CONDITION
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
2979 TD
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
2979f
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7
LTC2979
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Sensor Error
vs Temperature
Reference Voltage vs Temperature
1.2325
ADC Total Unadjusted Error
vs Temperature
2.0
0.25
1.2320
1.5
0.20
1.2315
1.0
1.2310
0.5
1.2305
1.2300
VSENSEP0 = 1.8V
THREE TYPICAL PARTS
0.15
0.10
ERROR (%)
ERROR (°C)
REFERENCE OUTPUT VOLTAGE (V)
THREE TYPICAL PARTS
0
–0.5
0.05
0
–0.05
–0.10
1.2295
–1.0
1.2290
–1.5
–0.20
1.2285
–2.0
–0.25
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
–0.15
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
ADC Zero Code Center Offset
Voltage vs Temperature
VOLTAGE SENSE MODE
THREE TYPICAL PARTS
2.5
150
ERROR (LSBs)
100
OFFSET (µV)
50
0
–50
–100
ADC DNL
0.8
122µV/LSB
0.6
2.0
0.4
1.5
0.2
ERROR (LSBs)
200
ADC INL
3.0
1.0
0.5
–0.2
0
–0.4
–0.5
–0.6
–200
–1.0
–0.8
90
–1.5
–0.2
110
0.8
1.8
2.8
3.8
4.8
INPUT VOLTAGE (V)
2979 G04
600
400
200
8
–10
0
10
READ_VOUT (µV)
20
2979 G07
5.8
9
VSENSEP0 = 1.5V
0.8 HIGH RESOLUTION MODE
THREE TYPICAL PARTS
0.6
8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0
–20
1.8
2.8
3.8
4.8
INPUT VOLTAGE (V)
Input Sampling Current
vs Differential Input Voltage
1.0
VIN = 0V
HIGH RESOLUTION MODE
800
0.8
2979 G06
Voltage Supervisor Total
Unadjusted Error vs Temperature
SUPERVISOR ERROR (%)
NUMBER OF READINGS
1000
–1.0
–0.2
2979 G05
ADC Noise Histogram
1200
5.8
INPUT SAMPLING CURRENT (µA)
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
122µV/LSB
0
–150
–250
110
2979 G03
2979 G02
2979 G01
250
90
–1.0
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
2979 G08
7
6
5
4
3
2
1
0
0
1
2
3
4
INPUT VOLTAGE (V)
5
6
2979 G09
2979f
For more information www.linear.com/LTC2979
LTC2979
TYPICAL PERFORMANCE CHARACTERISTICS
2.68
80
2.67
70
60
50
40
30
20
10
GAIN SETTING = 1
THREE TYPICAL PARTS
8
DAC OUTPUT VOLTAGE (mV)
90
2.66
2.65
2.64
2.63
2.62
2.61
10
0
0
20 40 60 80 100 120 140 160 180
DIFFERENTIAL INPUT VOLTAGE (mV)
DAC Short-Circuit Current vs
Temperature
8
7
6
5
4
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
6
4
2
0
–2
–4
–6
90
110
2979 G11
–10
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
2979 G12
DAC Transient Response to 1LSB
DAC Code Change
DAC Output Impedance vs
Frequency
CODE ‘h200
OUTPUT IMPEDANCE (Ω)
SHORT-CIRCUIT CURRENT (mA)
9
1000
GAIN SETTING = 1
THREE TYPICAL PARTS
GAIN SETTING = 1
THREE TYPICAL PARTS
–8
2.60
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
2979 G10
10
DAC Offset Voltage vs
Temperature
DAC Full-Scale Output Voltage vs
Temperature
DAC OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT CURRENT (nA)
ADC High Resolution Mode
Differential Input Current
90
100
500µV/DIV
10
CODE ‘h1FF
1
2µs/DIV
0.1
0.01
0.01
110
0.1
10
1
FREQUENCY (kHz)
100
2979 G13
DAC Soft-Connect Transient
Response When Transitioning
from Hi-Z State to ON State
2979 G15
1000
2979 G14
DAC Soft-Connect Transient
Response When Transitioning
from ON State to Hi-Z State
HI-Z
HI-Z
10mV/DIV
10mV/DIV
CONNECTED
500µs/DIV
100k SERIES RESISTANCE ON
CODE: ‘h1FF
CONNECTED
2979 G16
500µs/DIV
100k SERIES RESISTANCE ON
CODE: ‘h1FF
2979 G17
2979f
For more information www.linear.com/LTC2979
9
LTC2979
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
(1/2 LTC2979)
9.6
VOUT_EN[3:0] and VIN_EN Output
VOL vs Current
1.4
THREE TYPICAL PARTS
1.2
9.4
105°C
9.3
9.2
9.1
0.8
–40°C
0.6
0.4
9.0
0.2
8.9
8.8
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
0
110
0
2979 G18
12
2979 G19
VDD33
105°C
0.5
0.8
VOUT_ENn VOLTAGE (V)
25°C
0.4
VOL (V)
8
6
10
4
CURRENT SINKING (mA)
1.0
0.6
0.3
–40°C
0.2
VOUT_EN[7:4]
VOUT_EN[3:0]
0.6
VOUT_ENn WITH 10k
PULL–UP TO VDD33
0.4
0.2
0.1
0
4
8
12
16
20
CURRENT SINKING (mA)
24
0
0
2979 G20
10
2
VOUT_EN[7:0] Output Voltage vs
VDD33
VOUT_EN[7:4] VOL vs Current
0
25°C
1.0
VOL (V)
SUPPLY CURRENT (mA)
9.5
0.5
1
1.5
VDD33 VOLTAGE (V)
2
2979 G21
2979f
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LTC2979
PIN FUNCTIONS
PIN NAME
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
VIN_EN
VIN_SNS
PIN
Device A Device B
G5
G11
H6
H12
E5
E11
D6
D12
A6
A12
A5
A11
B5
B11
C5
C11
B4
B10
A4
A10
C2
C8
B2
B8
E2
E8
F2
F8
A2
A8
A1
A7
B1
B7
C1
C7
D1
D7
J1
J7
H1
H7
E1
E7
M1
M7
L1
L7
K1
K7
G1
G7
PIN TYPE
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
VDD33
VDD33
VDD33
VDD25
WP
PWRGD
G2
H2
J2
K2
M2
L2
G8
H8
J8
K8
M8
L8
In
In
In
In/Out
In
Out
SHARE_CLK
K3
K9
In/Out
WDI/RESETB
L3
L9
In
FAULTB00
M3
M9
In/Out
FAULTB01
L4
L10
In/Out
FAULTB10
K4
K10
In/Out
FAULTB11
M4
M10
In/Out
SDA
M5
M11
In/Out
DESCRIPTION
DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-1 Sensing Pins
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-3 Sensing Pins
DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-4 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-5 Sensing Pins
DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-6 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Differential (–) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Enable-0 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-1 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-2 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-3 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-4 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-5 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-6 Pin. Open-Drain Pull-Down Output
DC/DC Converter Enable-7 Pin. Open-Drain Pull-Down Output
DC/DC Converter VIN ENABLE Pin. Open-Drain Pull-Down Output
VIN SENSE Input. This Voltage is Compared Against the VIN On and Off Voltage Thresholds in
Order to Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
3.13V to 3.47V Supply Input Pin. Short Pin G2 to H2 and J2 and Pin G8 to H8 and J8.
3.13V to 3.47V Supply Input Pin. Short Pin H2 to G2 and J2 and Pin H8 to G8 and J8.
Input for Internal 2.5V Sub-Regulator. Short Pin J2 to G2 and H2 and Pin J8 to G8 and H8.
2.5V Internally Regulated Voltage Output. Do not connect to VDD25 pins of any other devices
Digital Input. Write-Protect Input Pin, Active High
Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as
System Power-On Reset. The Latency of This Signal May Be as Long as the ADC Latency. See
Note 7
Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to VDD33. Connect to all other
SHARE_CLK pins in the system
Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to VDD33. Rising
Edge Resets Watchdog Counter. Holding This Pin Low for More Than tRESETB Resets the Chip
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-00. Connect a 10k
Pull-Up Resistor to VDD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-01. Connect a 10k
Pull-Up Resistor to VDD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-10. Connect a 10k
Pull-Up Resistor to VDD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 10k
Pull-Up Resistor to VDD33
PMBus Bidirectional Serial Data Pin
2979f
For more information www.linear.com/LTC2979
11
LTC2979
PIN FUNCTIONS
PIN
Device A Device B
PIN TYPE
DESCRIPTION
M6
M12
In
PMBus Serial Clock Input Pin (400kHz Maximum)
L5
L11
Out
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
L6
L12
In
Control Pin 0 Input
K6
K12
In
Control Pin 1 Input
K5
K11
In
Ternary Address Select Pin 0 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States
J6
J12
In
Ternary Address Select Pin 1 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States
J5
J11
Out
Reference Voltage Output
H5
H11
Out
Reference Return Pin
F6
F12
Out
DAC0 Output
G6
G12
Out
DAC0 Return. Connect to Channel 0 DC/DC Converter’s GND Sense or Return to GND
E6
E12
Out
DAC1 Output
F5
F11
Out
DAC1 Return. Connect to Channel 1 DC/DC Converter’s GND Sense or Return to GND
C6
C12
Out
DAC2 Output
B6
B12
Out
DAC2 Return. Connect to Channel 2 DC/DC Converter’s GND Sense or Return to GND
D5
D11
Out
DAC3 Output
C4
C10
Out
DAC3 Return. Connect to Channel 3 DC/DC Converter’s GND Sense or Return to GND
E4
E10
Out
DAC4 Output
D4
D10
Out
DAC4 Return. Connect to Channel 4 DC/DC Converter’s GND Sense or Return to GND
A3
A9
Out
DAC5 Output
B3
B9
Out
DAC5 Return. Connect to Channel 5 DC/DC Converter’s GND Sense or Return to GND
D3
D9
Out
DAC6 Output
C3
C9
Out
DAC6 Return. Connect to Channel 6 DC/DC Converter’s GND Sense or Return to GND
E3
E9
Out
DAC7 Output
D2
D8
Out
DAC7 Return. Connect to Channel 7 DC/DC Converter’s GND Sense or Return to GND
F3, F4, F9, F10,
Ground
Device A Ground Pins are Isolated from the Device B Ground Pins
G3, G4, G9, G10,
H3, H4, H9, H10,
J3, J4 J9, J10
DNC
F1
F7
Do Not Connect Do Not Connect to This Pin
*Any unused VSENSEPn or VSENSEMn or VDACMn pins must be tied to GND.
PIN NAME
SCL
ALERTB
CONTROL0
CONTROL1
ASEL0
ASEL1
REFP
REFM
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
GND
12
2979f
For more information www.linear.com/LTC2979
LTC2979
BLOCK DIAGRAM
G4
VDD25
DNC
REFP
GND
REFM
GND
GND
REFP
REFM
VDD25
VDD33
GND
GND
VDD33
G3
VIN_EN
VDD33
F3
F4
VDD33
VIN_SNS
F1
VIN_SNS
DNC
K1
VDD33
VIN_EN
G1
VDD33
GND
G2
GND
GND
G4
G5
H6
F6
G6
B1
E5
D6
E6
F5
C1
A6
A5
C6
B6
D1
B5
C5
D5
C4
J1
K5
J6
L6
K6
M3
L4
K4
M4
VSENSEP0
VSENSEM0
VDACP0
VDACM0
VOUT_EN0
VSENSEP1
VSENSEM1
VDACP1
VDACM1
VOUT_EN1
VSENSEP2
VSENSEM2
VDACP2
VDACM2
VOUT_EN2
VSENSEP3
VSENSEM3
VDACP3
VDACM3
VOUT_EN3
ASEL0
ASEL1
CONTROL0
CONTROL1
FAULTB00
FAULTB01
FAULTB10
FAULTB11
GND
VSENSEP0
VSENSEP7
VSENSEM0
VSENSEM7
VDACP0
VDACP7
VDACM0
VDACM7
VOUT_EN0
VOUT_EN7
VSENSEP1
VSENSEP6
VSENSEM1
VSENSEM6
VDACP1
VDACP6
VDACM1
VDACM6
VOUT_EN1
VOUT_EN6
VSENSEP2
VSENSEP5
VSENSEM2
VDACP2
VDACM2
VSENSEM5
1/2 LTC2979
Device A (LTC2977)
VDACP5
VDACM5
VOUT_EN2
VOUT_EN5
VSENSEP3
VSENSEP4
VSENSEM3
VSENSEM4
VDACP3
VDACM3
VOUT_EN3
ASEL0
ASEL1
CONTROL0
CONTROL1
FAULTB00
FAULTB01
FAULTB10
VDACP4
VDACM4
VOUT_EN4
SCL
SDA
ALERTB
WDI/RESETB
SHARE_CLK
WP
PWRGD
GND
VSENSEP7
VSENSEM7
VDACP7
VDACM7
VOUT_EN7
VSENSEP6
VSENSEM6
VDACP6
VDACM6
VOUT_EN6
VSENSEP5
VSENSEM5
VDACP5
VDACM5
VOUT_EN5
VSENSEP4
VSENSEM4
VDACP4
VDACM4
VOUT_EN4
SCL
SDA
ALERTB
WDI/RESETB
SHARE_CLK
WP
PWRGD
H2
J2
K2
J5
H5
H3
H4
J3
J4
A2
A1
E3
D2
L1
E2
F2
D3
C3
M1
C2
B2
A3
B3
E1
B4
A4
E4
D4
H1
M6
M5
L5
L3
K3
M2
L2
FAULTB11
2979 BD
2979f
For more information www.linear.com/LTC2979
13
LTC2979
BLOCK DIAGRAM
G10
VDD25
DNC
REFP
GND
REFM
GND
GND
REFP
REFM
VDD25
VDD33
GND
GND
VDD33
G9
VIN_EN
VDD33
F9
F10
VDD33
VIN_SNS
F7
VIN_SNS
DNC
K7
VDD33
VIN_EN
G7
VDD33
GND
G8
GND
GND
G11
G4
H12
F12
G12
B7
E11
D12
E12
F11
C7
A12
A11
C12
B12
D7
B11
C11
D11
C10
J7
K11
J12
L12
K12
M9
L10
K10
M10
VSENSEP0
VSENSEM0
VDACP0
VDACM0
VOUT_EN0
VSENSEP1
VSENSEM1
VDACP1
VDACM1
VOUT_EN1
VSENSEP2
VSENSEM2
VDACP2
VDACM2
VOUT_EN2
VSENSEP3
VSENSEM3
VDACP3
VDACM3
VOUT_EN3
ASEL0
ASEL1
CONTROL0
CONTROL1
FAULTB00
FAULTB01
FAULTB10
FAULTB11
GND
VSENSEP0
VSENSEP7
VSENSEM0
VSENSEM7
VDACP0
VDACP7
VDACM0
VDACM7
VOUT_EN0
VOUT_EN7
VSENSEP1
VSENSEP6
VSENSEM1
VSENSEM6
VDACP1
VDACP6
VDACM1
VDACM6
VOUT_EN1
VOUT_EN6
VSENSEP2
VSENSEP5
VSENSEM2
VDACP2
VDACM2
VSENSEM5
1/2 LTC2979
Device B (LTC2977)
VDACP5
VDACM5
VOUT_EN2
VOUT_EN5
VSENSEP3
VSENSEP4
VSENSEM3
VSENSEM4
VDACP3
VDACM3
VOUT_EN3
ASEL0
ASEL1
CONTROL0
CONTROL1
FAULTB00
FAULTB01
FAULTB10
VDACP4
VDACM4
VOUT_EN4
SCL
SDA
ALERTB
WDI/RESETB
SHARE_CLK
WP
PWRGD
GND
VSENSEP7
VSENSEM7
VDACP7
VDACM7
VOUT_EN7
VSENSEP6
VSENSEM6
VDACP6
VDACM6
VOUT_EN6
VSENSEP5
VSENSEM5
VDACP5
VDACM5
VOUT_EN5
VSENSEP4
VSENSEM4
VDACP4
VDACM4
VOUT_EN4
SCL
SDA
ALERTB
WDI/RESETB
SHARE_CLK
WP
PWRGD
H8
J8
K8
J11
H11
H9
H10
J9
J10
A8
A7
E9
D8
L7
E8
F8
D9
C9
M7
C8
B8
A9
B9
E7
B10
A10
E10
D10
H7
M12
M11
L11
L9
K9
M8
L8
FAULTB11
2979 BD
14
2979f
For more information www.linear.com/LTC2979
LTC2979
OPERATION
Overview
Device Address
The LTC2979 contains two independent LTC2977 devices.
Each half of the LTC2979 behaves the same as a standalone LTC2977, including independent power supply and
ground pins, with the following exceptions:
Since the LTC2979 consists of two independent LTC2977
devices, each half of the LTC2979 must be configured
for a unique address. The I2C/SMBus addresses of the
LTC2979 are configured in the same manner as for individual LTC2977 devices. The LTC2979 also responds
to the LTC2977 global address and the SMBus alert
response address, regardless of the state of the ASEL
pins and the MFR_I2C_BASE_ADDRESS register. Please
refer to the Device Address section in the LTC2977 data
sheet for more details.
n
The VPWR pin has been removed and replaced with an
additional VDD33 pin.
n
The LTC2979 can only be powered from 3.3V.
n
The VOUT_EN and VIN_EN pins are limited to 6V.
n
The ADC Total Unadjusted Error (TUE_ADC_VOLT_
SNS) is 0.5%.
Refer to the LTC2977 data sheet for a detailed description
of the device operation, the PMBus command set, and
applications information.
MFR_SPECIAL_ID
The LTC2979 contains unique MFR_SPECIAL_ID values to differentiate it from the LTC2977. Table 1 lists the
MFR_SPECIAL_ID values for the LTC2979.
Table 1. LTC2979 MFR_SPECIAL_ID Values
LTC2979 DEVICE
MFR_SPECIAL_ID
Device A
0x8061
Device B
0x8071
2979f
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15
LTC2979
APPLICATIONS INFORMATION
OVERVIEW
Unused ADC Sense Inputs
The LTC2979 is a digital power system manager that
is capable of sequencing, margining, trimming, supervising output voltage for OV/UV conditions, providing
fault management, and voltage readback for sixteen
DC/DC converters. Input voltage and LTC2979 junction
temperature readback are also available. Odd numbered
channels can be configured to read back current sense
resistor voltages. Multiple LTC2979s can be synchronized
to operate in unison using the SHARE_CLK, FAULTB and
CONTROL pins. The LTC2979 utilizes a PMBus compliant
interface and command set.
Connect all unused ADC sense inputs (VSENSEPn or
VSENSEMn) to GND. In a system where the inputs are connected to removable cards and may be left floating in
certain situations, connect the inputs to GND using 100k
resistors, as shown in Figure 3.
VSENSEP
100k
VSENSEM
100k
The LTC2979 is powered from a 3.13V to 3.47V supply
connected to the VDD33 pins. Tie all the VDD33 pins on each
half of the device together. See Figure 2. Separate 3.3V
supplies can be used for VDD33(A) and VDD33(B).
3.3V
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD25
VDD25
LTC2979*
DEVICE A
LTC2979*
DEVICE B
GND
GND
2979 F02
*SOME DETAILS
OMITTED FOR CLARITY
Figure 2. Powering LTC2979 from a 3.3V Supply
PCB ASSEMBLY AND LAYOUT SUGGESTIONS
Bypass Capacitor Placement
The LTC2979 requires 0.1µF bypass capacitors between
the VDD33 pins and GND, the VDD25 pins and GND, and
between the REFP and REFM pins. In order to be effective,
these capacitors should be made of high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible. The PCB layout should adhere to
good layout guidelines. A multilayer PCB that dedicates
a layer to power and ground is recommended. Low resistance and low inductance power and ground connections
are important to minimize power supply noise and ensure
proper device operation.
DESIGN CHECKLIST
I2C
APPLICATION CIRCUITS
n
VIN Sense
Voltages other than VIN can be monitored and supervised
using the VIN_SNS pins. Each VIN_SNS pin has a calibrated
internal divider allowing it to directly sense voltages up
to 15V.
16
2979 F03
Figure 3. Undedicated Pull-Up Resistors
POWERING THE LTC2979
3.3V
LTC2979
n
n
Each half of the LTC2979 must be configured for a
unique address. Unique hardware ASELn values are
recommended for simplest in-system programming.
The address select pins (ASELn) are tri-level; Check
Table 1 of the LTC2977 data sheet.
Check addresses for collision with other devices on the
bus and any global addresses.
2979f
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LTC2979
APPLICATIONS INFORMATION
Unused Inputs
Output Enables
n
n
Use appropriate pull-up resistors on all VOUT_ENn pins.
Verify that the absolute maximum ratings of the VOUT_
ENn pins are not exceeded.
VIN Sense
n
No external resistive divider is required to sense VIN
over the range of 0V to 15V; VIN_SNS already has an
internal calibrated divider.
Logic Signals
n
n
n
n
n
n
Verify the absolute maximum ratings of the digital pins
(SCL, SDA, ALERTB, FAULTBzn, CONTROLn, SHARE_
CLK, WDI/RESETB, ASELn, PWRGD) are not exceeded.
Connect all SHARE_CLK pins in the system together
and pull up to 3.3V with a 5.49k resistor.
Connect all unused VSENSEPn, VSENSEMn and DACMn
pins to GND. Do not float unused inputs. Refer
to Unused ADC Sense Inputs in the Applications
Information section of the LTC2977 data sheet.
DAC Outputs
n
Select appropriate resistor for desired margin range.
Refer to the resistor selection tool in LTpowerPlay for
assistance.
For a more complete list of design considerations and
a schematic checklist, see the Design Checklist on the
LTC2979 product page:
www.linear.com/LTC2979
Do not leave CONTROLn pins floating. Pull up to 3.3V
with a 10k resistor.
Tie WDI/RESETB to VDD33 with a 10k resistor. Do not
connect a capacitor to the WDI/RESETB pin.
Tie WP to either VDD33 or GND. Do not leave floating.
2979f
For more information www.linear.com/LTC2979
17
LTC2979
PACKAGE DESCRIPTION
LTC2979 Component BGA Pinout (Top View)
DEVICE A
1
2
DEVICE B
3
4
5
6
7
8
9
10
11
12
A
VSENSEM7
VSENSEP7
VDACP5
VSENSEM4
VSENSEM2
VSENSEP2
VSENSEM7
VSENSEP7
VDACP5
VSENSEM4
VSENSEM2
VSENSEP2
B
VOUT_EN0
VSENSEM5
VDACM5
VSENSEP4
VSENSEP3
VDACM2
VOUT_EN0
VSENSEM5
VDACM5
VSENSEP4
VSENSEP3
VDACM2
C
VOUT_EN1
VSENSEP5
VDACM6
VDACM3
VSENSEM3
VDACP2
VOUT_EN1
VSENSEP5
VDACM6
VDACM3
VSENSEM3
VDACP2
D
VOUT_EN2
VDACM7
VDACP6
VDACM4
VDACP3
VSENSEM1
VOUT_EN2
VDACM7
VDACP6
VDACM4
VDACP3
VSENSEM1
E
VOUT_EN5
VSENSEP6
VDACP7
VDACP4
VSENSEP1
VDACP1
VOUT_EN5
VSENSEP6
VDACP7
VDACP4
VSENSEP1
VDACP1
F
DNC
VSENSEM6
GND
GND
VDACM1
VDACP0
DNC
VSENSEM6
GND
GND
VDACM1
VDACP0
G
VIN_SNS
VDD33
GND
GND
VSENSEP0
VDACM0
VIN_SNS
VDD33
GND
GND
VSENSEP0
VDACM0
H
VOUT_EN4
VDD33
GND
GND
REFM
VSENSEM0
VOUT_EN4
VDD33
GND
GND
REFM
VSENSEM0
J
VOUT_EN3
VDD33
GND
GND
REFP
ASEL1
VOUT_EN3
VDD33
GND
GND
REFP
ASEL1
K
VIN_EN
VDD25
SHARE_CLK
FAULTB10
ASEL0
CONTROL1
VIN_EN
VDD25
SHARE_CLK
FAULTB10
ASEL0
CONTROL1
L
VOUT_EN7
PWRGD
WDI
FAULTB01
ALERTB
CONTROL0
VOUT_EN7
PWRGD
WDI
FAULTB01
ALERTB
CONTROL0
M
VOUT_EN6
WP
FAULTB00
FAULTB11
SDA
SCL
VOUT_EN6
WP
FAULTB00
FAULTB11
SDA
SCL
18
2979f
For more information www.linear.com/LTC2979
aaa Z
0.35 ±0.025 Ø 144x
2.500
2.500
SUGGESTED PCB LAYOUT
TOP VIEW
1.500
PACKAGE TOP VIEW
E
0.500
0.0000
0.500
4
1.500
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
For more
information
www.linear.com/LTC2979
subject to change without notice. No license
is granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
5.500
4.500
3.500
2.500
1.500
0.500
0.0000
0.500
1.500
2.500
3.500
4.500
5.500
Y
X
D
aaa Z
H2
DETAIL B
MOLD
CAP
4.500
3.500
3.500
4.500
5.500
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
NOM
1.29
0.32
0.97
0.60
0.50
12.00
12.00
1.00
11.00
11.00
0.27
0.70
MAX
1.34
0.37
1.02
0.70
0.53
DIMENSIONS
Z
BALL DIMENSION
PAD DIMENSION
BALL HT
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
A
SUBSTRATE THK
0.32
MOLD CAP HT
0.75
0.15
0.10
0.12
0.15
0.08
TOTAL NUMBER OF BALLS: 144
0.22
0.65
MIN
1.24
0.27
0.92
0.50
0.47
H1
SUBSTRATE
A1
(Y144AH)
ddd M Z X Y
eee M Z
DETAIL A
Øb (144 PLACES)
b1
ccc Z
Z
(Reference LTC DWG # 05-08-1967 Rev B)
// bbb Z
PIN “A1”
CORNER
5.500
BGA Package
144-Lead (12mm × 12mm × 1.29mm)
e
11
b
10
9
7
G
6
5
e
PACKAGE BOTTOM VIEW
8
4
3
2
DETAIL A
1
M
L
K
J
H
G
F
E
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTXXXXXX
BGA 144 1116 REV B
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu
OR Sn Pb EUTECTIC
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
PIN 1
7
SEE NOTES
3
SEE NOTES
2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
F
b
12
LTC2979
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2979#packaging for the most recent package drawings.
2979f
19
LTC2979
TYPICAL APPLICATION
12V
IN
OUT
INTERMEDIATE
BUS CONVERTER
3.3V
ASEL0
VIN_SNS
VDD33
ASEL1
VDD33
VDD33
WP
VDD25
REFP
GND
VIN_EN
DNC
REFM
ASEL0
VIN_SNS
VDD33
ASEL1
VDD33
VDD33
WP
VDD25
LOAD
3.3V
REGULATOR
VOUT
VDACP0
VSENSEP0
VIN
DC/DC
CONVERTER
VFB
LOAD
VSENSEM0
VSENSEM0
VDACM0
RUN/SS SGND
GND
48V
0.1µF 0.1µF
WDI/RESETB
VFB
0.1µF
0.1µF
0.1µF
GND
VSENSEP0
DNC
VDACP0
REFM
VOUT
DC/DC
CONVERTER
VIN_EN
VIN
0.1µF
WDI/RESETB
EN
REFP
48V
VDACM0
VOUT_EN0
SGND RUN/SS
GND
DC/DC
CONVERTER
VDACP1
VSENSEP1
VSENSEM1
VDACM1
VOUT_EN1
VOUT_EN0
VDACP1
VSENSEP1
VSENSEM1
VDACM1
VOUT_EN1
DC/DC
CONVERTER
VDACP2
VSENSEP2
VSENSEM2
VDACM2
VOUT_EN2
VDACP2
VSENSEP2
VSENSEM2
VDACM2
VOUT_EN2
DC/DC
CONVERTER
DC/DC
CONVERTER
VDACP3
VSENSEP3
VSENSEM3
VDACM3
VOUT_EN3
VDACP3
VSENSEP3
VSENSEM3
VDACM3
VOUT_EN3
DC/DC
CONVERTER
DC/DC
CONVERTER
VDACP4
VSENSEP4
VSENSEM4
VDACM4
VOUT_EN4
VDACP4
VSENSEP4
VSENSEM4
VDACM4
VOUT_EN4
DC/DC
CONVERTER
DC/DC
CONVERTER
VDACP5
VSENSEP5
VSENSEM5
VDACM5
VOUT_EN5
VDACP5
VSENSEP5
VSENSEM5
VDACM5
VOUT_EN5
DC/DC
CONVERTER
DC/DC
CONVERTER
VDACP6
VSENSEP6
VSENSEM6
VDACM6
VOUT_EN6
VDACP6
VSENSEP6
VSENSEM6
VDACM6
VOUT_EN6
DC/DC
CONVERTER
DC/DC
CONVERTER
VDACP7
VSENSEP7
VSENSEM7
VDACM7
VOUT_EN7
VDACP7
VSENSEP7
VSENSEM7
VDACM7
VOUT_EN7
DC/DC
CONVERTER
PWRGD
CONTROL1
CONTROL0
ALERTB
SCL
SDA
SHARE_CLK
FAULTB11
FAULTB10
FAULTB01
FAULTB00
PWRGD
CONTROL1
CONTROL0
LTC2979
DEVICE B
ALERTB
SCL
SDA
SHARE_CLK
FAULTB11
FAULTB10
FAULTB01
FAULTB00
LTC2979
DEVICE A
DC/DC
CONVERTER
2979 F04
10k
3.3V
3.3V
5.49k
10k
TO/FROM OTHER ADI POWER SYSTEM MANAGERS AND MICROCONTROLLER
Figure 4. LTC2979 16-Channel Application Circuit
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC2972
2-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision, Input Current and Power, Input Energy Accumulator
LTC2974
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision
LTC2975
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision, Input Current and Power, Input Energy Accumulator
LTC2977
8-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
LTC2980
16-Channel PMBus Power System Manager
Dual LTC2977
LTM®2987
16-Channel µModule PMBus Power System Manager
Dual LTC2977 with Integrated Passive Components
20
2979f
LT 0218 • PRINTED IN USA
For more information www.linear.com/LTC2979
www.linear.com/LTC2979
 ANALOG DEVICES, INC. 2018