Cypress CY62177EV18LL-70BAXI 32-mbit (2 m ã 16 / 4 m ã 8) static ram Datasheet

CY62177EV18 MoBL®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
Functional Description
■
Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M × 8 static RAM (SRAM)
■
Very high speed
❐ 70 ns
■
Wide voltage range
❐ 1.65 V to 2.25 V
■
Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■
Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
The CY62177EV18 is a high-performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications, such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-ball TSOP I and 48-ball FBGA package
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
For a complete list of related documentation, click here.
Logic Block Diagram
2M × 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number: 001-76091 Rev. *C
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised November 28, 2014
CY62177EV18 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-76091 Rev. *C
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62177EV18 MoBL®
Pin Configuration
Figure 1. 48-pin TSOP I pinout (Front View) [1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Figure 2. 48-ball FBGA pinout (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 NC
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
A20
H
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62177EV18LL
Speed
(ns)
Operating ICC (mA)
f = 1 MHz
Min
Typ[3]
Max
1.65
1.8
2.25
70
Standby ISB2 (A)
f = fMax
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
4.5
5.5
35
45
3
25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 4 M × 8
SRAM by tying the BYTE signal to VSS. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-76091 Rev. *C
Page 3 of 17
CY62177EV18 MoBL®
DC input voltage [4, 5] .................... –0.2 V to VCC(max) + 0.2 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage to ground
potential ....................................... –0.2 V to VCC(max) + 0.2 V
DC voltage applied to outputs
in High Z state [4, 5] ....................... –0.2 V to VCC(max) + 0.2 V
Device
Range
Ambient
Temperature
VCC[6]
CY62177EV18LL Industrial –40 °C to +85 °C 1.65 V to 2.25 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
70 ns
Min
Typ [7]
Max
Unit
VOH
Output HIGH voltage
IOH = –0.1 mA
VCC = 1.65 V
1.4
–
–
V
VOL
Output LOW voltage
IOL = 0.1 mA
VCC = 1.65 V
–
–
0.2
V
VIH
Input HIGH voltage
VCC = 1.65 V to 2.25 V
1.4
–
VCC + 0.2 V
V
VIL[8]
Input LOW voltage
VCC = 1.65 V to 2.25 V
–0.2
–
0.4
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fMax = 1/tRC
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–
35
45
mA
–
4.5
5.5
mA
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
–
3
25
A
f = 1 MHz
ISB2 [9, 10]
Automatic CE power down
current – CMOS inputs
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0,
VCC = VCC(max)
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M × 16 SRAM. The 48-TSOP I package can also be used as a 4 M × 8 SRAM
by tying the BYTE signal to VSS. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-76091 Rev. *C
Page 4 of 17
CY62177EV18 MoBL®
Capacitance
Parameter [11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
15
pF
15
pF
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
FBGA
TSOPI
Unit
Still air, soldered on a 3 × 4.5 inch, 2-layer
printed circuit board
38.10
44.66
C/W
7.54
12.12
C/W
AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC
90%
90%
10%
10%
GND
Fall Time = 1 V/ns
R2
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Table 1. AC Test Loads
Parameters
Value
Unit
R1
13500

R2
10800

RTH
6000

VTH
0.80
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-76091 Rev. *C
Page 5 of 17
CY62177EV18 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR [13]
Data retention current
Conditions
VCC = 1.0 V,
Min
Typ [12]
Max
Unit
1.0
–
–
V
–
–
17
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V, or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR[14]
Chip deselect to data retention
time
0
–
–
ns
tR[15]
Operation recovery time
70
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform [16]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-76091 Rev. *C
Page 6 of 17
CY62177EV18 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [17, 18]
Description
70 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
70
–
ns
tAA
Address to data valid
–
70
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
70
ns
tDOE
OE LOW to data valid
–
35
ns
[19]
5
–
ns
–
25
ns
tLZOE
tHZOE
OE LOW to LOW Z
OE HIGH to High
Z[19, 20]
Z[19]
tLZCE
CE1 LOW and CE2 HIGH to Low
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z[19, 20]
–
25
ns
tPU
CE1 LOW and CE2 HIGH to power up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power down
–
70
ns
tDBE
BLE/BHE LOW to data valid
–
70
ns
tLZBE
BLE/BHE LOW to Low Z [19]
10
–
ns
–
25
ns
tHZBE
Write Cycle
BLE/BHE HIGH to HIGH Z
[19, 20]
[21, 22]
tWC
Write cycle time
70
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
60
–
ns
tAW
Address setup to write end
60
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
45
–
ns
tBW
BLE/BHE LOW to write end
60
–
ns
tSD
Data setup to write end
30
–
ns
tHD
Data hold from Write End
0
–
ns
tHZWE
WE LOW to High Z[19, 20]
–
25
ns
10
–
ns
tLZWE
[19]
WE HIGH to Low Z
Notes
17. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in Table 1 on page 5.
18. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
19. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-76091 Rev. *C
Page 7 of 17
CY62177EV18 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [23, 24]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle 2 (OE Controlled) [24, 25]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
Notes
23. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
24. WE is HIGH for read cycle.
25. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-76091 Rev. *C
Page 8 of 17
CY62177EV18 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle 1 (WE Controlled) [26, 27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 29
tHZOE
Figure 8. Write Cycle 2 (CE1 or CE2 Controlled) [26, 27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 29
tHZOE
Notes
26. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
29. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-76091 Rev. *C
Page 9 of 17
CY62177EV18 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle 3 (WE Controlled, OE LOW) [30, 31, 32]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 31
tHD
VALID DATA
tLZWE
tHZWE
Figure 10. Write Cycle 4 (BHE/BLE Controlled, OE LOW) [30, 32]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 31
tHD
VALID DATA
Notes
30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
31. During this period the I/Os are in output state and input signals should not be applied.
32. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 001-76091 Rev. *C
Page 10 of 17
CY62177EV18 MoBL®
Truth Table
CE1
H
CE2
WE
OE
BHE
BLE
[33]
X
X
X
X
X
X[33]
Inputs Outputs
Mode
Power
High Z
Deselect/Power Down
Standby (ISB)
L
X
X
X
X
High Z
Deselect/Power Down
Standby (ISB)
[33]
X
X
H
H
High Z
Deselect/Power Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
[33]
X
X
Note
33. The ‘X’ (Don’t care) state for the chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-76091 Rev. *C
Page 11 of 17
CY62177EV18 MoBL®
Ordering Information
Speed
(ns)
70
Ordering Code
CY62177EV18LL-70BAXI
Package
Diagram
51-85191
Package Type
48 ball FBGA (8 × 9.5 × 1.2 mm) Pb-free
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 7 7 E V18 LL - 70 Z,BA X I
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Z = 48TSOP I, BA = 48 ball FBGA
Speed Grade: 70 ns
Low Power
Voltage Range: V18 = 1.8 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-76091 Rev. *C
Page 12 of 17
CY62177EV18 MoBL®
Package Diagrams
Figure 11. 48-ball FBGA (8 × 9.5 × 1.2 mm) Package Outline, 51-85191
51-85191 *C
Document Number: 001-76091 Rev. *C
Page 13 of 17
CY62177EV18 MoBL®
Package Diagrams (continued)
Figure 12. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Package Outline, 51-85183
51-85183 *C
Document Number: 001-76091 Rev. *C
Page 14 of 17
CY62177EV18 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ms
millisecond
ns
nanosecond
SRAM
Static Random Access Memory
TSOP
Thin Small Outline Package
WE
Write Enable
Document Number: 001-76091 Rev. *C
Symbol
Unit of Measure

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 15 of 17
CY62177EV18 MoBL®
Document History Page
Document Title: CY62177EV18 MoBL®, 32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Document Number: 001-76091
Revision
ECN
Orig. of
Change
Submission
Date
**
3528465
AJU
02/17/2012
New data sheet.
*A
4116295
MEMJ
09/10/2013
Changed status from Preliminary to Final.
Updated Features:
Added 48-ball FBGA package related information.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85191 – Changed revision from *B to *C.
Updated in new template.
*B
4301112
NILE
03/07/2014
Updated Switching Characteristics:
Added Note 18 and referred the same note in “Parameter” column.
Completing Sunset Review.
*C
4571881
NILE
11/28/2014
Added related documentation hyperlink in page 1.
Added Note 22 in Switching Characteristics.
Added note reference 22 in the Switching Characteristics table.
Added Note 32 in Switching Waveforms.
Added note reference 32 in Figure 9.
Document Number: 001-76091 Rev. *C
Description of Change
Page 16 of 17
CY62177EV18 MoBL®
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2012-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-76091 Rev. *C
Revised November 28, 2014
Page 17 of 17
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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