Micron MT5VDDT3272AG Ddr sdram udimm Datasheet

64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
DDR SDRAM UDIMM
MT5VDDT872A – 64MB1
MT5VDDT1672A – 128MB2
MT5VDDT3272A – 256MB2
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
Figure 1:
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes:
64MB = 15.625µs and 128MB, 256MB = 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Table 1:
184-Pin UDIMM (MO-206 R/C C)
PCB height: 31.75mm (1.25in)
Options
Marking
• Operating temperature3
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)
• Package
– 184-pin DIMM (standard)
– 184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
– 5.0ns (200 MHz), 400 MT/s, CL = 3.0
– 6.0ns (167 MHz), 333 MT/s, CL = 2.5
– 7.5ns (133 MHz), 266 MT/s, CL = 2.0
– 7.5ns (133 MHz), 266 MT/s, CL = 2.0
– 7.5ns (133 MHz), 266 MT/s, CL = 2.5
None
I
G
Y
-40B
-335
-262
-26A
-265
Notes: 1. End of life.
2. Not recommended for new designs.
3. Contact Micron for industrial temperature
module offerings.
Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
CL = 3
CL = 2.5
CL = 2
(ns)
tRP
(ns)
tRC
(ns)
-40B
-335
-262
-26A
-265
PC3200
PC2700
PC2100
PC2100
PC2100
400
–
–
–
–
333
333
266
266
266
266
266
266
266
200
15
18
15
20
20
15
18
15
20
20
55
60
60
65
65
Notes:
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
tRCD
Notes
1
1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
Table 2:
Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Table 3:
64MB
128MB
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
Part Numbers and Timing Parameters – 64MB Modules
Base device: MT46V8M16,1 128Mb DDR SDRAM
Part Number2
MT5VDDT872AG-335__
MT5VDDT872AG-262__
MT5VDDT872AG-26A__
MT5VDDT872AG-265__
Table 4:
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
64MB
64MB
64MB
64MB
8 Meg x 72
8 Meg x 72
8 Meg x 72
8 Meg x 72
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
2.5-3-3
2-2-2
2-3-3
2.5-3-3
Part Numbers and Timing Parameters – 128MB Modules
Base device: MT46V16M16,1 256Mb DDR SDRAM
Part Number2
MT5VDDT1672AG-40B__
MT5VDDT1672AG-335__
MT5VDDT1672AY-335__
MT5VDDT1672AG-262__
MT5VDDT1672AG-26A__
MT5VDDT1672AG-265__
Table 5:
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
128MB
128MB
128MB
128MB
128MB
128MB
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
3-3-3
2.5-3-3
2.5-3-3
2-2-2
2-3-3
2.5-3-3
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT46V32M16,1 512Mb DDR SDRAM
Part Number2
MT5VDDT3272AG-40B__
MT5VDDT3272AY-40B__
MT5VDDT3272AG-335__
MT5VDDT3272AY-335__
MT5VDDT3272AG-265__
Notes:
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
256MB
256MB
256MB
256MB
256MB
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
3-3-3
3-3-3
2.5-3-3
2.5-3-3
2.5-3-3
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672AY-335F3.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6:
Pin Assignments
184-Pin DDR UDIMM Front
184-Pin DDR UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
VREF
DQ0
24
25
DQ17
DQS2
47
48
DQS8
A0
70
71
VDD
NC
93
94
VSS
DQ4
116
117
VSS
DQ21
139
140
3
4
VSS
DQ1
26
27
VSS
A9
49
50
CB2
VSS
72
73
DQ48
DQ49
95
96
DQ5
VDDQ
118
119
5
DQS0
28
DQ18
51
CB3
74
VSS
97
120
6
7
8
DQ2
VDD
DQ3
29
30
31
A7
VDDQ
DQ19
52
53
54
BA1
DQ32
VDDQ
75
76
77
CK2#
CK2
VDDQ
98
99
100
DM0/
DQS9
DQ6
DQ7
VSS
A11
DM2/
DQS11
VDD
121
122
123
9
10
11
NC
NC
VSS
32
33
34
A5
DQ24
VSS
55
56
57
DQ33
DQS4
DQ34
78
79
80
DQS6
DQ50
DQ51
101
102
103
NC
NC
NC
12
13
14
DQ8
DQ9
DQS1
35
36
37
DQ25
DQS3
A4
58
59
60
VSS
BA0
DQ35
81
82
83
VSS
NC
DQ56
104
105
106
15
VDDQ
38
VDD
61
DQ40
84
DQ57
107
16
CK1
39
DQ26
62
VDDQ
85
VDD
17
18
19
20
21
CK1#
VSS
DQ10
DQ11
CKE0
40
41
42
43
44
DQ27
A2
VSS
A1
CB0
63
64
65
66
67
WE#
DQ41
CAS#
VSS
DQS5
86
87
88
89
90
22
23
VDDQ
DQ16
45
46
CB1
VDD
68
69
DQ42
DQ43
91
92
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
162
163
DQ47
NC
141
142
VSS
DM8/
DQS17
A10
CB6
164
165
VDDQ
DQ52
143
VDDQ
166
DQ53
DQ22
A8
DQ23
144
145
146
CB7
VSS
DQ36
167
168
169
124
125
126
VSS
A6
DQ28
147
148
149
170
171
172
VDDQ
DQ12
DQ13
127
128
129
150
151
152
173
174
175
NC
DQ60
DQ61
130
153
DQ44
176
VSS
108
DM1/
DQS10
VDD
DQ29
VDDQ
DM3/
DQS12
A3
DQ37
VDD
DM4/
DQS13
DQ38
DQ39
VSS
NC
VDD
DM6/
DQS15
DQ54
DQ55
VDDQ
131
DQ30
154
RAS#
177
DQS7
DQ58
DQ59
VSS
NC
109
110
111
112
113
DQ14
DQ15
NC
VDDQ
NC
132
133
134
135
136
VSS
DQ31
CB4
CB5
VDDQ
155
156
157
158
159
178
179
180
181
182
SDA
SCL
114
115
DQ20
A12
137
138
CK0
CK0#
160
161
DQ45
VDDQ
S0#
NC
DM5/
DQS14
VSS
DQ46
DM7/
DQS16
DQ62
DQ63
VDDQ
SA0
SA1
183
184
SA2
VDDSPD
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Table 7:
Pin Descriptions
Symbol
Type
Description
A0–A12
Input
BA0, BA1
Input
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
Input
CKE1
Input
DM0–DM8
(DQS9–DQS17)
Input
RAS#, CAS#, WE#
Input
S0#
Input
SA0–SA2
Input
SCL
Input
CB0–CB7
DQ0–DQ63
DQS0–DQS7
I/O
I/O
I/O
SDA
I/O
VDD/VDDQ
VDDSPD
VREF
VSS
NC
Supply
Supply
Supply
Supply
–
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command. A0–A11 (64MB) and A0–A12 (128MB, 256MB).
Bank address: BA0 and BA1 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK
and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates the internal clock, input buffers, and output drivers.
Data input mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-only,
the DM loading is designed to match that of DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Chip selects: S# (registered LOW) enables and (registered HIGH) disables the
command decoder.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data, input with write data. DQS is edgealigned with read data, center-aligned with write data. Used to capture data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
Serial EEPROM positive power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (VDD/2).
Ground.
No connect: These pins are not connected on the module.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
S0#
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2
DM2/DQS11
DQS3
DM3/DQS12
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BA0–BA1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS4
DM4/DQS13
U1
DQS5
DM5/DQS14
S0#
DQS6
DM6/DQS15
U2
DQS7
DM7/DQS16
S0#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U4
VSS
VDD
NC
NC
NC
NC
NC
NC
NC
NC
U3
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
U6
DDR SDRAM
A0–A11/A12 DDR SDRAM
RAS#
DDR SDRAM
CAS#
WE#
CKE0
CK0
CK0#
CK1
CK1#
CK2
CK2#
DDR SDRAM
VSS SA0 SA1 SA2
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
S0#
S0#
SPD EEPROM
WP A0 A1 A2
A0–A11/A12
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS8
DM8/DQS17
SCL
DDR SDRAM
DDR SDRAM
DDR SDRAM U3
DDR SDRAM U1, U2
DDR SDRAM U4, U5
5
SDA
VDDSPD
SPD EEPROM
VDD/VDDQ
DDR SDRAM
VREF
DDR SDRAM
VSS
DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
General Description
General Description
The MT5VDDT872A, MT5VDDT1672A, and MT5VDDT3272A are high-speed CMOS,
dynamic random access 64MB, 128MB, and 256MB memory modules organized in a x72
configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 8 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions outside those indicated on the device data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect reliability.
Table 8:
Symbol
VDD/VDDQ
VIN, VOUT
II
IOZ
TA
Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD/VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
Address inputs,
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA,
test = 0V)
S#, CKE
CK0, CK0#
CK1, CK1#, CK2, CK2#
DM
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are DQ, DQS
disabled
DRAM ambient operating temperature1
Commercial
Industrial
–1.0
–0.5
–10
+3.6
+3.2
+10
V
V
µA
–2
–4
–2
–5
+2
+4
+2
+5
µA
0
–40
+70
+85
°C
°C
Notes:
1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 9.
Table 9:
Module and Component Speed Grades
Module Speed Grade
Component Speed Grade
-40B
-335
-262
-26A
-265
-5B
-6
-75E
-75Z
-75
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
IDD Specifications
Table 10:
IDD Specifications and Conditions – 64MB
Values are shown for the MT46V8M16 DDR SDRAM only and are computed from values specified in the
128Mb (8 Meg x 16) component data sheet
Parameter/Condition
t
t
Operating one bank active-precharge current: RC = RC (MIN);
t
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS, and DM
Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
tREFC = tRFC (MIN)
Auto refresh current
tREFC = 15.625µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during active READ or WRITE commands
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
8
Symbol
-335
-262
-26A/
-265
Units
IDD0
625
575
550
mA
IDD1
675
675
625
mA
IDD2P
15
15
15
mA
IDD2F
225
225
200
mA
IDD3P
125
125
100
mA
IDD3N
250
250
225
mA
IDD4R
725
700
675
mA
IDD4W
775
675
650
mA
IDD5
IDD5A
IDD6
IDD7
1,325
25
15
1,925
1,250
25
15
1,875
1,250
25
10
1,875
mA
mA
mA
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 11:
IDD Specifications and Conditions – 128MB
Values are shown for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
Parameter/Condition
Symbol
t
t
IDD0
Operating one bank active-precharge current: RC = RC (MIN);
t
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
IDD1
Operating one bank active-read-precharge current: BL = 2;
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
IDD2P
Precharge power-down standby current: All device banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD2F
Idle standby current: CS# = HIGH; All device banks idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ, DQS, and DM
IDD3P
Active power-down standby current: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3N
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD4R
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One IDD4W
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle
tREFC = tRFC (MIN)
IDD5
Auto refresh current
tREFC = 7.8125µs
IDD5A
IDD6
Self refresh current: CKE ≤ 0.2V
IDD7
Operating bank interleave read current: Four device bank
interleaving reads; BL = 4 with auto precharge; tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only during active
READ or WRITE commands
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
9
-40B
-335
-262
-26A/
-265
Units
675
625
625
600
mA
925
900
850
775
mA
20
20
20
20
mA
300
250
225
225
mA
200
150
125
125
mA
350
300
250
250
mA
1,300
1,100
925
925
mA
1,075
975
800
800
mA
1,300
30
20
2,550
1,275
30
20
2,200
1,175
30
20
1,900
1,175
30
20
1,900
mA
mA
mA
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 12:
IDD Specifications and Conditions – 256MB
Values are shown for the MT46V32M16 DDR SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
Parameter/Condition
t
t
Operating one bank active-precharge current: RC = RC (MIN);
CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock
cycle; VIN = VREF for DQ, DQS, and DM
Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
tREFC = tRFC (MIN)
Auto refresh current
tREFC = 7.8125µs
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during active READ or WRITE
commands
Symbol
-40B
-335
-265
Units
IDD0
775
650
575
mA
IDD1
975
800
725
mA
IDD2P
25
25
25
mA
IDD2F
275
225
200
mA
IDD3P
225
175
150
mA
IDD3N
300
250
225
mA
IDD4R
1,050
825
725
mA
IDD4W
1,075
975
675
mA
IDD5
IDD5A
IDD6
IDD7
1,725
55
30
2,400
1,450
50
25
2,025
1,400
50
25
1,750
mA
mA
mA
mA
t
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Serial Presence-Detect
Serial Presence-Detect
Table 13:
Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
2.3
VDDSPD × 0.7
–1.0
–
–
–
–
–
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
10
10
30
2.0
V
V
V
V
µA
µA
µA
mA
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 kHz
Table 14:
Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Notes:
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
–
0
0.6
0.6
–
1.3
–
–
100
0.6
0.6
–
0.9
–
–
300
–
–
–
50
–
0.3
400
–
–
–
10
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
kHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
t
WRC
2
2
3
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Module Dimensions
Module Dimensions
Figure 3:
184-Pin DDR UDIMM
3.18 (0.125)
MAX
Front view
133.50 (5.256)
133.20 (5.244)
2.0 (0.079) R
(4X)
U1
U3
U2
U4
U5
31.90 (1.256)
31.60 (1.244)
U6
17.78 (0.70)
TYP
2.5 (0.098) D
(2X)
2.31 (0.091) TYP
0.9 (0.035) R
Pin 1
2.21 (0.087) TYP
1.27 (0.05)
TYP
64.77 (2.55)
TYP
1.0 (0.039) TYP
1.02 (0.04)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 92
6.35 (0.25) TYP
49.53 (1.95)
TYP
120.65 (4.75)
Back view
No components this side of module
3.8 (0.15) TYP
Pin 184
10.0 (0.394)
TYP
Pin 93
73.28 (2.88)
TYP
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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