CYSTEKEC MTE130N20F3 N-channel enhancement mode power mosfet Datasheet

CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 1/ 9
N-Channel Enhancement Mode Power MOSFET
MTE130N20F3
BVDSS
ID @ VGS=10V, TC=25°C
RDS(ON)@VGS=10V, ID=9A
200V
18A
139 mΩ(typ)
Features
• Simple Drive Requirement
• Low Gate Charge
• Fast Switching Characteristic
• RoHS compliant package
Symbol
Outline
TO-263
MTE130N20F3
G
D
S
G:Gate D:Drain S:Source
Ordering Information
Device
MTE130N20F3-0-T7-X
Package
Shipping
TO-263
800 pcs / Tape & Reel
(Pb-free lead plating and RoHS compliant package)
Environment friendly grade : S for RoHS compliant products, G for RoHS compliant
and green compound products
Packing spec, T7 : 800 pcs / tape & reel, 13” reel
Product rank, zero for no rank products
Product name
MTE130N20F3
CYStek Product Specification
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 2/ 9
CYStech Electronics Corp.
Absolute Maximum Ratings (TC=25°C)
Parameter
Drain-Source Voltage (Note 1)
Gate-Source Voltage
Continuous Drain Current @TC=25°C, VGS=10V
(Note 1)
Continuous Drain Current @TC=100°C, VGS=10V
(Note 1)
Continuous Drain Current @TA=25°C, VGS=10V
(Note 2)
Continuous Drain Current @TA=70°C, VGS=10V
(Note 2)
Pulsed Drain Current @ VGS=10V
(Note 3)
Avalanche Current@ L=0.1mH
(Note 3)
Single Pulse Avalanche Energy @ L=1mH, ID=8 Amps, VDD=50V
(Note 4)
TC=25°C
(Note 1)
TC=100°C
(Note 1)
Power Dissipation
TA=25°C
(Note 2)
TA=70°C
(Note 2)
Maximum Temperature for Soldering @ Lead at 0.063 in(1.6mm)
from case for 10 seconds
Maximum Temperature for Soldering @ Package Body for 10
seconds
Operating Junction and Storage Temperature
Symbol
Limits
VDS
VGS
IDM
IAS
200
±20
18*
12.7*
3.1
2.5
36*
8
EAS
32
mJ
71
35.5
2
1.3
W
ID
IDSM
PD
PDSM
TL
300
TPKG
260
Tj, Tstg
-55~+175
Unit
V
A
°C
*Drain current limited by maximum junction temperature
Thermal Data
Parameter
Thermal Resistance, Junction-to-case, max
Thermal Resistance, Junction-to-ambient, max
(Note 2)
Symbol
RθJC
RθJA
Value
2.1
62.5
Unit
°C/W
Note : 1.The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful
in setting the upper dissipation limit for cases where additional heatsinking is used.
2. The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air
environment with TA=25°C. The power dissipation PDSM is based on RθJA and the maximum allowed junction
temperature of 150°C. The value in any given application depends on the user’s specific board design, and the
maximum temperature of 175°C may be used if the PCB allows it.
3. Pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and low duty cycles
to keep initial TJ=25°C.
4.100% tested by conditions of L=0.1mH, VGS=10V, IAS=2A, VDD=50V
MTE130N20F3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 3/ 9
Characteristics (Tj=25°C, unless otherwise specified)
Symbol
Static
BVDSS
∆BVDSS/∆Tj
VGS(th)
*GFS
IGSS
IDSS
Min.
Typ.
Max.
Unit
Test Conditions
200
2.0
-
0.2
10.5
139
4.0
±100
1
10
180
V
V/°C
V
S
nA
mΩ
VGS=0V, ID=250μA
Reference to 25°C, ID=250μA
VDS = VGS, ID=250μA
VDS =10V, ID=9A
VGS=±20V
VDS =180V, VGS =0V
VDS =180V, VGS =0V, Tj=125°C
VGS =10V, ID=9A
17.9
4.4
7.2
13.4
25.2
25.8
35.8
676
42
19
4.4
-
nC
VDS=160V, ID=11A, VGS=10V
ns
VDS=100V, ID=11A, VGS=10V,
RG=2.5Ω
pF
VGS=0V, VDS=100V, f=1MHz
Ω
VDS=0V, f=1MHz
0.87
75
226
18
36
1.5
-
*RDS(ON)
Dynamic
*Qg
*Qgs
*Qgd
*td(ON)
*tr
*td(OFF)
*tf
Ciss
Coss
Crss
Rg
Source-Drain Diode
*IS
*ISM
*VSD
*trr
*Qrr
-
μA
A
V
ns
nC
IS=18A, VGS=0V
VGS=0V, IF=11A, dIF/dt=100A/μs
*Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%
MTE130N20F3
CYStek Product Specification
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 4/ 9
CYStech Electronics Corp.
Typical Characteristics
Brekdown Voltage vs Ambient Temperature
Typical Output Characteristics
1.4
35
ID, Drain Current (A)
30
BVDSS, Normalized Drain-Source
Breakdown Voltage
10V,9V,8V,7V
25
20
6V
15
5.5V
10
5
VGS=4V
5V
1.2
1
0.8
ID=250μA,
VGS=0V
0.6
0.4
0
0
3
6
9
12
VDS, Drain-Source Voltage(V)
-75 -50 -25
15
Reverse Drain Current vs Source-Drain Voltage
Static Drain-Source On-State resistance vs Drain Current
1.2
VSD, Source-Drain Voltage(V)
R DS(on), Static Drain-Source On-State
Resistance(mΩ)
1000
100
VGS=6V
VGS=10V
VGS=0V
1
Tj=25°C
0.8
0.6
Tj=150°C
0.4
0.2
10
0.01
0.1
1
10
ID, Drain Current(A)
0
100
2
4
6
8
IDR , Reverse Drain Current(A)
10
Drain-Source On-State Resistance vs Junction Tempearture
Static Drain-Source On-State Resistance vs Gate-Source
Voltage
1000
2.8
ID=9A
R DS(on), Normalized Static DrainSource On-State Resistance
900
R DS(on), Static Drain-Source OnState Resistance(mΩ)
0 25 50 75 100 125 150 175 200
Tj, Junction Temperature(°C)
800
700
600
500
400
300
200
100
2.4
VGS=10V, ID=9A
2
1.6
1.2
0.8
RDS(ON) @Tj=25°C : 139mΩtyp.
0.4
0
0
0
MTE130N20F3
2
4
6
8
VGS, Gate-Source Voltage(V)
10
-75 -50 -25
0 25 50 75 100 125 150 175 200
Tj, Junction Temperature(°C)
CYStek Product Specification
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 5/ 9
CYStech Electronics Corp.
Typical Characteristics(Cont.)
Threshold Voltage vs Junction Tempearture
Capacitance vs Drain-to-Source Voltage
VGS(th), Normalized Threshold Voltage
Capacitance---(pF)
10000
Ciss
1000
100
C oss
Crss
1.4
1.2
ID=1mA
1
0.8
0.6
ID=250μA
0.4
0.2
10
0
20
40
60
80
VDS, Drain-Source Voltage(V)
-75 -50 -25
100
Forward Transfer Admittance vs Drain Current
Gate Charge Characteristics
10
VDS=100V
VDS=10V
VGS, Gate-Source Voltage(V)
GFS , Forward Transfer Admittance(S)
100
10
1
VDS=15V
0.1
Ta=25°C
Pulsed
0.01
0.001
8
VDS=40V
6
VDS=160V
4
2
ID=11A
0
0.01
0.1
1
ID, Drain Current(A)
10
0
100
4
8
12
16
Qg, Total Gate Charge(nC)
20
24
Maximum Drain Current vs Case Temperature
Maximum Safe Operating Area
25
10μs
RDSON
Limited
10
100μs
1ms
10ms
1
100ms
DC
TC=25°C, Tj=175°C
VGS=10V, RθJC=2.1°C/W
Single Pulse
0.1
ID, Maximum Drain Current(A)
100
ID, Drain Current(A)
0 25 50 75 100 125 150 175 200
Tj, Junction Temperature(°C)
20
15
10
5
VGS=10V, RθJC=2.1°C/W
0
0.01
0.1
MTE130N20F3
1
10
100
VDS, Drain-Source Voltage(V)
1000
25
50
75
100
125
TC , Case Temperature(°C)
150
175
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 6/ 9
Typical Characteristics(Cont.)
Single Pulse Power Rating, Junction to Case
Typical Transfer Characteristics
2000
35
TJ(MAX) =175°C
TC=25°C
RθJC=2.1°C/W
1600
1400
25
Power (W)
ID, Drain Current(A)
1800
VDS=10V
30
20
15
1200
1000
800
600
10
400
5
200
0
0
2
4
6
8
VGS, Gate-Source Voltage(V)
10
0
0.0001
0.001
0.01
0.1
Pulse Width(s)
1
10
Transient Thermal Response Curves
1
r(t), Normalized Effective Transient
Thermal Resistance
D=0.5
0.2
1.RθJC(t)=r(t)*RθJC
2.Duty Factor, D=t1/t2
3.TJM-TC=PDM*Rθ JC(t)
4.RθJC=2.1°C/W
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
1.E-04
MTE130N20F3
1.E-03
1.E-02
1.E-01
t1, Square Wave Pulse Duration(s)
1.E+00
1.E+01
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 7/ 9
Reel Dimension
Carrier Tape Dimension
MTE130N20F3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 8/ 9
Recommended wave soldering condition
Product
Pb-free devices
Peak Temperature
260 +0/-5 °C
Soldering Time
5 +1/-1 seconds
Recommended temperature profile for IR reflow
Profile feature
Average ramp-up rate
(Tsmax to Tp)
Preheat
−Temperature Min(TS min)
−Temperature Max(TS max)
−Time(ts min to ts max)
Time maintained above:
−Temperature (TL)
− Time (tL)
Peak Temperature(TP)
Time within 5°C of actual peak
temperature(tp)
Ramp down rate
Time 25 °C to peak temperature
Sn-Pb eutectic Assembly
Pb-free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
240 +0/-5 °C
217°C
60-150 seconds
260 +0/-5 °C
10-30 seconds
20-40 seconds
6°C/second max.
6 minutes max.
6°C/second max.
8 minutes max.
Note : All temperatures refer to topside of the package, measured on the package body surface.
MTE130N20F3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C966F3
Issued Date : 2016.12.19
Revised Date :
Page No. : 9/ 9
TO-263 Dimension
Marking :
Device Name
E130
N20
Date Code
□□□□
Style : Pin 1.Gate 2.Drain
3.Source
3-Lead Plastic Surface Mounted Package
CYStek Package Code : F3
Date Code : (From left to right)
First Code : Year code, the last digit of Christinr year. For example, 2014→4, 2015→, 2016→6, …, etc.
Second Code : Month code, Jan→A, Feb→B, Mar→C, Apr→D, May→E, Jun→F, Jul→G, Aug→H, Sep→J,
Oct→K, Nov→L, Dec→M
Third and fourth codes : production serial number, 01~99
A
A1
A2
b
b1
b2
b3
c
c1
c2
D
Millimeters
Min.
Max.
4.40
4.70
0.00
0.25
2.59
2.79
0.77
0.90
0.76
0.86
1.23
1.36
1.22
1.32
0.34
0.47
0.33
0.43
1.22
1.32
9.05
9.25
Inches
Min.
Max.
0.173
0.185
0.000
0.010
0.102
0.110
0.030
0.035
0.030
0.034
0.048
0.054
0.048
0.052
0.013
0.019
0.013
0.017
0.048
0.052
0.356
0.364
D1
6.60
0.260
DIM
-
-
DIM
E
E1
e
H
L
L1
L2
L3
L4
θ
Θ1
Millimeters
Min.
Max.
10.06
10.26
7.80
8.20
2.54 BSC
14.70
15.50
2.00
2.60
1.17
1.40
1.75
0.25 BSC
2.00 REF
0°
8°
5°
9°
Θ2
1°
Inches
Min.
Max.
0.396
0.404
0.307
0.323
0.100 BSC
0.579
0.610
0.079
0.102
0.046
0.055
0.069
0.010 BSC
0.079 BSC
0°
8°
5°
9°
5°
1°
5°
Notes : 1.Controlling dimension : millimeters.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Material :
• Lead : Pure tin plated.
• Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0.
Important Notice:
• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
• CYStek reserves the right to make changes to its products without notice.
• CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
• CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
MTE130N20F3
CYStek Product Specification
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