STMicroelectronics BLUENRG-MSCSP Upgradable bluetooth low energy network processor Datasheet

BlueNRG-MS
Upgradable Bluetooth® Low Energy network processor
Datasheet - production data
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Features
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Bluetooth specification v4.1 compliant
master and slave single-mode Bluetooth low
energy network processor
Embedded Bluetooth low energy protocol
stack: GAP, GATT, SM, L2CAP, LL, RFPHY
Bluetooth low energy profiles provided
separately
Operating supply voltage: from 1.7 to 3.6 V
8.2 mA maximum TX current (@0 dBm, 3.0
V)
Down to 1.7 µA current consumption with
active BLE stack
Integrated linear regulator and DC-DC stepdown converter
Up to +8 dBm available output power (at
antenna connector)
Excellent RF link budget (up to 96 dB)
Accurate RSSI to allow power control
Proprietary application controller interface
(ACI), SPI based, allows interfacing with an
external host application microcontroller
February 2016
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Full link controller and host security
High performance, ultra-low power CortexM0 32-bit based architecture core
Upgradable BLE stack (stored in embedded
Flash memory, via SPI)
AES security co-processor
Low power modes
16 or 32 MHz crystal oscillator
12 MHz ring oscillator
32 kHz crystal oscillator
32 kHz ring oscillator
Battery voltage monitor
Compliant with the following radio frequency
regulations: ETSI EN 300 328, EN 300 440,
FCC CFR47 Part 15, ARIB STD-T66
Available in QFN32 (5 x 5 mm) and
WLCSP34 (2.66 x 2.56 mm) packages
Operating temperature range:
-40 °C to 85 °C
Applications
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Watches
Fitness, wellness and sports
Consumer medical
Security/proximity
Remote control
Home and industrial automation
Assisted living
Mobile phone peripherals
PC peripherals
Table 1: Device summary
Order code
Package
Packing
BLUENRG-MSQTR
QFN32
(5 x 5 mm)
Tape and
reel
BLUENRG-MSCSP
WLCSP34
(2.66 x 2.56 mm)
Tape and
reel
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www.st.com
List of tables
BlueNRG-MS
Contents
1
Description....................................................................................... 5
2
3
General description ......................................................................... 6
Pin description ................................................................................ 8
4
Application circuits ....................................................................... 11
5
Block diagram and descriptions .................................................. 15
5.1
Core, memory and peripherals ........................................................ 15
5.2
Power management ........................................................................ 16
5.3
Clock management ......................................................................... 17
5.4
Bluetooth low energy radio .............................................................. 17
6
7
Operating modes ........................................................................... 19
Application controller interface .................................................... 22
8
Absolute maximum ratings and thermal data ............................. 23
9
General characteristics ................................................................. 24
10
Electrical specification.................................................................. 25
10.1
Electrical characteristics .................................................................. 25
10.2
RF general characteristics .............................................................. 28
10.3
RF transmitter characteristics.......................................................... 28
10.4
RF receiver characteristics .............................................................. 29
10.5
High speed crystal oscillator (HSXOSC) characteristics ................. 30
10.5.1
11
12
13
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High speed crystal oscillator (HSXOSC) .......................................... 31
10.6
Low speed crystal oscillator (LSXOSC) characteristics................... 32
10.7
High speed ring oscillator (HSROSC) characteristics ..................... 32
10.8
Low speed ring oscillator (LSROSC) characteristics ....................... 32
10.9
N-fractional frequency synthesizer characteristics .......................... 32
10.10
Auxiliary blocks characteristics........................................................ 33
10.11
SPI characteristics .......................................................................... 33
Package information ..................................................................... 35
11.1
QFN32 package information ........................................................... 36
11.2
WLCSP34 package information ...................................................... 38
PCB assembly guidelines ............................................................. 40
Revision history ............................................................................ 41
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BlueNRG-MS
List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pinout description ......................................................................................................................... 9
Table 3: External component list .............................................................................................................. 13
Table 4: SPI interface ............................................................................................................................... 15
Table 5: BlueNRG-MS operating modes .................................................................................................. 20
Table 6: BlueNRG-MS transition times ..................................................................................................... 21
Table 7: Absolute maximum ratings ......................................................................................................... 23
Table 8: Thermal data ............................................................................................................................... 23
Table 9: Recommended operating conditions .......................................................................................... 24
Table 10: RF general characteristics ........................................................................................................ 28
Table 11: RF Transmitter characteristics .................................................................................................. 28
Table 12: RF receiver characteristics ....................................................................................................... 29
Table 13: High speed crystal oscillator characteristics ............................................................................. 30
Table 14: Low speed crystal oscillator characteristics .............................................................................. 32
Table 15: High speed ring oscillator characteristics ................................................................................. 32
Table 16: Low speed ring oscillator characteristics .................................................................................. 32
Table 17: N-fractional frequency synthesizer characteristics ................................................................... 33
Table 18: Auxiliary blocks characteristics ................................................................................................. 33
Table 19: SPI characteristics .................................................................................................................... 33
Table 20: QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data .................................................................... 37
Table 21: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data .................................................. 39
Table 22: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation ....... 40
Table 23: Document revision history ........................................................................................................ 41
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List of figures
BlueNRG-MS
List of figures
Figure 1: BlueNRG-MS application block diagram ..................................................................................... 7
Figure 2: BlueNRG-MS pinout top view (QFN32) ....................................................................................... 8
Figure 3: BlueNRG-MS pinout top view (WLCSP34) ................................................................................. 8
Figure 4: BlueNRG-MS pinout bottom view (WLCSP34) ........................................................................... 9
Figure 5: BlueNRG-MS application circuit: active DC-DC converter QFN32 package ............................ 11
Figure 6: BlueNRG-MS application circuit: non active DC-DC converter QFN32 package ..................... 12
Figure 7: BlueNRG-MS application circuit: active DC-DC converter WLCSP package ........................... 12
Figure 8: BlueNRG-MS application circuit: non active DC-DC converter WLCSP package .................... 13
Figure 9: Block diagram ............................................................................................................................ 15
Figure 10: Power management strategy using LDO ................................................................................ 16
Figure 11: Power management strategy using step-down DC-DC converter .......................................... 17
Figure 12: Simplified state machine.......................................................................................................... 20
Figure 13: Simplified block diagram of the amplitude regulated oscillator ............................................... 31
Figure 14: SPI timings............................................................................................................................... 34
Figure 15: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline .................................................................... 36
Figure 16: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A" ................................................................ 37
Figure 17: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline.................................................. 38
Figure 18: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation ...... 40
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BlueNRG-MS
1
Description
Description
The BlueNRG-MS is a very low power Bluetooth low energy (BLE) single-mode network
processor, compliant with Bluetooth specification v4.1. The BlueNRG-MS supports multiple
roles simultaneously, and can act at the same time as Bluetooth Smart sensor and hub
device.
The Bluetooth Low Energy stack runs on the embedded ARM Cortex-M0 core. The stack is
stored on the on-chip non-volatile Flash memory and can be easily upgraded via SPI. The
device comes pre-programmed with a production-ready stack image (whose version could
change at any time without notice). A different or more up-to-date stack image can be
downloaded from the ST web site and programmed on the device through the ST provided
software tools.
The BlueNRG-MS allows applications to meet of the tight advisable peak current
requirements imposed with the use of standard coin cell batteries. The maximum peak
current is only 10 mA at 1 dBm of output power. Ultra low-power sleep modes and very
short transition times between operating modes allow very low average current
consumption, resulting in longer battery life. The BlueNRG-MS offers the option of
interfacing with external microcontrollers using SPI transport layer.
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General description
2
BlueNRG-MS
General description
The BlueNRG-MS is a single-mode Bluetooth low energy master/slave network processor,
compliant with the Bluetooth specification v4.1.
It integrates a 2.4 GHz RF transceiver and a powerful Cortex-M0 microcontroller, on which
a complete power-optimized stack for Bluetooth single mode protocol runs, providing:
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Master, slave role support
GAP: central, peripheral, observer or broadcaster roles
ATT/GATT: client and server
SM: privacy, authentication and authorization
L2CAP
Link Layer: AES-128 encryption and decryption
An on-chip non-volatile Flash memory allows on-field Bluetooth low energy stack upgrade.
In addition, according the Bluetooth specification v4.1 the BlueNRG-MS can support the
following features through firmware updates:
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Multiple roles simultaneously support
Support simultaneous advertising and scanning
Support being Slave of up to two Masters simultaneously
Privacy V1.1
Low Duty Cycle Directed Advertising
The device allows applications to meet of the tight advisable peak current requirements
imposed with the use of standard coin cell batteries. If the high efficiency embedded DCDC step-down converter is used, the maximum input current is only 15 mA at the highest
output power (+8 dBm). Even if the DC-DC converter is not used, the maximum input
current is only 29 mA at the highest output power, still preserving battery life.
Ultra low-power sleep modes and very short transition time between operating modes
result in very low average current consumption during real operating conditions, providing
very long battery life.
Two different external matching networks are suggested: standard mode (TX output power
up to +5 dBm) and high power mode (TX output power up to +8 dBm).
The external host application processor, where the application resides, is interfaced with
the BlueNRG-MS through an application controller interface protocol which is based on a
standard SPI interface.
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BlueNRG-MS
General description
Figure 1: BlueNRG-MS application block diagram
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Pin description
3
BlueNRG-MS
Pin description
The BlueNRG-MS pinout is shown in Figure 2, Figure 3 and Figure 4. In Table 2 a short
description of the pins is provided.
Figure 2: BlueNRG-MS pinout top view (QFN32)
Figure 3: BlueNRG-MS pinout top view (WLCSP34)
Top view (balls are underneath).
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BlueNRG-MS
Pin description
Figure 4: BlueNRG-MS pinout bottom view (WLCSP34)
Table 2: Pinout description
Pins
Name
I/O
Description
SPI_MOSI
I
SPI_MOSI
SPI_CLK
I
SPI_CLK
D2
SPI_IRQ
O
SPI_IRQ
4
D1
TEST1
I/O
Test pin
5
C1
VBAT3
VDD
1.7-3.6 battery voltage input
6
C2
TEST2
I/O
Test pin connected to GND
7
B1
TEST3
I/O
Test pin connected to GND
8
B2
TEST4
I/O
Test pin connected to GND
9
A1
TEST5
I/O
Test pin connected to GND
10
B3
TEST6
I/O
Test pin connected to GND
11
A2
TEST7
I/O
Test pin connected to GND
12
A3
VDD1V8
O
1.8 V digital core
13
A4
TEST8
I/O
Test pin not connected
14
A5
TEST9
I/O
Test pin not connected
15
B4
TEST11
I/O
Test pin not connected (QFN32)
Test pin connected to GND (WLCSP)
16
B5
TEST12
I/O
Test pin not connected (QFN32)
Test pin connected to GND (WLCSP)
17
A6
FXTAL1
I
16/32 MHz crystal
18
B6
FXTAL0
I
16/32 MHz crystal
19
-
VBAT2
VDD
1.8-3.6 battery voltage input
20
C6
RF1
I/O
Antenna + matching circuit
21
D6
RF0
I/O
Antenna + matching circuit
22
E6
SXTAL1
I
32 kHz crystal
23
E5
SXTAL0
I
32 kHz crystal
24
D5
VBAT1
VDD
1.7-3.6 battery voltage input
25
E4
RESETN
I
Reset
26
F6
SMPSFILT1
O
SMPS output
QFN32
WLCSP
1
E2
2
E1
3
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Pin description
BlueNRG-MS
Pins
Name
I/O
Description
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NO_SMPS
I
Power management strategy selection
28
F5
SMPSFILT2
I/O
SMPS input/output
29
F3
VDD1V2
O
1.2 V digital core
30
E3
TEST10
I/O
TEST pin connected to GND
31
F2
SPI_CS
I
SPI_CS
32
F1
SPI_MISO
O
SPI_MISO
-
C3
GND
GND
Ground
-
D3
GND
GND
Ground
-
D4
GND
GND
Ground
-
F4
SMPS-GND
GND
SMPS ground
QFN32
WLCSP
27
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BlueNRG-MS
4
Application circuits
Application circuits
The schematics below are purely indicative. For more detailed schematics, please refer to
the "Reference design" and "Layout guidelines" which are provided as separate
documents.
Figure 5: BlueNRG-MS application circuit: active DC-DC converter QFN32 package
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Application circuits
BlueNRG-MS
Figure 6: BlueNRG-MS application circuit: non active DC-DC converter QFN32 package
Figure 7: BlueNRG-MS application circuit: active DC-DC converter WLCSP package
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BlueNRG-MS
Application circuits
Figure 8: BlueNRG-MS application circuit: non active DC-DC converter WLCSP package
Table 3: External component list
Component
Description
C1
Decoupling capacitor
C2
DC-DC converter output capacitor
C3
DC-DC converter output capacitor
C4
Decoupling capacitor for 1.2 V digital regulator
C5
Decoupling capacitor for 1.2 V digital regulator
C6
Decoupling capacitor
C7
32 kHz crystal loading capacitor (1)
C8
32 kHz crystal loading capacitor (1)
C9
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
C10
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
C11
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
C12
Decoupling capacitor
C13
Decoupling capacitor
C14
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
C15
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
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Application circuits
BlueNRG-MS
Component
Description
C16
RF balun/matching network capacitor High Performance
RF balun/matching network capacitor Standard mode
C17
16/32 MHz crystal loading capacitor
C18
16/32 MHz crystal loading capacitor
C19
Decoupling capacitor for 1.8 V digital regulator
C20
Decoupling capacitor for 1.8 V digital regulator
C21
RF balun/matching network capacitor High Performance, RF balun/matching network capacitor
Standard mode
L1
DC-DC converter input inductor, Isat > 100 mA, Q > 25
L2
RF balun/matching network inductor High Performance
RF balun/matching network inductor Standard mode
L3
RF balun/matching network inductor High Performance
RF balun/matching network inductor Standard mode
L4
RF balun/matching network inductor High Performance
RF balun/matching network inductor Standard mode
R1
Pull-down resistor on the SPI_IRQ line
(can be replaced by the internal pull-down of the Application MCU)
XTAL1
32 kHz crystal (optional)
XTAL2
16/32 MHz crystal
Notes:
(1)Values valid only for the crystal NDK NX3215SA-32.768 kHz-EXS00A-MU00003. For other crystals refer to what specified in
their datasheet.
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BlueNRG-MS
5
Block diagram and descriptions
Block diagram and descriptions
A block diagram of the device is shown in Figure 9: "Block diagram". In the following
subsections a short description of each module is given.
Figure 9: Block diagram
5.1
Core, memory and peripherals
The BlueNRG-MS contains an ARM Cortex-M0 microcontroller core that supports ultra-low
leakage state retention mode and almost instantaneously returning to fully active mode on
critical events.
The memory subsystem consists of 64 KB Flash, and 12 KB RAM, divided in two blocks of
6 KB (RAM1 and RAM2). Flash is used for the M0 program. No RAM or FLASH resources
are available to the external microcontroller driving the BlueNRG-MS.
The application controller interface (ACI) uses a standard SPI slave interface as transport
layer, basing in five physical wires:
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2 control wires (clock and slave select)
2 data wires with serial shift-out (MOSI and MISO) in full duplex
1 wire to indicate data availability from the slave
Table 4: SPI interface
Name
Direction
Width
Description
SPI_CS
In
1
SPI slave select = SPI enable.
SPI_CLK
In
1
SPI clock (max 8 MHz).
SPI_MOSI
In
1
Master output, slave input.
SPI_MISO
Out
1
Master input, slave output.
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Block diagram and descriptions
Name
SPI_IRQ
BlueNRG-MS
Direction
Width
Out
1
Description
Slave has data for master.
All the SPI pins have an internal pull-down except for the CSN that has a pull-up. All the
SPI pins, except the CSN, are in high impedance state during the low-power states. The
IRQ pin needs a pull-down external resistor.
The device embeds a battery level detector to monitor the supply voltage. The
characteristics of the battery level detector are defined in Table 19.
5.2
Power management
The BlueNRG-MS integrates both a low dropout voltage regulator (LDO) and a step-down
DC-DC converter, and one of them can be used to power the internal BlueNRG-MS
circuitry. However even when the LDO is used, the stringent maximum current
requirements, which are advisable when coin cell batteries are used, can be met and
further improvements can be obtained with the DC-DC converter at the sole additional cost
of an inductor and a capacitor.
The internal LDOs supplying both the 1.8 V digital blocks and 1.2 V digital blocks require
decoupling capacitors for stable operation. When the VBAT voltage is below 1.8 V, the
LDO 1.8 V output follows the VBAT value.
Figure 10 and Figure 11, show the simplified power management schemes using LDO and
DC-DC converter.
Figure 10: Power management strategy using LDO
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BlueNRG-MS
Block diagram and descriptions
Figure 11: Power management strategy using step-down DC-DC converter
5.3
Clock management
The BlueNRG-MS integrates two low-speed frequency oscillators (LSOSC) and two High
speed (16 MHz or 32 MHz) frequency oscillators (HSOSC).
The low frequency clock is used in Low Power mode and can be supplied either by a 32.7
kHz oscillator that uses an external crystal and guarantee up to ±50 ppm frequency
tolerance, or by a ring oscillator with maximum ±500 ppm frequency tolerance, which does
not require any external components.
The primary high frequency clock is a 16 MHz or 32 MHz crystal oscillator. There is also a
fast-starting 12 MHz ring oscillator that provides the clock while the crystal oscillator is
starting up. Frequency tolerance of high speed crystal oscillator is ±50 ppm.
The usage of the 16 MHz (or 32 MHz) crystal is strictly necessary.
5.4
Bluetooth low energy radio
The BlueNRG-MS integrates a RF transceiver compliant to the Bluetooth specification and
to the standard national regulations in the unlicensed 2.4 GHz ISM band.
The RF transceiver requires very few external discrete components. It provides 96 dB link
budgets with excellent link reliability, keeping the maximum peak current below 15 mA.
In Transmit mode, the power amplifier (PA) drives the signal generated by the frequency
synthesizer out to the antenna terminal through a very simple external network. The power
delivered as well as the harmonic content depends on the external impedance seen by the
PA.
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Block diagram and descriptions
BlueNRG-MS
The output power is programmable from -18 dBm to +8 dBm, to allow a user-defined power
control system and to guarantee optimum power consumption for each scenario.
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BlueNRG-MS
6
Operating modes
Operating modes
Several operating modes are defined for the BlueNRG-MS:
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Reset mode
Sleep mode
Standby mode
Active mode
Radio mode
−
Receive Radio mode
−
Transmit Radio mode
In Reset mode, the BlueNRG-MS is in ultra-low power consumption: all voltage regulators,
clocks and the RF interface are not powered. The BlueNRG-MS enters Reset mode by
asserting the external reset signal. As soon as it is de-asserted, the device follows the
normal activation sequence to transit to Active mode.
In Sleep mode either the low speed crystal oscillator or the low speed ring oscillator are
running, whereas the high speed oscillators are powered down as well as the RF interface.
The state of the BlueNRG-MS is retained and the content of the RAM is preserved.
Depending on the application, part of the RAM (RAM2 block) can be switched off during
sleep to save more power (refer to stack mode 1, described in UM1868).
While in Sleep mode, the BlueNRG-MS waits until an internal timer expires and then it
goes into Active mode. The transition from Sleep mode to Active mode can also be
activated through the SPI interface.
Standby mode and Sleep mode are equivalent but the low speed frequency oscillators are
powered down. In Standby mode the BlueNRG-MS can be activated through the SPI
interface.
In Active mode the BlueNRG-MS is fully operational: all interfaces, including SPI and RF,
are active as well as all internal power supplies together with the high speed frequency
oscillator. The MCU core is also running.
Radio mode differs from Active mode as also the RF transceiver is active and it is capable
of either transmitting or receiving.
Figure 12 reports the simplified state machine:
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Operating modes
BlueNRG-MS
Figure 12: Simplified state machine
Table 5: BlueNRG-MS operating modes
State
Digital LDO
SPI
LSOSC
HSOSC
Core
RF
synt.
RX
chain
TX
chain
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
-
ON
ON
OFF
OFF
OFF
ON
-
ON
ON
ON
ON
OFF
ON
-
ON
ON
ON
OFF
ON
OFF
Reset
Register contents
lost
ON
Standby
Register contents
retained
ON
Sleep
Register contents
retained
ON
Active
Register contents
retained
ON
RX
Register contents
retained
ON
TX
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Register contents
retained
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BlueNRG-MS
Operating modes
Table 6: BlueNRG-MS transition times
Transition
Maximum time
1.5 ms
Reset-active
(1)
Standby-active (1)
Sleep-active
(1)
Active-RX
Active-TX
RX-TX or TX-RX
Condition
32 kHz not available
7 ms
32 kHz RO
94 ms
32 kHz XO
0.42 ms
32 kHz not available
6.2 ms
32 kHz RO
93 ms
32 kHz XO
0.42 ms
125 µs
Channel change
61 µs
No channel change
131 µs
Channel change
67 µs
No channel change
150 µs
Notes:
(1)These
measurements are taken using NX3225SA-16.000 MHz-EXS00A-CS05997.
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Application controller interface
7
BlueNRG-MS
Application controller interface
The application controller interface (ACI) is based on a standard SPI module with speeds
up to 8 MHz. The ACI defines a protocol providing access to all the services offered by the
layers of the embedded Bluetooth stack. The ACI commands are described in the
BlueNRG-MS ACI command interface document (UM1865). In addition, the ACI provides a
set of commands that allow to program BlueNRG-MS firmware from an external device
connected to SPI. The complete description of updater commands and procedures is
provided in a separate application note (AN4491).
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BlueNRG-MS
8
Absolute maximum ratings and thermal data
Absolute maximum ratings and thermal data
Absolute maximum ratings are those values above which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages are referred to
GND.
Table 7: Absolute maximum ratings
Pin
Parameter
5, 19, 24, 26, 28
12, 29
1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27,
30, 31, 32
Value
Unit
DC-DC converter supply voltage
input and output
-0.3 to +3.9
V
DC voltage on linear voltage
regulator
-0.3 to +3.9
V
DC voltage on digital input/output
pins
-0.3 to +3.9
V
13, 14, 15,16
DC voltage on analog pins
-0.3 to +3.9
V
17, 18, 22, 23
DC voltage on XTAL pins
-0.3 to +1.4
V
DC voltage on RF pins
-0.3 to +1.4
V
Storage temperature range
-40 to +125
°C
±2.0
kV
20, 21 (1)
TSTG
VESD-HBM
Electrostatic discharge voltage
Notes:
(1)+8
dBm input power at antenna connector in Standard mode, +11 dBm in High Power mode, with given
reference design.
Table 8: Thermal data
Symbol
Rthj-amb
Rthj-c
Parameter
Thermal resistance junction-ambient
Thermal resistance junction-case
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Value
34 (QFN32)
50 (WLCSP36)
2.5 (QFN32)
25 (WLCSP36)
Unit
°C/W
°C/W
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General characteristics
9
BlueNRG-MS
General characteristics
Table 9: Recommended operating conditions
Symbol
V BAT
TA
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Parameter
Min.
Typ.
Max.
Unit
Operating battery supply voltage
1.7
3.6
V
Operating ambient temperature range
-40
+85
°C
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BlueNRG-MS
Electrical specification
10
Electrical specification
10.1
Electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to TA = 25 °C, VBAT = 3.0 V. All performance data are
referred to a 50 W antenna connector, via reference design, QFN32 package version.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Power consumption when DC-DC converter active
5
Reset
RAM2 OFF
1.3
RAM2 ON
2
32 kHz XO
ON (RAM2
OFF)
1.7
32 kHz XO
ON (RAM2
ON)
2.4
Standby
µA
Sleep
µA
32 kHz RO
ON (RAM2
OFF)
2.8
32 kHz RO
ON (RAM2
ON)
3.5
CPU, Flash
and RAM off
2
CPU, Flash
and RAM on
3.3
High Power
mode
7.7
Standard
mode
7.3
Active
IBAT
Supply current
mA
RX
TX
TX
nA
mA
Standard
mode
High Power
DocID027103 Rev 6
+5 dBm
11
0 dBm
8.2
-2 dBm
7.2
-6 dBm
6.7
-9 dBm
6.3
-12
dBm
6.1
-15
dBm
5.9
-18
dBm
5.8
+8 dBm
15.1
mA
mA
25/42
Electrical specification
Symbol
BlueNRG-MS
Parameter
Test conditions
mode
Min.
Typ.
+4 dBm
10.9
+2 dBm
9
-2 dBm
8.3
-5 dBm
7.7
Max.
Unit
Power consumption when DC-DC converter not active
Reset
5
RAM2 OFF
1.4
RAM2 ON
2
32 kHz XO
ON (RAM2
OFF)
1.7
32 kHz XO
ON (RAM2
ON)
2.4
Standby
µA
Sleep
Active
µA
32 kHZ RO
ON (RAM2
OFF)
2.8
32 kHZ RO
ON (RAM2
ON)
3.5
CPU, flash
and RAM off
2.3
high power
mode
14.5
standard
mode
14.3
+5 dBm
21
0 dBm
15.4
-2 dBm
13.3
-6 dBm
12.2
-9 dBm
11.5
-12 dBm
11
-15 dBm
10.6
-18 dBm
10.4
+8 dBm
28.8
+4 dBm
20.5
+2 dBm
17.2
-2 dBm
15.3
-5 dBm
14
-8 dBm
13
-11 dBm
12.3
RX
IBAT
Supply current
26/42
mA
mA
TX standard mode
TX High Power
mode
nA
mA
DocID027103 Rev 6
mA
BlueNRG-MS
Symbol
Electrical specification
Parameter
Test conditions
Min.
-14 dBm
Typ.
Max.
Unit
1.67
pF
12
Digital I/O
CIN
Port I/O
capacitance
TRISE
Rise time
0.1*VDD to
0.9*VDD, CL=50pF
5
19
ns
TFALL
Fall time
0.9*VDD to
0.1*VDD, CL=50pF
6
22
ns
T(RST)L
Hold time for
reset
TC
VBAT range
3
3.3
3.6
V
TC1
VBAT range
2.25
2.5
2.75
V
TC2
VBAT range
1.7
1.8
1.98
V
VIL
VIH
VOL
VOH
IOL
IOH
Input low voltage
Input high voltage
Output low
voltage
Output high
voltage
Low level output
current @VOL
(max)
High level output
current @VOH
(min)
1.29
1.38
1.5
ms
-0.3
0.8
-0.3
0.7
-0.3
0.63
VBAT range: TC
2
3.6
VBAT range: TC1
1.7
3.6
VBAT range: TC2
1.17
3.6
VBAT range: TC
VBAT range: TC1
VBAT range: TC2
VBAT range: TC
0.4
VBAT range: TC1
0.7
VBAT range: TC2
0.45
VBAT range: TC
2.4
VBAT range: TC1
1.7
VBAT range: TC2
1.35
VBAT range: TC
3.4
5.6
7.9
VBAT range: TC1
3.8
6.6
10.1
VBAT range: TC2
1.6
3
5
VBAT range: TC
5.5
10.6
17.6
VBATrange: TC1
3.7
7.2
12
VBAT range: TC2
1.4
3
5.6
DocID027103 Rev 6
V
V
V
V
mA
mA
27/42
Electrical specification
10.2
BlueNRG-MS
RF general characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V. All performance data are
referred to a 50 W antenna connector, via reference design, QFN32 package version.
Table 10: RF general characteristics
Symbol
10.3
Parameter
Test conditions
FREQ
Frequency range
F CH
Channel spacing
RF ch
RF channel center
frequency
Min.
Typ.
2400
Max.
Unit
2483.5
MHz
2
MHz
2402
2480
MHz
RF transmitter characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to TA = 25 °C, VBAT = 3.0 V. All performance data are
referred to a 50 W antenna connector, via reference design, QFN32 package version.
Table 11: RF Transmitter characteristics
Symbol
Test conditions
MOD
Modulation scheme
BT
Bandwidth-bit period
product
Mindex
28/42
Parameter
Air data rate
STacc
Symbol time
accuracy
PMAX
Maximum output
power at antenna
connector
Typ.
Max.
Unit
GFSK
0.5
Modulation index
DR
Min.
0.45
0.5
0.55
1
Mbps
50
ppm
High power
+8
+10
dBm
Standard mode
+5
+7
dBm
High power
-15
Standard mode
-18
PRFC
Minimum output
power
PRFC
RF power accuracy
PBW1M
6 dB bandwidth for
modulated carrier (1
Mbps)
Using resolution bandwidth of
100 kHz
PRF1
1st adjacent channel
transmit power 2
MHz
Using resolution bandwidth of
100 kHz and average
detector
-20
dBm
PRF2
2nd adjacent channel
transmit power >3
MHz
Using resolution bandwidth of
100 kHz and average
detector
-30
dBm
PSPUR
Spurious emission
Harmonics included. Using
resolution bandwidth of 1
MHz and average detector
-41
dBm
CFdev
Center frequency
deviation
During the packet and
including both initial
frequency offset and drift
±150
kHz
dB
±2
DocID027103 Rev 6
500
dB
kHz
BlueNRG-MS
Electrical specification
Symbol
Parameter
Test conditions
Freqdrift
Frequency drift
During the packet
IFreqdrift
DriftRatemax
ZLOAD
10.4
Max.
Unit
±50
kHz
Initial carrier
frequency drift
±20
kHz
Maximum drift rate
400
Hz/µs
Optimum differential
load
Min.
Typ.
Standard mode @ 2440 MHz
25.9 +
j44.4
High power mode @ 2440
MHz
25.4 +
j20.8
Ω
RF receiver characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V. All performance data are
referred to a 50 W antenna connector, via reference design, QFN32 package version.
Table 12: RF receiver characteristics
Symbol
RX SENS
P SAT
z IN
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Sensitivity
BER <0.1%
-88
dBm
Saturation
Standard mode
High power mode
BER <0.1%
8
11
dBm
Input differential impedance
Standard mode @ 2440 MHz
High power mode @ 2440
MHz
31.4 - j26.6
28.8 - j18.5
Ω
-
RF selectivity with BLE equal modulation on interfering signal
Co-channel interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
9
dBc
C/I 1 MHz
Adjacent (+1 MHz)
Interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
2
dBc
C/I 2 MHz
Adjacent (+2 MHz)
Interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
-34
dBc
C/I 3 MHz
Adjacent (+3 MHz)
Interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
-40
dBc
C/I ≥4 MHz
Adjacent (≥±4 MHz)
Interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
-34
dBc
C/I ≥6 MHz
Adjacent (≥±6 MHz
Interference
Wanted signal = -67 dBm
BER ≤ 0.1%
-45
dBc
C/I ≥25 MHz
Adjacent (≥±25 MHz)
Interference
Wanted signal = -67 dBm,
BER ≤ 0.1%
-64
dBc
Image frequency
Interference
-2MHz
Wanted signal = -67 dBm,
BER ≤ 0.1%
-20
dBc
C/I COchannel
C/I Image
DocID027103 Rev 6
-
29/42
Electrical specification
Symbol
C/I
Image±1MHz
BlueNRG-MS
Parameter
Test conditions
Adjacent (±1 MHz)
Interference to in-band
image frequency
-1MHz
-3MHz
Min.
Typ.
Max.
Unit
5
Wanted signal = -67 dBm,
BER ≤ 0.1%
dBc
-25
Out of Band Blocking (Interfering signal CW)
C/I Block
Interfering signal frequency
30 MHz – 2000 MHz
Wanted signal = -67 dBm,
BER ≤ 0.1%, Measurement
resolution 10 MHz
C/I Block
Interfering signal frequency
2003 MHz – 2399 MHz
Wanted signal = -67 dBm,
BER ≤ 0.1%, Measurement
resolution 3 MHz
C/I Block
Interfering signal frequency
2484 MHz – 2997 MHz
Wanted signal = -67 dBm,
BER ≤ 0.1%, measurement
resolution 3 MHz
C/I Block
Interfering signal frequency
3000 MHz – 12.75 GHz
Wanted signal = -67 dBm,
BER ≤ 0.1%, measurement
resolution 25 MHz
-30
dBm
-35
dBm
-35
dBm
-30
dBm
-
-
Intermodulation characteristics (CW signal at f 1, BLE interfering signal at f 2)
P_IM(3)
Input power of IM interferes
at 3 and 6 MHz distance
from wanted signal
Wanted signal = -64 dBm,
BER ≤ 0.1%
-33
dBm
P_IM(-3)
Input power of IM interferes
at -3 and -6 MHz distance
from wanted signal
Wanted signal = -64 dBm,
BER ≤ 0.1%
-43
dBm
P_IM(4)
Input power of IM interferes
at ±4 and ±8 MHz distance
from wanted signal
Wanted signal = -64 dBm,
BER ≤ 0.1%
-33
dBm
P_IM(5)
Input power of IM interferes
at ±5 and ±10 MHz distance
from wanted signal
Wanted signal = -64 dBm,
BER ≤ 0.1%
-33
dBm
10.5
-
High speed crystal oscillator (HSXOSC) characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT= 3.0 V.
Table 13: High speed crystal oscillator characteristics
Symbol
Parameter
f NOM
Nominal
frequency
f TOL
Frequency
tolerance
ESR
PD
30/42
Test conditions
Min.
Typ.
Max.
16/32
Includes initial accuracy, stability over temperature,
aging and frequency pulling due to incorrect load
capacitance.
Unit
MHz
±50
ppm
Equivalent series
resistance
100
Ω
Drive level
100
µW
DocID027103 Rev 6
BlueNRG-MS
10.5.1
Electrical specification
High speed crystal oscillator (HSXOSC)
The BlueNRG-MS includes a fully integrated, low power 16/32 MHz Xtal oscillator with an
embedded amplitude regulation loop. In order to achieve low power operation and good
frequency stability of the Xtal oscillator, certain considerations with respect to the quartz
load capacitance C0 need to be taken into account. Figure 13 shows a simplified block
diagram of the amplitude regulated oscillator used on the BlueNRG-MS.
Figure 13: Simplified block diagram of the amplitude regulated oscillator
Low power consumption and fast startup time is achieved by choosing a quartz crystal with
a low load capacitance C0. To achieve good frequency stability, the following equation
needs to be satisfied:
𝐶𝐶0 =
𝐶𝐶1′ ∗ 𝐶𝐶2′
𝐶𝐶1′ + 𝐶𝐶2′
Where C1’=C1+CPCB1+CPAD, C2’= C2+CPCB2+CPAD, where C1 and C2 are external
(SMD) components, CPCB1 and CPCB2 are PCB routing parasites and CPAD is the
equivalent small-signal pad-capacitance. The value of CPAD is around 0.5 pF for each
pad. The routing parasites should be minimized by placing quartz and C1/C2 capacitors
close to the chip, not only for an easier matching of the load capacitance C0, but also to
ensure robustness against noise injection. Connect each capacitor of the Xtal oscillator to
ground by a separate via.
DocID027103 Rev 6
31/42
Electrical specification
10.6
BlueNRG-MS
Low speed crystal oscillator (LSXOSC) characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V.
Table 14: Low speed crystal oscillator characteristics
Symbol
Parameter
f NOM
Nominal
frequency
f TOL
Frequency
tolerance
ESR
PD
Test conditions
Min.
Typ.
Max.
32.768
Includes initial accuracy, stability over
temperature, aging and frequency
pulling due to incorrect load capacitance.
kHz
±50
ppm
Equivalent
series resistance
90
kΩ
Drive level
0.1
µW
These values are the correct ones for NX3215SA-32.768 kHz-EXS00A-MU00003.
10.7
High speed ring oscillator (HSROSC) characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V, QFN32 package version.
Table 15: High speed ring oscillator characteristics
Symbol
f NOM
10.8
Parameter
Test conditions
Min.
Nominal frequency
Typ.
12
Max.
16
Unit
MHz
Low speed ring oscillator (LSROSC) characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V, QFN32 package version.
Table 16: Low speed ring oscillator characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
32 kHz ring oscillator (LSROSC)
f NOM
Nominal frequency
f TOL
Frequency tolerance
10.9
37.4
kHz
±500
N-fractional frequency synthesizer characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V, f c= 2440 MHz.
32/42
Unit
DocID027103 Rev 6
ppm
BlueNRG-MS
Electrical specification
Table 17: N-fractional frequency synthesizer characteristics
Symbol
Test conditions
RF carrier phase
noise
PN SYNTH
10.10
Parameter
LOCK TIME
PLL lock time
TO TIME
PLL turn on / hop
time
Min.
Typ.
Max.
Unit
At ±1 MHz offset from carrier
-113
dBc/Hz
At ±3 MHz offset from carrier
-119
dBc/Hz
Including calibration
40
µs
150
µs
Auxiliary blocks characteristics
Characteristics measured over recommended operating conditions unless otherwise
specified. Typical value are referred to T A= 25 °C, V BAT=3.0 V, f c= 2440 MHz. QFN32
package version.
Table 18: Auxiliary blocks characteristics
Symbol
Parameter
Battery indicator and brown-out reset (BOR)
Test conditions
Min.
Typ.
Max.
Unit
(1)
V BLT1
Battery level thresholds 1
2.7
V
V BLT2
Battery level thresholds 2
2.5
V
V BLT3
Battery level thresholds 3
2.3
V
V BLT4
Battery level thresholds 4
2.1
V
A BLT
Battery level thresholds accuracy
V ABOR
Ascending brown-out threshold
1.79
V
V DBOR
Descending brown-out threshold
1.73
V
5
%
Notes:
(1)BOR
10.11
is disabled by default and it can be enabled by software.
SPI characteristics
Table 19: SPI characteristics
Symbol
Parameter
f CLK
1/t (CLK)
SPI clock frequency
DuCy (CLK)
SPI clock duty cycle
t s(CS)
CS setup time
Min
Max
Unit
8
MHz
50
%
40
t lh(CS)
CS low hold time
40
t hh(CS)
CS high hold time
10t (CLK)
t s(SI)
MOSI setup time
20
t h(SI)
MOSI hold time
10
t v(SO)
MISO valid time
DocID027103 Rev 6
Typ
ns
40
33/42
Electrical specification
BlueNRG-MS
The values for the parameters given in this table are based on characterization, not tested
in production.
Figure 14: SPI timings
34/42
DocID027103 Rev 6
BlueNRG-MS
11
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID027103 Rev 6
35/42
Package information
11.1
BlueNRG-MS
QFN32 package information
Figure 15: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline
36/42
DocID027103 Rev 6
BlueNRG-MS
Package information
Table 20: QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.85
1.00
A1
0
0.02
0.05
A3
b
0.20 REF
0.25
D
0.25
0.30
5.00 BSC
E
5.00 BSC
D2
3.2
3.70
E2
3.2
3.70
e
0.5 BSC
L
0.30
Ф
0°
K
0.20
0.40
0.50
14°
Figure 16: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A"
DocID027103 Rev 6
37/42
Package information
11.2
BlueNRG-MS
WLCSP34 package information
Figure 17: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline
See Note 1
WLCSP34_POA_8165249
1.
38/42
The corner of terminal A1 must be identified on the top surface by using a laser
marking dot.
DocID027103 Rev 6
BlueNRG-MS
Package information
Table 21: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data
mm.
Dim.
Notes
Min.
Typ.
A
0.50
A1
0.20
b
0.27
D
2.50
D1
E
Max.
2.56
(1)
2.58
(2)
2.68
(3)
2.00
2.60
2.66
E1
2.00
e
0.40
f
0.28
g
0.33
ccc
0.05
Notes:
(1)
The typical ball diameter before mounting is 0.25 mm.
(2)D
= f + D1 + f.
(3)E
= g + E1 + g.
DocID027103 Rev 6
39/42
PCB assembly guidelines
12
BlueNRG-MS
PCB assembly guidelines
For Flip Chip mounting on the PCB, STMicroelectronics recommends the use of a solder
stencil aperture of 330 x 330 µm maximum and a typical stencil thickness of 125 µm.
Flip Chips are fully compatible with the use of near eutectic 95.8% Sn, 3.5% Ag, 0.7% Cu
solder paste with no-clean flux. ST's recommendations for Flip Chip board mounting are
illustrated on the soldering reflow profile shown in Figure 17.
Figure 18: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile
recommendation
Table 22: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile
recommendation
Value
Profile
Typ.
Max.
0.9 °C/s
3 °C/s
2 °C/s
3 °C/s
Peak temp. in reflow
240 - 245 °C
260 °C
Time above 220 °C
60 s
90 s
-2 to - 3 °C/s
-6 °C/s
Temp. gradient in preheat (T = 70 – 180 °C)
Temp. gradient (T = 200 – 225 °C)
Temp. gradient in cooling
Time from 50 to 220 °C
160 to 220 s
Dwell time in the soldering zone (with temperature higher than 220 °C) has to be kept as
short as possible to prevent component and substrate damage. Peak temperature must not
exceed 260 °C. Controlled atmosphere (N 2or N 2H 2) is recommended during the whole
reflow, especially above 150 °C.
Flip Chips are able to withstand three times the previous recommended reflow profile to be
compatible with a double reflow when SMDs are mounted on both sides of the PCB plus
one additional repair.
A maximum of three soldering reflows are allowed for these lead-free packages (with repair
step included).
The use of a no-clean paste is highly recommended to avoid any cleaning operation. To
prevent any bump cracks, ultrasonic cleaning methods are not recommended.
40/42
DocID027103 Rev 6
BlueNRG-MS
13
Revision history
Revision history
Table 23: Document revision history
Date
Revision
Changes
24-Nov-2014
1
Initial release.
19-Jun-2015
2
Document status promoted from “Preliminary data” to “Production
data”.
Minor changes in the structure of the document to improve
readability. Updated: Figure in cover page, Section 2: General
description, Figure 5, Figure 6, Figure 7, Figure 8, Section 10:
Electrical specification. Added: Figure 15: QFN32 (5 x 5 x 1 pitch 0.5
mm) package detail "A".
01-Oct-2015
3
Modified: Figure 5, Figure 6, Figure 7 and Figure 8
29-Oct-2015
4
Updated: General description.
Added: SPI characteristics.
16-Nov-2015
5
Updated title, Features , Section 1: "Description" and Section 2:
"General description".
01-Feb-2016
6
Updated Section 8: "Application controller interface"
DocID027103 Rev 6
41/42
BlueNRG-MS
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
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DocID027103 Rev 6