TI OPA2314-EP 3-mhz, low-power, low-noise, rri/o, 1.8-v cmos operational amplifier Datasheet

OPA2314-EP
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SBOS597 – SEPTEMBER 2012
3-MHz, LOW-POWER, LOW-NOISE, RRI/O, 1.8-V CMOS OPERATIONAL AMPLIFIER
Check for Samples: OPA2314-EP
FEATURES
1
•
•
•
•
•
•
•
•
Low IQ: 150 µA/ch (max)
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 14 nV/√Hz at 1 kHz
Gain Bandwidth: 3 MHz
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RF/EMI Filter
APPLICATIONS
•
•
•
•
•
•
Battery-Powered Instruments:
– Consumer, Industrial, Medical
– Notebooks, Portable Media Players
Photodiode Amplifiers
Active Filters
Remote Sensing
Wireless Metering
Handheld Test Equipment
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly or Test Site
One Fabrication Site
Available in Extended (–40°C to 150°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Additional temperature ranges available - contact factory
DESCRIPTION
The OPA2314 is a dual channel operational amplifier and represents a new generation of low-power, generalpurpose CMOS amplifiers. Rail-to-rail input and output swings, low quiescent current (150 μA typ at
5.0 VS) combined with a wide bandwidth of 3 MHz, and very low noise (14 nV/√Hz at 1 kHz) make this family
very attractive for a variety of battery-powered applications that require a good balance between cost and
performance. The low input bias current supports applications with mega-ohm source impedances.
The robust design of the OPA2314 provides ease-of-use to the circuit designer: unity-gain stability with
capacitive loads of up to 300 pF, an integrated RF/EMI rejection filter, no phase reversal in overdrive conditions,
and high ESD protection (4-kV HBM).
This device is optimized for low-voltage operation as low as +1.8 V (±0.9 V) and up to +5.5 V (±2.75 V), and is
specified over the full extended temperature range of –40°C to +150°C.
The OPA2314 (dual) is offered in a DFN-8 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
OPA2314-EP
SBOS597 – SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
VID NUMBER
-40°C to 150°C
DFN-8 – DRB
OPA2314ASDRBTEP
OUVS
V62/12626-01XE
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage
7
V
Voltage (2)
(V–) – 0.5 to (V+) + 0.5
V
Current (2)
±10
mA
Output short-circuit (3)
Continuous
mA
Operating temperature, TA
–40 to +150
°C
Storage temperature, Tstg
–65 to +150
°C
Junction temperature, TJ
+170
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Signal input terminals
ESD rating
(1)
(2)
(3)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V (1)
Boldface limits apply over the specified temperature range: TA = –40°C to +150°C.
At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
2.5
mV
3.5
mV
OFFSET VOLTAGE
VOS
Input offset voltage
Over temperature
VCM = (VS+) – 1.3 V
TA = –40°C to +150°C
dVOS/dT
vs Temperature
PSRR
vs Power supply
VCM = (VS+) – 1.3 V
78
VS = 5.5 V, (VS–) – 0.2 V <
VCM < (VS+) – 1.3 V
TA = –40°C to +150°C
72
Channel separation, dc
At dc
1
μV/°C
92
dB
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.2
(V+) + 0.2
V
VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V,
TA = –40°C to +150°C
68
86
dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V,
TA = –40°C to +150°C
71
90
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2),
TA = –40°C to +150°C
60
INPUT BIAS CURRENT
IB
Input bias current
Over temperature
IOS
±0.2
TA = –40°C to +150°C
Input offset current
Over temperature
±0.2
TA = –40°C to +150°C
±10
pA
±2
nA
±10
pA
±2
nA
NOISE
Input voltage noise (peak-topeak)
5
μVPP
f = 10 kHz
13
nV/√Hz
f = 1 kHz
14
nV/√Hz
f = 1 kHz
5
fA/√Hz
Differential
VS = 5.0 V
1
pF
Common-mode
VS = 5.0 V
5
pF
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
INPUT CAPACITANCE
CIN
OPEN-LOOP GAIN
AOL
Open-Loop Voltage Gain
Over temperature
Phase margin
(1)
(2)
VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
115
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
100
128
dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ
90
100
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ
94
110
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
110
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ
VS = 5.0 V, G = +1, RL = 10 kΩ
100
dB
65
deg
Parameters with MIN and/or MAX specification limits are 100% production tested, unless otherwise noted.
Limits are based on characterization and statistical analysis; not production tested.
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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V(1) (continued)
Boldface limits apply over the specified temperature range: TA = –40°C to +150°C.
At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
VS = 1.8 V, RL = 10 kΩ, CL = 10 pF
2.7
MHz
VS = 5.0 V, RL = 10 kΩ, CL = 10 pF
3
MHz
VS = 5.0 V, G = +1
1.5
V/μs
To 0.1%, VS = 5.0 V, 2-V step , G = +1
2.3
μs
To 0.01%, VS = 5.0V, 2-V step , G = +1
3.1
μs
Overload recovery time
VS = 5.0 V, VIN × Gain > VS
5.2
μs
Total harmonic distortion +
noise (4)
VS = 5.0 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ
0.001
%
GBW
Gain-bandwidth product
SR
Slew rate (3)
tS
Settling time
THD+N
OUTPUT
Voltage output swing from supply
rails
VO
VS = 1.8 V, RL = 10 kΩ
5
15
mV
VS = 5.5 V, RL = 10 kΩ
5
20
mV
VS = 1.8 V, RL = 2 kΩ
15
30
mV
VS = 5.5 V, RL = 2 kΩ
22
40
mV
30
mV
VS = 5.5 V, RL = 10 kΩ
Over temperature
VS = 5.5 V, RL = 2 kΩ
60
mV
ISC
Short-circuit current
VS = 5.0 V
±20
mA
RO
Open-loop output impedance
VS = 5.5 V, f = 100 Hz
570
Ω
POWER SUPPLY
VS
Specified voltage range
IQ
1.8
Quiescent current per amplifier
Over temperature
5.5
V
VS = 1.8 V, IO = 0 mA
130
180
µA
VS = 5.0 V, IO = 0 mA
150
190
µA
220
µA
VS = 5.0 V, IO = 0 mA
Power-on time
VS = 0 V to 5 V, to 90% IQ level
44
µs
TEMPERATURE
(3)
(4)
Specified range
–40
+150
°C
Operating range
–40
+150
°C
Storage range
–65
+150
°C
Signifies the slower value of the positive or negative slew rate.
Third-order filter; bandwidth = 80 kHz at –3 dB.
THERMAL INFORMATION
OPA2314ASDRBTEP
THERMAL METRIC (1)
DRB (DFN)
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
53.8
θJC(top)
Junction-to-case(top) thermal resistance
69.2
θJB
Junction-to-board thermal resistance
20.1
ψJT
Junction-to-top characterization parameter
3.8
ψJB
Junction-to-board characterization parameter
20.0
θJC(bottom)
Junction-to-case(bottom) thermal resistance
11.6
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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PIN CONFIGURATIONS
DRB PACKAGE(1)
DFN-8
(TOP VIEW)
OUT A
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
8
V+
7
OUT B
6
-IN B
5
+IN B
(1) Pitch: 0,65mm.
(2) Connect thermal pad to V–. Pad size: 1,8mm × 1,5mm.
xxxx
xxxx
10000.00
Estimated Life (Years)
1000.00
100.00
Wirebond Voiding
Fail Mode
Electromigration Fail Mode
10.00
1.00
0.10
80
100
120
140
160
180
200
Continuous T J (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
Enhanced plastic product disclaimer applies.
Figure 1. OPA2314-EP Operating Life Derating Chart
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TYPICAL CHARACTERISTICS
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
RL = 10 kW/10 pF
VS = ±2.5 V
130
100
-40
80
-60
60
-80
40
-100
20
-120
0
-140
-20
-160
10M
1
10
100
1k
10k
100k
1M
N
-20
Phase (°)
Gain (dB)
120
0
Open-Loop Gain (dB)
140
OPEN-LOOP GAIN
vs TEMPERATURE
120
N
±50
9
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 2.
Figure 3.
QUIESCENT CURRENT
vs SUPPLY
QUIESCENT CURRENT
vs TEMPERATURE
180
160
170
155
Quiescent Current ( A/Ch)
Quiescent Current (mA/Ch)
N
100
160
150
140
130
120
110
100
VS = 5.5 V
150
145
140
135
VS = 1.8 V
130
125
120
90
80
115
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
±50
±25
0
Supply Voltage (V)
25
50
75
100
125
150
Temperature (ƒC)
Figure 4.
C002
Figure 5.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
30
10
25
Percent of Amplifiers (%)
12
8
6
4
20
15
10
2
5
0
0
-1.4
-1.3
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
Percent of Amplifiers (%)
9
110
Frequency (Hz)
0.2
Offset Voltage (mV)
Figure 6.
6
9
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Offset Voltage Drift (mV/°C)
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
OFFSET VOLTAGE vs TEMPERATURE
1000
800
800
600
Offset Voltage ( V)
Offset Voltage (mV)
600
400
200
0
-200
-400
-600
-800
Typical Units
VS = ±2.75 V
-1000
-2.75
Typical Units
VS = “2.75 V
400
200
0
±200
±400
±600
±800
-2
-1.25
-0.5
0
0.5
1.25
2
2.75
±50
±25
0
Common-Mode Voltage (V)
CMRR AND PSRR
vs FREQUENCY (Referred-to-Input)
CMRR AND PSRR
vs TEMPERATURE
100
125
150
C003
119
Common-Mode Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
75
Figure 9.
+PSRR
100
-PSRR
60
CMRR
40
20
0
50
Figure 8.
120
80
25
Temperature (ƒC)
VS = ±2.75 V
114
CMRR
109
104
99
PSRR
94
89
84
10
100
1k
10k
100k
±50
1M
±25
0
Frequency (Hz)
25
50
75
100
125
150
Temperature (ƒC)
C004
Figure 10.
Figure 11.
0.1-Hz to 10-Hz INPUT VOLTAGE NOISE
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
Voltage (0.5 mV/div)
Voltage Noise (nv/ÖHz)
100
VS = ±0.9 V
VS = ±2.75 V
Time (1 s/div)
10
10
100
1k
10k
100k
Frequency (Hz)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
VOLTAGE NOISE
vs COMMON-MODE VOLTAGE
INPUT BIAS AND OFFSET CURRENT
vs TEMPERATURE
20
1000
900
18
800
Input Bias Current (pA)
Voltage Noise (nV/ÖHz)
VS = ±2.75 V
f = 1 kHz
16
14
12
700
IB
600
500
400
300
200
IOS
100
10
0
0.5
0
1
1.5
2
2.5
3
4
3.5
4.5
5.5
5
-50
-25
0
25
Common-Mode Input Voltage (V)
50
75
Figure 15.
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY AND SUPPLY VOLTAGE
150
6
VIN = 5.5 V
VIN = 3.3 V
VIN = 1.8 V
5
10k
Voltage (VPP)
Output Impedance (W)
125
Figure 14.
100k
VS = ±0.9 V
1k
4
3
2
1
RL = 10 kW
CL = 10 pF
VS = ±2.75 V
0
1
1
10
100
1k
10k
100k
1M
10M
10k
100k
Frequency (Hz)
1M
10M
Frequency (Hz)
Figure 16.
Figure 17.
OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (OVER TEMPERATURE)
CLOSED-LOOP GAIN vs FREQUENCY
3
40
VS = 1.8 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
2
20
1
-40°C
+150°C
+125°C
+25°C
0
5
10
15
20
25
37.6
30
35
Gain (dB)
Output Voltage Swing (V)
100
Temperature (°C)
0
-1
-2
-20
10k
-3
Output Current (mA)
1M
10M
Frequency (Hz)
Figure 18.
8
100k
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
CLOSED-LOOP GAIN vs FREQUENCY
40
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
70
VS = 5.5 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
60
50
Gain (dB)
Overshoot (%)
20
0
40
30
20
VS = ±2.75 V
Gain = +1 V/V
RL = 10 kW
10
-20
0
10k
100k
1M
10M
0
400
600
800
1000
1200
Capacitive Load (pF)
Figure 20.
Figure 21.
SMALL-SIGNAL PULSE RESPONSE (NONINVERTING)
SMALL-SIGNAL PULSE RESPONSE (INVERTING)
Voltage (25 mV/div)
VIN
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
Time (1 ms/div)
Time (1 ms/div)
Figure 22.
Figure 23.
LARGE-SIGNAL PULSE RESPONSE (INVERTING)
1
2
Gain = +1
VS = ±0.9 V
RL = 10 kW
VIN
0.5
0.25
0
-0.25
VOUT
1
VIN
0.5
0
-0.5
-0.5
-1
-0.75
-1.5
-1
Gain = +1
VS = ±2.75 V
RL = 10 kW
1.5
Voltage (V)
0.75
Gain = +1
VS = ±2.75 V
RF = 10 kW
VIN
Voltage (25 mV/div)
Gain = +1
VS = ±0.9 V
RF = 10 kW
LARGE-SIGNAL PULSE RESPONSE (NONINVERTING)
Voltage (V)
200
Frequency (Hz)
VOUT
-2
Time (1 ms/div)
Time (1 ms/div)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
POSITIVE OVERLOAD RECOVERY
NEGATIVE OVERLOAD RECOVERY
3
1
0.5
Output
2
Voltage (0.5 V/div)
Voltage (0.5 V/div)
2.5
1.5
1
0.5
0
Input
0
-0.5
-1
-1.5
-2
Output
Input
-0.5
-2.5
-1
-3
0
4
2
6
8
10
12
14
0
6
8
10
Figure 26.
Figure 27.
NO PHASE REVERSAL
CHANNEL SEPARATION vs FREQUENCY
OPA2314
-60
Channel Separation (dB)
VIN
VOUT
3
12
Time (2 ms/div)
4
2
Voltage (1 V/div)
4
2
Time (2 ms/div)
1
0
-1
-2
14
VS = ±2.75 V
-80
-100
-120
-3
-4
-140
0
250
500
750
1000
100
1k
10k
Figure 29.
THD+N vs OUTPUT AMPLITUDE
(G = +1 V/V)
THD+N vs OUTPUT AMPLITUDE
(G = –1 V/V)
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
10M
0.1
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = +1 V/V
0.01
Load = 2 kW
0.001
Load = 10 kW
0.1
1
10
0.01
Load = 2 kW
0.001
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = -1 V/V
0.0001
0.01
Output Amplitude (VRMS)
Load = 10 kW
0.1
1
10
Output Amplitude (VRMS)
Figure 30.
10
1M
Figure 28.
0.1
0.0001
0.01
100k
Frequency (Hz)
Time (125 ms/div)
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
Total Harmonic Distortion + Noise (%)
0.1
VS = ±2.5 V
VOUT = 0.5 VRMS
BW = 80 kHz
G = +1 V/V
0.01
Load = 2 kW
0.001
Load = 10 kW
0.0001
10
100
1k
10k
100k
EMIRR IN+ (dB)
ELECTROMAGNETIC INTERFERENCE REJECTION RATIO
Referred to Noninverting Input (EMIRR IN+) vs FREQUENCY
THD+N vs FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
10M
PRF = −10 dBm
VS = ±2.5 V
VCM = 0 V
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 32.
10G
G001
Figure 33.
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11
OPA2314-EP
SBOS597 – SEPTEMBER 2012
www.ti.com
APPLICATION INFORMATION
The OPA2314 is a low-power, rail-to-rail input/output operational amplifier specifically designed for portable
applications. This device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range of
general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA2314 to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly
increases dynamic range, especially in low-supply applications, and makes them ideal for driving sampling
analog-to-digital converters (ADCs).
The OPA2314 features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel,
providing good ac performance at very low power consumption. DC applications are also well served with a very
low input noise voltage of 14 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of
0.5 mV (typical).
Operating Voltage
The OPA2314 is fully specified and ensured for operation from +1.8 V to +5.5 V. In addition, many specifications
apply from –40°C to +150°C. Parameters that vary significantly with operating voltages or temperature are shown
in the Typical Characteristics graphs. Power-supply pins should be bypassed with 0.01-μF ceramic capacitors.
Rail-to-Rail Input
The input common-mode voltage range of the OPA2314 extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in Figure 34. The N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputs
from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically
(V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV
with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V
on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR,
offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Figure 34. Simplified Schematic
12
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OPA2314-EP
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Input and ESD Protection
The OPA2314 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 35 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10mA max
OPA2314
VOUT
VIN
5kW
Figure 35. Input Current Protection
Common-Mode Rejection Ratio (CMRR)
CMRR for the OPA2314 is specified in several ways so the best match for a given application may be used; see
the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition
region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when
the application requires use of one of the differential input pairs. Second, the CMRR over the entire commonmode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the
transition region (see Figure 8).
EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from its nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most
susceptible. The OPA2314 operational amplifier incorporates an internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. The
filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 33 shows the results of this testing
on the OPAx314. Detailed information can also be found in the application report, EMI Rejection Ratio of
Operational Amplifiers (SBOA128), available for download from the TI website.
Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPA2314 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails, as can be seen in the typical characteristic graph, Output Voltage Swing vs Output
Current.
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OPA2314-EP
SBOS597 – SEPTEMBER 2012
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Capacitive Load and Stability
The OPA2314 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA2314 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA2314 remains stable with a pure capacitive load up to
approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL greater than 1 μF)
is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.
Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.
See the typical characteristic graph, Small-Signal Overshoot vs. Capacitive Load.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
OPA2314
VIN
10 W to
20 W
RL
CL
Figure 36. Improving Capacitive Load Drive
DFN Package
The OPA2314 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download from the TI website at www.ti.com.
NOTE: The exposed leadframe die pad on the bottom of the DFN package should be connected to the
most negative potential (V-).
14
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OPA2314-EP
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SBOS597 – SEPTEMBER 2012
APPLICATION EXAMPLES
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as Figure 37 illustrates.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 37. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 38 shows. For best results, the amplifier should have a bandwidth that is eight to 10 times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 38. Two-Pole Low-Pass Sallen-Key Filter
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15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA2314ASDRBREP
PREVIEW
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
OUVS
OPA2314ASDRBTEP
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
OUVS
V62/12626-01XE
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
OUVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF OPA2314-EP :
• Catalog: OPA2314
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2314ASDRBTEP
Package Package Pins
Type Drawing
SON
DRB
8
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2314ASDRBTEP
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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