NXP MK24FN1M0VLQ12 Kinetis k24f sub-family Datasheet

NXP Semiconductors
Data Sheet: Technical Data
K24P144M120SF5
Rev. 7, 11/2016
Kinetis K24F Sub-Family Data
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K24 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, and up to
256 KB of embedded SRAM. These devices share the
comprehensive enablement and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 250 μA/MHz. Static
power consumption down to 5.8 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 339 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
Vreg, with USB device crystal-less operation
Performance
• Up to 120 MHz ARM® Cortex®-M4 core with DSP
instructions and floating point unit
Memories and memory interfaces
• Up to 1 MB program flash memory and 256 KB RAM
• FlexBus external bus interface
System peripherals
• Multiple low-power modes, low-leakage wake-up unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog
Security and integrity modules
• Hardware CRC module
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
• Three analog comparators (CMP)
• Voltage reference
MK24FN1M0VLQ12
MK24FN1M0VLL12
MK24FN1M0VDC12
121 XFBGA
8 x 8 x 0.5 mm Pitch
0.65 mm
144 LQFP
20 x 20 x 1.6 mm Pitch
0.5 mm
100 QFP
14 x 14 x 1.7 mm Pitch 0.5 mm
Communication interfaces
• USB full-/low-speed On-the-Go controller
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules. Support for up to 1 Mbit/s
• Six UART modules
• Secure Digital Host Controller (SDHC)
• I2S module
Timers
• Two 8-channel Flex-Timers (PWM/Motor control)
• Two 2-channel FlexTimers (PWM/Quad decoder)
• 32-bit PITs and 16-bit low-power timers
• Real-time clock
• Programmable delay block
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
• 48 MHz Internal Reference Clock (IRC48M)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MK24FN1M0VLL12
1 MB
256
66
MK24FN1M0VDC12
1 MB
256
83
MK24FN1M0VLQ12
1 MB
256
100
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K60PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K24P144M120SF5RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
K24P144M120SF51
Package
drawing
Package dimensions are provided in package drawings.
• 100-pin LQFP:
98ASS233081
• XFBGA 121-pin:
98ASA00595D1
• LQFP 144-pin:
98ASS23177W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Kinetis K24 Family
ARM ® Cortex™-M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
RAM
Phaselocked loop
Serial
programming
interface
FlexBus
Frequencylocked loop
Debug
interfaces
DSP
DMA
Interrupt
controller
Floating
point
Low-leakage
wakeup
Low/high
frequency
oscillators
Memory
Protection
Internal
reference
clocks
Communication Interfaces
Security
Analog
Timers
CRC
16-bit ADC
x2
Timers
x2 (8ch)
x2 (2ch)
I C
x3
I S
x1
Random
number
generator
Analog
comparator
x3
Programmable
delay block
UART
x6
USB OTG
LS/FS
Hardware
encryption
6-bit DAC
x3
Periodic
interrupt
timers
SPI
x3
USB LS/FS
transceiver
12-bit DAC
x2
Low power
timer
SDHC
x1
USB charger
detect
Voltage
reference
Independent
real-time
clock
CAN
x1
USB voltage
regulator
and Integrity
2
Human-Machine
Interface (HMI)
2
GPIO
Figure 1. K24 block diagram
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1
Voltage and current operating requirements.....6
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 8
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 11
2.2.6
EMC radiated emissions operating behaviors...16
2.2.7
Designing with radiated emissions in mind....... 17
2.2.8
Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1
Device clock specifications............................... 17
2.3.2
General switching specifications....................... 18
2.4 Thermal specifications..................................................... 19
2.4.1
Thermal operating requirements....................... 19
2.4.2
Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1
Debug trace timing specifications..................... 21
3.1.2
JTAG electricals................................................ 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1
MCG specifications........................................... 25
3.3.2
IRC48M specifications...................................... 27
3.3.3
Oscillator electrical specifications..................... 28
3.3.4
32 kHz oscillator electrical characteristics.........30
3.4 Memories and memory interfaces................................... 31
3.4.1
Flash (FTFE) electrical specifications............... 31
3.4.2
EzPort switching specifications......................... 33
3.4.3
Flexbus switching specifications....................... 34
3.5 Security and integrity modules........................................ 37
3.6 Analog............................................................................. 37
3.6.1
ADC electrical specifications.............................38
4
NXP Semiconductors
4
5
6
7
8
3.6.2
CMP and 6-bit DAC electrical specifications.....42
3.6.3
12-bit DAC electrical characteristics................. 44
3.6.4
Voltage reference electrical specifications........ 47
3.7 Timers..............................................................................48
3.8 Communication interfaces............................................... 48
3.8.1
USB electrical specifications............................. 49
3.8.2
USB DCD electrical specifications.................... 49
3.8.3
USB VREG electrical specifications..................49
3.8.4
CAN switching specifications............................ 50
3.8.5
DSPI switching specifications (limited voltage
range)................................................................50
3.8.6
DSPI switching specifications (full voltage
range)................................................................52
3.8.7
Inter-Integrated Circuit Interface (I2C) timing....54
3.8.8
UART switching specifications.......................... 55
3.8.9
SDHC specifications......................................... 56
3.8.10 I2S switching specifications.............................. 56
Dimensions............................................................................. 62
4.1 Obtaining package dimensions....................................... 62
Pinout...................................................................................... 63
5.1 K24 Signal Multiplexing and Pin Assignments.................63
5.2 Unused analog interfaces................................................ 69
5.3 K24 Pinouts..................................................................... 70
Ordering parts......................................................................... 73
6.1 Determining valid orderable parts....................................73
Part identification.....................................................................74
7.1 Description.......................................................................74
7.2 Format............................................................................. 74
7.3 Fields............................................................................... 74
7.4 Example...........................................................................75
Terminology and guidelines.................................................... 75
8.1 Definitions........................................................................ 75
8.2 Examples......................................................................... 76
8.3 Typical-value conditions.................................................. 76
8.4 Relationship between ratings and operating
requirements....................................................................77
8.5 Guidelines for ratings and operating requirements..........77
9 Revision History...................................................................... 78
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
5
NXP Semiconductors
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
–0.3
5.5
V
–0.3
VBAT + 0.3
V
Analog1, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
VDRTC_WAKEU RTC Wakeup input voltage
P
VAIO
ID
VDDA
Analog supply voltage
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VREGIN
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
IICAIO
IICcont
1
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
mA
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
Notes
VBAT voltage required to retain the VBAT register file
4
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VINVAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
4. Open drain outputs must be pulled to VDD.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
7
NXP Semiconductors
General
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
Notes
Output high voltage — high drive strength
Table continues on the next page...
8
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
—
100
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
—
100
mA
Notes
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOH_RTC_WA Output high voltage — high drive strength
KEUP
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
IOH_RTC_WAK Output high current total for RTC_WAKEUP pins
EUP
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
Output low current total for all ports
VOL_RTC_WA Output low voltage — high drive strength
KEUP
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
IOL_RTC_WAK Output low current total for RTC_WAKEUP pins
EUP
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
1
IIN
Input leakage current (per pin) at 25°C
—
0.025
μA
1
IIN_RTC_WAK Input leakage current (per RTC_WAKEUP pin) for full
temperature range
EUP
—
1
μA
IIN_RTC_WAK Input leakage current (per RTC_WAKEUP pin) at
25°C
EUP
—
0.025
μA
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
9
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
IOZ
Description
Hi-Z (off-state) leakage current (per pin)
IOZ_RTC_WAK Hi-Z (off-state) leakage current (per RTC_WAKEUP
pin)
EUP
Min.
Max.
Unit
—
0.25
μA
—
0.25
μA
Notes
RPU
Internal pullup resistors (except RTC_WAKEUP pins)
20
50
kΩ
2
RPD
Internal pulldown resistors (except RTC_WAKEUP
pins)
20
50
kΩ
3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
10
NXP Semiconductors
Min.
Max.
Unit
—
300
μs
—
156
μs
—
156
μs
—
78
μs
—
78
μs
—
4.8
μs
—
4.5
μs
—
4.5
μs
Notes
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
31.1
36.65
mA
—
31
36.75
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
42.7
48.35
mA
• @ 25°C
—
40
41.60
mA
• @ 105°C
—
48.33
51.50
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
17.9
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
6.9
—
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
—
1.0
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
—
1.7
—
mA
7
—
0.678
—
mA
8
• @ –40 to 25°C
—
0.49
1.24
mA
• @ 70°C
—
1.18
4.3
mA
• @ 105°C
—
3.0
12.5
mA
• @ –40 to 25°C
—
57
139.31
μA
• @ 70°C
—
291
679.33
μA
• @ 105°C
—
927.3
1869.85
μA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP
IDD_VLPS
IDD_LLS
Stop mode current at 3.0 V
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
9
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• @ –40 to 25°C
—
5.8
10.48
μA
• @ 70°C
—
26.7
47.99
μA
• @ 105°C
—
114.9
196.49
μA
• @ –40 to 25°C
—
4.4
5.54
μA
• @ 70°C
—
21
36.46
μA
• @ 105°C
—
90.2
150.17
μA
• @ –40 to 25°C
—
2.1
2.34
μA
• @ 70°C
—
6.84
10.36
μA
• @ 105°C
—
29.4
46.74
μA
• @ –40 to 25°C
—
0.817
0.86
μA
• @ 70°C
—
3.97
5.77
μA
• @ 105°C
—
21.3
33.99
μA
—
0.52
0.62
μA
—
3.67
5.7
μA
—
21.20
34.9
μA
—
0.339
0.412
μA
—
3.36
4.2
μA
—
20.3
29.9
μA
—
0.16
0.19
μA
—
0.55
0.72
μA
—
2.5
3.68
μA
—
0.18
0.21
μA
—
0.66
0.86
μA
—
2.92
4.30
μA
Notes
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32 kHz disabled
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
12
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_VBAT
Average current when CPU is not accessing
RTC registers
Typ.
Max.
Unit
Notes
10
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.59
0.70
μA
—
1.0
1.30
μA
—
3.0
4.42
μA
—
0.71
0.84
μA
—
1.22
1.59
μA
—
3.5
5.15
μA
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured
for PEE mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Data reflects devices with 256 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
13
NXP Semiconductors
General
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol
Description
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
Temperature (°C)
Unit
-40
25
50
70
85
105
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
nA
STOP
I48MIRC
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
OSCERCLK (4 MHz external crystal)
214
237
246
254
260
268
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
MCGIRCLK (4 MHz internal reference
clock)
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
14
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Run Mode Current Consumption vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
40.00E-03
35.00E-03
Current Consumption on VDD (A)
30.00E-03
25.00E-03
All Peripheral Clk Gates
20.00E-03
ALLOFF
ALLON
15.00E-03
10.00E-03
5.00E-03
000.00E+00
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-1
'1-1-2
'1-2-3
'1-2-4
'1-2-5
1
2
4
6.25
12.5
25
50
75
100
120
Clk Ratio
Core-BusFlaxbus-Flash
Core Freq (MHz)
Figure 3. Run mode supply current vs. core frequency
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
15
NXP Semiconductors
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
1.40E-03
1.20E-03
Current Consumption on VDD (A)
1.00E-03
800.00E-06
All Peripheral Clk Gates
ALLOFF
ALLON
600.00E-06
400.00E-06
200.00E-06
000.00E+00
'1-1-2
'1-1-1
'1-2-4
1
'1-1-4
'1-1-2
'1-2-4
2
'1-1-4
Clk Ratio
Core-Bus-Flash
Core Freq (MHz)
4
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
144 LQFP
VRE1
Radiated emissions voltage, band 1
0.15–50
16
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
22
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
21
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
16
dBμV
IEC level
0.15–1000
L
—
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
16
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
—
4
MHz
Notes
Normal run mode
fSYS
fBUS
FB_CLK
VLPR
fSYS
System and core clock
mode1
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
17
NXP Semiconductors
General
Table 10. Device clock specifications (continued)
Symbol
Min.
Max.
Unit
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
0.8
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
fLPTMR_ERCLK LPTMR external reference clock
—
16
MHz
fFlexCAN_ERCLK FlexCAN external reference clock
—
8
MHz
fBUS
FB_CLK
fLPTMR_pin
Description
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength) - 3 V
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
8
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
18
ns
• 2.7 ≤ VDD ≤ 3.6V
—
12
ns
• Slew enabled
Port rise and fall time (high drive strength) - 5 V
4
• Slew disabled
Table continues on the next page...
18
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
General
Table 11. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
• 1.71 ≤ VDD ≤ 2.7V
—
6
ns
• 2.7 ≤ VDD ≤ 3.6V
—
4
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
14
ns
Notes
• Slew enabled
Port rise and fall time (low drive strength) - 3 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
24
ns
• 2.7 ≤ VDD ≤ 3.6V
—
16
ns
• Slew enabled
Port rise and fall time (low drive strength) - 5 V
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
17
ns
• 2.7 ≤ VDD ≤ 3.6V
—
10
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
20
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 25 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
TA
Description
Min.
Max.
Unit
Die junction temperature
–40
125
°C
–40
105
°C
Ambient
temperature1
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
19
NXP Semiconductors
General
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type
Symbol
Description
144 LQFP
121 XFBGA
100 LQFP
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
51
33.3
51
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient
(natural
convection)
43
21.1
39
°C/W
1
Single-layer
(1s)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
42
26.2
41
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
36
17.8
32
°C/W
1
—
RθJB
Thermal
resistance,
junction to
board
30
16.3
24
°C/W
2
—
RθJC
Thermal
resistance,
junction to
case
11
12
11
°C/W
3
—
ΨJT
Thermal
2
characterizati
on parameter,
junction to
package top
outside center
(natural
convection)
0.2
2
°C/W
4
20
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
1.5
—
ns
Th
Data hold
1
—
ns
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 5. TRACE_CLKOUT specifications
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
21
NXP Semiconductors
Peripheral operating requirements and behaviors
TRACE_CLKOUT
Ts
Ts
Th
Th
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.6
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 16. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
22
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 16. JTAG full voltage range electricals (continued)
Symbol
J1
Description
Min.
Max.
TCLK frequency of operation
Unit
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
2.9
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
—
22.1
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
24
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Iints
Internal reference (slow clock) current
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 0.5
±2
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
±1
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
Iintf
1
,2
1
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
120
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
8
8
9
• fvco = 48 MHz
—
120
—
ps
• fvco = 120 MHz
—
80
—
ps
PLL accumulated jitter over 1µs (RMS)
9
Table continues on the next page...
26
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 17. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• fvco = 48 MHz
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
10-6
—
150 ×
+ 1075(1/
fpll_ref)
Notes
s
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 IRC48M specifications
Table 18. IRC48M specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDD48M
Supply current
—
400
500
μA
firc48m
Internal reference frequency
—
48
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
• Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Notes
1
—
± 0.5
± 1.5
—
± 0.5
± 2.0
%firc48m
1
—
± 0.5
± 1.5
%firc48m
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 18. IRC48M specifications (continued)
Symbol
Description
Min.
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0 to 85 °C
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Typ.
Max.
Unit
1
—
± 0.5
± 1.0
%firc48m
Δfirc48m_cl
Closed loop total deviation of IRC48M frequency
over voltage and temperature
—
—
± 0.1
%fhost
Jcyc_irc48m
Period Jitter (RMS)
—
35
150
ps
Startup time
—
2
3
μs
tirc48mst
Notes
2
3
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean ± 3 sigma)
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by setting USB_CLK_RECOVER_IRC_EN[IRC_EN]=1.
3.3.3 Oscillator electrical specifications
3.3.3.1
Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Table continues on the next page...
28
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
5
Vpp
1.
2.
3.
4.
5.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
29
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.3.2
Symbol
Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1
32 kHz oscillator DC electrical specifications
Table 21. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
—
100
—
MΩ
RF
Internal feedback resistor
Table continues on the next page...
30
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 21. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.4.2
Symbol
32 kHz oscillator frequency specifications
Table 22. 32 kHz oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
fec_extal32 Externally provided input clock frequency
—
32.768
—
kHz
2
vec_extal32 Externally provided input clock amplitude
700
—
VBAT
mV
2, 3
fosc_lo
tstart
Description
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm8
thversscr
Program Phrase high-voltage time
—
7.5
18
μs
Erase Flash Sector high-voltage time
—
13
113
ms
1
—
416
3616
ms
1
thversblk512k Erase Flash Block high-voltage time for 512 KB
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Notes
31
NXP Semiconductors
Peripheral operating requirements and behaviors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Symbol
Flash timing specifications — commands
Table 24. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
—
—
1.8
ms
Notes
Read 1s Block execution time
trd1blk512k
• 512 KB program flash
trd1sec4k
Read 1s Section execution time (4 KB flash)
—
—
100
μs
1
tpgmchk
Program Check execution time
—
—
95
μs
1
trdrsrc
Read Resource execution time
—
—
40
μs
1
tpgm8
Program Phrase execution time
—
90
150
μs
Erase Flash Block execution time
tersblk512k
tersscr
• 512 KB program flash
Erase Flash Sector execution time
2
—
435
3700
ms
—
15
115
ms
—
—
3.4
ms
2
Read 1s All Blocks execution time
trd1alln
trdonce
• Program flash only devices
Read Once execution time
—
—
30
μs
Program Once execution time
—
70
—
μs
tersall
Erase All Blocks execution time
—
870
7400
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1
Swap Control execution time
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
IDD_ERS
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
32
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.4.1.4
Symbol
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3.4.2 EzPort switching specifications
Table 27. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
18
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
33
NXP Semiconductors
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 11. EzPort Timing Diagram
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given
in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency
may be the same as the internal system bus frequency or an integer divider of that
frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can
be derived from these values.
Table 28. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
—
11.5
ns
1
FB3
Address, data, and control output hold
0.5
—
ns
1
FB4
Data and FB_TA input setup
8.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
34
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 29. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
FB_CLK
MHz
1/FB_CLK
—
ns
Frequency of operation
Notes
FB1
Clock period
FB2
Address, data, and control output valid
—
13.5
ns
1
FB3
Address, data, and control output hold
0
—
ns
1
FB4
Data and FB_TA input setup
15.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
35
NXP Semiconductors
Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
FB3
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
electricals_read.svg
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
S0
S1
S2
S3
S0
Figure 12. FlexBus read timing diagram
36
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
electricals_write.svg
FB4
TSIZ
Figure 13. FlexBus write timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
37
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 30 and Table 31 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1
16-bit ADC operating conditions
Table 30. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
• 16-bit mode
—
8
10
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
RADIN
RAS
Input series
resistance
Notes
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
ksps
Continuous conversions
enabled, subsequent
conversion time
38
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 14. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
See Reference Manual chapter for sample times
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
TUE
DNL
INL
EFS
EQ
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
Notes
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN = VDDA5
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
Integral non-linearity
Full-scale error
Quantization error
Effective number of
bits
–0.3 to
0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB4
16-bit differential mode
6
• Avg = 32
12.8
14.5
• Avg = 4
11.9
13.8
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise plus See ENOB
distortion
Total harmonic
distortion
12.2
13.9
11.4
13.1
—
—
6.02 × ENOB + 1.76
16-bit differential mode
• Avg = 32
bits
bits
dB
dB
—
-94
7
—
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
—
-85
82
95
16-bit differential mode
• Avg = 32
16-bit single-ended mode
78
—
—
dB
—
dB
7
90
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's
voltage and
Table continues on the next page...
40
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Symbol Description
Typ.2
Min.
Max.
Unit
Notes
current
operating
ratings)
Temp sensor slope
VTEMP25 Temp sensor
voltage
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1, PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1, PMODE=0)
80
250
600
ns
—
—
40
μs
—
7
—
μA
Analog comparator initialization
IDAC6b
delay2
6-bit DAC current adder (enabled)
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
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NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
43
NXP Semiconductors
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
44
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and highspeed mode
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
AC
Offset aging coefficient
—
—
100
μV/yr
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
45
NXP Semiconductors
Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 19. Typical INL error vs. digital code
46
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature °C
Figure 20. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
—
Operating temperature
range of the device
°C
—
100
nF
1, 2
TA
Temperature
CL
Output load capacitance
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
47
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 36. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature= 25 °C
1.192
1.195
1.198
V
1
Vout
Voltage reference output with user trim at
nominal VDDA and temperature= 25 °C
1.1945
1.195
1.1955
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
2
15
mV
1
Ibg
Bandgap only current
—
60
80
µA
1
Ilp
Low-power buffer current
—
180
360
uA
1
Ihp
High-power buffer current
—
480
960
mA
1
µV
1, 2
—
ΔVLOAD
Load regulation
• current = ± 1.0 mA
Tstup
Buffer startup time
—
200
—
—
—
100
µs
35
ms
2
mV
Tchop_osc_st Internal bandgap start-up delay with chop
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
0.5
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 37. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 38. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
Notes
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
48
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org.
NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter or
signaling rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the
USB clock recovery mode is enabled. It does not meet the
USB signaling rate specifications for certification in Host
mode operation.
3.8.2 USB DCD electrical specifications
Table 39. USB0 DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
3.8.3 USB VREG electrical specifications
Table 40. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
Notes
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
49
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 40. USB VREG electrical specifications
(continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
125
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and
temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
3
3.3
3.6
V
2.1
2.8
3.6
V
2.1
—
3.6
V
1.76
2.2
8.16
μF
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
• Standby mode
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
COUT
External output capacitor
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.4 CAN switching specifications
See General switching specifications.
50
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Peripheral operating requirements and behaviors
3.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 41. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS4
DS8
First data
DSPI_SOUT
DS1
DS2
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 21. DSPI classic SPI timing — master mode
Table 42. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
2.7
3.6
V
151
MHz
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 42. Slave mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 22. DSPI classic SPI timing — slave mode
3.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 43. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
—
3.6
V
1
15
MHz
Table continues on the next page...
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Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 43. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
21
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS1
DS2
DS4
DS8
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 23. DSPI classic SPI timing — master mode
Table 44. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
7.5
MHz
8 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
23.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
4
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
21
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
53
NXP Semiconductors
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 24. DSPI classic SPI timing — slave mode
3.8.7 Inter-Integrated Circuit Interface (I2C) timing
Table 45. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003, 6
Data set-up time
Rise time of SDA and SCL signals
tr
—
1000
—
ns
7
300
ns
6
20 +0.1Cb
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
54
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 46. I 2C 1 Mbps timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
tLOW
0.5
—
HIGH period of the SCL clock
tHIGH
0.26
—
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
Data hold time for I2C bus devices
tHD; DAT
0
—
µs
Data set-up time
tSU; DAT
50
Rise time of SDA and SCL signals
tr


µs
µs
µs
—
ns
,2
120
ns
2
120
ns
20 +0.1Cb
Fall time of SDA and SCL signals
tf
20 +0.1Cb
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START
condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 25. Timing definition for devices on the I2C bus
3.8.8 UART switching specifications
See General switching specifications.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
55
NXP Semiconductors
Peripheral operating requirements and behaviors
3.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 47. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
8.3
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5.5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 26. SDHC timing
56
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
3.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 48. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
80
—
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
0
—
ns
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
17
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 27. I2S timing — master mode
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
57
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 49. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
80
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
5
—
ns
S14
I2S_FS input hold after I2S_BCLK
2
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
19.5
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
5
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
21
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 28. I2S timing — slave modes
3.8.10.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 50. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
Table continues on the next page...
58
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 50. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
22.5
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 29. I2S/SAI timing — master modes
Table 51. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
7
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
59
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 51. I2S/SAI slave mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
25.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
3
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 30. I2S/SAI timing — slave modes
3.8.10.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
Table continues on the next page...
60
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Peripheral operating requirements and behaviors
Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
45
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 31. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
11
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
ns
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
61
NXP Semiconductors
Dimensions
Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S18
I2S_RXD hold after I2S_RX_BCLK
11
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1 —
72
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 32. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
100-pin LQFP
98ASS23308W
121-pin XFBGA
98ASA00595D
144-pin LQFP
98ASS23177W
62
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
5 Pinout
5.1 K24 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
—
L7
—
RTC_
RTC_
RTC_
WAKEUP_B WAKEUP_B WAKEUP_B
—
B11
—
PTB12
DISABLED
PTB12
UART3_
RTS_b
FTM1_CH0
FTM0_CH4
FTM1_QD_
PHA
—
C11
—
PTB13
DISABLED
PTB13
UART3_
CTS_b
FTM1_CH1
FTM0_CH5
FTM1_QD_
PHB
—
A11
—
NC
NC
NC
—
K3
—
NC
NC
NC
—
H4
—
NC
NC
NC
1
E4
1
PTE0
ADC1_
SE4a
ADC1_
SE4a
PTE0
SPI1_PCS1 UART1_TX
SDHC0_D1 TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
2
E3
2
PTE1/
LLWU_P0
ADC1_
SE5a
ADC1_
SE5a
PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 TRACE_D3 I2C1_SCL
SPI1_SIN
3
E2
3
PTE2/
LLWU_P1
ADC0_DP2/ ADC0_DP2/ PTE2/
ADC1_
ADC1_
LLWU_P1
SE6a
SE6a
SPI1_SCK
UART1_
CTS_b
SDHC0_
DCLK
TRACE_D2
4
F4
4
PTE3
ADC0_DM2/ ADC0_DM2/ PTE3
ADC1_
ADC1_
SE7a
SE7a
SPI1_SIN
UART1_
RTS_b
SDHC0_
CMD
TRACE_D1
5
E7
—
VDD
VDD
VDD
6
F7
—
VSS
VSS
VSS
7
H7
5
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX
8
G4
6
PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
FTM3_CH0
9
F3
7
PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_
CTS_b
I2S0_MCLK
FTM3_CH1
10
—
—
PTE7
DISABLED
PTE7
UART3_
RTS_b
I2S0_RXD0
FTM3_CH2
11
—
—
PTE8
DISABLED
PTE8
I2S0_RXD1 UART5_TX
I2S0_RX_
FS
FTM3_CH3
12
—
—
PTE9
DISABLED
PTE9
I2S0_TXD1
UART5_RX I2S0_RX_
BCLK
FTM3_CH4
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
EzPort
SPI1_SOUT
SDHC0_D3 TRACE_D0
USB_SOF_
OUT
63
NXP Semiconductors
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
13
—
—
PTE10
DISABLED
PTE10
UART5_
CTS_b
I2S0_TXD0
FTM3_CH5
14
—
—
PTE11
DISABLED
PTE11
UART5_
RTS_b
I2S0_TX_
FS
FTM3_CH6
15
—
—
PTE12
DISABLED
PTE12
I2S0_TX_
BCLK
FTM3_CH7
16
E6
8
VDD
VDD
VDD
17
G7
9
VSS
VSS
VSS
18
L6
—
VSS
VSS
VSS
19
F1
10
USB0_DP
USB0_DP
USB0_DP
20
F2
11
USB0_DM
USB0_DM
USB0_DM
21
G1
12
VOUT33
VOUT33
VOUT33
22
G2
13
VREGIN
VREGIN
VREGIN
23
H1
14
ADC0_DP1
ADC0_DP1
ADC0_DP1
24
H2
15
ADC0_DM1 ADC0_DM1 ADC0_DM1
25
J1
16
ADC1_DP1
26
J2
17
ADC1_DM1 ADC1_DM1 ADC1_DM1
27
K1
18
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
28
K2
19
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
29
L1
20
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
30
L2
21
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
31
F5
22
VDDA
VDDA
VDDA
32
G5
23
VREFH
VREFH
VREFH
33
G6
24
VREFL
VREFL
VREFL
34
F6
25
VSSA
VSSA
VSSA
35
J3
—
ADC1_
SE16/
CMP2_IN2/
ADC0_
SE22
ADC1_
SE16/
CMP2_IN2/
ADC0_
SE22
ADC1_
SE16/
CMP2_IN2/
ADC0_
SE22
36
H3
—
ADC0_
SE16/
CMP1_IN2/
ADC0_
SE21
ADC0_
SE16/
CMP1_IN2/
ADC0_
SE21
ADC0_
SE16/
CMP1_IN2/
ADC0_
SE21
37
L3
26
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
64
NXP Semiconductors
ADC1_DP1
ALT7
EzPort
ADC1_DP1
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
38
K5
27
DAC0_OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_OUT/
CMP1_IN3/
ADC0_
SE23
39
K4
—
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_
SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_
SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_
SE23
40
L4
28
XTAL32
XTAL32
XTAL32
41
L5
29
EXTAL32
EXTAL32
EXTAL32
42
K6
30
VBAT
VBAT
VBAT
43
—
—
VDD
VDD
VDD
44
—
—
VSS
VSS
VSS
45
H5
31
PTE24
ADC0_
SE17
ADC0_
SE17
PTE24
UART4_TX
I2C0_SCL
EWM_
OUT_b
46
J5
32
PTE25
ADC0_
SE18
ADC0_
SE18
PTE25
UART4_RX
I2C0_SDA
EWM_IN
47
H6
33
PTE26
DISABLED
PTE26
UART4_
CTS_b
48
—
—
PTE27
DISABLED
PTE27
UART4_
RTS_b
49
—
—
PTE28
DISABLED
PTE28
50
J6
34
PTA0
JTAG_
TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
JTAG_
TCLK/
SWD_CLK
EZP_CLK
51
H8
35
PTA1
JTAG_TDI/
EZP_DI
PTA1
UART0_RX FTM0_CH6
JTAG_TDI
EZP_DI
52
J7
36
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_
SWO
53
H9
37
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
54
J8
38
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
55
K7
39
PTA5
DISABLED
PTA5
USB_CLKIN FTM0_CH2
56
E5
40
VDD
VDD
VDD
57
G3
41
VSS
VSS
VSS
58
—
—
PTA6
DISABLED
PTA6
FTM0_CH3
59
—
—
PTA7
ADC0_
SE10
PTA7
FTM0_CH4
ADC0_
SE10
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
RTC_
CLKOUT
USB_CLKIN
CMP2_OUT I2S0_TX_
BCLK
JTAG_
TRST_b
CLKOUT
TRACE_
CLKOUT
EZP_CS_b
TRACE_D3
65
NXP Semiconductors
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
60
—
—
PTA8
ADC0_
SE11
61
—
—
PTA9
62
J9
—
63
J4
64
ALT0
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
PTA8
FTM1_CH0
FTM1_QD_ TRACE_D2
PHA
DISABLED
PTA9
FTM1_CH1
FTM1_QD_ TRACE_D1
PHB
PTA10
DISABLED
PTA10
FTM2_CH0
FTM2_QD_ TRACE_D0
PHA
—
PTA11
DISABLED
PTA11
FTM2_CH1
I2C2_SDA
FTM2_QD_
PHB
K8
42
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2C2_SCL
I2S0_TXD0
FTM1_QD_
PHA
65
L8
43
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
I2C2_SDA
I2S0_TX_
FS
FTM1_QD_
PHB
66
K9
44
PTA14
DISABLED
PTA14
SPI0_PCS0 UART0_TX
I2C2_SCL
I2S0_RX_
BCLK
I2S0_TXD1
67
L9
45
PTA15
DISABLED
PTA15
SPI0_SCK
68
J10
46
PTA16
DISABLED
PTA16
SPI0_SOUT UART0_
CTS_b/
UART0_
COL_b
I2S0_RX_
FS
69
H10
47
PTA17
ADC1_
SE17
ADC1_
SE17
PTA17
SPI0_SIN
I2S0_MCLK
70
L10
48
VDD
VDD
VDD
71
K10
49
VSS
VSS
VSS
72
L11
50
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2 FTM_
CLKIN0
73
K11
51
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0 FTM_
CLKIN1
74
J11
52
RESET_b
RESET_b
RESET_b
75
—
—
PTA24
DISABLED
PTA24
FB_A29
76
—
—
PTA25
DISABLED
PTA25
FB_A28
77
—
—
PTA26
DISABLED
PTA26
FB_A27
78
—
—
PTA27
DISABLED
PTA27
FB_A26
79
—
—
PTA28
DISABLED
PTA28
FB_A25
80
H11
—
PTA29
DISABLED
PTA29
FB_A24
81
G11
53
PTB0/
LLWU_P5
ADC0_SE8/ ADC0_SE8/ PTB0/
ADC1_SE8 ADC1_SE8 LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
82
G10
54
PTB1
ADC0_SE9/ ADC0_SE9/ PTB1
ADC1_SE9 ADC1_SE9
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
83
G9
55
PTB2
ADC0_
SE12
ADC0_
SE12
PTB2
I2C0_SCL
UART0_
RTS_b
FTM0_FLT3
84
G8
56
PTB3
ADC0_
SE13
ADC0_
SE13
PTB3
I2C0_SDA
UART0_
CTS_b/
UART0_
COL_b
FTM0_FLT0
66
NXP Semiconductors
ADC0_
SE11
ALT1
UART0_RX
UART0_
RTS_b
EzPort
I2S0_RXD0
I2S0_RXD1
LPTMR0_
ALT1
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
85
—
—
PTB4
ADC1_
SE10
ADC1_
SE10
PTB4
FTM1_FLT0
86
—
—
PTB5
ADC1_
SE11
ADC1_
SE11
PTB5
FTM2_FLT0
87
F11
—
PTB6
ADC1_
SE12
ADC1_
SE12
PTB6
FB_AD23
88
E11
—
PTB7
ADC1_
SE13
ADC1_
SE13
PTB7
FB_AD22
89
D11
—
PTB8
DISABLED
PTB8
UART3_
RTS_b
FB_AD21
90
E10
57
PTB9
DISABLED
PTB9
SPI1_PCS1 UART3_
CTS_b
FB_AD20
91
D10
58
PTB10
ADC1_
SE14
ADC1_
SE14
PTB10
SPI1_PCS0 UART3_RX
FB_AD19
FTM0_FLT1
92
C10
59
PTB11
ADC1_
SE15
ADC1_
SE15
PTB11
SPI1_SCK
FB_AD18
FTM0_FLT2
93
—
60
VSS
VSS
VSS
94
—
61
VDD
VDD
VDD
95
B10
62
PTB16
DISABLED
PTB16
SPI1_SOUT UART0_RX FTM_
CLKIN0
FB_AD17
EWM_IN
96
E9
63
PTB17
DISABLED
PTB17
SPI1_SIN
UART0_TX
FTM_
CLKIN1
FB_AD16
EWM_
OUT_b
97
D9
64
PTB18
DISABLED
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15
FTM2_QD_
PHA
98
C9
65
PTB19
DISABLED
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_
FS
FB_OE_b
FTM2_QD_
PHB
99
F10
66
PTB20
DISABLED
PTB20
SPI2_PCS0
FB_AD31
CMP0_OUT
100
F9
67
PTB21
DISABLED
PTB21
SPI2_SCK
FB_AD30
CMP1_OUT
101
F8
68
PTB22
DISABLED
PTB22
SPI2_SOUT
FB_AD29
CMP2_OUT
102
E8
69
PTB23
DISABLED
PTB23
SPI2_SIN
103
B9
70
PTC0
ADC0_
SE14
ADC0_
SE14
PTC0
SPI0_PCS4 PDB0_
EXTRG
USB_SOF_ FB_AD14
OUT
I2S0_TXD1
104
D8
71
PTC1/
LLWU_P6
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6
SPI0_PCS3 UART1_
RTS_b
FTM0_CH0
FB_AD13
I2S0_TXD0
105
C8
72
PTC2
ADC0_
SE4b/
CMP1_IN0
ADC0_
SE4b/
CMP1_IN0
PTC2
SPI0_PCS2 UART1_
CTS_b
FTM0_CH1
FB_AD12
I2S0_TX_
FS
106
B8
73
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
107
—
74
VSS
VSS
VSS
108
—
75
VDD
VDD
VDD
109
A8
76
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX
FB_AD11
CMP1_OUT
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
UART3_TX
SPI0_PCS5
EzPort
FB_AD28
FTM0_CH3
67
NXP Semiconductors
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
110
D7
77
PTC5/
LLWU_P9
DISABLED
111
C7
78
PTC6/
LLWU_P10
CMP0_IN0
112
B7
79
PTC7
113
A7
80
114
D6
115
ALT0
ALT1
ALT2
ALT3
ALT5
ALT6
PTC5/
LLWU_P9
SPI0_SCK
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT PDB0_
EXTRG
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
PTC8
ADC1_
SE4b/
CMP0_IN2
ADC1_
SE4b/
CMP0_IN2
PTC8
FTM3_CH4
I2S0_MCLK FB_AD7
81
PTC9
ADC1_
SE5b/
CMP0_IN3
ADC1_
SE5b/
CMP0_IN3
PTC9
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6
C6
82
PTC10
ADC1_
SE6b
ADC1_
SE6b
PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_
FS
FB_AD5
116
C5
83
PTC11/
LLWU_P11
ADC1_
SE7b
ADC1_
SE7b
PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1 FB_RW_b
117
B6
84
PTC12
DISABLED
PTC12
UART4_
RTS_b
FB_AD27
118
A6
85
PTC13
DISABLED
PTC13
UART4_
CTS_b
FB_AD26
119
A5
86
PTC14
DISABLED
PTC14
UART4_RX
FB_AD25
120
B5
87
PTC15
DISABLED
PTC15
UART4_TX
FB_AD24
121
—
88
VSS
VSS
VSS
122
—
89
VDD
VDD
VDD
123
D5
90
PTC16
DISABLED
PTC16
UART3_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b
124
C4
91
PTC17
DISABLED
PTC17
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_
0_b
125
B4
92
PTC18
DISABLED
PTC18
UART3_
RTS_b
FB_TBST_
b/
FB_CS2_b/
FB_BE15_
8_BLS23_
16_b
126
A4
—
PTC19
DISABLED
PTC19
UART3_
CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_0_
BLS31_24_
b
127
D4
93
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
68
NXP Semiconductors
LPTMR0_
ALT2
ALT4
ALT7
I2S0_RXD0 FB_AD10
CMP0_OUT FTM0_CH2
I2S0_RX_
BCLK
FB_AD9
I2S0_MCLK
USB_SOF_ I2S0_RX_
OUT
FS
FB_AD8
SPI0_PCS0 UART2_
RTS_b
FTM3_CH0
EzPort
FTM2_FLT0
FTM3_FLT0
FB_ALE/
FB_CS1_b/
FB_TS_b
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Pinout
144 121 100
LQFP XFB LQFP
GA
Pin Name
Default
128
D3
94
PTD1
ADC0_
SE5b
129
C3
95
PTD2/
LLWU_P13
130
B3
96
131
A3
132
ALT0
ADC0_
SE5b
ALT1
ALT2
ALT3
UART2_
CTS_b
ALT4
ALT5
FTM3_CH1
FB_CS0_b
ALT6
ALT7
PTD1
SPI0_SCK
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT UART2_RX FTM3_CH2
FB_AD4
I2C0_SCL
PTD3
DISABLED
PTD3
SPI0_SIN
FTM3_CH3
FB_AD3
I2C0_SDA
97
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1 UART0_
RTS_b
FTM0_CH4
FB_AD2
EWM_IN
SPI1_PCS0
A2
98
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI0_PCS2 UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
FB_AD1
EWM_
OUT_b
SPI1_SCK
133
B2
99
PTD6/
LLWU_P15
ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6
FB_AD0
FTM0_FLT0 SPI1_SOUT
134
—
—
VSS
VSS
VSS
135
—
—
VDD
VDD
VDD
136
A1
100
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
137
A10
—
PTD8
DISABLED
PTD8
I2C0_SCL
UART5_RX
FB_A16
138
A9
—
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17
139
B1
—
PTD10
DISABLED
PTD10
UART5_
RTS_b
FB_A18
140
C2
—
PTD11
DISABLED
PTD11
SPI2_PCS0 UART5_
CTS_b
141
C1
—
PTD12
DISABLED
PTD12
SPI2_SCK
FTM3_FLT0 SDHC0_D4
FB_A20
142
D2
—
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
143
D1
—
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
144
E1
—
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
UART2_TX
FTM0_CH7
EzPort
FTM0_FLT1 SPI1_SIN
SDHC0_
CLKIN
FB_A19
5.2 Unused analog interfaces
Table 54. Unused analog interfaces
Module name
Pins
Recommendation if unused
ADC
ADC0_DP1, ADC0_DM1, ADC1_DP1, Ground
ADC1_DM1, ADC0_DP0/ADC1_DP3,
ADC0_DM0/ADC1_DM3, ADC1_DP0/
ADC0_DP3, ADC1_DM0/ADC0_DM3,
ADC1_SE16/ADC0_SE22,
ADC0_SE16/ADC0_SE21,
ADC1_SE18
DAC 1
DAC0_OUT, DAC1_OUT
USB
VREGIN, USB0_GND,
VOUT332
Float
Connect VREGIN and VOUT33
together and tie to ground through a 10
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
69
NXP Semiconductors
Pinout
Table 54. Unused analog interfaces (continued)
Module name
Pins
Recommendation if unused
kΩ resistor. Do not tie directly to
ground, as this causes a latch-up risk.
USB0_DM, USB0_DP
Float
1. Unused DAC signals do not apply to all parts. See the Pinout section for details.
2. USB0_VBUS and USB0_GND are board level signals
5.3 K24 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
70
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
111
110
109
PTC13
PTC8
PTC14
118
112
PTC15
119
PTC9
VSS
120
113
VDD
121
PTC10
PTC16
122
115
PTC17
123
114
PTC18
124
PTC12
PTC19
125
PTC11/LLWU_P11
PTD0/LLWU_P12
126
116
PTD1
127
117
PTD2/LLWU_P13
VSS
134
128
VDD
135
PTD3
PTD7
136
129
PTD8
137
PTD4/LLWU_P14
PTD9
138
131
PTD10
139
130
PTD11
140
PTD6/LLWU_P15
PTD12
141
PTD5
PTD13
142
132
PTD14
143
133
PTD15
144
Pinout
PTE0
1
108
VDD
PTE1/LLWU_P0
2
107
VSS
PTE2/LLWU_P1
3
106
PTC3/LLWU_P7
PTE3
4
105
PTC2
VDD
5
104
PTC1/LLWU_P6
VSS
6
103
PTC0
PTE4/LLWU_P2
7
102
PTB23
PTE5
8
101
PTB22
PTE6
9
100
PTB21
PTE7
10
99
PTB20
PTE8
11
98
PTB19
PTE9
12
97
PTB18
PTE10
13
96
PTB17
PTE11
14
95
PTB16
PTE12
15
94
VDD
VDD
16
93
VSS
VSS
17
92
PTB11
VSS
18
91
PTB10
USB0_DP
19
90
PTB9
USB0_DM
20
89
PTB8
VOUT33
21
88
PTB7
VREGIN
22
87
PTB6
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD
VSS
PTA6
PTA7
PTA8
PTA9
PTA10
PTA11
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
55
RESET_b
73
PTA5
74
36
54
35
PTA4/LLWU_P3
ADC1_SE16/CMP2_IN2/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
53
PTA24
PTA3
75
52
34
PTA2
PTA25
VSSA
51
PTA26
76
50
77
33
PTA1
32
VREFL
PTA0
VREFH
49
PTA27
PTE28
78
48
31
PTE27
PTA28
VDDA
47
79
PTE26
30
46
PTA29
ADC1_DM0/ADC0_DM3
PTE25
80
45
29
PTE24
PTB0/LLWU_P5
ADC1_DP0/ADC0_DP3
44
81
VSS
28
43
PTB1
ADC0_DM0/ADC1_DM3
VDD
82
42
27
VBAT
PTB2
ADC0_DP0/ADC1_DP3
41
83
EXTAL32
26
40
PTB3
ADC1_DM1
XTAL32
84
39
25
DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23
PTB4
ADC1_DP1
38
PTB5
85
37
86
24
DAC0_OUT/CMP1_IN3/ADC0_SE23
23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
ADC0_DP1
ADC0_DM1
Figure 33. 144 LQFP Pinout Diagram
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
71
NXP Semiconductors
Pinout
1
2
3
4
5
6
7
8
9
10
11
A
PTD7
PTD5
PTD4/
LLWU_P14
PTC19
PTC14
PTC13
PTC8
PTC4/
LLWU_P8
PTD9
PTD8
NC
A
B
PTD10
PTD6/
LLWU_P15
PTD3
PTC18
PTC15
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
PTB16
PTB12
B
C
PTD12
PTD11
PTD2/
LLWU_P13
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
PTB19
PTB11
PTB13
C
D
PTD14
PTD13
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
LLWU_P9
PTC1/
LLWU_P6
PTB18
PTB10
PTB8
D
E
PTD15
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
VDD
VDD
VDD
PTB23
PTB17
PTB9
PTB7
E
F
USB0_DP
USB0_DM
PTE6
PTE3
VDDA
VSSA
VSS
PTB22
PTB21
PTB20
PTB6
F
G
VOUT33
VREGIN
VSS
PTE5
VREFH
VREFL
VSS
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
NC
PTE24
PTE26
PTE4/
LLWU_P2
PTA1
PTA3
PTA17
PTA29
H
PTA11
PTE25
PTA0
PTA2
PTA4/
LLWU_P3
PTA10
PTA16
RESET_b
J
VBAT
PTA5
PTA12
PTA14
VSS
PTA19
K
PTA15
VDD
PTA18
L
9
10
11
ADC0_SE16/
H
ADC0_DP1 ADC0_DM1 CMP1_IN2/
ADC0_SE21
ADC1_SE16/
J
ADC1_DP1 ADC1_DM1 CMP2_IN2/
ADC0_SE22
K
ADC0_DP0/ ADC0_DM0/
ADC1_DP3 ADC1_DM3
L
VREF_OUT/
ADC1_DP0/ ADC1_DM0/ CMP1_IN5/
ADC0_DP3 ADC0_DM3 CMP0_IN5/
ADC1_SE18
1
2
NC
3
DAC1_OUT/
DAC0_OUT/
CMP0_IN4/
CMP1_IN3/
CMP2_IN3/
ADC0_SE23
ADC1_SE23
XTAL32
EXTAL32
VSS
4
5
6
RTC_
PTA13/
WAKEUP_B LLWU_P4
7
8
Figure 34. 121 XFBGA Pinout Diagram
72
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
PTC16
VDD
VSS
PTC15
PTC14
PTC13
PTC12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
89
88
87
86
85
84
83
82
81
80
PTC4/LLWU_P8
PTC17
90
PTC5/LLWU_P9
PTC18
91
76
PTD0/LLWU_P12
92
77
PTD1
93
PTC7
PTD2/LLWU_P13
94
PTC6/LLWU_P10
PTD3
96
95
78
PTD4/LLWU_P14
79
PTD5
98
97
PTD7
PTD6/LLWU_P15
100
99
Ordering parts
PTE0
1
75
VDD
PTE1/LLWU_P0
2
74
VSS
PTE2/LLWU_P1
3
73
PTC3/LLWU_P7
PTE3
4
72
PTC2
PTE4/LLWU_P2
5
71
PTC1/LLWU_P6
PTE5
6
70
PTC0
PTE6
7
69
PTB23
VDD
8
68
PTB22
VSS
9
67
PTB21
PTB20
USB0_DP
10
66
USB0_DM
11
65
PTB19
VOUT33
12
64
PTB18
VREGIN
13
63
PTB17
ADC0_DP1
14
62
PTB16
ADC0_DM1
15
61
VDD
VSS
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
38
RESET_b
51
PTA5
52
25
PTA4/LLWU_P3
24
VSSA
37
VREFL
PTA3
PTB0/LLWU_P5
36
53
PTA2
23
35
VREFH
PTA1
PTB1
34
54
PTA0
22
33
PTB2
VDDA
PTE26
55
32
21
PTE25
PTB3
ADC1_DM0/ADC0_DM3
31
PTB9
56
30
57
20
VBAT
19
ADC1_DP0/ADC0_DP3
PTE24
ADC0_DM0/ADC1_DM3
EXTAL32
PTB10
29
58
28
18
XTAL32
PTB11
ADC0_DP0/ADC1_DP3
27
59
26
60
DAC0_OUT/CMP1_IN3/ADC0_SE23
16
17
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
ADC1_DP1
ADC1_DM1
Figure 35. 100 LQFP Pinout Diagram
6 Ordering parts
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
73
NXP Semiconductors
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MK24
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K24 = USB with high RAM density
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
Table continues on the next page...
74
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Terminology and guidelines
Field
Description
Values
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK24FN1M0VLQ12
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
Table continues on the next page...
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
75
NXP Semiconductors
Terminology and guidelines
Term
Definition
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
8.2 Examples
EX
AM
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
76
NXP Semiconductors
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
Terminology and guidelines
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
Supply voltage
3.3
V
8.4 Relationship between ratings and operating requirements
.)
)
era
Op
g
tin
ng
)
in.
(m
i
rat
in.
(m
g
tin
era
Op
t
en
rem
ax
(m
.)
ui
req
g
tin
era
Op
ng
i
rat
ax
(m
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
g
lin
nd
Ha
in
rat
n.)
mi
g(
–∞
g
tin
era
Op
m
e
uir
req
t
en
g(
ng
li
nd
Ha
in
rat
.)
x
ma
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
77
NXP Semiconductors
Revision History
9 Revision History
The following table provides a revision history for this document.
Table 55. Revision History
Rev. No.
Date
2
01/2014
3
04/2014
• Format changes
4
09/2014
• Updated Table 6 "Power consumption operating behavior."
• Updated Table 17 "IRC48M specifications
• Updated Table 35 "VREF full-range operating behavior"
5
12/2014
• Updated Table 6 "Power consumption operating behavior."
• Added a note to the section "Power consumption operating behaviors."
6
08/2015
• Added a footnote to the maximum SCL clock frequency value in the table "I2C timing"
• Changed the title of the table "I2C 1 MHZ timing" to "I2C 1 Mbps timing"
• Added a footnote and updated the table "IRC48M specifications" for open loop total
deviation of IRC48M frequency at high voltage and low voltage.
• Added a footnote on the ambient temperature entry to the section "Thermal operating
requirements."
• Added a note to the section "Power consumption operating behaviors" and updated
values in the table "Power consumption operating behaviors."
• Added a note to the maximum frequency value in the table "Slave mode DSPI timing
(limited voltage range)."
• Redeveloped the section "Terminology and guidelines."
7
10/2016
• Updated the values of IDD_STOP and IDD_VLLS0 in the table "Power consumption
operating behaviors"
78
NXP Semiconductors
Substantial Changes
Initial public release.
Kinetis K24F Sub-Family Data Sheet, Rev. 7, 11/2016
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
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NXP, NXP logo, and Kinetis are trademarks of NXP B.V. All other product or
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©2014–2016 NXP B.V.
Document Number K24P144M120SF5
Revision 7, 11/2016
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