MC74HC153A Dual 4-Input Data Selector/Multiplexer High−Performance Silicon−Gate CMOS The MC74HC153 is identical in pinout to the LS153. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The Address Inputs select one of four Data Inputs from each multiplexer. Each multiplexer has an active−low Strobe control and a noninverting output. The HC153 is similar in function to the HC253, which has 3−state outputs. http://onsemi.com 16 MARKING DIAGRAMS SOIC−16 D SUFFIX CASE 751B 16 1 HC153AG AWLYWW 1 16 Features • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices These are Pb−Free Devices ADDRESS INPUTS D0a 6 D1 5 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT 7 Y a a D2a STROBE a 1 16 VCC A1 2 15 STROBE b D3a 3 14 A0 D2a 4 13 D3b D1a 5 12 D2b D0a 6 11 D1b Ya 7 10 D0b GND 8 9 Yb 4 D3a 3 STROBE a 1 DATAWORD b INPUTS D0b 10 D1 11 HC 153A ALYWG G 1 A0 14 A1 2 DATAWORD a INPUTS TSSOP−16 DT SUFFIX CASE 948F 16 9 Y b FUNCTION TABLE b D2b 12 D3 13 Inputs b STROBE b 15 PIN 16 = VCC PIN 8 = GND Output A1 A0 Strobe Y X L L H H X L H L H H L L L L L D0 D1 D2 D3 D0, D1, D2, and D3 = the level of the respective data input. Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 1 1 Publication Order Number: MC74HC153A/D MC74HC153A MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to + 7.0 V DC Input Voltage (Referenced to GND) −1.5 to VCC + 1.5 V DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air 500 TBD mW Tstg Storage Temperature −65 to +150 °C SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 2) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V −55 +125 °C 0 0 0 1000 500 400 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V − 55 to 25°C v 85°C v 125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 8 80 160 mA http://onsemi.com 2 MC74HC153A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Parameter Symbol VCC V − 55 to 25°C v 85°C v 125°C Unit tPLH, tPHL Maximum Propagation Delay, Input D to Output Y (Figures 2 and 5) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 3 and 5) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH, tPHL Maximum Propagation Delay, Strobe to Output Y (Figures 4 and 5) 2.0 4.5 6.0 95 19 16 120 24 20 145 29 25 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 5) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance — 10 10 10 pF Cin Typical @ 25°C, VCC = 5.0 V CPD 31 Power Dissipation Capacitance (Per Multiplexer) pF SWITCHING WAVEFORMS tr tf VALID INPUT D VCC 50% INPUT A GND tPLH GND tPLH tPHL 90% 50% 10% OUTPUT Y OUTPUT Y tTLH tPHL 50% tTHL Figure 2. Figure 3. tf tr 90% STROBE 50% 10% TEST POINT VCC OUTPUT DEVICE UNDER TEST GND tPLH tPHL 90% 50% 10% OUTPUT Y VALID VCC 90% 50% 10% tTLH CL* tTHL *Includes all probe and jig capacitance Figure 4. Figure 5. Test Circuit http://onsemi.com 3 MC74HC153A PIN DESCRIPTIONS DATA INPUTS Strobe (Pins 1, 15) D0a − D3a, D0b − D3b (Pins 3, 4, 5, 6, 10, 11, 12, 13) Active−low Strobe. A low level applied to these pins enables the corresponding outputs. Data Inputs. With the outputs enabled, the addressed Data Inputs appear at the Y outputs. OUTPUTS CONTROL INPUTS Ya, Yb (Pins 7, 9) Noninverting data outputs. A0, A1 (Pins 2, 14) Address Inputs. These inputs address the pair of Data Inputs which appear at the corresponding outputs. D0a 6 STROBE a DATA WORD a INPUTS 1 D1a 5 D2a 7 Y a 4 D3a 3 NONINVERTING DATA OUTPUTS D0b 10 DATA WORD b INPUTS D1b 11 9 D2b 12 STROBE b 15 D3b 13 ADDRESS INPUTS Yb A1 2 A0 14 Figure 6. Expanded Logic Diagram ORDERING INFORMATION Package Shipping† MC74HC153ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC153ADR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74HC153ADTR2G TSSOP−16* 2500 Tape & Reel MC74HC153ADTG TSSOP−16* 96 Units / Tube Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 4 MC74HC153A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S K1 2X L/2 16 9 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ J1 0.25 (0.010) M 0.15 (0.006) T U S A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 −W− J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MC74HC153A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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