ON LC898240-2H High efficient stepper motor controller Datasheet

LC898240
Advance Information
High Efficient
Stepper Motor Controller
Overview
The LC898240 is a current controller IC for a stepper motor, co-working
with a conventional driver. It provides additional functions to a stepper
motor control system. The drive current of a motor coil is adopted for the
motor load, so that minimize the waste of power. By this current control, the
stepper motor moves smoothly. And, it gives higher efficiency power
consumption, lower acoustic noise, lower vibration and lower heat
generation.
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PACKAGE PICTURE
The LC898240 also provides speed acceleration profile control function and
step-out detection/prevention. These functions can be configured by the
registers through an SPI serial port interface flexibly. The preset parameters
and configuration can be stored to the companion non-volatile memory.
The LC898240 consists of the monitor inputs from motor terminal, serial
port inter face, the step control signal inputs from a microprocessor and the
outputs to a stepper motor driver. The topology of a microprocessor, a
stepper motor driver and LC898240, can be arranged to match various
drivers and system architecture. Thus, it can be used as an interface
converter between a microprocessor and a driver with the advanced control
functions.
Features
• Unipolar and bipolar motor applicable
• Supported excitation mode:
o Half step
o Quarter step
o 1/8 step
o 1/16 step
o Full step (high efficient function not applicable)
• SPI interface for the motor control and setting
• Interface for the driver control
• Non-volatile memory (E2PROM)
o Setting of the controller
o Acceleration curve: 9 curves, 440 steps for each
Recommended Stepper Motor Driver
•
•
•
•
•
SQFP48
0.5mm pitch
MARKING DIAGRAM
898240
13T
YMMXXX
1
Y: Year
MM: Month
XXX: ID
ORDERING INFORMATION
Ordering Code:
LC898240-2H (tray)
LC898240-WH (reel)
Package
SQFP48
(Pb-Free / Halogen Free)
LV8726TA
LV8736V
LV8740V
STK672-6XXX
STK672-4XXX
Shipping (Qty / packing)
1250 / Tray
1000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
Typical Applications
• Multi-Function Printer
• Consumer
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2016
April 2016- Rev. P1
1
Publication Order Number:
LC898240/D
LC898240
LC898240 BLOCK DIAGRAM
LC898240
E2PROM
HOLD
WP
SO_E
CSB_E
DVDD1
Main Chip
AVDD
AVSS
CLK
DVDD2
DVSS
CSB
SCK
SI
SO
STS1
STS0
RSB
TSMO
CSB_M
SO_M
Serial Interface
ST
RSTI
RSTO
START
WSEL3
WSEL2
WSEL1
WSEL0
Driver
Acceleration Control
Control
INTP1
INTP0
STP
OUTAI
OUTBI
AMPO
ADCI
VREFI
VREFO
OE
FR
MD2
MD1
MD0
Driver Waveform
Monitor
ECO Mode Control
Reference Voltage Source
Figure 1 LC898240 Block Diagram
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2
GAD
LC898240
APPLICATION BLOCK DIAGRAM
LC898240
3.3V
DVDD1
+
22uF 0.1uF 0.1uF
5V
+
22uF 0.1uF
AVSS
DVDD2
0.1uF 22uF
LVXXXXX
Rref1
VREF
VREFO
DVSS
Rref2
CLK
reset in
RSB
SO_M
CSB
CSB_M
SCK
CSB_E
SI
SO_E
SO
ST(O)
START
RSTI
GAD
status out
+
VREFI
clock in
SPI
3.3V
AVDD
STS1~0
WSEL3~0
Bipolar Motor
ST
STEP
OUT1A
RSTO
RST
OUT1B
OE(O)
OE
OUT2A
FR(O)
FR
OUT2B
STP
MD1~0(O)
MD2~1
MD2(O)
INTP1~0
OUTAI
TSMOD
OUTBI
HOLD
AMPO
WP
0.1uF
Ratb1
Rata1
Rfil
Rata2
ADCI
Cfil
Figure 2 Example of SPI control for IO port control driver
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Ratb2
LC898240
WP
NC
INTP1
INTP0
WSEL3
WSEL2
DVSS
NC
WSEL1
WSEL0
NC
START
PIN ASSIGNMENTS
36
25
37
24
DVDD1
OUTBI
CSB
OUTAI
SCK
AMPO
SI
AVDD
LC898240
SO
STS1
AVSS
ADCI
SQFP48
7mm x 7mm
STS0
DVDD2
ST
VREFO
VREFI
TSMOD
MD2
CLK
MD1
RSB
MD0
GAD
48
13
12
SO_E
CSB_E
CSB_M
SO_M
RSTI
DVDD1
DVSS
STP
FR
RSTO
OE
HOLD
1
Figure 3: LC898240 Pinout
NUMBER
NAME
TYPE
NUMBER
NAME
TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HOLD
OE
RSTO
FR
STP
DVSS
DVDD1
RSTI
SO_M
CSB_M
CSB_E
SO_E
GAD
RSB
CLK
TSMOD
VREFI
VREFO
ADCI
AVSS
AVDD
AMPO
OUTAI
OUTBI
I
B(I)
O
B(I)
O
P
P
I
I
O
I
O
I
I
I
I
I
O
I
P
P
O
I
I
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MD0
MD1
MD2
ST
DVDD2
STS0
STS1
SO
SI
SCK
CSB
DVDD1
START
NC
WSEL0
WSEL1
NC
DVSS
WSEL2
WSEL3
INTP0
INTP1
NC
WP
B(I)
B(I)
B(I)
B(I)
P
O
O
O
I
I
I
P
I
I
I
P
I
I
I
I
I
Where,
Termination of unused pins
O: open
I : pull-up or pull-down if no on-chip
pull-up/down
B: open (on-chip pull-down installed)
I : input
O: output
B(I) : bidirectional (input at reset)
B(O) : bidirectional (output at reset)
P: power supply
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LC898240
PIN DESCRIPTION
1. HOLD
Hold E2PROM. It must be connected to DVDD1.
For more detail, see the E2PROM datasheet.
14. RSB
System Reset Input
LC898240 is reset by RSB = L. After the reset is
released, it will start the E2PROM data download
to the registers.
2. OE
Output Enable
For IO port control mode:
- bit OERST = 0: OE acts as an input.
- bit OERST = 1: OE acts as an output with
respect to the pin ST transparently.
For register control mode:
- OE outputs the value of the bit OE_REG.
15. CLK
Clock Input
Frequency range is from 840kHz through 10MHz
16. TSMOD
Test Mode
It must be connected to DVSS or open.
3. RSTO
Driver Reset Output
To force synchronization of the step position with
the driver, the driver reset pulse is output once an
electrical cycle, while the bit RSTAD is set 1.
For IO port control mode:
- RSTO outputs with respect to the pin RSTI
transparently.
For register control mode:
- RSTO outputs the value of the bit
RST_REG.
17. VREFI
Reference Voltage Input
It must be connected to AVDD.
18. VREFO
Current Control Reference Voltage Output
19. ADCI
ADC Input
20. AVSS
Ground of the Analog Portion
4. FR
Rotation Direction
For IO port control mode:
- Input
For register control mode:
- FR outputs the value of the bit FR_REG.
21. AVDD
Power Supply for the Analog Portion
22. AMPO
Amplifier Output
5. STP
Step Pulse Output
23. OUTAI and 24. OUTBI
Motor Signal Input
6. DVSS
Digital Ground
25. WP
Write Protection of E2PROM
7. DVDD1
Power Supply for the E2PROM and the Digital
Portion of the Main Chip
26. NC, 32. NC and 35. NC
No Connection
27. INTP1 and 28. INTP0
Interpolation Setting for the Acceleration Curve
For IO port control mode:
- INTP[1:0] = 0h: not interpolation
- INTP[1:0] = 1h: interpolate 1 point between
the steps based on E2PROM data
- INTP[1:0] = 2h: interpolate 3 point between
the steps based on E2PROM data
- INTP[1:0] = 3h: interpolate 7 point between
the steps based on E2PROM data
For register control mode, it is ignored.
8. RSTI
Driver Reset Input for IO Port Control Mode
For register control mode, it is ignored.
9. SO_M and 12. SO_E
E2PROM output. They must be connected on a
board.
10. CSB_M and 11. CSB_E
E2PROM chip select pins. They must be
connected on a board.
13. GAD
High Efficient Current Control Mode
The adaptive motor current control mode is
enabled by GAD = H or the bit GAD_REG = 1.
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5
LC898240
29. WSEL3, 30. WSEL2, 33. WSEL1 and 34. WSEL0
Acceleration Curve Selection
For IO port control mode:
- WSEL[3:0] = 0h: the acceleration curve #0
- WSEL[3:0] = 1h: the acceleration curve #1
- WSEL[3:0] = 2h: the acceleration curve #2
- WSEL[3:0] = 3h: the acceleration curve #3
- WSEL[3:0] = 4h: the acceleration curve #4
- WSEL[3:0] = 5h: the acceleration curve #5
- WSEL[3:0] = 6h: the acceleration curve #6
- WSEL[3:0] = 7h: the acceleration curve #7
- WSEL[3:0] = 8h: the acceleration curve #8
- WSEL[3:0] = 9h - Fh: N.A.
38. CSB, 39. SCK, 40. SI and 41. SO
SPI Interface
42. STS1 and 43. STS0
Status Output of LC898240
44. DVDD2
Power Supply for the Digital Portion of the Main
Chip
45. ST
Driver Standby
For IO port control mode:
- The bit DERST = 0: ST signal input
- The bit DERST = 1: ST signal input to
output to OE
For register control mode:
- ST outputs the value of the bit ST_REG.
- For the unipolar driver STK672-XXXX,
this pin must be open.
31. DVSS
Digital Ground
36. START
Motor Rotation Control
The bit STPSEL = 0: START acts as the step pulse
input
The bit STPSEL = 1: START acts as the start/stop
command input
46. MD2, 47. MD1 and 48. MD0
Mode Switch
For IO port control mode: MD signal input
For register control mode: the value of the register
MD_REG is output.
37. DVDD1
Power Supply for the E2PROM and the Digital
Portion of the Main Chip
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LC898240
ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Supply voltage
Pins
DVDD1
DVDD2
Ratings
−0.3 to 4.6
Unit
V
−0.3 to 6.0
−0.3 to 4.6
V
V
VINd1,
VOUTd1
−0.3 to DVDD1 + 0.3
V
VINd1t
−0.3 to 6.0
V
VINd2,
VOUTd2
−0.3 to DVDD2 + 0.3
V
VINa, VOUTa
−0.3 to AVDD + 0.3
±20
V
AVDD
Input/output voltage
Input/output current
Storage temperature
Ii , Io
Tstg
Operating ambient
temperature
Topg
−55 to 125
°C
-40 to 85
°C
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS Ta: -40 to 85°C (Note 2)
Parameter
Supply-voltage range
Symbol
DVDD1
DVDD2
Condition
Min
Typ
Max
Unit
|DVDD1 – AVDD| ≤ 0.3
3.0
3.3
3.6
V
3.0
3.3
5.5
V
3.0
3.3
3.6
V
DVDD1 ≤ DVDD2 + 0.3
AVDD ≤ DVDD2 + 0.3
|DVDD1 – AVDD| ≤ 0.3
DIGITAL INPUTS (HOLD, WP, CSB_E)
High level input voltage
VIH
0.7 × DVDD1
DVDD1
V
Low level input voltage
VIL
0
0.3 × DVDD1
V
High level input voltage
VIH
0.7 × DVDD1
5.5
V
Low level input voltage
VIL
0
0.2 × DVDD1
V
DIGITAL INPUTS (CLK)
DIGITAL INPUTS (RSB, RSTI, GAD, TSMOD, START, SO_M, WSEL3, WSEL2, WSEL1, WSEL0, INTP1, INTP0)
High level input voltage
Low level input voltage
VIH
VIL
0.75 ×
DVDD1
5.5
V
0
0.15 ×
DVDD1
V
0.75 ×
DVDD2
DVDD2
V
0
0.15 ×
DVDD2
V
DIGITAL INPUTS (CSB, SCK, SI, OE, FR, ST, MD2, MD1, MD0)
High level input voltage
Low level input voltage
VIH
VIL
DIGITAL OUTPUTS (SO_E)
High level output voltage
VOH
IOH = -2mA
Low level output voltage
VOL
IOL = 2mA
V
0.8 × DVDD1
0.4
V
DIGITAL OUTPUTS (CSB_M)
High level output voltage
VOH
IOH = -2mA
Low level output voltage
VOL
IOL = 2mA
V
DVDD1 – 0.4
0.4
V
DIGITAL OUTPUTS (RSTO, STP, STS1, STS0, SO, OE, FR, ST, MD2, MD1, MD0)
High level output voltage
VOH
IOH = -2mA
Low level output voltage
VOL
IOL = 2mA
V
DVDD2 – 0.4
0.4
V
Continued on next page
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LC898240
Continued from preceding page
Parameter
Symbol
Condition
Min
Ta: -40 to 85°C
Ta: -40 to 85°C
Typ
Max
Unit
0
AVDD
V
0
AVDD
V
MOTOR SIGNAL INPUTS (OUTAI, OUTBI)
Input voltage range
VOUTI
AMPLIFIER OUTPUT (AMPO)
Output voltage range
VAMPO
Maximum gain
GHAMPO
Ta = 25°C
16
V/V
Minimum gain
GLAMPO
Ta = 25°C
1
V/V
ADC INPUTS (ADCI)
Input voltage range
VADCI
Ta: -40 to 85°C
ADC offset error
ILADCI
ADC differential
non-linearity
DILADCI
0
AVDD
V
Ta = 25°C
±2.0
LSB
Ta = 25°C
±1.0
LSB
AVDD
V
3.07
V
REFERENCE VOLTAGE INPUT (VREFI)
Input voltage range
VVREFI
Ta: -40 to 85°C
AVDD
REFERENCE VOLTAGE OUTPUT (VREFO)
Output voltage range
DAC integral
non-linearity
DAC differential
non-linearity
VVREFO
Ta: -40 to 85°C
AVDD = 3.3V
VREFI = 3.3V
0.24
INLVREFO
Ta = 25°C
±2.0
LSB
DNLVREFO
Ta = 25°C
±1.0
LSB
DAC zero scale voltage
VZVREFO
Ta = 25°C
0.14
0.24
0.34
V
DAC full scale voltage
VFVREFO
Ta = 25°C
2.97
3.07
3.17
V
2. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
FUNCTIONAL DESCRIPTON
Control Functions
Speed Acceleration Control
LC898240 provides the following control functions.
This function is activated by set 1 to the bit STPSEL.
When the pin START is set H, or bit START_REG is set
1, the step pulses are generated and output to the pin STP,
based on the acceleration curve data written in the
E2PROM.
(1) Driver Control: It controls a stepper motor driver
connected to LC898240.
(2) Programmable Speed Control: The step pulses
are generated based on the target speed and
acceleration/deceleration curve.
Current Control
The motor current is adjusted by the reference voltage at
the pin VREFO driven by 8-bit DAC.
(3) High Efficient Current Control: The motor
driving current is adapted against the load, and it
gives high power efficiency.
Power On/Off
Ideally, he power should be supplied to DVDD1, AVDD,
DVDD2 and driver at the same time. But, if the
simultaneity is impossible, the power-on sequence must
be conformed to the following order within 100ms.
DVDD1 > AVDD > DVDD2 > driver
The power-off should also be done at the same time as
well as power-on. And, the power-off sequence must be
conformed to the following order within 100ms.
Driver > DVDD2 > AVDD > DVDD1
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LC898240
REGISTER DESCRIPTION
E2PROM
Initial Default Settings
Register Map
After the reset is released, the data written in the address
0000h to 002Fh of the E2PROM will be downloaded to
the same address of the main chip registers. This
function allows to set the initial default value for the
registers. The register setting can be overwritten
through the SPI.
Addre
ss
from
to
Description
0000h
002Fh
0030h
003Fh
initial default settings for the
main chip registers
unused (filled by FFh)
0040h
03AFh
acceleration curve #0
Acceleration Curve
03B0h
03BFh
unused (filled by FFh)
03C0h
072Fh
acceleration curve #1
0730h
073Fh
unused (filled by FFh)
The E2PROM has the registers for nine acceleration
curves with 440 steps for each. The step interval time is
represented in 16-bit code.
𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆 = (𝐷𝐷𝑅𝑅𝑅𝑅𝑅𝑅 + 1) × 𝑇𝑇𝐶𝐶𝐶𝐶𝐶𝐶
Where,
𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆 : step interval time [s]
𝐷𝐷𝑅𝑅𝑅𝑅𝑅𝑅 : E2PROM data. MSB in even address,
and LSB in odd address.
𝑇𝑇𝐶𝐶𝐶𝐶𝐶𝐶 : clock period [s]
The end of the acceleration curve sequence is set by
𝐷𝐷𝑅𝑅𝑅𝑅𝑅𝑅 = FFFFh, and the motor rotation is kept in
the constant speed.
0740h
0AAFh
acceleration curve #2
0AB0h
0ABFh
unused (filled by FFh)
0AC0h
0E2Fh
acceleration curve #3
0E30h
0E3Fh
unused (filled by FFh)
0E40h
11AFh
acceleration curve #4
11B0h
11BFh
unused (filled by FFh)
11C0h
152Fh
acceleration curve #5
1530h
153Fh
unused (filled by FFh)
1540h
18AFh
acceleration curve #6
18B0h
18BFh
unused (filled by FFh)
18C0h
1C2Fh
acceleration curve #7
1C30h
1C3Fh
unused (filled by FFh)
1C40h
1FAFh
acceleration curve #8
1FB0h
1FFFh
unused (filled by FFh)
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LC898240
Main Chip Register
Register Map
ADDR[6:0]
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0030h
0031h
0032h
0033h
0034h
Register Name
AIFSEL
START
WSEL
INTP
DSKIP
SETST
SETED
STMODE
STCNTL
STCNTH
DPSTG
DTSTG
GCKRTO
GADSLIM
GPSTG
NMBUSTG
BDSTG
SOSTG
GADMAX
GADSTOP
GADSTAT
ADTDLT
ADTBSE
ADTLIM
ADMDRTO2
ADMDRTO3
ADMDRTO4
ADBURTO
ADSTO
IPSTG
STSSEL
IFSEL
STS
PHSCNT
SPDCEF
ADDAT_LT_ADJ
GADDAT
Default
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
-
Function
acceleration control interface configuration
start/stop acceleration control
acceleration curve selection
interpolation setting between steps
skip setting at deceleration
wait time for acceleration
wait time for stop
constant speed period programming mode selection
step counts for constant speed period (LSB)
step counts for constant speed period (MSB)
driver initial setting
driver active setting
clock setting
speed setting for high efficient mode
initial setting for High efficient mode
NM/BU setting
BD setting
step out detection setting
upper limit of VREFO level
VREFO level setting at motor stop
FF value
AD increment value target
AD base value target
AD minimum value target
excitation mode ratio setting #2
excitation mode ratio setting #3
excitation mode ratio setting #4
burst up threshold
AD step out level
analog portion
status out setting
interface setting
status
phase
speed coefficient
ADC judgement point voltage
VREFO coefficient
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Register Function Description
AIFSEL: acceleration control interface configuration
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0000h
00h
-
-
-
-
-
-
-
AIFSEL
AIFSEL = 0: I/O port control mode, using pins; START, WSEL3/2/1/0 and INTP1/0.
AIFSEL = 1: register control mode, using registers; START_REG, WSEL_REG and INTP_REG.
START: start/stop acceleration control (R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0001h
00h
-
-
-
-
-
-
-
START_REG
It is effective during the register control mode (AIFSEL = 1).
Set START_REG from 0 to 1 during motor stop: start acceleration
Set START_REG from 1 to 0 during motor running in the constant speed: start deceleration
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LC898240
WSEL
acceleration curve selection
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
0002h
00h
-
-
-
-
Bit3
Bit2
Bit1
Bit0
WSEL_REG[3:0]
It is effective during the register control mode (AIFSEL = 1).
WSEL_REG[3:0] = 0h: the acceleration curve #0
WSEL_REG[3:0] = 1h: the acceleration curve #1
WSEL_REG[3:0] = 2h: the acceleration curve #2
WSEL_REG[3:0] = 3h: the acceleration curve #3
WSEL_REG[3:0] = 4h: the acceleration curve #4
WSEL_REG[3:0] = 5h: the acceleration curve #5
WSEL_REG[3:0] = 6h: the acceleration curve #6
WSEL_REG[3:0] = 7h: the acceleration curve #7
WSEL_REG[3:0] = 8h: the acceleration curve #8
WSEL_REG[3:0] = 9h - Fh: N.A.
INTP
interpolation setting between steps
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0003h
00h
-
-
-
-
-
-
Bit1
Bit0
INTP_REG[1:0]
It is effective during the register control mode (AIFSEL = 1).
INTP_REG[1:0] = 0h: not interpolation
INTP_REG[1:0] = 1h: interpolate 1 point between the steps based on E2PROM data
INTP_REG[1:0] = 2h: interpolate 3 point between the steps based on E2PROM data
INTP_REG[1:0] = 3h: interpolate 7 point between the steps based on E2PROM data
DSKIP
skip setting at deceleration
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0004h
00h
-
-
-
-
-
-
Bit1
Bit0
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
DSKIP[1:0]
The number of skip of the acceleration curve data for deceleration
DSKIP = 0: no skip
DSKIP = 1: 1 point skip
DSKIP = 2: 2 points skip
DSKIP = 3: 3 points skip
SETST
wait time for acceleration
Address
Default
0005h
00h
Bit7
R/W
Bit6
Bit5
Bit4
SETST[7:0]
Waiting time for acceleration
𝑇𝑇𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 = 𝑇𝑇𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 × 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆[7: 0]
Where,
𝑇𝑇𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 : waiting time [s]
𝑇𝑇𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 : initial acceleration pulse width [s]
SETED
wait time for stop
Address
Default
0006h
00h
Bit7
R/W
Bit6
Bit5
Bit4
Bit3
SETED[7:0]
Waiting time for stop
𝑇𝑇𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 = 𝑇𝑇𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 × 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆[7: 0]
Where,
𝑇𝑇𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 : waiting time [s]
𝑇𝑇𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 : initial acceleration pulse width [s]
STMODE constant speed period programming mode selection (R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0007h
00h
-
-
-
-
-
-
-
STMODE
STMODE = 0: continue rotation at the constant speed after the acceleration until START = 0
STMODE = 1: rotate at the constant speed after the acceleration for the number of steps which is set in the register
STCNT, followed by automatic deceleration and stop
START must be set 0 after the motor stops.
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LC898240
STCNTL step counts for constant speed period (LSB)
(R/W)
Address
Default
Bit4
0008h
00h
Bit7
Bit6
Bit5
Bit3
Bit2
Bit1
Bit0
STCNT[7:0]
STCNTL step counts for constant speed period (MSB)
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0009h
00h
-
-
-
-
-
-
-
STCNT[8]
The number of steps for the constant speed in STMODE = 1
STCNT must not be zero.
DPSTG
driver initial setting (R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0010h
00h
RSTIV
RSTPHS
RSTAD
OERST
OEIV
OEMV
Bit1
Bit0
MDSEL[1:0]
RSTIV
Polarity of RST signal.
RSTIV = 0: low active (reset by L)
RSTIV = 0: high active (reset by H)
RSTPHS
Synchronize with driver
RSTPHS = 0: reset at 315 degree
RSTPHS = 1: reset at 315 degree for full step excitation mode, reset at 0 degree for others
RSTAD
Reset phase adjustment
RSTAD = 0: no adjustment for bipolar driver
RSTAD = 1: adjustment enabled for unipolar driver
OERST
OE signal control
OERST = 0: no OE signal control. The pin OE is switched to input of OE signal during I/O port control mode
OERST = 1: activate OE single control. The pin OE is switched to output of OE signal. The pin ST is the OE signal
input
OEIV
OE signal polarity
OEIV = 0: high active
OEIV = 1: low active
OEMV
OEMV = 0: ignore step pulse while the output is disabled
OEMV = 1: advance phase with respect to the step pulse input even though the output is disabled
MDSEL[1:0]
MDSEL = 0h
MD = 0h: full step, both edges
MD = 1h: half step, both edges
MD = 2h: full step, rising edge
MD = 3h: half step, rising edge
MD = 4h: quarter step, both edges
MD = 5h: 1/8 step, both edges
MD = 6h: quarter step, rising edge
MD = 7h: 1/8 step, rising edge
Pin connection
LC898240 pin MD2 --- open
LC898240 pin MD1 --- STK672-6XXX pin MODE2
LC898240 pin MD0 --- STK672-6XXX pin MODE1
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12
LC898240
MDSEL = 1h
MD = 0h: half step, both edges
MD = 1h: quarter step, both edges
MD = 2h: 1/8 step, both edges
MD = 3h: 1/16 step, both edges
MD = 4h: full step, rising edge
MD = 5h: half step, rising edge
MD = 6h: quarter step, rising edge
MD = 7h: 1/8 step, rising edge
Pin connection
LC898240 pin MD2 --- STK672-4XXX pin MODE3
LC898240 pin MD1 --- STK672-4XXX pin MODE2
LC898240 pin MD0 --- STK672-4XXX pin MODE1
MDSEL = 2h
MD = 0h: full step, rising edge
MD = 1h: half step, rising edge
MD = 2h: quarter step, rising edge
MD = 3h: 1/8 step, rising edge
MD = 4h: full step, rising edge
MD = 5h: half step, rising edge
MD = 6h: quarter step, rising edge
MD = 7h: 1/16 step, rising edge
Pin connection
LC898240 pin MD2 --- open
LC898240 pin MD1 --- LV8736V pin MD2
LC898240 pin MD0 --- LV8736V pin MD 1
MDSEL = 3h
MD = 0h: full step, rising edge
MD = 1h: half step, rising edge
MD = 2h: half step, rising edge
MD = 3h: quarter step, rising edge
MD = 4h: full step, rising edge
MD = 5h: half step, rising edge
MD = 6h: quarter step, rising edge
MD = 7h: half step, rising edge
Pin connection
LC898240 pin MD2 --- open
LC898240 pin MD1 --- LV8740V pin MD2
LC898240 pin MD0 --- LV8740V pin MD 1
DTSTG driver active setting (R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
0011h
00h
GAD_REG
ST_REG
RST_REG
OE_REG
FR_REG
Bit2
Bit1
MD_REG[2:0]
GAD_REG
Enable/disable the high efficient (adaptive current control) function
Enabled when bit GAD_REG = 1 or pin GAD = H
ST_REG
Outputs ST signal from the pin ST during the register control mode
When it used with the unipolar driver STK672-XXXX, ST_REG value must be same as bit RST_REG.
During IO port control mode, ST_REG is ignored.
RST_REG
Outputs RST signal from the pin RSTO during the register control mode
During IO port control mode, RST_REG is ignored.
OE_REG
Outputs OE signal from the pin OE during the register control mode
During IO port control mode, OE_REG is ignored.
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Bit0
LC898240
FR_REG
Outputs FR signal from the pin FR during the register control mode
During IO port control mode, FR_REG is ignored.
MD_REG[2:0]
Outputs MD signal from the pins MD2, MD1 and MD0 during the register control mode
During IO port control mode, MD_REG is ignored.
GCKRTO clock setting
(R/W)
Address
Default
Bit7
Bit6
0012h
00h
-
-
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit1
Bit0
GCKRTO[5:0]
GCKRTO[5:0]
Defines the ratio between CLK and virtual clock (GCK = 840kHz)
𝑓𝑓𝑔𝑔𝑔𝑔𝑔𝑔
= 2−1 𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺[5] + 2−2 𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺[4] + ⋯ + 2−6 𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺[0]
𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐
For example, in case of a clock of 4MHz at the pin CLK,
𝑓𝑓𝑔𝑔𝑔𝑔𝑔𝑔 0.84
=
= 0.21
𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐
4
𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺[5: 0] = 0Dh → 0.203125
The virtual step pulse velocity is defined by,
𝑓𝑓𝑆𝑆𝑆𝑆𝑆𝑆 × 𝑓𝑓𝑔𝑔𝑔𝑔𝑔𝑔
𝑓𝑓VSTP =
𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 × 𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺[5: 0] × 𝑘𝑘𝑀𝑀𝑀𝑀
𝑓𝑓𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 : virtual step pulse velocity [pps]
𝑓𝑓𝑆𝑆𝑆𝑆𝑆𝑆 : step pulse velocity [pps]
𝑘𝑘𝑀𝑀𝑀𝑀 : excitation mode factor (1 for half, 2 for quarter, 4 for 1/8 and 8 for 1/16 step)
GADSLIM
speed setting for smooth stepper mode
Address
Default
Bit7
Bit6
0013h
00h
-
GADAC
Bit5
(R/W)
Bit4
Bit3
Bit2
GADSLIM[5:0]
GADAC
The high efficient mode (adoptive current control) and the acceleration control works concurrently.
GADAC = 0: not concurrent
GADAC = 1: high efficient mode activated after the acceleration completed
GADSLIM
The high efficient mode is activated when the motor speed is faster than the speed specified by GADSLIM.
For example, to specify the virtual step pulse speed threshold 1900pps, set 0Bh for GADSLM[5:0].
GPSTG
initial setting for high efficient mode
Address
Default
Bit7
Bit6
0014h
00h
-
GADPHS
(R/W)
Bit5
Bit4
GADNUM[1:0]
GADPHS
Defines the motor signal for OUTAI and OUTBI
GADPHS = 0: phase B (phase OUT2)
GADPHS = 1: phase A (phase OUT1)
GADNUM
VREFO control frequency (over sampling)
GADNUM = 0h: default
GADNUM = 1h: 2x
GADNUM = 2h: 4x
GADNUM = 3h: 8x
OVPSLIM
ADCI waveform tuning
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Bit3
Bit2
Bit1
OVPSLIM[3:0]
Bit0
LC898240
NMBUSTG
NM/BU setting
(R/W)
Address
Default
Bit7
Bit6
0015h
00h
-
NMSEL
Bit5
Bit4
NMSTEP[1:0]
Bit3
Bit2
BUEN
Bit1
Bit0
BUSTEP[2:0]
NMSEL
VREFO adjust method
NMSEL = 0: constant type
NMSEL = 1: differential type
NMSTEP
VREFO adjust step
NMSEL = 0
NMSTEP = 0h: 1/256 of VREFO full scale voltage
NMSTEP = 1h: 2/256 of VREFO full scale voltage
NMSTEP = 2h: 4/256 of VREFO full scale voltage
NMSTEP = 3h: 8/256 of VREFO full scale voltage
NMSEL = 1
NMSTEP = 0h: (|target – judge point| / 32) × (1/256 of VREFO full scale voltage)
NMSTEP = 1h: (|target – judge point| / 16) × (1/256 of VREFO full scale voltage)
NMSTEP = 2h: (|target – judge point| / 8) × (1/256 of VREFO full scale voltage)
NMSTEP = 3h: (|target – judge point| / 4) × (1/256 of VREFO full scale voltage)
BUEN
BUEN = 0: burst up off
BUEN = 1: burst up on
BUSTEP
VREFO adjustment resolution at the bust up
BUSTEP = 0h: 2/256 of the VREFO full scale voltage
BUSTEP = 1h: 4/256 of the VREFO full scale voltage
BUSTEP = 2h: 8/256 of the VREFO full scale voltage
BUSTEP = 3h: 16/256 of the VREFO full scale voltage
BUSTEP = 4h: 32/256 of the VREFO full scale voltage
BUSTEP = 5h: 64/256 of the VREFO full scale voltage
BUSTEP = 6h: 128/256 of the VREFO full scale voltage
BUSTEP = 7h: 256/256 of the VREFO full scale voltage
BDSTG BD setting
(R/W)
Address
Default
Bit7
Bit6
0016h
00h
-
BDSEL
Bit5
Bit4
BDNUM[1:0]
Bit3
BDEN
Bit2
Bit1
Bit0
BDSTEP[2:0]
BDSEL
Burst down condition
BDSEL = 0: higher voltage than the judgement point
BDSEL = 1: ADCI waveform is convex.
BDNUM
The bust down condition qualifier: when the event consecutively repeated for the following number of times, this
function is activated.
BDNUM = 0h: twice
BDNUM = 0h: 4 times
BDNUM = 0h: 8 times
BDNUM = 0h: 16 times
BDEN
BDEN = 0: burst down deactivated
BDEN = 1: burst down activated
BDSTEP
VREFO adjustment resolution at the bust down
BDSTEP = 0h: 8/256 of the VREFO full scale voltage
BDSTEP = 1h: 12/256 of the VREFO full scale voltage
BDSTEP = 2h: 16/256 of the VREFO full scale voltage
BDSTEP = 3h: 24/256 of the VREFO full scale voltage
BDSTEP = 4h: 32/256 of the VREFO full scale voltage
BDSTEP = 5h: 48/256 of the VREFO full scale voltage
BDSTEP = 6h: 64/256 of the VREFO full scale voltage
BDSTEP = 7h: 96/256 of the VREFO full scale voltage
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LC898240
SOSTG
step out detection setting
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0017h
00h
-
-
-
-
-
SOMD
Bit1
Bit0
SONUM
SOMD
SOMD = 0: set the flag STPOUT = 1 whenever the step out is detected
SOMD = 1: latch the flag STPOUT = 1 when the step out is detected, and clear the flag by RST or ST reset
SONUM
The step out detection qualifier: when the event consecutively repeated for the following number of times, the step
out detection is flagged.
SONUM = 0h: once
SONUM = 1h: twice
SONUM = 2h: 8 times
SONUM = 3h: 16 times
GADMAX
upper limit of VREFO level
Address
Default
0018h
00h
Bit7
Bit6
(R/W)
Bit5
Bit4
VREFO level setting at motor stop
Address
Default
0019h
00h
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
GADMAX[7:0]
GADMAX[7:0]
Upper limit of VREFO voltage level
𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺
𝑉𝑉𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 = 𝑉𝑉𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ×
256
GADSTOP
Bit3
Bit7
Bit6
(R/W)
Bit5
Bit4
Bit3
GADSTOP[7:0]
GADSTOP
VREFO voltage level during motor stop (RDY = L and MACT L)
𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺
𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 = 𝑉𝑉𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ×
256
GADSTOP value must be equal to or less than GADMAX. If this function is not used, set the same value to
GADSTOP as GADMAX.
GADSTAT
FF value (R/W)
Address
Default
001Ah
00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
GADSTAT[7:0]
GADSTAT
The initial value of VREFO for the high efficient mode as feedforward control
𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺
𝑉𝑉𝐹𝐹𝐹𝐹 = 𝑉𝑉𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ×
256
GADSTAT value must be equal to or less than GADMAX. If this function is not used, set the same value to
GADSTAT as GADMAX.
ADTDLT AD increment value target
Address
Default
001Bh
00h
Bit7
(R/W)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
ADTDLT[7:0]
See the illustration below.
ADTBSE AD base value target
Address
Default
001Ch
00h
Bit7
(R/W)
Bit6
Bit5
Bit4
Bit3
ADTBSE[7:0]
See the illustration below.
ADTLIM AD minimum value target
Address
Default
001Dh
00h
Bit7
(R/W)
Bit6
Bit5
Bit4
Bit3
ADTLIM[7:0]
See the illustration below.
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LC898240
Code for target
255d
ADTDLT
ADTBSE
ADTLIM
Virtual step pulse speed
2000pps
ADMDRTO2
6000pps
excitation mode ratio setting #2
Address
Default
Bit7
Bit6
001Eh
00h
-
-
(R/W)
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
ADMDRTO2[5:0]
ADMDRTO2[5:0]
The target value ratio between half step and quarter step excitation mode
ratio = 2−1 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴2[5] + 2−2 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴2[4] + ⋯ + 2−6 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴2[0]
ADMDRTO3
excitation mode ratio setting #3
Address
Default
Bit7
Bit6
001Fh
00h
-
-
(R/W)
Bit5
Bit4
Bit3
Bit2
ADMDRTO3[5:0]
ADMDRTO3[5:0]
The target value ratio between half step and 1/8 step excitation mode
ratio = 2−1 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴3[5] + 2−2 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴3[4] + ⋯ + 2−6 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴3[0]
ADMDRTO4
excitation mode ratio setting #4
Address
Default
Bit7
Bit6
0020h
00h
-
-
(R/W)
Bit5
Bit4
Bit3
Bit2
ADMDRTO4[5:0]
ADMDRTO4[5:0]
The target value ratio between half step and 1/16 step excitation mode
ratio = 2−1 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴4[5] + 2−2 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴4[4] + ⋯ + 2−6 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴4[0]
ADBURTO
burst up threshold
(R/W)
Address
Default
Bit7
Bit6
0021h
00h
-
-
Bit5
Bit4
Bit3
Bit2
ADBURTO[5:0]
ADBURTO[5:0]
The target value ration against the burst up threshold
ratio = 2−1 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴[5] + 2−2 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴[4] + ⋯ + 2−6 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴[0]
ADSTO AD step out level
Address
Default
0022h
00h
Bit7
(R/W)
Bit6
Bit5
Bit4
Bit3
ADSTO[7:0]
ADSTO[7:0]
The code for tentative step out judgement
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Bit2
LC898240
IPSTG
analog portion
(R/W)
Address
Default
Bit7
Bit6
0023h
00h
-
-
Bit5
Bit4
Bit3
Bit2
ADCWDT[2:0]
Bit1
Bit0
AMPGN[2:0]
ADCWDT[2:0]
Analog characteristics setting
It must be 2.
AMPGN[2:0]
Gain of the amplifier for AMPO output
AMPGN = 0h: 1x
AMPGN = 1h: 2x
AMPGN = 2h: 4x
AMPGN = 3h: 8x
AMPGN = 4h: 16x
AMPGN = 5h to 7h: inhibited
STSSEL status out setting
Address
Default
0024h
00h
(R/W)
Bit7
Bit6
Bit5
Bit4
Bit3
STS1SEL[3:0]
Bit2
Bit1
Bit0
STS0SEL[3:0]
STS1SEL[3:0]
Status signal selection for the pin STS1
STS0SEL[3:0]
Status signal selection for the spin STS0
The spins STS1 and STS0 get H during E2PROM down load, after the reset by RSB is released.
STS1SEL = 0h: L
STS1SEL = 1h: RDY
STS1SEL = 2h: MACT
STS1SEL = 3h: ACB
STS1SEL = 4h: MONI (driver home position)
STS1SEL = 5h: STPOUT (step out detected)
STS1SEL = 6h: GAD_EN (high efficient mode)
STS1SEL = 7h: ADJ_EN (VREF adjusted)
STS1SEL = Ah: BSTDWN (bust down)
STS1SEL = Bh: BSTUP (burst up)
STS1SEL = Ch to Fh: not allowed
IFSEL
interface setting
(R/W)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0025h
00h
-
-
-
-
-
-
STPSEL
IFSEL
STPSEL
Step pulse source selection
STPSEL = 0: input from external through the pin START
STPSEL = 1: acceleration control mode. The step pulse is generated by the acceleration controller. The pin START
is used for acceleration start (START = H) and deceleration start (START = L)
IFSEL
Control mode selection
IFSEL = 0: IO port control mode
Input pins: ST, FR, MD2, MD1, MD0, and either OE (OERST = 0) or ST (OERST = 1, OE output)
Registers ST_REG, RST_REG, OE_REG, FR_REG and MD_REG are ignored.
IFSEL = 1: register control mode
Outputs ST, FR, MD2, MD1, MD0, OE and RSTO are driven by ST_REG, FR_REG, MD_REG,
OE_REG and RST_REG.
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LC898240
STS
status
(Read Only)
Address
Default
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0030h
00h
-
GAD_EN
STPOUT
MONI
ACB
MACT
RDY
INIT
GAD_EN
1: the high efficient mode
STPOUT
1: step out detected
MONI
1: driver home position
ACB
1: acceleration completed
MACT
1: motor active excluding wait time
0: motor inactive
If the acceleration function is not used, set 1 by step pulse input, and set 0 when speed gets lower than approximately
350pps (pulse interval equivalent to half step).
RDY
1: motor active including wait time
INIT
1: E2PROM download on-going
PHSCNT phase
(Read Only)
Address
Default
Bit7
Bit6
0031h
00h
-
-
PHSCNT
Phase count
phase = 360° ×
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit1
Bit0
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
PHSCNT[5:0]
𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃[5: 0]
64
SPDCEF speed coefficient
(Read Only)
Address
Default
Bit7
Bit6
0032h
00h
-
-
Bit5
Bit4
Bit3
Bit2
SPDCEF[5:0]
SPDCEF[5:0]
Motor speed coefficient
ADDAT_LT_ADJ ADC judgement point voltage (Read Only)
Address
Default
0033h
00h
Bit7
Bit6
Bit5
Bit4
Bit3
ADDAT_LT_ADJ[7:0]
ADDAT_LT_ADJ[7:0]
Code of the ADC judgement point voltage
GADDAT
VREFO coefficient (Read Only)
Address
Default
0034h
00h
GADAT
𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 ×
Bit7
Bit6
Bit5
Bit4
Bit3
GADDAT[7:0]
𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺
256
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LC898240
SERIAL INTERFACE (SPI)
LC898240 has the main chip registers and the
non-volatile memory (E2PROM). They can be
accessed through a serial interface (SPI).
During E2PROM data down load to the main chip
registers, the only status register STS can be read.
During acceleration operation, the only main chip
registers can be access (write/read).
Regarding E3PROM access, refer to the E2PROM
datasheet.
Write/Read Sequence
Main Chip Register Write
CSB
SCK
SI
12h (8bit)
Address (16bit)
Data (8bit)
Hi-Z: pulled-down by resistor
SO
Hi-Z
Hi-Z
Main Chip Register Read
CSB
SCK
SI
13h (8bit)
Address (16bit)
Hi-Z: pulled-down by resistor
SO
Data (8bit)
Hi-Z
Hi-Z
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LC898240
SPI Timing
tCPH
90%
90%
90%
CSB
10%
tCLS
10%
tCSS
90%
tR
tF
tCLHI
tCLLO
tCSH
90%
10%
90%
tCLH
90%
SCK
90%
10%
10%
10%
10%
tDS
tDH
90%
90%
10%
10%
SI
tV
tHO
tCLZ
tCHZ
90%
90%
10%
10%
SO
Ta = -40 to 85°C, DVSS = 0V, DVDD1 = 3.0 to 3.6V, DVDD2 = 3.0 to 5.0V, SO load = 30pF
Symbol
max.
unit
SCK clock frequency
5
MHz
tR
SCK rising time
20
ns
tF
SCK falling time
20
ns
FCLK
Parameter
min.
typ.
tCLHI
SCK H-pulse width
100
ns
tCLLO
SCK L-pulse width
100
ns
tCSS
CSB setup time
100
ns
tCLS
SCK setup time
100
ns
tDS
SI setup time
30
ns
tDH
SI hold time
40
ns
tCSH
CSB hold time
100
ns
tCLH
SCK hold time
100
ns
tCPH
CSB H-pules width
100
ns
tCHZ
SO transition time to high impedance state
tV
170
SO data transition time
90
ns
ns
tHO
SO data hold time
0
ns
tCLZ
SO high impedance state hold time
0
ns
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LC898240
PACKAGE DIMENSIONS
unit : mm
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LC898240
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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23
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