ETC AD484M1644VTA-10LI Ascend semiconductor corporation(64mb sdram) Datasheet

Ascend Semiconductor Corporation
64Mb SDRAM
ASCEND
ASCEND
Semiconductor
Semiconductor
64M
64M SDRAM
SDRAM
Data
Data sheet
sheet
Tel: (03)5635888 / Fax: (03)5635188/ http://www.ascendsemi.com.tw
Preliminary
1
Ascend Semiconductor Corporation
64Mb SDRAM
Ordering Information
AD 48 4M 16 4 4 V T A – 7 L I
Ascend
Semiconductor
EDO
FPM
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
:
:
:
:
:
:
Operating Range
I : Industrial
-40℃ ~ 85℃
Non : Commercial
0℃ ~ 70℃
S : Special
0℃ ~ 85℃
40
41
42
43
46
48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Power
Non : Standard
L : Low power
Min Cycle Time ( Max Freq.)
-55 : 5.5ns ( 183MHz )
-6 : 6ns
( 167MHz )
-7 : 7ns
( 143MHz )
-8 : 8ns
( 125MHz )
-10 : 10ns ( 100MHz )
-15 : 15ns (66MHz,CL1 applicable)
Organization
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32
Refresh
1 : 1K, 8 : 8K
2 : 2K, 6 :16K
4 : 4K
Bank
2 : 2Bank 6 : 16Bank
4 : 4Bank 3 : 32Bank
8 : 8Bank
Interface
V: 3.3V
R: 2.5V
Preliminary
Revision
A : 1st B : 2nd
C : 3rd D :4th
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
2
Ascend Semiconductor Corporation
64Mb SDRAM
64Mb( 4Banks ) Synchronous DRAM
AD484M1644VTA ( 4Mx16 )
Description
The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM )
organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized
with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer rates and is designed to operate in 3.3V
low power memory system. It also provides auto refresh with power saving / down mode.
All inputs and outputs voltage levels are compatible with LVTTL .
Features
• Fully synchronous to positive clock edge
• Single 3.3V +/- 0.3V power supply
• LVTTL compatible with multiplexed address
• Industrial temperature available
• Programmable Burst Length ( BL ) - 1,2,4,8 or full page
• Programmable CAS Latency ( CL ) -1, 2 or 3
• Data Mask ( DQM ) for Read/Write masking
• Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page )
- Interleave ( BL = 1/2/4/8 )
• Burst read with single-bit write operation
• All inputs are sampled at the positive rising edge of the system clock.
• Auto refresh and self refresh
• 4,096 refresh cycles / 64ms
Ordering Information
Part number
Max
Freg.
Package
Operation Range
Power
AD484M1644VTA-55
183MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-6
167MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-7
143MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-15
66MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-7L
143MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Low power
AD484M1644VTA-8L
125MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Low power
AD484M1644VTA-10L
100MHz
54pins,
TSOPII
Commercial Range : 0℃ ~ 70℃
Low power
Note
CL1
* Ascend Semiconductor reserves the right to change products or specification without notice.
Preliminary
3
Ascend Semiconductor Corporation
64Mb SDRAM
Ordering Information
Part number
Max
Freg.
Package
Operation Range
Power
AD484M1644VTA-7I
143MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Standard
AD484M1644VTA-8I
125MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Standard
AD484M1644VTA-10I
100MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Standard
AD484M1644VTA-7LI
143MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Low power
AD484M1644VTA-8LI
125MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Low power
AD484M1644VTA-10LI
100MHz
54pins,
TSOPII
Industrial Range : -40℃ ~ 85℃
Low power
Note
* Ascend Semiconductor reserves the right to change products or specification without notice.
Pin Assignment ( Top View )
V1DD
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
VSSQ
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
VSSQ
12
DQ7
13
V14
DD
LDQM
15
/WE
16
/CAS
17
/RAS
18
/CS
19
BA0
20
BA1
21
A10/AP
22
A0
23
A1
24
A2
25
A3
26
V27
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
54pin TSOP-II
(400milx875mil)
(0.8mm Pin pitch)
Preliminary
4
Ascend Semiconductor Corporation
64Mb SDRAM
Pin Descriptions ( Simplified )
Pin
Name
CLK
/CS
System Clock
Chip select
CKE
Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge)
Selects chip when active
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
Row address (A0 to A11) is determined by A0 to A11 level
at the bank active command cycle CLK rising edge.
CA(CA0 to CA7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge.
And this column address becomes burst access start
address. A10 defines the pre-charge mode. When A10 = High
at the pre-charge command cycle, all banks are pre-charged.
But when A10 = Low at the pre-charge command cycle,
only the bank that is selected by BA0/BA1 is pre-charged.
A0 ~ A11
Address
BA0, BA1
Bank Address
/RAS
Row address strobe
/CAS
Column address strobe
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
/WE
Write Enable
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
LDQM/ UDQM
Data input/output Mask
DQ0 ~ 15
Data input/output
VDD /VSS
Power supply/Ground
VDD and VSS are power supply pins for internal circuits.
VDDQ/VSSQ
Power supply/Ground
VDDQ and VSSQ are power supply pins for the output buffers.
NC
No connection
Selects which bank is to be active.
Latches Row Addresses on the positive rising edge of the
CLK with /RAS “L”. Enables row access & pre-charge.
DQM controls I/O buffers.
DQ pins have the same function as I/O pins on a conventional
DRAM.
This pin is recommended to be left No Connection on the
device.
Preliminary
5
Ascend Semiconductor Corporation
64Mb SDRAM
Block Diagram
Row Decoder
Row Add. Buffer
DQM
Address Register
Memory
Array
Write DQM
Control
Data In
S/A & I/O gating
DQi
Col. Decoder
Data Out
Col. Add. Buffer
Mode Register Set
Read DQM
Control
Col. Add. Counter
DQM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
Auto/Self
Refresh Counter
Burst Counter
Timing Register
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
Preliminary
DQM
6
Ascend Semiconductor Corporation
64Mb SDRAM
Simplified State Diagram
Self
Refresh
LF
SE
LF
SE
Mode
Register
Set
MRS
it
Ex
CBR
Refresh
REF
IDLE
CK
E↓
CK
E
ACT
Power
Down
Read
WRITE
CKE
BS
T
Re
ad
Read
READ
Active
Power
Down
CKE↓
Write
CKE
READ
Suspend
CKE
CKE↓
READA
CKE
POWER
ON
Precharge
PR
E
WRITEA
E
PR
WRITEA
Suspend
h
wit
ad
Re
CKE↓
Wr
ite
wit
h
Write
WRITE
Suspend
CKE↓
Row
Active
CKE↓
READA
Suspend
CKE
Precharge
Manual Input
Automatic Sequence
Preliminary
7
Ascend Semiconductor Corporation
64Mb SDRAM
Address Input for Mode Register Set
BA1 BA0 A11 A10
A9
A8
A7
A6
Operation Mode
A5
A4
CAS Latency
A3
BT
A2
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
BA1
0
0
BA0
0
0
A11
0
0
A10
0
0
A9
0
1
A8
0
0
A6
0
0
0
0
1
1
1
1
A7
0
0
A5
0
0
1
1
0
0
1
1
A0
Burst Length
Burst Length
Sequential Interleave A2
1
1
0
2
2
0
4
4
0
8
8
0
Reserved Reserved
1
Reserved Reserved
1
Reserved Reserved
1
Full Page Reserved
1
Burst Type
Sequential
Interleave
A1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A3
0
1
A4
0
1
0
1
0
1
0
1
Operation Mode
Normal
Burst read with Single-bit Write
Preliminary
8
Ascend Semiconductor Corporation
64Mb SDRAM
Burst Type ( A3 )
Burst Length
2
4
8
Full Page *
A2 A1 A0
XX0
XX1
X00
X01
X10
X11
000
001
010
011
100
101
110
111
nnn
Sequential Addressing
01
10
0123
1230
2301
3012
01234567
12345670
23456701
34567012
45670123
56701234
67012345
70123456
Cn Cn+ 1 Cn+ 2 … ...
Interleave Addressing
01
10
0123
1032
2301
3210
01234567
10325476
23016745
32107654
45670123
54761032
67452301
76543210
-
* Page length is a function of I/O organization and column addressing
x32 (CA0 ~ CA7) : Full page = 256 bits
Preliminary
9
Ascend Semiconductor Corporation
64Mb SDRAM
Truth Table
1. Command Truth Table ( AD484M1644VTA )
Command
Symbol
Ignore Command
No operation
Burst stop
Read
Read with auto pre-charge
Write
Write with auto pre-charge
Bank activate
Pre-charge select bank
Pre-charge all banks
Mode register set
DESL
NOP
BSTH
READ
READA
WRIT
WRITA
ACT
PRE
PALL
MRS
CKE
n-1
n
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
/CS
/RAS /CAS
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
L
L
L
L
L
/WE
X
H
H
L
L
L
H
H
H
H
L
BA0,
A11,
A10
BA1
A9~A0
X
H
L
H
H
L
H
H
L
L
L
X
X
X
V
V
V
V
V
V
X
L
X
X
X
L
H
L
H
V
L
H
L
X
X
X
V
V
V
V
V
X
X
V
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. DQM Truth Table
Command
Symbol
Data write / output enable
Data mask / output disable
Upper byte write enable / output enable
Read
Read with auto pre-charge
Write
Write with auto pre-charge
Bank activate
Pre-charge select bank
Pre-charge all banks
Mode register set
ENB
MASK
BSTH
READ
READA
WRIT
WRITA
ACT
PRE
PALL
MRS
CKE
n-1
n
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
/CS
H
L
L
L
L
L
L
L
L
L
L
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
3. CKE Truth Table
Command
Command
Symbol
Activating
Any
Clock suspend
Idle
Idle
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
CBR refresh command
Self refresh entry
Self refresh
Self refresh exit
Idle
Power down
Power down entry
Power down exit
REF
SELF
CKE
n-1
n
H
L
L
H
H
L
L
H
L
L
L
H
H
L
H
H
L
H
/CS
X
X
X
L
L
L
H
X
X
/RAS /CAS
X
X
X
L
L
H
X
X
X
X
X
X
L
L
H
X
X
X
/WE Addr.
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Remark H = High level, L = Low level, X = High or Low level (Don't care)
Preliminary
10
Ascend Semiconductor Corporation
64Mb SDRAM
4. Operative Command Table
Current
state
Idle
Row active
Read
Write
/CS /R
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
L
X
H
H
H
L
L
L
L
L
/C /W
X
H
L
L
H
H
L
L
X
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
Addr.
Command
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA/A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA/A10
X
Op-Code
DESL
NOP or BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP or BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Action
Nop or power down
Nop or power down
ILLEGAL
ILLEGAL
Row activating
Nop
Refresh or self refresh
Mode register accessing
Nop
Nop
Begin read : Determine AP
Begin write : Determine AP
ILLEGAL
Precharge
ILLEGAL
ILLEGAL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
Terminate burst, new read : Determine AP
Terminate burst, start write : Determine AP
ILLEGAL
Terminate burst, pre-charging
ILLEGAL
ILLEGAL
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
Terminate burst, start read : Determine AP 7, 8
Terminate burst, new write : Determine AP 7
ILLEGAL
Terminate burst, pre-charging
ILLEGAL
ILLEGAL
Notes
2
2
3
3
4
5
5
3
6
4
7
7, 8
3
4
7,8
7
3
9
Remark H = High level, L = Low level, X = High or Low level (Don't care)
Preliminary
11
Ascend Semiconductor Corporation
Current
state
Read with AP
Write with AP
Precharging
Row activating
/CS /R
/C /W
Addr.
Command
64Mb SDRAM
Action
Continue burst to end → Precharging
Continue burst to end → Precharging
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
H
L
H
L
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
H
X
X
X
X
DESL
burst to end → Write
recovering with auto precharge
L
H
H
H
X
NOP
Continue burst to end → Write
recovering with auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
3
3
3
3
3
3
3
3
3
3
3
Nop → Enter idle after tRP
ILLEGAL
ILLEGAL
Nop → Enter idle after tRCD
Nop → Enter idle after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
3
3
3,10
3
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Preliminary
12
Ascend Semiconductor Corporation
Current
state
Write recovering
Write recovering
with AP
Refreshing
Mode Register
Accessing
/CS /R
/C /W
Addr.
Command
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
L
L
X
H
H
H
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
X
H
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
BA/CA/A10
BA/CA/A10
BA/RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/ BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
L
L
X
X
X
ACT/PRE/PALL/
REF/SELF/MRS
64Mb SDRAM
Action
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
8
3
3
3,8
3
3
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states;
→ Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recov ery requirements.
9. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Preliminary
13
Ascend Semiconductor Corporation
64Mb SDRAM
5. Command Truth Table for CKE
Current
state
CKE
n-1
H
L
L
Self refresh
L
L
L
H
H
H
H
Self refresh
recovery
H
H
H
H
H
Power down L
L
H
H
H
H
H
Both banks
H
idle
H
H
H
H
L
H
Row active
L
H
Any state
H
other than
listed above L
L
n
X
H
H
H
H
L
H
H
H
H
L
L
L
L
X
H
L
H
H
H
H
H
L
L
L
L
L
X
X
X
H
L
H
L
/CS /R
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
X
X
/C /W
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
Addr.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Op-Code
X
Op-Code
X
X
X
X
X
X
Action
Notes
INVALID, CLK (n – 1) would exit self refresh
Self refresh recovery
Self refresh recovery
ILLEGAL
ILLEGAL
Maintain self refresh
Idle after tRC
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
INVALID, CLK(n-1) would exit power down
Exit power down → Idle
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refresh
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Self refresh
Refer t o operations in Operative Command Table
Power down
Refer to operations in Operative Command Table
Power down
Refer to operations in Operative Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
1
1
1
2
Remark : H = High level, L = Low level, X = High or Low level (Don't care)
Notes 1. Self refresh can be entered only from the both banks idle state.
Power down can be entered only from both banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Preliminary
14
Ascend Semiconductor Corporation
64Mb SDRAM
Operating Range
Range
Ambient Temperature
Vcc
Commercial
0°C to +70°C
3 V ~ 3.6V
Industrial
-40°C to +85°C
3 V ~ 3.6V
Special
0°C to +85°C
3 V ~ 3.6V
Absolute Maximum Ratings
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-0.3 ~ 4.6
V
VDD , V DDQ
Power Supply Voltage
-0.3 ~ 4.6
V
TSTG
Storage Temperature
-55 ~ 150
C
PD
Power Dissipation
1
W
IOS
Short Circuit Current
50
mA
Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended DC Operation Conditions ( All Operating Range )
Symbol
Parameter
Min.
Typical
Max.
Units
VDD
Power Supply Voltage
3.0
3.3
3.6
V
VDDQ
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
VIH
Input logic high voltage
2.0
VDD+0.3
V
VIL
Input logic low voltage
-0.3
0.8
V
Note : 1. All voltage referred to VSS.
2. VIH (max) = 5.6V for pulse width ≤ 3ns
3. VIL (min) = -2.0V for pulse width ≤ 3ns
Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25 C )
Symbol
Parameter
Min.
Max.
Units
CCLK
Clock capacitance
2.5
4.0
pF
CI
Input capacitance for CLK, CKE, Address, /CS,
/RAS, /CAS, /WE, DQML,DQMU
2.5
5.0
pF
CO
Input/Output capacitance
4.0
6.5
pF
Preliminary
15
Ascend Semiconductor Corporation
64Mb SDRAM
Recommended DC Operating Conditions
( VDD = 3.3V +/- 0.3 V, All Operating Range)
Parameter
Operating current
Precharge standby
current in power down
mode
Precharge standby
current in non-power
down mode
Active standby current
in power down mode
Active standby current
in non-power down
mode
(4 bank activated)
Operating current
(Burst mode)
Symbol
ICC1
MAX
Test condition
Burst length = 1,
tRC ≥ tRC (min), IOL = 0 mA,
One bank active
Units Notes
-5.5
-6
-7
-8
CL=1
--
--
--
--
CL=2
--
--
--
CL=3
Standard
-10 -15
--
75
100 95
--
135 120 110 100 95
1000
500
1000
500
--
mA
uA
uA
uA
ICC2P
CKE ≤ VIL (max.), tCk = 15 ns
ICC2PS
CKE ≤ VIL (max.), tCk = ∞
ICC2N
CKE ≥ VIH (min.), tCK = 15 ns,
/CS ≥ VIH (min.)Input signals are changed
one time during 30ns
35
mA
ICC2NS
CKE ≥ VIH(min.), tCK = ∞
Input signals are stable
25
mA
ICC3P
CKE ≤ VIL(max), tCK = 15ns
8
mA
ICC3PS
CKE ≤ VIL(max), tCK = ∞
8
mA
ICC3N
CKE ≥ VIH(min), tCK = 15ns,
/ CS ≥ VIH(min) Input signals are
changed one time during 30ns
50
mA
ICC3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
40
mA
ICC4
tCCD = 2CLKs , I OL = 0 mA
Low power
Standard
Low power
CL=1
--
--
--
CL=2
--
--
--
ICC5
tRC ≥ t RC(min.)
Self Refresh current
ICC6
CKE ≤ 0.2V
--
uA
80
mA
2
160 150 145 140 130 85
mA
3
Standard
1
mA
4
Low power
500
uA
5
CL=3
Refresh current
--
1
110 100
--
150 140 130 120 110
--
Note : 1. ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK(min)
2. ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK(min)
3. Input signals are changed only one time during tCK(min)
4. Standard power version.
5. Low power version.
Preliminary
16
Ascend Semiconductor Corporation
64Mb SDRAM
Recommended DC Operating Conditions ( Continued )
Parameter
Symbol
Input leakage current
IIL
Output leakage current
Test condition
Min.
Max.
Unit
0 ≤ VI ≤ VDDQ, VDDQ=VDD
All other pins not under test=0 V
-0.5
+0.5
uA
IOL
0 ≤ VO ≤ VDDQ, DOUT is disabled
-0.5
+0.5
uA
High level output voltage
VOH
Io = -4mA
2.4
Low level output voltage
VOL
Io = +4mA
V
0.4
V
AC Operating Test Conditions
( VDD = 3.3V +/- 0.3 V, All Operating Range )
Output Reference Level
1.4V / 1.4V
Output Load
See diagram as below
Input Signal Level
2.4V / 0.4V
Transition Time of Input Signals
2ns
Input Reference Level
1.4V
Vtt = 1.4V
50Ω
Output
Z = 50Ω
50pF
Preliminary
17
Ascend Semiconductor Corporation
64Mb SDRAM
Operating AC Characteristics
( V DD = 3.3V +/- 0.3 V, All Operating Range )
-55
Symbol
Parameter
-6
-7
-8
-10
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CL = 3
Clock cycle time
tCK
CL = 2
CL = 3
Access time from CLK
5.5
_
6
_
4.5
_
tAC
CL = 2
7
8
10
ns
10
10
10
ns
5.5
5.5
6
6
ns
_
6
6
6
ns
CLK high level width
tCH
2.0
2.5
3
3
3
ns
CLK low level width
tCL
2.0
2.5
3
3
3
ns
2.0
2.5
_
2.5
2.5
2.5
ns
2
1.5
1.5
1.5
ns
3
Data-out hold time
CL = 3
tOH
CL = 2
Data-out to high impedance time
CL = 3
_
tHZ
CL = 2
4.5
5
5.5
6
6
ns
_
_
5.5
6
6
ns
4
Data-out to low impedance time
tLZ
1
1
1
1
1
ns
Input hold time
1
1
1
1
1
ns
6
Input setup time
tIH
tIS
1.5
1.5
2
2
2
ns
6
ACTIVE to ACTIVE command period
tRC
60
60
63
64
70
ns
5
ACTIVE to PRECHARGE command period
tRAS
42 100k
42
50
100k ns
5
PRECHARGE to ACTIVE command period
tRP
18
18
18
18
20
ns
5
ACTIVE to READ/WRITE delay time
tRCD
18
18
18
18
20
ns
5
ACTIVE(one) to ACTIVE(another) command
tRRD
10
12
14
16
18
ns
5
READ/WRITE command to READ/WRITE
command
tCCD
1
1
1
1
1
CLK
Data-in to PRECHARGE command
tDPL
2
2
2
2
2
CLK
Data-in to BURST stop command
tBDL
1
1
1
1
1
CLK
3
3
3
3
3
CLK
2
2
2
2
2
CLK
Data-out to high impedance from
PRECHARGE command
Refresh time(4,096 cycle)
CL = 3
tROH
CL = 2
tREF
64
100k
45
64
Preliminary
100k
64
46
100k
64
64
ms
18
Ascend Semiconductor Corporation
Operating AC Characteristics--
64Mb SDRAM
Continues
( V DD = 3.3V +/- 0.3 V, All Operating Range )
-15
Symbol
Parameter
Units Notes
Min. Max.
Clock cycle time
CL = 1
tCK
Access time from CLK
CL = 1
tAC
15
ns
12
ns
CLK high level width
tCH
3
ns
CLK low level width
tCL
3
ns
tOH
2
ns
3
ns
4
CL = 1
Data-out hold time
Data-out to high impedance time
CL = 1
tHZ
6
Data-out to low impedance time
tLZ
1
ns
Input hold time
1
ns
6
Input setup time
tIH
tIS
2
ns
6
ACTIVE to ACTIVE command period
tRC
90
ns
5
ACTIVE to PRECHARGE command period
tRAS
60
100k ns
5
PRECHARGE to ACTIVE command period
tRP
22
ns
5
ACTIVE to READ/WRITE delay time
tRCD
25
ns
5
ACTIVE(one) to ACTIVE(another) command
tRRD
15
ns
5
READ/WRITE command to READ/WRITE
command
tCCD
1
CLK
Data-in to PRECHARGE command
tDPL
1
CLK
Data-in to BURST stop command
tBDL
1
CLK
tROH
1
CLK
Data-out to high impedance from
PRECHARGE command
Refresh time(4,096 cycle)
CL = 1
tREF
64
ms
Note :
1. All voltages referenced to Vss.
2. For commercial range parts.
3. For industrial range parts.
4. tHZ defines the time at which the output achieve the open circuit
condition and is not referenced to output voltage levels.
5. These parameters account for the number of clock cycle and
depend on the operating frequency of the clock, as follows :
The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number)
6.These parameters are for address/command/data/CLK/CKE.
7. Any “– “ sign on the data means “ No guarantee” .
Preliminary
19
Ascend Semiconductor Corporation
64Mb SDRAM
Package Dimension
Dimension in Milimeter/Inchs
1.20 MAX
0.047
1.00+/- 0.10
0.039+/- 0.004
0.463 +/- 0.008
0.05 MIN
0.002
#1
#54
#27
#28
0.125 +0.075 / -0.035
0.005+0.003 / -0.001
10.16
0.400
0
–
8’
0.50
0.020
0.45 ~ 0.75
0.018 ~ 0.030
0.25
TYP
0.010
0.10
MAX
0.004
0.71
0.028
0.80
0.035
22.22+/- 0.10
0.875+/- 0.004
22.62 MAX
0.891
0.35 +0.1 / -0.1
0.014+0.004 / -0.004
0.21+/- 0.05
0.008+/- 0.002
11.76 +/- 0.20
* Ascend reserves the right to change products or specification without notice.
Preliminary
20
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