ETC2 FT25C32A Spi serial eeprom Datasheet

Fremont Micro Devices
FT25C32A DS
SPI Serial EEPROM
32K (8-bit wide)
FEATURES

Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 (0,0) and 3 (1,1)


Data Sheet Describes Mode 0 Operation
Low voltage and low power operations

FT25C32A VCC = 1.8V to 5.5V

20MHz clock rate (5V)

Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively)

Partial page write operation allowed (32 bytes page write mode)

Self-timed programming cycle (5 ms max)

Block Write Protection (Protect 1/4, 1/2, or Entire Array)

Write protect pin for hardware data protection

High reliability: typically 1,000,000 cycles endurance

100 years data retention

Industrial temperature range (-40℃to 85℃)

Standard 8-pin DIP/SOP/TSSOP Pb-free packages
DESCRIPTION
The FT25C32A is 32768 bits of serial Electrical Erasable and Programmable Read Only Memory,
commonly known as EEPROM. They are organized as 4096 words of 8 bits (1 byte) each. The devices are
fabricated with proprietary advanced CMOS process for low power and low voltage applications. These
devices are available in standard 8-lead DIP, 8-lead SOP and 8-lead TSSOP packages. The memory is
accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence. While the device is
paused, transitions on its inputs will be ignored. Our extended VCC range (1.8V to 5.5V) devices enables
wide spectrum of applications.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A - Page1
Fremont Micro Devices
FT25C32A DS
PIN CONFIGURATION
Pin Name
Pin Function
Pin Name
Pin Function
CS
Chip Select
GND
Ground
SCL
Serial Clock Input
VCC
Power Supply
SI
Serial Data Input
WP
Write Protest
SO
Serial Data Output
HOLD
Suspends Serial Input
All these packaging types come in conventional or Pb-free certified.
FT25C32A
CS 1
SO
WP
GND
2
3
4
8 VCC
7 HOLD
6 SCL
5 SI
8L DIP
8L SOP
8L TSSOP
Figure 1: Packaging Types
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature………………………………………………………………………-40℃ to 85℃
Storage temperature………………………………………………………………………………….-50℃ to 125℃
Input voltage on any pin relative to ground……………………………………………………-0.3V to VCC + 0.3V
Maximum voltage……………………………………………………………………………………………………8V
ESD protection on all pins……………………………………………………………………………………>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to
the device. Functional operation of the device at conditions beyond those listed in the specification
is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or
functionality.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page2
Fremont Micro Devices
FT25C32A DS
Block Diagram
VCC
STATUS
REGISTER
GND
MEMORY
ARRAY
ADDRESS
DECODER
DATA
REGISTER
SI
CS
WP
SCK
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
SO
HOLD
Figure 2: Block Diagram
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Confidential Rev 0.81
DS25C32A-Page3
Fremont Micro Devices
FT25C32A DS
PIN DESCRIPTIONS
(A) CHIP SELECT ( CS )
The FT25C32A is selected when the CS pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
(B) Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
(C)Serial Output (SO)
The SO pin is used to transfer data out of the FT25C32A. During a read cycle, data is shifted out on this pin
after the falling edge of the serial clock.
(D) Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the FT25C32A. Instructions,
addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock input.
(E) Write Protect ( WP )
This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile
bits in the status register. When WP is low and WPEN is high, writing to the non-volatile bits in the status
register is disabled. All other operations function normally. When WP is high, all functions, including
writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set, WP low during
a status register write sequence will disable writing to the status register. If an internal write cycle has
already begun, WP going low will have no effect on the write. The WP pin function is blocked when the
WPEN bit in the status register is low. This allows the user to install the FT25C32A in a system with WP
pin grounded and still be able to write to the status register. The WP pin functions will be enabled when
the WPEN bit is set high.
(F) Hold ( HOLD )
The HOLD pin is used in conjunction with the CS pin to select the FT25C32A. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with
the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low
while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK
pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
MEMORY ORGANIZATION
The FT25C32A devices have 128 pages respectively. Since each page has 32 bytes, random word
addressing to FT25C32A will require 12 bits data word addresses respectively.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page4
Fremont Micro Devices
FT25C32A DS
DEVICE OPERATION
The FT25C32A utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in Table A. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Table A Instruction Set for the FT25C32A
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
(A) STATUS REGISTER OPERATION
Table B Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction
disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status
register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR
instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits
are set by using the WRSR instruction.
Table C Status Register Bit Definition
Bit
Bit 0 ( RDY )
Bit 1 (WEN)
Definition
Bit 0 = “0” ( RDY ) indicates the device is READY. Bit 0 = “1”
indicates the write cycle is in progress.
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1”
indicates the device is write enabled.
Bit 2 (BP0)
See table D.
Bit 3 (BP1)
See table D.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See table E.
Bits 0-7 are “1” during an internal write cycle.
© 2013 Fremont Micro Devices Inc.
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DS25C32A-Page5
Fremont Micro Devices
FT25C32A DS
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of
protection. The FT25C32A is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The
block write protection levels and corresponding status register control bits are shown in Table D. The three
bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular
memory cells.
Table D Block Write Protect Bits
Level
Status Register Bits
Array Address Protected
BP1
BP0
0
0
0
None
1(1/4)
0
1
0C00-0FFF
2(1/2)
1
0
0800-0FFF
3(All)
1
1
0000-0FFF
The WRSR instruction also allows the user to enable or disable the write protect ( WP ) pin through the use
of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and
the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN
bit is “0”. When the device is hardware write protected, writes to the status register, including the block
protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as
the WP pin is held low.
Table E WPEN Operation
WPEN
WP
WEN
0
X
0
Protected Unprotected
Status Register
Blocks
Blocks
0
Protected
Protected
Protected
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
(B) EEPROM OPERATION
READ SEQUENCE (READ): Reading the FT25C32A via the serial output (SO) pin requires the following
sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line
followed by the byte address to be read (A15−A0, see Table F). Upon completion, any data on the SI line
will be ignored. The data (D7−D0) at the specified address is then shifted out onto the SO line. If only one
byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be
continued since the byte address is automatically incremented and data will continue to be shifted out.
When the highest address is reached, the address counter will roll over to the lowest address (0000h),
allowing the entire memory to be read in one continuous read cycle.
© 2013 Fremont Micro Devices Inc.
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DS25C32A-Page6
Fremont Micro Devices
FT25C32A DS
WRITE SEQUENCE (WRITE): In order to program the FT25C32A, two separate instructions must be
executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE)
instruction may be executed. Also, the address of the memory location(s) to be programmed must be
outside the protected address field location selected by the block write protection level. During an internal
write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the
WRITE op-code is transmitted via the SI line followed by the byte address (A15−A0) and the data (D7–D0)
to be programmed (See Table F). Programming will start after the CS pin is brought high. The low-to-high
transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB)
data bit.
The FT25C32A is capable of a 32-byte page write operation. After each byte of data is received, the five
low-order address bits are internally incremented by one; the high order bits of the address will remain
constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously
written data will be overwritten. The FT25C32A is automatically returned to the write disable state at the
completion of a write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the write instruction and will return
to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
The READY/BUSY status of the device can be determined by initiating a read status register (RDSR)
instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
Table F
Address Key
Address
FT25C32A
AN
A11-A0
Don’t Care Bits
A15-A12
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DS25C32A-Page7
Fremont Micro Devices
FT25C32A DS
CS
tHDN
tHDN
SCL
tHDS
tHDS
HOLD
tHZ
SO
tLZ
Figure 3: HOLD Timing
VIH
CS
tCS
VIL
tCSH
tCSS
VIH
SCL
VIL
tWH
tSU
tWL
tH
VIH
SI
VALID IN
VIL
tHO
tV
VOH
SO
tDIS
HI-Z
HI-Z
VOL
Figure 4: Synchronous Data Timing (for Mode 0)
CS
SCL
SI
SO
WREN INST
HI-Z
Figure 5: WREN Timing
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DS25C32A-Page8
Fremont Micro Devices
FT25C32A DS
CS
SCL
SI
WRDI INST
HI-Z
SO
Figure 6: WRDI Timing
CS
SCL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7
6
5
4
3
2
1
0
R D S R IN S T
SI
H I-Z
SO
MSB
Figure 7: RDSR Timing
CS
0
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
WRSR INST
SI
7
3
2
HI-Z
SO
Figure 8: WRSR Timing
CS
SCL
0
1
2
3
4
5
6
7
8
9
15
14
22
23
24
25
26
27
7
6
5
4
28
29
30
31
1
0
Byte Address
SI
SO
READ INST
1
0
DATA OUT
HI-Z
3
2
MSB
Figure 9: READ Timing
© 2013 Fremont Micro Devices Inc.
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DS25C32A-Page9
Fremont Micro Devices
FT25C32A DS
CS
SCL
0
1
2
3
4
5
6
7
8
9
22
23
24
25
26
WRITE INST
15
14
28
29
30
31
1
0
DATA IN
Byte Address
SI
27
1
0
7
6
5
4
3
2
HI-Z
SO
Figure 10: WRITE Timing
AC CHARACTERISTICS
Applicable over recommended operating range from: TAI =-40℃ to +85℃，VCC = As Specified, CL= 1 TTL
Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
FT25C32A
1.8-2.7 V
Min
Max
2.7-4.5 V
Min
Max
4.5-5.5 V
Min
Unit
Max
fSCK
Clock frequency, SCK
5
10
20
MHz
tRI
Input Rise Time
2
2
2
µs
tFI
Input Fall Time
2
2
2
µs
tWH
SCK High Time
80
40
20
ns
tWL
SCK Low Time
80
40
20
ns
tCS
CS High Time
100
50
25
ns
tCSS
CS Setup Time
100
50
25
ns
tCSH
CS Hold Time
100
50
25
ns
tSU
Data In Setup Time
20
10
5
ns
tH
Data In Hold Time
20
10
5
ns
tHD
HOLD Setup Time
20
10
5
ns
tCD
HOLD Hold Time
20
10
5
ns
tV
Output Valid
0
tHO
Output Hold Time
0
tLZ
HOLD to Output Low Z
0
tHZ
HOLD to Output High Z
200
tDIS
Output Disable Time
tWC
Write Cycle Time
© 2013 Fremont Micro Devices Inc.
80
0
40
0
100
0
0
20
0
50
ns
25
ns
80
40
ns
200
80
40
ns
5
5
5
ms
Confidential Rev 0.81
0
ns
DS25C32A-Page10
Fremont Micro Devices
FT25C32A DS
DC CHARACTERISTICS
Applicable over recommended operating range from:TAI =-40℃ to +85℃，VCC = +1.8V to +5.5V(unless
otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typi
cal
Max
Unit
VCC1
Supply Voltage
1.8
5.5
V
VCC2
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
10.0
mA
ICC2
Supply Current
10.0
mA
ICC3
Supply Current
6.0
mA
ISB1
Standby current
VCC = 1.8V, CS = VCC
1.0
µA
ISB2
Standby current
VCC = 2.7V, CS = VCC
1.0
µA
ISB3
Standby current
VCC = 5.0V, CS = VCC
1.0
µA
IIL
Input leakage
VIN = VCC or VSS
3.0
µA
IOL
Output leakage
VIN = VCC or VSS
3.0
µA
VIL (1)
Input low level
-0.6
VCC 0.3
V
VIH(1)
Input high level
VCC 0.7
VCC  0.5
V
VOL1
Output low level
3.6V≤VCC≤5.5V, IOL = 3.0mA
0.4
V
VOH1
Output High level
3.6V≤VCC≤5.5V, IOH =-1.6mA
VOL2
Output low level
1.8V≤VCC≤3.6V, IOL = 0.15mA
0.2
V
VOH2
Output High level
1.8V≤VCC≤3.6V, IOH =-100uA
VCC=5.0V @ 20MHz, SO=Open,
Read
VCC=5.0V @ 20MHz, SO=Open,
Write
VCC=5.0V @ 5MHz, SO=Open,
Read, Write
0.06
VCC 
VCC 
Notes:1. VIL min and VIH max are reference only and are not tested.
© 2013 Fremont Micro Devices Inc.
Confidential Rev 0.81
DS25C32A-Page11
Fremont Micro Devices
FT25C32A DS
ORDERING INFORMATION:
FT25C32A - X X X - X
Circuit Type
Packaging
B: Tube
T: Tape and Reel
Temp. Range
HSF
U: -40℃-85℃
R: RoHS
G: Green
Package
D: DIP8
S: SOP8
T: TSSOP8
Density
Package
DIP8
Temperature
Range
-40℃-85℃
Vcc
1.8V-5.5V
HSF
Packaging
Ordering Code
RoHS
Tube
FT25C32A-UDR-B
Green
Tube
FT25C32A-UDG-B
Tube
FT25C32A-USR-B
Tape and Reel
FT25C32A-USR-T
Tube
FT25C32A-USG-B
Tape and Reel
FT25C32A-USG-T
Tube
FT25C32A-UTR-B
Tape and Reel
FT25C32A-UTR-T
Tube
FT25C32A-UTG-B
Tape and Reel
FT25C32A-UTG-T
RoHS
SOP8
-40℃-85℃
1.8V-5.5V
Green
32kbits
RoHS
TSSOP8
-40℃-85℃
1.8V-5.5V
Green
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Confidential Rev 0.81
DS25C32A-Page12
Fremont Micro Devices
FT25C32A DS
DIP8 PACKAGE OUTLINE DIMENSIONS
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
3.710
4.310
0.146
0.170
A1
0.510
A2
3.200
3.600
0.126
0.142
B
0.380
0.570
0.015
0.022
B1
0.020
1.524（BSC）
0.060（BSC）
C
0.204
0.360
0.008
0.014
D
9.000
9.400
0.354
0.370
E
6.200
6.600
0.244
0.260
E1
7.320
7.920
0.288
0.312
e
2.540 (BSC)
0.100（BSC）
L
3.000
3.600
0.118
0.142
E2
8.400
9.000
0.331
0.354
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DS25C32A-Page13
Fremont Micro Devices
FT25C32A DS
SOP8 PACKAGE OUTLINE DIMENSIONS
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
1.350
1.750
0.053
0.069
A1
0.100
0.250
0.004
0.010
A2
1.350
1.550
0.053
0.061
b
0.330
0.510
0.013
0.020
c
0.170
0.250
0.006
0.010
D
4.700
5.100
0.185
0.200
E
3.800
4.000
0.150
0.157
E1
5.800
6.200
0.228
0.244
e
1.270 (BSC)
0.050 (BSC)
L
0.400
1.270
0.016
0.050
θ
0°
8°
0°
8°
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DS25C32A-Page14
Fremont Micro Devices
FT25C32A DS
TSSOP8 PACKAGE OUTLINE DIMENSIONS
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
D
2.900
3.100
0.114
0.122
E
4.300
4.500
0.169
0.177
b
0.190
0.300
0.007
0.012
c
0.090
0.200
0.004
0.008
E1
6.250
6.550
0.246
0.258
A
1.100
0.043
A2
0.800
1.000
0.031
0.039
A1
0.020
0.150
0.001
0.006
e
L
0.65 (BSC)
0.500
H
θ
0.026 (BSC)
0.700
0.020
0.25 (TYP)
1°
© 2013 Fremont Micro Devices Inc.
0.028
0.01 (TYP)
7°
1°
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7°
DS25C32A-Page15
Fremont Micro Devices
FT25C32A DS
Fremont Micro Devices (SZ) Limited
#5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen, Guangdong 518057
Tel: (86 755) 86117811
Fax: (86 755) 86117810
Fremont Micro Devices (Hong Kong) Limited
#16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong
Tel: (852) 27811186
Fax: (852) 27811144
Fremont Micro Devices (USA), Inc.
42982 Osgood Road Fremont, CA 94539
Tel: (1-510) 668-1321
Fax: (1-510) 226-9918
Web Site: http://www.fremontmicro.com/
* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices,
Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any
infringement of patents of other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI).
Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI)
products are not authorized for use as critical components in life support devices or systems without
express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered
trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their
respective owners.
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