LM5112 www.ti.com SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 LM5112 Tiny 7A MOSFET Gate Driver Check for Samples: LM5112 FEATURES DESCRIPTION • The LM5112 MOSFET gate driver provides high peak gate drive current in the tiny WSON-6 package (SOT23 equivalent footprint) or an 8-Lead exposed-pad MSOP package, with improved power dissipation required for high frequency operation. The compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 7A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is provided to prevent damage to the MOSFET due to insufficient gate turn-on voltage. The LM5112 provides both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive with a single device type. 1 2 • • • • • • • • Compound CMOS and Bipolar Outputs Reduce Output Current Variation 7A sink/3A Source Current Fast Propagation Times (25 ns Typical) Fast Rise and Fall Times (14 ns/12 ns Rise/Fall with 2 nF Load) Inverting and Non-inverting Inputs Provide Either Configuration with a Single Device Supply Rail Under-voltage Lockout Protection Dedicated Input Ground (IN_REF) for Split Supply or Single Supply Operation Power Enhanced 6-pin WSON Package (3.0mm x 3.0mm) or Thermally Enhanced MSOPPowerPAD Package Output Swings from VCC to VEE Which can be Negative Relative to Input Ground Block Diagram VCC UVLO IN OUT Level Shift INB VEE IN_REF Figure 1. Block Diagram of LM5112 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated LM5112 SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 www.ti.com Pin Configurations IN VEE VCC 6 1 INB IN_REF 2 IN_REF 1 8 N/C INB 2 7 OUT VEE 3 6 VCC IN 4 5 N/C 5 4 3 OUT Figure 2. WSON-6 Figure 3. MSOP-PowerPAD-8 PIN DESCRIPTIONS Pin Name Description Application Information WSON-6 MSOP-8 1 4 IN Non-inverting input pin TTL compatible thresholds. Pull up to VCC when not used. 2 3 VEE Power ground for driver outputs Connect to either power ground or a negative gate drive supply for positive or negative voltage swing. 3 6 VCC Positive Supply voltage input Locally decouple to VEE. The decoupling capacitor should be located close to the chip. 4 7 OUT Gate drive output Capable of sourcing 3A and sinking 7A. Voltage swing of this output is from VEE to VCC. 5 1 IN_REF Ground reference for control inputs Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply. 6 2 INB Inverting input pin TTL compatible thresholds. Connect to IN_REF when not used. --- 5, 8 N/C Not internally connected --- --- Exposed Pad Exposed Pad, underside of package Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 LM5112 www.ti.com SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 Absolute Maximum Ratings (1) (2) VCC to VEE −0.3V to 15V VCC to IN_REF −0.3V to 15V IN/INB to IN_REF −0.3V to 15V −0.3V to 5V IN_REF to VEE −55°C to +150°C Storage Temperature Range Maximum Junction Temperature +150°C Operating Junction Temperature −40°C+125°C ESD Rating (1) (2) 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Electrical Characteristics TJ = −40°C to +125°C, VCC = 12V, INB = IN_REF = VEE = 0V, No Load on output, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 14 V 3.0 3.5 SUPPLY VCC VCC Operating Range VCC – IN_REF and VCC - VEE 3.5 UVLO VCC Under-voltage Lockout (rising) VCC – IN_REF 2.4 VCCH VCC Under-voltage Hysteresis 230 ICC VCC Supply Current 1.0 V mV 2.0 mA CONTROL INPUTS VIH Logic High 2.3 V VIL Logic Low 0.8 V VthH High Threshold 1.3 1.75 2.3 V VthL Low Threshold 0.8 1.35 2.0 V HYS Input Hysteresis IIL Input Current Low IN = INB = 0V -1 0.1 1 µA IIH Input Current High IN = INB = VCC -1 0.1 1 µA 400 mV OUTPUT DRIVER ROH Output Resistance High IOUT = -10mA (1) 30 50 Ω ROL Output Resistance Low IOUT = 10mA (1) 1.4 2.5 Ω ISOURCE Peak Source Current OUT = VCC/2, 200ns pulsed current 3 A ISINK Peak Sink Current OUT = VCC/2, 200ns pulsed current 7 A (1) The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 3 LM5112 SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 www.ti.com Electrical Characteristics (continued) TJ = −40°C to +125°C, VCC = 12V, INB = IN_REF = VEE = 0V, No Load on output, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SWITCHING CHARACTERISTICS td1 Propagation Delay Time Low to High, IN/ INB rising ( IN to OUT) CLOAD = 2 nF, see Figure 4 and Figure 5 25 40 ns td2 Propagation Delay Time High to Low, IN / INB falling (IN to OUT) CLOAD = 2 nF, see Figure 4 and Figure 5 25 40 ns tr Rise time CLOAD = 2 nF, see Figure 4 and Figure 5 14 ns tf Fall time CLOAD = 2 nF, see Figure 4 and Figure 5 12 ns TJ = 150°C 500 mA LATCHUP PROTECTION AEC –Q100, METHOD 004 THERMAL RESISTANCE θJA Junction to Ambient, 0 LFPM Air Flow WSON-6 Package MSOP-PowerPAD Package 40 60 °C/W θJC Junction to Case WSON-6 Package MSOP-PowerPAD Package 7.5 4.7 °C/W Timing Waveforms 50% 50% 50% 50% IN INB tD1 tD2 tD1 tD2 OUTPUT 90% 90% OUTPUT 10% 10% tf tr tr Figure 4. Inverting 4 tf Figure 5. Non-Inverting Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 LM5112 www.ti.com SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 Typical Performance Characteristics Supply Current vs Frequency 100 Supply Current vs Capacitive Load 100 f = 500kHz SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VCC = 15V 10 VCC = 10V 1 VCC = 5V 10 f = 100kHz 1 f = 10kHz TA = 25°C TA = 25°C VCC = 12V CL = 2200pF 0.1 1 0.1 10 100 1000 CAPACITIVE LOAD (pF) FREQUENCY (kHz) Figure 6. Figure 7. Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 18 20 TA = 25°C VCC = 12V CL = 2200pF 18 tr 16 14 tr CL = 2200pF 16 TIME (ns) TIME (ns) 10k 1k 100 14 tf 12 tf 10 12 10 8 5 6 4 50 7 8 9 10 11 12 13 14 15 16 -75 -50 -25 0 25 50 75 100 125 150 175 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 8. Figure 9. Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 32.5 TA = 25°C 40 30 VCC = 12V tD2 30 TIME (ns) TIME (ns) 27.5 tr 20 25 tD1 22.5 tf 10 TA = 25°C 20 CL = 2200pF 0 17.5 100 1k 10k CAPACITIVE LOAD (pF) 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 5 LM5112 SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 www.ti.com Typical Performance Characteristics (continued) Delay Time vs Temperature 35 RDSON vs Supply Voltage 3.25 65 VCC = 12V 32.5 TA = 25°C CL = 2200pF IOUT = 10mA 2.75 tD2 55 25 tD1 45 2.25 ROH 1.75 35 ROH (:) 27.5 ROL (:) TIME (ns) 30 22.5 1.25 17.5 -75 -50 -25 0 15 0.75 25 50 75 100 125 150 175 3 0 TEMPERATURE (°C) 9 12 15 Figure 13. UVLO Thresholds and Hysteresis vs Temperature Peak Current vs Supply Voltage 8 0.450 7 SINK 0.390 2.9 18 SUPPLY VOLTAGE (V) VCC - rising VCC - falling 2.6 0.330 2.3 0.270 Hysteresis CURRENT (A) 6 HYSTERESIS (V) UVLO THRESHOLDS (V) 6 Figure 12. 3.2 5 4 SOURCE 3 2 0.210 2.0 TA = 25°C 1 1.7 -75 -50 -25 0 0.150 25 50 75 100 125 150 175 VOUT = 5V 0 5 7 9 11 13 15 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 14. 6 25 ROL 20 Figure 15. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 LM5112 www.ti.com SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 Simplified Application Block Diagram VOUT VIN +10V +5V VCC LM5110-1 VCC UVLO LM5025 CONTROLLER IN_REF IN_REF IN OUT INB OUT_B OUT_B IN_REF IN_REF FB VEE INB OUT_A IN_A OUT_A VEE VEE LM5112 -3V Dual Supply utilizing negative Output voltage Drive Figure 16. Simplified Application Block Diagram DETAILED OPERATING DESCRIPTION The LM5112 is a high speed , high peak current (7A) single channel MOSFET driver. The high peak output current of the LM5112 will switch power MOSFET’s on and off with short rise and fall times, thereby reducing switching losses considerably. The LM5112 includes both inverting and non-inverting inputs that give the user flexibility to drive the MOSFET with either active low or active high logic signals. The driver output stage consists of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical Miller plateau region of the MOSFET VGS , while the MOS device provides rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the driver are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. When driving the MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power ground. The isolated input and output stage grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the LM5112 inputs. The VEE pin is connected to a negative bias supply that can range from the IN_REF potential to as low as 14 V below the Vcc gate drive supply. For reliable operation, the maximum voltage difference between VCC and IN_REF or between VCC and VEE is 14V. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 7 LM5112 SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 www.ti.com The minimum recommended operating voltage between Vcc and IN_REF is 3.5V. An Under Voltage Lock Out (UVLO) circuit is included in the LM5112 which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.8V the driver is disabled and the output pin is held in the low state. The UVLO hysteresis prevents chattering during brown-out conditions; the driver will resume normal operation when the VCC to IN_REF differential voltage exceeds 3.0V. Layout Considerations Attention must be given to board layout when using LM5112. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET. 2. Proper grounding is crucial. The driver needs a very low impedance path for current return to ground avoiding inductive loops. Two paths for returning current to ground are a) between LM5112 IN_REF pin and the ground of the circuit that controls the driver inputs and b) between LM5112 VEE pin and the source of the power MOSFET being driven. Both paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. These ground paths should be distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5112. With rise and fall times in the range of 10 to 30nsec, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated when driving large capacitive loads. 3. If either channel is not being used, the respective input pin (IN or INB) should be connected to either VEE or VCC to avoid spurious output signals. Thermal Performance INTRODUCTION The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (Tj) below a specified limit to ensure reliable long term operation. The maximum TJ of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the PCB design and the operating environment. DRIVE POWER REQUIREMENT CALCULATIONS IN LM5112 LM5112 is a single low side MOSFET driver capable of sourcing / sinking 3A / 7A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. VGATE VHIGH Q1 RG VTRIG CIN Q2 The schematic above shows a conceptual diagram of the LM5112 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. Rg is the gate resistance of the external MOSFET, and Cin is the equivalent gate capacitance of the MOSFET. The equivalent gate capacitance is a difficult parameter to measure as it is the combination of Cgs (gate to source capacitance) and Cgd (gate to drain capacitance). The Cgd is not a constant and varies with the drain voltage. The better way of quantifying gate capacitance is the gate charge Qg in coloumbs. Qg combines the charge required by Cgs and Cgd for a given gate drive voltage Vgate. The gate resistance Rg is usually very small and losses in it can be neglected. The total power dissipated in the MOSFET driver due to gate charge is approximated by: PDRIVER = VGATE x QG x FSW 8 Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 LM5112 www.ti.com SNVS234B – SEPTEMBER 2004 – REVISED APRIL 2006 where • FSW = switching frequency of the MOSFET (1) For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. Therefore, the power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. (2) In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. When either output of the LM5112 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5112 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.118 + 0.008 + 0.012 = 0.138W. (3) We know that the junction temperature is given by TJ = PD x θJA + TA (4) Or the rise in temperature is given by TRISE = TJ − TA = PD x θJA (5) For WSON-6 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance (θJA). By providing suitable means of heat dispersion from the IC to the ambient through exposed copper pad, which can readily dissipate heat to the surroundings, θJA as low as 40°C / Watt is achievable with the package. The resulting Trise for the driver example above is thereby reduced to just 5.5 degrees. Therefore TRISE is equal to TRISE = 0.138 x 40 = 5.5°C (6) For MSOP-PowerPAD θJA is typically 60°C/W. Submit Documentation Feedback Copyright © 2004–2006, Texas Instruments Incorporated Product Folder Links: LM5112 9 PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5112MY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJJB LM5112MYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SJJB LM5112Q1SD/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L250B LM5112Q1SDX/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L250B LM5112SD NRND WSON NGG 6 1000 TBD Call TI Call TI -40 to 125 L132B LM5112SD/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L132B LM5112SDX NRND WSON NGG 6 4500 TBD Call TI Call TI -40 to 125 L132B LM5112SDX/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L132B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5112, LM5112-Q1 : • Catalog: LM5112 • Automotive: LM5112-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jan-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5112MY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5112MYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5112Q1SD/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5112Q1SDX/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5112SD WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5112SD/NOPB WSON NGG 6 1000 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5112SDX WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5112SDX/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jan-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5112MY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0 LM5112MYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0 LM5112Q1SD/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LM5112Q1SDX/NOPB WSON NGG 6 4500 367.0 367.0 35.0 LM5112SD WSON NGG 6 1000 210.0 185.0 35.0 LM5112SD/NOPB WSON NGG 6 1000 203.0 203.0 35.0 LM5112SDX WSON NGG 6 4500 367.0 367.0 35.0 LM5112SDX/NOPB WSON NGG 6 4500 346.0 346.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.com MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated