ADS7842 ADS 784 2 SBAS103C – SEPTEMBER 2000 – REVISED OCTOBER 2006 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER DESCRIPTION FEATURES ● SINGLE SUPPLY: 2.7V to 5V The ADS7842 is a complete, 4-channel, 12-bit Analog-toDigital Converter (ADC). It contains a 12-bit, capacitorbased, Successive Approximation Register (SAR) ADC with a sample-and-hold amplifier, interface for microprocessor use, and parallel, 3-state output drivers. The ADS7842 is specified at a 200kHz sampling rate while dissipating only 2mW of power. The reference voltage can be varied from 100mV to VCC with a corresponding LSB resolution from 24µV to 1.22mV. The ADS7842 is tested down to 2.7V operation. ● 4-CHANNEL INPUT MULTIPLEXER ● UP TO 200kHz SAMPLING RATE ● ● ● ● ● ● FULL 12-BIT PARALLEL INTERFACE ±1LSB INL AND DNL NO MISSING CODES 72dB SINAD LOW POWER: 2mW SSOP-28 PACKAGE Low power, high speed, and an onboard multiplexer make the ADS7842 ideal for battery-operated systems such as portable, multi-channel dataloggers and measurement equipment. The ADS7842 is available in an SSOP-28 package and is tested over the –40°C to +85°C temperature range. APPLICATIONS ● ● ● ● ● DATA ACQUISITION TEST AND MEASUREMENT INDUSTRIAL PROCESS CONTROL MEDICAL INSTRUMENTS LABORATORY EQUIPMENT A0 SAR A1 AIN0 AIN1 ADS7842 3-State Parallel Data Bus 4-Channel MUX AIN2 CDAC AIN3 Comparator Output Latches and 3-State Drivers CLK BUSY WR CS VREF RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2000-2006, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION PRODUCT MINIMUM RELATIVE ACCURACY (LSB) SINAD (dB) ADS7842E ±2 " " ADS7842EB " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY 68 SSOP-28 DB –40°C to +85°C ADS7842E " " " " " ADS7842E ADS7842E/1K Rails, 48 Tape and Reel, 1000 ±1 70 SSOP-28 DB –40°C to +85°C ADS7842EB " " " " " " ADS7842EB ADS7842EB/1K Rails, 48 Tape and Reel, 1000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS(1) PIN DESCRIPTIONS +VCC to GND ........................................................................ –0.3V to +6V Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V Digital Inputs to GND ........................................................... –0.3V to +6V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C PIN NAME 1 AIN0 Analog Input Channel 0 2 AIN1 Analog Input Channel 1 3 AIN2 Analog Input Channel 2 4 AIN3 Analog Input Channel 3 5 VREF Voltage Reference Input. See Electrical Characteristics Tables for ranges. 6 AGND Analog Ground 7 DB11 Data Bit 11 (MSB) 8 DB10 Data Bit 10 9 DB9 Data Bit 9 10 DB8 Data Bit 8 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. 11 DB7 Data Bit 7 12 DB6 Data Bit 6 13 DB5 14 DGND ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 15 DB4 Data Bit 4 16 DB3 Data Bit 3 17 DB2 Data Bit 2 18 DB1 Data Bit 1 19 DB0 Data Bit 0 (LSB) 20 RD Read Input. Active LOW. Reads the data outputs in combination with CS. 21 CS Chip Select Input. Active LOW. The combination of CS taken LOW and WR taken LOW initiates a new conversion and places the outputs in the tri-state mode. 22 WR Write Input. Active LOW. Starts a new conversion and selects an analog channel via address inputs A0 and A1, in combination with CS. 23 BUSY 24 CLK 25, 26 A0, A1 NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top View SSOP Data Bit 5 Digital Ground AIN0 1 28 VANA AIN1 2 27 VDIG AIN2 3 26 A1 AIN3 4 25 A0 VREF 5 24 CLK AGND 6 23 BUSY DB11 7 22 WR DB10 8 21 CS DB9 8 20 RD DB8 10 19 DB0 A1 A0 Channel Selected DB7 11 18 DB1 0 0 AIN0 DB2 0 1 AIN1 1 0 AIN2 1 1 AIN3 DB6 12 DB5 13 DGND 14 2 DESCRIPTION ADS7842E 17 16 15 DB3 DB4 BUSY goes LOW and stays LOW during a conversion. BUSY rises when a conversion is complete and enables the parallel outputs. External Clock Input. The clock speed determines the conversion rate by the equation fCLK = 16 • fSAMPLE. Address Inputs. Selects one of four analog input channels in combination with CS and WR. The address inputs are latched on the rising edge of either RD or WR. 27 VDIG Digital Supply Input. Nominally +5V. 28 VANA Analog Supply Input. Nominally +5V. ADS7842 www.ti.com SBAS103C ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. ADS7842E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 VREF 0.15 0.1 30 70 ✻ ✻ ✻ ✻ 10kHz 10kHz 10kHz 50kHz –78 71 79 120 68 72 0.1 5 40 2.5 0.001 –72 70 76 3.0 –0.3 3.5 –80 72 81 ✻ ✻ ✻ ✻ ✻ ✻ 100 3 ±1 ±1 ✻ ✻ ±3 ✻ 5.5 +0.8 ✻ ✻ ✻ 4.75 550 300 –40 dB dB dB dB ✻ V GΩ µA µA µA ✻ ✻ ✻ V V V V ✻ MHz ✻ ✻ ✻ ✻ V µA µA µA mW ✻ °C ✻ 3.2 ✻ 5.25 900 ✻ ✻ ✻ 3 4.5 Power Dissipation Clk Cycles Clk Cycles kHz ns ns ps –76 ✻ ✻ 0.4 Straight Binary 0.2 Bits LSB(1) LSB LSB LSB LSB LSB µVrms dB ✻ CMOS Specified Performance V pF µA ✻ ✻ ✻ +VCC DCLK Static | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA ✻ ✻ 200 at at at at Bits ✻ 500 30 100 5Vp-p 5Vp-p 5Vp-p 5Vp-p ✻ ✻ fSAMPLE = 12.5kHz Power-Down Mode(3), CS = +VCC TEMPERATURE RANGE Specified Performance ±0.5 ±3 1.0 ±4 1.0 12 fSAMPLE = 12.5kHz DCLK Static POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current ±2 3 = = = = UNITS ✻ ±0.8 VIN VIN VIN VIN MAX ✻ ✻ 12 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format External Clock TYP ✻ 25 ±1 SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection REFERENCE INPUT Range Resistance Input Current MIN 12 ANALOG INPUT Full-Scale Input Span Capacitance Leakage Current DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious-Free Dynamic Range Channel-to-Channel Isolation ADS7842EB MAX +85 ✻ ✻ Same specifications as ADS7842E. NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Power-down mode at end of conversion when WR, CS, and BUSY conditions have all been met. Refer to Table III of this data sheet. ADS7842 SBAS103C www.ti.com 3 ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. ADS7842E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current ±0.8 0.15 0.1 30 70 ±2 ±0.5 ±5 1.0 ±4 1.0 ✻ ✻ ✻ ✻ ✻ V pF µA Bits LSB(1) LSB LSB LSB LSB LSB µVrms dB ±1 ±1 ✻ ✻ ±3 ✻ Clk Cycles Clk Cycles kHz ns ns ps ✻ ✻ ✻ –77 –70 –79 –74 dB –77 –70 ✻ ✻ dB 68 71 70 72 dB 68 71 ✻ ✻ dB 72 78 76 80 dB 72 78 ✻ ✻ dB ✻ dB 100 0.1 +VCC DCLK Static 5 13 2.5 0.001 ✻ +VCC • 0.7 –0.3 +VCC • 0.8 ✻ ✻ ✻ ✻ ✻ 40 3 5.5 +0.8 ✻ ✻ ✻ 2.7 280 220 –40 ✻ ✻ V V V V ✻ MHz ✻ ✻ ✻ ✻ V µA µA µA mW ✻ °C ✻ 2 ✻ 3.6 650 ✻ ✻ ✻ 3 1.8 Power Dissipation ✻ ✻ ✻ 0.4 Straight Binary 0.2 V GΩ µA µA µA ✻ CMOS Specified Performance Bits ✻ 125 | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA ✻ ✻ 500 30 100 3.6V ≥ VCC ≥ 3.0V, VIN = 2.5Vp-p at 10kHz 3.0V > VCC ≥ 2.7V, VIN = 2.5Vp-p at 10kHz 3.6V ≥ VCC ≥ 3.0V, VIN = 2.5Vp-p at 10kHz 3.0V > VCC ≥ 2.7V, VIN = 2.5Vp-p at 10kHz 3.6V ≥ VCC ≥ 3.0V, VIN = 2.5Vp-p at 10kHz 3.0V > VCC ≥ 2.7V, VIN = 2.5Vp-p at 10kHz VIN = 2.5Vp-p at 50kHz UNITS ✻ 12 3 fSAMPLE = 12.5kHz Power-Down Mode(3), CS = +VCC TEMPERATURE RANGE Specified Performance ✻ MAX ✻ fSAMPLE = 12.5kHz DCLK Static DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format External Clock TYP ✻ ✻ 12 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Spurious-Free Dynamic Range VREF 25 ±1 SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection Signal-to-(Noise + Distortion) MIN 12 ANALOG INPUT Full-Scale Input Span Capacitance Leakage Current DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) ADS7842EB MAX +85 ✻ ✻ Same specifications as ADS7842E. NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Power-down mode at end of conversion when WR, CS, and BUSY conditions have all been met. Refer to Table III of this data sheet. 4 ADS7842 www.ti.com SBAS103C TYPICAL CHARACTERISTICS: +5V At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.3kHz, –0.2dB) 0 0 –20 –20 –40 –40 Amplitude (dB) –60 –80 –60 –80 –100 –100 –120 –120 0 25 50 75 100 0 25 50 Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE + DISTORTION) vs INPUT FREQUENCY 100 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 74 –85 85 SNR SFDR 73 –80 80 72 SFDR (dB) SNR and SINAD (dB) 75 Frequency (kHz) SINAD 71 THD 75 –75 70 –70 70 69 1 10 1 100 10 Input Frequency (kHz) Input Frequency (kHz) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 0.6 12.0 0.4 11.8 Delta from +25°C (dB) Effective Number of Bits –65 100 65 68 11.6 11.4 11.2 0.2 0.0 –0.2 –0.4 fIN = 10kHz, –0.2dB –0.6 11.0 1 10 –40 100 ADS7842 SBAS103C –20 0 20 40 60 80 100 Temperature (°C) Input Frequency (kHz) www.ti.com 5 THD (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,123Hz, –0.2dB) TYPICAL CHARACTERISTICS: +2.7V At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.6kHz, –0.2dB) 0 0 –20 –20 –40 –40 Amplitude (dB) –60 –80 –60 –80 –100 –100 –120 –120 0 15.6 31.3 46.9 0 62.5 62.5 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 90 –90 85 74 –85 SFDR 70 SFDR (dB) SNR and SINAD (dB) 46.9 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE + DISTORTION) vs INPUT FREQUENCY SNR 66 SINAD 62 58 54 80 –80 75 –75 70 –70 THD 65 –65 60 –60 55 –55 50 1 10 Input Frequency (kHz) –50 1 100 10 100 Input Frequency (kHz) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE 12.0 0.4 11.5 0.2 fIN = 10kHz, –0.2dB Delta from +25°C (dB) Effective Number of Bits 31.3 Frequency (kHz) 78 11.0 10.5 10.0 9.5 0.0 –0.2 –0.4 –0.6 9.0 –0.8 1 10 100 –40 Input Frequency (kHz) 6 15.6 Frequency (kHz) –20 0 20 40 60 80 100 Temperature (°C) ADS7842 www.ti.com SBAS103C THD (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,129Hz, –0.2dB) TYPICAL CHARACTERISTICS: +2.7V (Continued) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 400 140 350 120 Supply Current (nA) Supply Current (µA) SUPPLY CURRENT vs TEMPERATURE 300 250 200 150 100 80 60 40 100 20 –40 –20 0 20 40 60 80 100 –40 –20 0 40 60 80 100 DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 1.00 0.75 0.75 0.50 0.50 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 0.25 0.00 –0.25 0.25 0.00 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 000H –1.00 000H FFFH 800H FFFH 800H Output Code Output Code CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 0.15 0.6 0.10 0.4 Delta from +25°C (LSB) Delta from +25°C (LSB) 20 Temperature (°C) Temperature (°C) 0.05 0.00 –0.05 0.2 0.0 –0.2 –0.4 –0.10 –0.6 –0.15 –40 –20 0 20 40 60 80 –40 100 0 20 40 60 80 100 Temperature (°C) Temperature (°C) ADS7842 SBAS103C –20 www.ti.com 7 TYPICAL CHARACTERISTICS: +2.7V (Continued) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. REFERENCE CURRENT vs TEMPERATURE 18 12 16 Reference Current (µA) Reference Current (µA) REFERENCE CURRENT vs SAMPLE RATE 14 10 8 6 4 14 12 10 8 2 6 0 0 25 50 75 100 –40 125 –20 0 20 40 60 80 100 Temperature (°C) Sample Rate (kHz) SUPPLY CURRENT vs +VCC MAXIMUM SAMPLE RATE vs +VCC 1M 320 300 Sample Rate (Hz) Supply Current (µA) fSAMPLE = 12.5kHz 280 VREF = +VCC 260 240 220 100k 10k VREF = +VCC 200 1k 180 2 2.5 3 3.5 4 4.5 2 5 8 2.5 3 3.5 4 4.5 5 +VCC (V) +VCC (V) ADS7842 www.ti.com SBAS103C THEORY OF OPERATION some operating modes. While the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1GΩ. The ADS7842 is a classic SAR ADC. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process. EXTERNAL CLOCK The ADS7842 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5kHz throughput) and 3.2MHz (200kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 150ns and the clock period is at least 300ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7842. The basic operation of the ADS7842 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 100mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7842. BASIC OPERATION ANALOG INPUTS The ADS7842 features four, single-ended inputs. The input current into each analog input depends on input voltage and sampling rate. Essentially, the current into the device must charge the internal hold capacitor during the sample period. After this capacitance has fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance to a 12-bit settling level within the same period, which can be as little as 350ns in Figure 1 shows the simple circuit required to operate the ADS7842 with Channel 0 selected. A conversion can be initiated by bringing the WR pin (pin 22) LOW for a minimum of 25ns. BUSY (pin 23) will output a LOW during the conversion process and rises only after the conversion is complete. The 12 bits of output data will be valid on pins 7-13 and 15-19 following the rising edge of BUSY. ADS7842 0V to VREF 1 +5V + 2.2µF AIN0 VANA 28 + 0.1µF + +5V Analog Supply 10µF 2 AIN1 VDIG 27 3 AIN2 A1 26 4 AIN3 A0 25 5 VREF CLK 24 3.2MHz Clock 6 AGND BUSY 23 BUSY Output 7 DB11 WR 22 8 DB10 CS 21 9 DB9 RD 20 10 DB8 DB0 19 11 DB7 DB1 18 12 DB6 DB2 17 13 DB5 DB3 16 14 DGND DB4 15 Write Input Read Input FIGURE 1. Basic Operation of the ADS7842. ADS7842 SBAS103C www.ti.com 9 STARTING A CONVERSION SYMBOL DESCRIPTION tCONV tACQ tCKP tCKL tCKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to WR/RD Setup Time Address to CS Hold Time CS LOW CLK to WR Setup Time CS to BUSY LOW CLK to WR LOW CLK to WR HIGH WR to CLK HIGH Address Hold Time Address Setup Time BUSY to RD Delay CLK LOW to BUSY HIGH BUS Access BUS Relinquish Address to RD HIGH Address Hold Time RD HIGH to CLK LOW A conversion is initiated on the falling edge of the WR input, with valid signals on A0, A1, and CS . The ADS7842 will enter the conversion mode on the first rising edge of the external clock following the WR pin going LOW. The ADS7842 will start the conversion on the 1st clock cycle. The MSB will be approximated by the Capacitive Digital-to-Analog Converter (CDAC) on the 1st clock cycle, the 2nd-MSB on the 2nd cycle, and so on until the LSB has been decided on the 12th clock cycle. The BUSY output will go LOW 20ns after the falling edge of the WR pin. The BUSY output will return HIGH just after the ADS7842 has finished a conversion and the data will be valid on pins 7-13, 15-19. The rising edge of BUSY can be used to latch the data. It is recommended that the data be read immediately after each conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance. See Figure 2. MIN TYP MAX UNITS 6.5 1.5 500 150 150 0 0 25 25 20 5 25 25 5 5 0 10 25 25 2 2 50 µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns READING DATA Data from the ADS7842 will appear at pins 7-13 and 15-19. The MSB will output on pin 7 while the LSB will output on pin 19. The outputs are coded in Straight Binary (with 0V = 000H and VREF = FFFH, see Table IV). Following a conversion, the BUSY pin will go HIGH. After BUSY goes HIGH, the CS and RD pins may be brought LOW to enable the 12-bit output bus. CS and RD must be held LOW for at least 25ns seconds following BUSY HIGH. Data will be valid 25ns seconds after the falling edge of both CS and RD. The output data will remain valid for 25ns seconds following the rising edge of both CS and RD. See Figure 4 for the read cycle timing diagram. TABLE I. Timing Specifications (+VCC = +2.7V to 3.6V, TA = –40°C to +85°C, CLOAD = 50pF). SYMBOL DESCRIPTION tCONV tACQ tCKP tCKL tCKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to WR/RD Setup Time Address to CS Hold Time CS LOW CLK to WR Setup Time CS to BUSY LOW CLK to WR LOW CLK to WR HIGH WR to CLK HIGH Address Hold Time Address Setup Time BUSY to RD Delay CLK LOW to BUSY HIGH BUS Access BUS Relinquish Address to RD HIGH Address Hold Time RD HIGH to CLK LOW POWER-DOWN MODE The ADS7842 incorporates a unique method of placing the ADC in the power-down mode. Rather than adding an extra pin to the package, the A0 address pin is used in conjunction with the RD pin to place the device in power-down mode and also to ‘wake-up’ the ADC following power-down. In this shutdown mode, all analog and digital circuitry is turned off. The simplest way to place the ADS7842 in power-down mode is immediately following a conversion. After a conversion has been completed and the BUSY output has returned HIGH, CS and RD must be brought LOW for a minimum of 25ns. While keeping CS LOW, RD is brought HIGH and the ADS7842 enters the power-down mode, provided the A0 pin is HIGH (see Figure 5 and Table III). In order to ‘wake-up’ the device following power-down, A0 must be LOW when RD switches from LOW to HIGH a second time (see Figure 6). MIN TYP MAX UNITS 3.5 1.5 300 150 150 0 0 25 25 20 5 25 25 5 5 0 10 25 25 2 2 50 µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TABLE II. Timing Specifications (+VCC = +4.75V to +5.25V, TA = –40°C to +85°C, CLOAD = 50pF). The typical supply current of the ADS7842 with a 5V supply and 200kHz sampling rate is 550µA. In the power-down mode the current is typically reduced to 3µA. 10 ADS7842 www.ti.com SBAS103C CS WR BUSY A0 A1 COMMENTS 0 RD X 1 1 X Power-Down Mode 0 X 1 0 X Wake-Up Mode DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION ANALOG INPUT Least Significant Bit (LSB) Full-Scale Midscale Midscale –1LSB Zero Full-Scale means rising edge triggered. X = Don't care. TABLE III. Truth Table for Power-Down and Wake-Up Modes. 1.2207mV 4.99878V 2.5V 2.49878V 0V BINARY CODE 1111 1000 0111 0000 1111 0000 1111 0000 HEX CODE 1111 0000 1111 0000 FFF 800 7FF 000 TABLE IV. Ideal Input Voltages and Output Codes (VREF = 5V). CS Latching in Address for Next Channel WR Sample Conversion CLK 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 BUSY RD A0 A1 DATA VALID DB0-DB11 FIGURE 2. Normal Operation, 16 Clocks per Conversion. CS t1 t2 t3 WR t6 t7 t8 t4 CLK tCKL t5 BUSY t10 t9 N + 1(1) A0, A1 NOTE: (1) Addresses for next conversion (N + 1) latched in with rising edge of current WR (N). FIGURE 3. Initiating a Conversion. ADS7842 SBAS103C www.ti.com 11 CS t1 t3 RD CLK t12 t11 BUSY n–1 Conversion n To prevent PWD A0 must be 0 A0 t13 DB0-DB11 t14 n-1 DATA VALID NOTE: Internal register of current conversion updated 1/2 clock cycle prior to BUSY going HIGH. FIGURE 4. Read Timing Following a Conversion. CS t2 t1 t3 RD CLK t12 t11 BUSY t15 t16 A0 NOTE: Rising edge of RD while A0 = 1 initiates power down immediately. FIGURE 5. Entering Power-Down Using RD and A0. CS t1 t2 t3 RD t15 A0 t16 NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7842 in sample mode. FIGURE 6. Initiating Wake-Up Using RD and A0. 12 ADS7842 www.ti.com SBAS103C LAYOUT REFERENCE INPUT The external reference sets the analog input range. The ADS7842 will operate with a reference in the range of 100mV to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, then it will typically be 10LSBs with a 0.5V reference. In each case, the actual offset of the device is the same, 1.22mV. Likewise, the noise or uncertainty of the digitized output will increase with lower LSB size. With a reference voltage of 100mV, the LSB size is 24µV. This level is below the internal noise of the device. As a result, the digital output code will not be stable and vary around a mean value by a number of LSBs. The distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. The voltage into the VREF input is not buffered and directly drives the CDAC portion of the ADS7842. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. Data Format The ADS7842 output data is in Straight Offset Binary format, see Table IV. This table shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. For optimum performance, care should be taken with the physical layout of the ADS7842 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. With this in mind, power to the ADS7842 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The ADS7842 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of CLK during a conversion). The ADS7842 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ADS7842 SBAS103C www.ti.com 13 Revision History DATE REVISION PAGE SECTION DESCRIPTION 10/06 C 4 Electrical Characteristics Dynamic Characteristics—total harmonic distortion: added new conditions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 14 ADS7842 www.ti.com SBAS103C PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7842E ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7842E/1K ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E ADS7842E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E ADS7842EB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E B ADS7842EB/1K ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E B ADS7842EB/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E B ADS7842EBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7842E B ADS7842EG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS7842E ADS7842E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7842E/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 ADS7842EB/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7842E/1K SSOP DB 28 1000 367.0 367.0 38.0 ADS7842EB/1K SSOP DB 28 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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