TI1 MSP430F5259IZQE Mixed-signal microcontroller Datasheet

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
MSP430F525x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Dual-Supply Voltage Device
– Primary Supply (AVCC, DVCC)
• Powered From External Supply:
3.6 V Down to 1.8 V
• Up to 18 General-Purpose I/Os With up to 8
External Interrupts
– Low-Voltage Interface Supply (DVIO)
• Powered From Separate External Supply:
1.62 V to 1.98 V
• Up to 35 General-Purpose I/Os With up to
16 External Interrupts
• Serial Communications
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active
290 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
150 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real-Time Clock (RTC) With Crystal, Watchdog,
and Supply Supervisor Operational, Full RAM
Retention, Fast Wakeup:
2.1 µA at 2.2 V, 2.3 µA at 3.0 V (Typical)
Low-Power Oscillator (VLO), General-Purpose
Counter, Watchdog, and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:
1.6 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wakeup:
1.3 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.18 µA at 3.0 V (Typical)
• Wakeup From Standby Mode in 3.5 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
25-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Watch Crystals (XT1)
– HF Crystals up to 32 MHz (XT2)
• 16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
• 16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
• 16-Bit Timer TA2, Timer_A With Three
Capture/Compare Registers
• 16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
• Four Universal Serial Communication Interfaces
– USCI_A0, A1, A2, A3 Each Support:
• Enhanced UART With Automatic Baud-Rate
Detection
• IrDA Encoder and Decoder
• Synchronous SPI
– USCI_B0, B1, B2, B3 Each Support:
• I2C
• Synchronous SPI
• 10-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold
• Comparator
• Hardware Multiplier Supports 32-Bit Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Three-Channel Internal DMA
• Basic Timer With RTC Feature
• Table 3-1 Summarizes the Available Family
Members and Packages
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
• For Design Guidelines, See Designing With
MSP430F522x and MSP430F521x Devices
(SLAA558)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
1.2
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•
•
Applications
"Always-On" System Controllers
Power-Management Hubs
Bluetooth® Controllers
1.3
www.ti.com
•
•
•
Analog and Digital Sensor Fusion Systems
Data Loggers
General-Purpose Applications
Description
Using an "always-on" ultra-low-power system controller can significantly reduce power consumption on
portable devices like handsets and tablets. These controllers can act as sensor hubs and monitor user
stimuli (for example, reading inertial sensors or touch sensors) and vital system parameters like battery
health and temperature, while power-hungry application processors and touch screen controllers are
turned off. The microcontroller can then "wake up" the system based on a user input or on a fault
condition that requires CPU intervention.
The MSP430F525x series is the latest addition to the 1.8-V split-rail I/O portfolio (previously only available
on MSP430F522x) and is specifically designed for "always-on" system controller applications. 1.8-V I/O
allows for seamless interface to application processors and other devices without the need for external
level translation, while the primary supply to the MCU can be on a higher voltage rail.
Compared to the MSP430F522x, the MSP430F525x provides up to four times more RAM (32KB) and
double the serial interfaces (four USCI_A and four USCI_B). The MSP430F525x also features four 16-bit
timers, a high-performance 10-bit analog-to-digital converter (ADC), a hardware multiplier, DMA, a
comparator, and a real-time clock (RTC) module with alarm capabilities. The MSP430F525x consumes
290 µA/MHz (typical) in active mode running from flash memory, and it consumes 1.6 µA (typical) in
standby mode (LPM3). The MSP430F525x can switch to active mode in 3.5 µs (typical), which makes it a
great fit for "always-on" low-power applications.
Key benefits of the MSP430F525x are as follows:
• Up to 32KB of RAM allows complex sensor hub algorithms and high levels of aggregation such as
keyboard control and power management.
• Four USCI_A and four USCI_B allow for eight concurrent dedicated hardware serial interfaces (for
example, four I2C and four SPI) for fast and robust communication to sensors or peripheral devices.
• Up to 35 I/Os that can be used in the 1.8-V voltage rail.
Typical applications include analog and digital sensor fusion systems, data loggers, and various generalpurpose applications.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430F5259IRGC
VQFN (64)
9 mm × 9 mm
MSP430F5252IZQE
BGA (80)
See Section 8
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Device Overview
Copyright © 2013–2015, Texas Instruments Incorporated
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MSP430F5253 MSP430F5252
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
1.4
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN XOUT
DVCC AVCC
DVSS AVSS
PA
DVIO VCORE
P1.x P2.x
PB
P4.x
P3.x
P5.x
PJ
PD
P7.x PJ.x
PC
P6.x
(1)
XT2IN
XT2OUT
RSTDVCC RST/NMI BSLEN
Unified
Clock
System
ACLK
32KB
16KB
Flash
RAM
SMCLK
MCLK
CPUXV2
and
Working
Registers
128KB
Power
Management
SYS
Watchdog
LDO
SVM, SVS
Brownout
(1)(2)
(1)(2)
P4
P5
P7
P3
P6
P2
P1
1×8 I/Os 1×8 I/Os 1×5 I/Os 1×8 I/Os 1×6 I/Os 1×8 I/Os 1×6 I/Os
(1)(2)
PA
1×16 I/Os
PB
1×13 I/Os
Port Map
Control
(P4)
PC
1×14 I/Os
PD
PJ
1×6 I/Os 1×4 I/Os
4x
USCI_Ax:
UART,
IrDA, SPI
I/O Ports
4x
USCI_Bx:
SPI, I2C
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
ADC10_A
JTAG,
SBW
Interface
MPY32
I/O are supplied by DVIO
TA0
TA1
TA2
TB0
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
(1) Interrupt capability
RTC_A
CRC16
10 Bit
200 KSPS
12 Channels
(10 ext,2 int)
COMP_B
REF
8 Channels
(2) Wakeup capability
Figure 1-1. Functional Block Diagram
Device Overview
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Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
Copyright © 2013–2015, Texas Instruments Incorporated
3
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1) ............................... 25
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
5.21
Crystal Oscillator, XT1, Low-Frequency Mode
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
5.22
5.23
Crystal Oscillator, XT2 .............................. 27
Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 28
Internal Reference, Low-Frequency Oscillator
(REFO) .............................................. 28
Revision History ......................................... 5
Device Comparison ..................................... 6
Terminal Configuration and Functions .............. 7
5.24
DCO Frequency ..................................... 29
PMM, BOR .......................................... 30
5.27
PMM, Core Voltage ................................. 30
5.28
PMM, SVS High Side
14
5.29
PMM, SVM High Side ............................... 32
14
5.30
PMM, SVS Low Side ................................ 32
14
5.31
5.32
PMM, SVM Low Side ............................... 33
Wake-Up Times From Low-Power Modes and
Reset ................................................ 33
5.33
Timer_A
5.34
Timer_B
4.2
Signal Descriptions ................................... 9
Specifications ........................................... 14
5.2
5.3
5.4
5.5
........................
ESD Ratings ........................................
Recommended Operating Conditions ...............
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 17
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 18
Thermal Characteristics ............................ 19
Schmitt-Trigger Inputs – General-Purpose I/O
DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC) .... 20
5.8
Schmitt-Trigger Inputs – General-Purpose I/O DVIO
Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0
to P7.5, RST/NMI, BSLEN) ................................ 20
5.9
Inputs – Interrupts DVCC Domain Port P6
(P6.0 to P6.7) .............................................. 20
5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7) ................................ 20
5.11 Leakage Current – General-Purpose I/O DVCC
Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................. 21
5.12 Leakage Current – General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0
to P7.5) ..................................................... 21
5.13 Outputs – General-Purpose I/O DVCC Domain (Full
Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................. 21
5.14 Outputs – General-Purpose I/O DVCC Domain
(Reduced Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................. 22
5.15 Outputs – General-Purpose I/O DVIO Domain (Full
Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0
to P7.5) ..................................................... 22
5.16 Outputs – General-Purpose I/O DVIO Domain
(Reduced Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0
to P7.5) ..................................................... 22
5.17 Output Frequency – General-Purpose I/O DVCC
Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) ................. 23
5.18 Output Frequency – General-Purpose I/O DVIO
Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0
to P7.5) ..................................................... 23
5.19 Typical Characteristics – Outputs, Reduced Drive
Strength (PxDS.y = 0) ............................... 24
5.6
5.7
Table of Contents
26
5.26
Pin Diagrams ......................................... 7
Absolute Maximum Ratings
.....
5.25
4.1
5.1
4
5.20
5.35
5.36
5.37
5.38
5.39
5.40
5.41
6
.............................................
.............................................
USCI (UART Mode) Clock Frequency ..............
USCI (UART Mode) .................................
USCI (SPI Master Mode) Clock Frequency .........
USCI (SPI Master Mode)............................
USCI (SPI Slave Mode) .............................
USCI (I2C Mode) ....................................
31
34
34
35
35
35
35
37
39
10-Bit ADC, Power Supply and Input Range
Conditions ........................................... 40
....................
5.42
10-Bit ADC, Timing Parameters
5.43
10-Bit ADC, Linearity Parameters................... 41
5.44
REF, External Reference
5.45
REF, Built-In Reference ............................. 42
5.46
Comparator_B ....................................... 43
5.47
Flash Memory ....................................... 44
5.48
JTAG and Spy-Bi-Wire Interface .................... 44
5.49
DVIO BSL Entry ..................................... 45
...........................
40
41
Detailed Description ................................... 46
.........................
6.1
CPU (Link to user's guide)
6.2
Operating Modes .................................... 47
6.3
Interrupt Vector Addresses.......................... 48
6.4
Memory Organization ............................... 49
6.5
Bootloader (BSL) .................................... 50
6.6
JTAG Operation ..................................... 52
...............
6.8
RAM (Link to user's guide) .........................
6.9
Peripherals ..........................................
6.10 Input/Output Schematics ............................
6.11 Device Descriptors ..................................
Device and Documentation Support ...............
7.1
Device Support ......................................
7.2
Documentation Support .............................
7.3
Related Links ........................................
7.4
Community Resources ..............................
7.5
Trademarks..........................................
6.7
7
...............................
Flash Memory (Link to user's guide)
46
54
54
55
77
93
95
95
98
98
99
99
Copyright © 2013–2015, Texas Instruments Incorporated
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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
7.6
Electrostatic Discharge Caution ..................... 99
7.7
Export Control Notice
...............................
99
7.8
8
Glossary ............................................. 99
Mechanical, Packaging, and Orderable
Information .............................................. 99
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2013) to Revision B
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Page
Document format and organization changes throughout, including addition of section numbering........................ 1
Added Device Information table .................................................................................................... 2
Moved Section 1.4, Functional Block Diagram ................................................................................... 3
Added 16KB RAM option in Figure 1-1, Functional Block Diagram ............................................................ 3
Added Section 3, Device Comparison, and moved Table 3-1, Family Members, to it ...................................... 6
Added Section 4, Terminal Configuration and Functions, and moved pinout drawings and terminal functions
table to it .............................................................................................................................. 7
Added indication of terminals powered by DVIO in RGC pinout ............................................................... 7
Added indication of terminals powered by DVIO in ZQE pinout ............................................................... 8
Removed preview YFF pinout....................................................................................................... 8
Added SUPPLY column and removed YFF column in Table 4-1, Terminal Functions ...................................... 9
Added Section 5 and moved all electrical specifications to it ................................................................. 14
Added Section 5.2, ESD Ratings.................................................................................................. 14
Added note on CVCORE .............................................................................................................. 14
Added second note "Under certain condtions during the rising transition..." on Figure 5-1 ............................... 15
Added Section 5.6, Thermal Characteristics .................................................................................... 19
Moved note on RPull from Section 5.7 to Section 5.8 ........................................................................... 20
Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 26
Corrected Test Conditions (removed VREF–) for all parameters in Section 5.43 ........................................... 41
Updated Test Conditions for all parameters in Section 5.43, 10-Bit ADC, Linearity Parameters: changed from
"CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; changed from "(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–)" to
"1.4 V ≤ (VeREF+ – VeREF–)" .......................................................................................................... 41
Added "CVeREF+ = 20 pF" to EI Test Conditions.................................................................................. 41
Added "ADC10SREFx = 11b" to Test Conditions for EG and ET .............................................................. 41
Corrected Test Conditions (removed VREF–) for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters in Section 5.44 .... 41
Changed MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V .............. 42
Corrected spelling of MRG bits in fMCLK,MRG parameter symbol and description ............................................ 44
Throughout document, changed "bootstrap loader" to "bootloader" ......................................................... 50
Added note to clarify that all JTAG pins are on DVCC ......................................................................... 52
Added note to indicate that all SBW pins are on DVCC ...................................................................... 53
Removed YFF package information from Table 6-12, TA0 Signal Connections............................................ 60
Removed YFF package information from Table 6-13, TA1 Signal Connections............................................ 61
Removed YFF package information from Table 6-14, TA2 Signal Connections............................................ 62
Removed YFF package information from Table 6-15, TB0 Signal Connections............................................ 63
Changed P5.3 schematic (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates) ......................... 85
Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows .................................................................. 85
Changed P5.5 schematic (added P5SEL.5 input and OR gate) .............................................................. 87
Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows .................................................................. 87
Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature,
Trademarks, and Electrostatic Discharge Caution sections to it .............................................................. 95
Added Section 8 .................................................................................................................... 99
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
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Copyright © 2013–2015, Texas Instruments Incorporated
5
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
www.ti.com
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members (1) (2)
USCI
CHANNEL
A:
UART,
IrDA, SPI
CHANNEL
B:
SPI, I2C
ADC10
_A
(Ch)
COMP
_B
(Ch)
I/O
DVCC (5)
I/O
DVIO (6)
BSL
TYPE
PACKAGE
7
4
4
10 ext,
2 int
8
18
35
I2C
64 RGC
80 ZQE
5, 3, 3
7
4
4
N/A
8
18
35
I2C
64 RGC
80 ZQE
16
5, 3, 3
7
4
4
10 ext,
2 int
8
18
35
I2C
64 RGC
80 ZQE
128
16
5, 3, 3
7
4
4
N/A
8
18
35
I2C
64 RGC
80 ZQE
MSP430F5255
128
32
5, 3, 3
7
4
4
10 ext,
2 int
8
18
35
UART
64 RGC
80 ZQE
MSP430F5254
128
32
5, 3, 3
7
4
4
N/A
8
18
35
UART
64 RGC
80 ZQE
MSP430F5253
128
16
5, 3, 3
7
4
4
10 ext,
2 int
8
18
35
UART
64 RGC
80 ZQE
MSP430F5252
128
16
5, 3, 3
7
4
4
N/A
8
18
35
UART
64 RGC
80 ZQE
DEVICE
FLASH
(KB)
SRAM
(KB)
MSP430F5259
128
32
5, 3, 3
MSP430F5258
128
32
MSP430F5257
128
MSP430F5256
(1)
(2)
(3)
(4)
(5)
(6)
6
Timer_A
(3)
Timer_B
(4)
For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at
www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
All of these I/O reside on a single voltage rail supplied by DVCC.
All of these I/O reside on a single voltage rail supplied by DVIO.
Device Comparison
Copyright © 2013–2015, Texas Instruments Incorporated
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MSP430F5253 MSP430F5252
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 shows the pinout of the 64-pin RGC package.
P7.0/UCA2TXD/UCA2SIMO
P7.1/UCA2RXD/UCA2SOMI
P7.2/UCB2CLK/UCA2STE
P7.3/UCB2SIMO/UCB2SDA
P7.4/UCB2SOMI/UCB2SCL
P7.5/UCB2STE/UCA2CLK
BSLEN
RST/NMI
P5.2/XT2IN
P5.3/XT2OUT
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
RSTDVCC/SBWTDIO
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/TA2CLK/SMCLK/CB0/A0
1
48
P4.7/PM_UCA3RXD/PM_UCA3SOMI
P6.1/TA2.0/CB1/A1
2
47
P4.6/PM_UCA3TXD/PM_UCA3SIMO
P6.2/TA2.1/CB2/A2
3
46
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P6.3/TA2.2/CB3/A3
4
45
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P6.4/CB4/A4
5
44
P4.3/PM_UCB1CLK/PM_UCA1STE
P6.5/CB5/A5
6
43
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P6.6/CB6/A6
7
42
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P6.7/CB7/A7
8
41
P4.0/PM_UCB1STE/PM_UCA1CLK
P5.0/A8/VeREF+
9
40
DVIO
P5.1/A9/VeREF-
10
39
DVSS
AVCC
11
38
P3.4/UCA0RXD/UCA0SOMI
P5.4/XIN
12
37
P3.3/UCA0TXD/UCA0SIMO
P5.5/XOUT
13
36
P3.2/UCB0CLK/UCA0STE
P2.7/UCB0STE/UCA0CLK
P2.6/RTCCLK/DMAE0
P2.5/UCB3STE/UCA3CLK
P2.4/UCB3CLK/UCA3STE
P2.3/UCB3SOMI/UCB3SCL
P2.1/TA1.2
Supplied by DVIO
P2.2/UCB3SIMO/UCB3SDA
P2.0/TA1.1
P1.7/TA1.0
P1.6/TA1CLK/CBOUT
P1.5/TA0.4
P1.4/TA0.3
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.3/TA0.2
P3.0/UCB0SIMO/UCB0SDA
DVSS
P1.2/TA0.1
P3.1/UCB0SOMI/UCB0SCL
34
P1.1/TA0.0
35
15
VCORE
14
P1.0/TA0CLK/ACLK
AVSS
DVCC
Figure 4-1. 64-Pin RGC Package (Top View)
Figure 4-2 shows the pinout of the 80-pin ZQE package.
Terminal Configuration and Functions
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ZQE PACKAGE
(TOP VIEW)
TEST RST/NMI P7.5
P7.4
P7.3
P7.1
A4
A5
A7
A8
A9
PJ.3
P5.3
P5.2
B3
B4
B5
P6.3
PJ.1
PJ.0
C2
C4
C5
C6
D3
D4
D5
D6
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F7
F8
F9
P1.3
P1.6
P2.1
P3.4
P3.2
P3.3
G4
G5
G6
G7
G8
G9
P1.1
P1.4
P1.7
P2.3
P2.7
P3.0
P3.1
H3
H4
H5
H6
H7
H8
H9
P1.5
P2.0
P2.2
P2.4
P2.5
P2.6
J4
J5
J6
J7
J8
J9
P6.0 RSTDVCC PJ.2
A1
A2
A3
P6.2
P6.1
B1
B2
P6.4
C1
P6.6
P6.5
P6.7
D1
D2
P5.0
P5.1
E1
E2
P5.4
AVCC
F1
F2
P5.5
AVSS
G1
G2
G3
DVCC
P1.0
H1
H2
J2
BSLEN P7.2
B6
P7.0
B7
B8
B9
P4.7
P4.6
P4.5
C7
C8
C9
P4.4
P4.3
P4.2
D7
D8
D9
P4.1
P4.0
DVIO
E9
DVSS
DVSS VCORE P1.2
J1
A6
J3
Supplied by DVIO
Figure 4-2. 80-Pin ZQE Package (Top View)
8
Terminal Configuration and Functions
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4.2
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Signal Descriptions
Table 4-1. Terminal Functions
TERMINAL
NAME
NO. (2)
RGC
I/O (1)
SUPPLY
DESCRIPTION
ZQE
General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input
P6.0/TA2CLK/SMCLK/CB0/A0
1
A1
I/O
DVCC
SMCLK output
Comparator_B input CB0
Analog input A0 – ADC (not available on all device types)
General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
P6.1/TA2.0/CB1/A1
2
B2
I/O
DVCC
Comparator_B input CB1
Analog input A1 – ADC (not available on all device types)
BSL transmit output
General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
P6.2/TA2.1/CB2/A2
3
B1
I/O
DVCC
Comparator_B input CB2
Analog input A2 – ADC (not available on all device types)
BSL receive input
General-purpose digital I/O with port interrupt
P6.3/TA2.2/CB3/A3
4
C2
I/O
DVCC
TA2 CCR2 capture: CCI2A input, compare: Out2 output
Comparator_B input CB3
Analog input A3 – ADC (not available on all device types)
General-purpose digital I/O with port interrupt
P6.4/CB4/A4
5
C1
I/O
DVCC
Comparator_B input CB4
Analog input A4 – ADC (not available on all device types)
General-purpose digital I/O with port interrupt
P6.5/CB5/A5
6
D2
I/O
DVCC
Comparator_B input CB5
Analog input A5 – ADC (not available on all device types)
General-purpose digital I/O with port interrupt
P6.6/CB6/A6
7
D1
I/O
DVCC
Comparator_B input CB6
Analog input A6 – ADC (not available on all device types)
General-purpose digital I/O with port interrupt
P6.7/CB7/A7
8
D3
I/O
DVCC
Comparator_B input CB7
Analog input A7 – ADC (not available on all device types)
General-purpose digital I/O
P5.0/A8/VeREF+
9
E1
I/O
DVCC
Analog input A8 – ADC (not available on all device types)
Input for an external reference voltage to the ADC (not
available on all device types)
General-purpose digital I/O
P5.1/A9/VeREF-
10
E2
I/O
DVCC
Analog input A9 – ADC (not available on all device types)
Negative terminal for the ADC reference voltage for an external
applied reference voltage (not available on all device types)
AVCC
(1)
(2)
11
F2
Analog power supply
I = input, O = output
N/A = not available
Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO. (2)
NAME
I/O (1)
SUPPLY
DESCRIPTION
RGC
ZQE
P5.4/XIN
12
F1
I/O
DVCC
P5.5/XOUT
13
G1
I/O
DVCC
AVSS
14
G2
Analog ground supply
DVCC
15
H1
Digital power supply
DVSS
16
J1
Digital ground supply
17
J2
18
H2
VCORE
(4)
DVCC
General-purpose digital I/O
Input terminal for crystal oscillator XT1 (3)
General-purpose digital I/O
Output terminal of crystal oscillator XT1
Regulated core power supply output (internal use only, no
external current loading)
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK (5)
I/O
DVIO
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 (5)
19
H3
I/O
DVIO
P1.2/TA0.1 (5)
20
J3
I/O
DVIO
P1.3/TA0.2 (5)
21
G4
I/O
DVIO
P1.4/TA0.3 (5)
22
H4
I/O
DVIO
P1.5/TA0.4 (5)
23
J4
I/O
DVIO
P1.6/TA1CLK/CBOUT (5)
24
G5
I/O
DVIO
General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0 (5)
25
H5
I/O
DVIO
P2.0/TA1.1 (5)
26
J5
I/O
DVIO
P2.1/TA1.2 (5)
27
G6
I/O
DVIO
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.2/UCB3SIMO/UCB3SDA
(5)
28
J6
I/O
DVIO
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
General-purpose digital I/O with port interrupt
P2.3/UCB3SOMI/UCB3SCL (5)
29
H6
I/O
DVIO
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
General-purpose digital I/O with port interrupt
P2.4/UCB3CLK/UCA3STE (5)
30
J7
I/O
DVIO
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
(3)
(4)
(5)
10
When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, the pin must be configured properly for the intended input swing.
VCORE is for internal use only. No external current loading is possible. VCORE should be connected only to the recommended
capacitor value, CVCORE (see Section 5.3).
This pin function is supplied by DVIO. See Section 5.8 for input and output requirements.
Terminal Configuration and Functions
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 4-1. Terminal Functions (continued)
TERMINAL
NO. (2)
NAME
RGC
I/O (1)
SUPPLY
DESCRIPTION
ZQE
General-purpose digital I/O with port interrupt
P2.5/UCB3STE/UCA3CLK (5)
31
J8
I/O
DVIO
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
General-purpose digital I/O with port interrupt
P2.6/RTCCLK/DMAE0
(5)
32
J9
I/O
DVIO
RTC clock output for calibration
DMA external trigger input
General-purpose digital I/O
P2.7/UCB0STE/UCA0CLK (5)
33
H7
I/O
DVIO
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
(5)
P3.0/UCB0SIMO/UCB0SDA
34
H8
I/O
DVIO
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.1/UCB0SOMI/UCB0SCL
(5)
35
H9
I/O
DVIO
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
P3.2/UCB0CLK/UCA0STE (5)
36
G8
I/O
DVIO
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
General-purpose digital I/O
P3.3/UCA0TXD/UCA0SIMO
(5)
37
G9
I/O
DVIO
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.4/UCA0RXD/UCA0SOMI
(5)
38
G7
I/O
DVIO
Receive data – USCI_A0 UART mode
DVSS
39
F9
Digital ground supply
DVIO (6)
40
E9
Digital I/O power supply
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.0/PM_UCB1STE/
PM_UCA1CLK (5)
Default mapping: Slave transmit enable – USCI_B1 SPI mode
41
E8
I/O
DVIO
Default mapping: Clock signal input – USCI_A1 SPI slave
mode
Default mapping: Clock signal output – USCI_A1 SPI master
mode
P4.1/PM_UCB1SIMO/
PM_UCB1SDA (5)
General-purpose digital I/O with reconfigurable port mapping
secondary function
42
E7
I/O
DVIO
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/
PM_UCB1SCL (5)
General-purpose digital I/O with reconfigurable port mapping
secondary function
43
D9
I/O
DVIO
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
(6)
The voltage on DVIO is not supervised or monitored.
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO. (2)
NAME
RGC
I/O (1)
SUPPLY
DESCRIPTION
ZQE
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.3/PM_UCB1CLK/
PM_UCA1STE (5)
44
D8
I/O
DVIO
Default mapping: Clock signal input – USCI_B1 SPI slave
mode
Default mapping: Clock signal output – USCI_B1 SPI master
mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.4/PM_UCA1TXD/
PM_UCA1SIMO (5)
45
D7
I/O
DVIO
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.5/PM_UCA1RXD/
PM_UCA1SOMI (5)
46
C9
I/O
DVIO
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.6/PM_UCA3TXD/
PM_UCA3SIMO (5)
47
C8
I/O
DVIO
Default mapping: Transmit data – USCI_A3 UART mode
Default mapping: Slave in, master out – USCI_A3 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.7/PM_UCA3RXD/
PM_UCA3SOMI (5)
48
C7
I/O
DVIO
Default mapping: Receive data – USCI_A3 UART mode
Default mapping: Slave out, master in – USCI_A3 SPI mode
General-purpose digital I/O
P7.0/UCA2TXD/UCA2SIMO (5)
49
B8, B9
I/O
DVIO
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
General-purpose digital I/O
P7.1/UCA2RXD/UCA2SOMI
(5)
50
A9
I/O
DVIO
Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
General-purpose digital I/O
P7.2/UCB2CLK/UCA2STE (5)
51
B7
I/O
DVIO
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
General-purpose digital I/O
P7.3/UCB2SIMO/UCB2SDA (5)
52
A8
I/O
DVIO
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
General-purpose digital I/O
P7.4/UCB2SOMI/UCB2SCL
(5)
53
A7
I/O
DVIO
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
General-purpose digital I/O
P7.5/UCB2STE/UCA2CLK (5)
54
A6
I/O
DVIO
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
BSLEN
12
(5)
55
Terminal Configuration and Functions
B6
I
DVIO
BSL enable with internal pulldown
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 4-1. Terminal Functions (continued)
TERMINAL
NO. (2)
NAME
I/O (1)
SUPPLY
RGC
ZQE
RST/NMI (5)
56
A5
I
DVIO
P5.2/XT2IN
57
B5
I/O
DVCC
P5.3/XT2OUT
58
B4
I/O
DVCC
TEST/SBWTCK (10)
59
A4
I
DVCC
PJ.0/TDO (11)
60
C5
I/O
DVCC
PJ.1/TDI/TCLK (11)
61
C4
I/O
DVCC
PJ.2/TMS (11)
62
A3
I/O
DVCC
PJ.3/TCK (11)
63
B3
I/O
DVCC
DESCRIPTION
Reset input active low (7) (8)
Nonmaskable interrupt input (7)
General-purpose digital I/O
Input terminal for crystal oscillator XT2 (9)
General-purpose digital I/O
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
JTAG test data output port
General-purpose digital I/O
JTAG test data input or test clock input
General-purpose digital I/O
JTAG test mode select
General-purpose digital I/O
JTAG test clock
Reset input active low (12)
RSTDVCC/SBWTDIO
(11)
64
A2
Reserved
N/A
(13)
QFN Pad
Pad
N/A
(7)
(8)
(9)
(10)
(11)
(12)
(13)
I/O
DVCC
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation
activated
Reserved
QFN package pad. Connection to VSS recommended.
This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels from
DVSS to DVIO are required.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, the must pin be configured properly for the intended input swing.
See Section 6.5.1 and Section 6.6 for use with BSL and JTAG functions, respectively.
See Section 6.6 for use with JTAG function.
This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input
swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI
reset as found on other devices in the MSP430 family. Refer to Section 6.5.1 and Section 6.6 for details regarding the use of this pin.
C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at VCC to VSS
–0.3
4.1
V
Voltage applied at VIO to VSS
–0.3
2.2
V
Voltage applied to any pin (excluding VCORE and VIO pins) (2)
–0.3
VCC + 0.3
V
Voltage applied to VIO pins
–0.3
VIO + 0.2
Diode current at any device pin
Storage temperature, Tstg (3)
(1)
(2)
(3)
–55
UNIT
V
±2
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage during program execution and flash
programming (AVCC = DVCC) (1) (2) (3)
VIO
Supply voltage applied to DVIO referenced to VSS
VSS
Supply voltage (AVSS = DVSS)
TA
Operating free-air temperature
TJ
Operating junction temperature
CVCORE
Recommended capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
(1)
(2)
(3)
(4)
14
MAX
1.8
3.6
PMMCOREVx = 0, 1
2.0
3.6
PMMCOREVx = 0, 1, 2
2.2
3.6
PMMCOREVx = 0, 1, 2, 3
(2)
NOM
PMMCOREVx = 0
UNIT
V
2.4
3.6
1.62
1.98
V
–40
85
°C
–40
85
°C
0
(4)
V
470
nF
10
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
During VCC and VIO power up, it is required that VIO ≥ VCC during the ramp up phase of VIO. During VCC and VIO power down, it is
required that VIO ≥ VCC during the ramp down phase of VIO (see Figure 5-1).
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for
the exact values and further details.
TI recommends a capacitor tolerance of ±20% or better.
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
fSYSTEM
(5)
Processor frequency (maximum MCLK frequency) (5)
(see Figure 5-3)
NOM
MAX
PMMCOREVx = 0 (default
condition),
1.8 V ≤ VCC ≤ 3.6 V
0
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
25.0
UNIT
MHz
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
VCC
VIO
VIO,min
VSS
t
VCC ≤ VIO
while VIO < VIO,min
VIO ≤ VCC
VCC ≤ VIO
while VIO < VIO,min
NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the
general-purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through
their internal pulldown resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to
VSS through its internal pulldown resistor. When VCC reaches above the BOR threshold, the general-purpose I/Os
become high-impedance inputs (no pullup or pulldown enabled), RST/NMI becomes an input pulled up to VIO through
its internal pullup resistor, and BSLEN remains pulled down to VSS through its internal pulldown resistor.
NOTE: Under certain condtions during the rising transition of VCC, the general-purpose I/Os that reside on the VIO supply
domain may actively transition high momentarily before settling to high-impedance inputs. These voltage transitions
are temporary (typically resolving to high impedance inputs when VCC exceeds approximately 0.9 V) and are bounded
by the VIO supply.
Figure 5-1. VCC and VIO Power Sequencing
Specifications
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VCC
V(SVSH_+), min
tWAKE_UP_RESET
tWAKE_UP_RESET
DVCC
tWAKE_UP_RESET
VCC
VIT+
RSTDVCC
VCC ≥ VRSTDVCC
VRSTDVCC = VCC
VIO
tWAKE_UP_RESET
DVIO
tWAKE_UP_RESET
VIO
VIT+
RST
VIO ≥ VRST
VRST = VIO
t
NOTE: The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on
DVCC voltage supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum
threshold, the device remains in its reset condition; that is, these conditions form a logical OR with respect to device
reset.
Figure 5-2. Reset Timing
16
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.2
2.0
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 5-3. Maximum System Frequency
5.4
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
PMMCOREVx
1 MHz
TYP
IAM,
IAM,
(1)
(2)
(3)
Flash
RAM
Flash
RAM
3.0 V
3.0 V
MAX
0.47
8 MHz
TYP
2.32
MAX
12 MHz
TYP
20 MHz
MAX
TYP
0
0.36
1
0.40
2.65
4.0
2
0.44
2.90
4.3
7.1
3
0.46
4.6
7.6
0
0.20
1
0.22
1.35
2.0
2
0.24
1.50
2.2
3.7
3
0.26
1.60
2.4
3.9
1.20
TYP
UNIT
MAX
2.60
3.10
0.29
25 MHz
MAX
4.4
mA
7.7
10.1
11.0
1.30
2.2
mA
4.2
5.3
6.2
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
Specifications
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5.5
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
0
73
78
91
84
93
103
3.0 V
3
89
95
105
101
112
124
2.2 V
0
6.7
6.7
12
10.6
13
29
3.0 V
3
7.2
7.2
13
11.6
14
30
0
1.8
2.1
3.4
8.4
1
1.9
2.2
3.6
8.7
2
2.0
2.4
3.8
9.0
0
2.0
2.3
3.6
8.6
1
2.1
2.5
3.8
8.9
2
2.2
2.6
3.9
9.2
3
2.3
2.7
4.1
4.0
9.2
25
0
1.3
1.6
2.9
2.6
8.5
24
1
1.3
1.6
2.8
8.8
2
1.4
1.7
2.9
9.2
3
1.5
1.8
3.2
2.9
9.2
25
0
1.1
1.3
1.7
2.6
7.5
22
1
1.3
1.4
2.7
7.7
2
1.4
1.4
2.8
7.9
3.0 V
ILPM4
Low-power mode 4 (8)
(4)
ILPM4.5
Low-power mode 4.5 (9)
IDVIO_START
Current supplied from
DVIO while
DVCC = AVCC = 0 V,
DVIO = 1.62 V to 1.98 V,
All DVIO I/O floating
including BSLEN and
RST/NMI
3.0 V
3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
18
85°C
2.2 V
3.0 V
ILPM3,VLO
60°C
PMMCOREVx
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
25°C
VCC
2.2 V
ILPM3,XT1LF
–40°C
(2)
TYP
MAX
TYP
MAX
3.1
TYP
MAX
TYP
MAX
24
UNIT
µA
µA
µA
µA
µA
1.5
1.5
1.8
2.8
7.9
23
3.0 V
0.15
0.18
0.35
0.26
0.5
1.0
µA
0V
1.40
1.40
2.0
1.45
1.5
2.1
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for the watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1
MHz operation, DCO bias generator enabled.)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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5.6
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Thermal Characteristics
VALUE (1)
RθJA
Junction-to-ambient thermal resistance, still air
RθJC(TOP)
Junction-to-case (top) thermal resistance
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
RθJB
Junction-to-board thermal resistance
ΨJT
Junction-to-package-top thermal characterization parameter
ΨJB
Junction-to-board thermal characterization parameter
(1)
(2)
VQFN 64 (RGC)
29.3
BGA 80 (ZQE)
52.0
VQFN 64 (RGC)
14.2
BGA 80 (ZQE)
23.9
VQFN 64 (RGC)
BGA 80 (ZQE)
1.1
N/A (2)
VQFN 64 (RGC)
8.2
BGA 80 (ZQE)
29.3
VQFN 64 (RGC)
0.2
BGA 80 (ZQE)
0.5
VQFN 64 (RGC)
8.1
BGA 80 (ZQE)
29.3
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
N/A = not applicable
Specifications
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5.7 Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (1)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
1.8 V
0.80
TYP
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
These same parametrics apply to the clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
5.8 Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VCC = 3.0 V
VIT–
Negative-going input threshold voltage
VCC = 3.0 V
Vhys
Input voltage hysteresis (VIT+ – VIT–)
VCC = 3.0 V
RPull
Pullup or pulldown resistor (1)
For pullup: VIN = VSS,
For pulldown: VIN = VIO
CI
Input capacitance
VIN = VSS or VIO
(1)
VIO
MIN
1.62 V
0.8
TYP
1.25
1.98 V
1.1
1.40
1.62 V
0.3
0.7
1.98 V
0.5
1.0
1.62 V to 1.98 V
0.3
0.8
V
50
kΩ
20
35
MAX
5
UNIT
V
V
pF
Also applies to the RST pin when the pullup or pulldown resistor is enabled.
5.9 Inputs – Interrupts DVCC Domain Port P6
(P6.0 to P6.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
TEST CONDITIONS
External interrupt timing (1)
VCC
External trigger pulse duration to set interrupt flag
1.8 V, 3 V
MIN
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
20
External interrupt timing
TEST CONDITIONS
(2)
External trigger pulse duration to set interrupt flag,
VCC = 1.8 V or 3.0 V
VIO (1)
1.62 V to
1.98 V
MIN
MAX
20
UNIT
ns
In all test conditions, VIO ≤ VCC.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Specifications
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5.11 Leakage Current – General-Purpose I/O DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
See
(1) (2)
VCC
MIN
MAX
1.8 V, 3 V
–50
50
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.12 Leakage Current – General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
(3)
High-impedance leakage current
TEST CONDITIONS
See
(2) (3)
VIO
(1)
1.62 V to 1.98 V
MIN
MAX
–50
50
UNIT
nA
In all test conditions, VIO ≤ VCC.
The leakage current is measured with VSS or VIO applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
5.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (2)
I(OHmax) = –5 mA (1)
I(OHmax) = –15 mA (2)
I(OLmax) = 3 mA
VOL
Low-level output voltage
(2)
1.8 V
3V
(1)
I(OLmax) = 10 mA (2)
I(OLmax) = 5 mA (1)
I(OLmax) = 15 mA (2)
(1)
VCC
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Specifications
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5.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (2)
VOH
High-level output voltage
I(OHmax) = –3 mA (3)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (3)
I(OLmax) = 1 mA (2)
VOL
Low-level output voltage
I(OLmax) = 3 mA (3)
I(OLmax) = 2 mA (2)
I(OLmax) = 6 mA (3)
(1)
(2)
(3)
VCC
1.8 V
3.0 V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
1.8 V
3.0 V
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA
VOH
High-level output voltage
VIO
(1)
(2)
I(OHmax) = –3 mA (2)
1.62 V to 1.98 V
I(OHmax) = –6 mA (2)
VOL
(1)
(2)
Low-level output voltage
I(OLmax) = 3 mA (2)
MIN
MAX
VIO – 0.05
VIO
VIO – 0.25
VIO
VIO – 0.50
VIO
VSS VSS + 0.25
1.62 V to 1.98 V
I(OLmax) = 6 mA (2)
VSS VSS + 0.50
UNIT
V
V
In all test conditions, VIO ≤ VCC.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
5.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA
VOH
High-level output voltage
VIO
(2)
(3)
I(OHmax) = –1 mA (3)
1.62 V to 1.98 V
I(OHmax) = –2 mA (3)
VOL
(1)
(2)
(3)
22
Low-level output voltage
I(OLmax) = 1 mA (3)
I(OLmax) = 2 mA (3)
1.62 V to 1.98 V
MIN
MAX
VIO – 0.05
VIO
VIO – 0.25
VIO
VIO – 0.50
VIO
VSS VSS + 0.25
VSS VSS + 0.50
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
In all test conditions, VIO ≤ VCC.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Specifications
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5.17 Output Frequency – General-Purpose I/O DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1) (2)
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
Clock output frequency
ACLK, SMCLK, or MCLK,
CL = 20 pF (2)
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
5.18 Output Frequency – General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
(3)
Clock output frequency
TEST CONDITIONS
(1) (2)
ACLK, SMCLK, or MCLK,
CL = 20 pF (2)
MIN
MAX
VIO = 1.62 V to 1.98 V (3),
PMMCOREVx = 0
16
VIO = 1.62 V to 1.98 V (3),
PMMCOREVx = 3
25
VIO = 1.62 V to 1.98 V (3),
PMMCOREVx = 0
16
VIO = 1.62 V to 1.98 V (3),
PMMCOREVx = 3
25
UNIT
MHz
MHz
A resistive divider with 2 × R1 between VIO and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VIO at the specified toggle frequency.
In all test conditions, VIO ≤ VCC.
Specifications
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5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
VCC = 3.0 V
Px.y
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL – Low-Level Output Voltage – V
Figure 5-4. Typical Low-Level Output Current vs Low-Level
Output Voltage
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
-5.0
-10.0
TA = 85°C
TA = 25°C
3.0
2.0
1.0
0.5
1.0
1.5
2.0
VCC = 1.8 V
Px.y
-1.0
-2.0
-3.0
-4.0
TA = 85°C
-5.0
-6.0
TA = 25°C
-7.0
-8.0
-25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-6. Typical High-Level Output Current vs High-Level
Output Voltage
24
4.0
0.0
VCC = 3.0 V
Px.y
-20.0
5.0
VOL – Low-Level Output Voltage – V
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
-15.0
TA = 85°C
6.0
0.0
0.0
3.5
TA = 25°C
VCC = 1.8 V
Px.y
7.0
Specifications
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage
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5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA = 25°C
VCC = 3.0 V
Px.y
55.0
50.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
TA = 85°C
-55.0
TA = 25°C
-60.0
0.0
TA = 85°C
16
12
8
4
0.5
1.0
1.5
2.0
0
VCC = 3.0 V
Px.y
-50.0
TA = 25°C
20
VOL – Low-Level Output Voltage – V
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
0.0
-5.0
VCC = 1.8 V
Px.y
0
0.0
3.5
VOL – Low-Level Output Voltage – V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
24
0.5
VCC = 1.8 V
Px.y
-4
-8
-12
TA = 85°C
-16
TA = 25°C
-20
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
0.0
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
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5.21 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
ΔIDVCC.LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
0.170
32768
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1 (2)
XT1BYPASSLV = 0 or 1
OALF
3.0 V
0.290
XT1 oscillator crystal frequency,
LF mode
CL,eff
10
fFault,LF
tSTART,LF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
26
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
XTS = 0,
XT1BYPASS = 1 (8),
XT1BYPASSLV = 0 or 1
Hz
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
50
kHz
1
5.5
Oscillator fault frequency,
LF mode (7)
µA
kΩ
XTS = 0, XCAPx = 1
Duty cycle, LF mode
Start-up time, LF mode
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
UNIT
(3)
XTS = 0, XCAPx = 0 (6)
Integrated effective load
capacitance, LF mode (5)
MAX
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
fXT1,LF0
Oscillation allowance for
LF crystals (4)
TYP
pF
30%
70%
10
10000
Hz
1000
3.0 V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square-wave with parametrics defined in
the Schmitt-Trigger Inputs section of this data sheet. When in crystal bypass mode, XIN can be configured so that it can support an
input digital waveform with swing levels from DVSS to DVCC (XT1BYPASSLV = 0) or DVSS to DVIO (XT1BYPASSLV = 1). In this case,
it is required that the pin be configured properly for the intended input swing.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but each application should be evaluated based on the actual crystal selected:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
• For XT1DRIVEx = 3, CL,eff ≥ 6 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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5.22 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
IDVCC.XT2
XT2 oscillator crystal current
consumption
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
(2)
TYP
MAX
UNIT
200
260
3.0 V
µA
325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
450
fXT2,HF0
XT2 oscillator crystal frequency,
mode 0
XT2DRIVEx = 0, XT2BYPASS = 0 (3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal frequency,
mode 1
XT2DRIVEx = 1, XT2BYPASS = 0 (3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal frequency,
mode 2
XT2DRIVEx = 2, XT2BYPASS = 0 (3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal frequency,
mode 3
XT2DRIVEx = 3, XT2BYPASS = 0 (3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level squarewave input frequency, bypass
mode
XT2BYPASS = 1 (4) (3)
XT2BYPASSLV = 0 or 1
0.7
32
MHz
OAHF
tSTART,HF
CL,eff
Oscillation allowance for
HF crystals (5)
Start-up time
Integrated effective load
capacitance, HF mode (6)
(3)
(4)
(5)
(6)
450
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Ω
3.0 V
ms
0.3
1
(1)
Duty cycle
(1)
(2)
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
Measured at ACLK, fXT2,HF2 = 20 MHz
40%
50%
pF
60%
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square-wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet. When in crystal bypass mode, XT2IN can be configured so that it can support an
input digital waveform with swing levels from DVSS to DVCC (XT2BYPASSLV = 0) or DVSS to DVIO (XT2BYPASSLV = 1). In this case,
it is required that the pin be configured properly for the intended input swing.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Specifications
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Crystal Oscillator, XT2 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
fFault,HF
(7)
(8)
Oscillator fault frequency
TEST CONDITIONS
(7)
VCC
XT2BYPASS = 1 (8),
XT2BYPASSLV = 0 or 1
MIN
TYP
30
MAX
UNIT
300
kHz
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals. Typically, an effective load capacitance of up to 18
pF can be supported.
5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
6
9.4
14
UNIT
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.5
%/°C
Measured at ACLK (2)
1.8 V to 3.6 V
4
%/V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
40%
50%
kHz
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
5.24 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
TYP
REFO oscillator current consumption
TA = 25°C
1.8 V to 3.6 V
3
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Full temperature range
1.8 V to 3.6 V
–3.5%
3.5%
3V
–1.5%
1.5%
REFO absolute tolerance calibrated
TA = 25°C
(1)
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK
1.8 V to 3.6 V
0.01
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK (2)
1.8 V to 3.6 V
1.0
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
28
MAX
40%
50%
UNIT
µA
Hz
%/°C
%/V
60%
25
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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5.25 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31) (1)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
(1)
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0) (1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
(1)
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31) (1)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40%
DCO frequency temperature
drift (2)
dfDCO/dT
dfDCO/dVCC
(1)
(2)
(3)
DCO frequency voltage drift
(3)
50%
60%
fDCO = 1 MHz
0.1
%/°C
fDCO = 1 MHz
1.9
%/V
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 5-12. Typical DCO frequency
Specifications
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5.26 PMM, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDVCC_BOR_IT–
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
VDVCC_BOR_IT+
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
VDVCC_BOR_hys
BORH hysteresis
tRESET
Pulse duration required at RST/NMI pin to accept a reset
MIN
TYP MAX UNIT
0.80
1.30
1.45
V
1.50
V
250
mV
60
2
µs
5.27 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
VCORE2(AM)
Core voltage, active mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.80
V
VCORE1(AM)
Core voltage, active mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.60
V
VCORE0(AM)
Core voltage, active mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.40
V
VCORE3(LPM)
Core voltage, low-current mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE2(LPM)
Core voltage, low-current mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.84
V
VCORE1(LPM)
Core voltage, low-current mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.64
V
VCORE0(LPM)
Core voltage, low-current mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.44
V
30
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
5.28 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
tpd(SVSH)
t(SVSH)
dVDVCC/dt
(1)
SVSH on voltage level (1)
SVSH off voltage level (1)
SVSH propagation delay
SVSH on or off delay time
DVCC rise time
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.57
1.68
1.78
SVSHE = 1, SVSHRVL = 1
1.79
1.88
1.98
SVSHE = 1, SVSHRVL = 2
1.98
2.08
2.21
SVSHE = 1, SVSHRVL = 3
2.10
2.18
2.31
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVSHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVSHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVSHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVSHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
20
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVSHFP = 1
12.5
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVSHFP = 0
100
µs
0
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.
Specifications
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5.29 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
SVMH current consumption
SVMH on or off voltage level
1.5
tpd(SVMH)
t(SVMH)
(1)
SVMH propagation delay
SVMH on or off delay time
µA
SVMHE = 1, SVSMHRRL = 0
1.62
1.74
1.85
SVMHE = 1, SVSMHRRL = 1
1.88
1.94
2.07
SVMHE = 1, SVSMHRRL = 2
2.07
2.14
2.28
SVMHE = 1, SVSMHRRL = 3
2.20
2.30
2.42
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.55
SVMHE = 1, SVSMHRRL = 5
2.52
2.70
2.88
SVMHE = 1, SVSMHRRL = 6
2.90
3.10
3.23
SVMHE = 1, SVSMHRRL = 7
2.90
3.10
3.23
SVMHE = 1, SVMHOVPE = 1
UNIT
nA
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
V(SVMH)
MAX
0
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
(1)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
µs
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
100
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.
5.30 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
t(SVSL)
32
SVSL propagation delay
SVSL on or off delay time
Specifications
TYP
MAX
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
UNIT
nA
µA
µs
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
100
µs
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5.31 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
tpd(SVML)
t(SVML)
SVML current consumption
SVML propagation delay
SVML on or off delay time
TYP
MAX
0
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
1.5
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
UNIT
nA
µA
µs
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
12.5
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
100
µs
5.32 Wake-Up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
fMCLK ≥ 4.0 MHz
MIN
3.5
7.5
UNIT
1.0 MHz < fMCLK <
4.0 MHz
4.5
9
150
175
µs
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode (2)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM5
Wake-up time from LPM4.5
to active mode (3)
2
3
ms
tWAKE-UP-RESET
Wake-up time from RST or
BOR event to active mode (3)
2
3
ms
(1)
(2)
(3)
µs
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSLand SVML in fullperformance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
This value represents the time from the wake-up event to the reset vector execution.
Specifications
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5.33 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
1.62 V to 1.8 V
25
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
1.8 V
fTA
3.0 V
1.62 V to 1.98 V
25
Timer_A capture timing (1)
All capture inputs,
Minimum pulse duration
required for capture
1.8 V
1.62 V to 1.8 V
20
tTA,cap
3.0 V
1.62 V to 1.98 V
20
(1)
MHz
ns
The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTA,cap.
5.34 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
1.62 V to 1.8 V
25
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
1.8 V
fTB
3.0 V
1.62 V to 1.98 V
25
Timer_B capture timing (1)
All capture inputs,
Minimum pulse duration
required for capture
1.8 V
1.62 V to 1.8 V
20
tTB,cap
3.0 V
1.62 V to 1.98 V
20
(1)
34
MHz
ns
The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTB,cap.
Specifications
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5.35 USCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
5.36 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
UART receive deglitch time (1)
tτ
(1)
VCC
VIO
MIN
MAX
1.8 V
1.62 V to 1.80 V
50
600
3.0 V
1.62 V to 1.98 V
50
600
UNIT
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.37 USCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
CONDITIONS
MIN
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
USCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
fSYSTEM
MHz
5.38 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-13 and Figure 5-14)
PARAMETER
fUSCI
USCI input clock frequency
TEST CONDITIONS
1.62 V to 1.80 V
55
3.0 V
1.62 V to 1.98 V
55
2.4 V
1.62 V to 1.98 V
35
3.0 V
1.62 V to 1.98 V
35
1.8 V
1.62 V to 1.80 V
0
3.0 V
1.62 V to 1.98 V
0
2.4 V
1.62 V to 1.98 V
0
3.0 V
1.62 V to 1.98 V
0
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
1.8 V
1.62 V to 1.80 V
20
3.0 V
1.62 V to 1.98 V
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
1.62 V to 1.98 V
16
3.0 V
1.62 V to 1.98 V
16
1.8 V
1.62 V to 1.80 V
–10
3.0 V
1.62 V to 1.98 V
–10
2.4 V
1.62 V to 1.98 V
–10
3.0 V
1.62 V to 1.98 V
–10
SOMI input data setup time
PMMCOREV = 0
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time (2)
CL = 20 pF, PMMCOREV = 0
tHD,MO
SIMO output data hold time (3)
CL = 20 pF, PMMCOREV = 3
(1)
(2)
(3)
MIN
1.8 V
PMMCOREV = 3
tHD,MI
VIO
SMCLK or ACLK,
Duty cycle = 50% ±10%
PMMCOREV = 0
tSU,MI
VCC
ns
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 513 and Figure 5-14.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-13. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 1
36
Specifications
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5.39 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
(see Figure 5-15 and Figure 5-16)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE
high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI
data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to
SOMI high impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
tHD,SO
(1)
(2)
(3)
SOMI output data valid time (2)
SOMI output data hold time (3)
VCC
VIO
1.8 V
1.62 V to 1.80 V
MIN
12
MAX
3.0 V
1.62 V to 1.98 V
12
2.4 V
1.62 V to 1.98 V
10
3.0 V
1.62 V to 1.98 V
10
1.8 V
1.62 V to 1.80 V
6
3.0 V
1.62 V to 1.98 V
6
2.4 V
1.62 V to 1.98 V
6
3.0 V
1.62 V to 1.98 V
6
1.8 V
1.62 V to 1.80 V
65
3.0 V
1.62 V to 1.98 V
65
2.4 V
1.62 V to 1.98 V
45
3.0 V
1.62 V to 1.98 V
45
1.8 V
1.62 V to 1.80 V
35
3.0 V
1.62 V to 1.98 V
35
2.4 V
1.62 V to 1.98 V
25
3.0 V
1.62 V to 1.98 V
1.8 V
1.62 V to 1.80 V
5
3.0 V
1.62 V to 1.98 V
5
2.4 V
1.62 V to 1.98 V
5
3.0 V
1.62 V to 1.98 V
5
1.8 V
1.62 V to 1.80 V
5
3.0 V
1.62 V to 1.98 V
5
2.4 V
1.62 V to 1.98 V
5
5
UNIT
ns
ns
ns
ns
25
ns
ns
3.0 V
1.62 V to 1.98 V
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0
1.8 V
1.62 V to 1.80 V
75
3.0 V
1.62 V to 1.98 V
75
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3
2.4 V
1.62 V to 1.98 V
50
3.0 V
1.62 V to 1.98 V
50
CL = 20 pF,
PMMCOREV = 0
1.8 V
1.62 V to 1.80 V
10
3.0 V
1.62 V to 1.98 V
10
CL = 20 pF,
PMMCOREV = 3
2.4 V
1.62 V to 1.98 V
10
3.0 V
1.62 V to 1.98 V
10
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-15
and Figure 5-16.
Specifications
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 1
38
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
5.40 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
tSU,DAT
VIO
(1)
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
UNIT
fSYSTEM
MHz
400
kHz
1.62 V to 1.98 V
2.2 V, 3 V
1.62 V to 1.98 V
2.2 V, 3 V
1.62 V to 1.98 V
Data hold time
2.2 V, 3 V
1.62 V to 1.98 V
0
ns
Data setup time
2.2 V, 3 V
1.62 V to 1.98 V
250
ns
Setup time for STOP
tSP
Pulse duration of spikes
suppressed by input filter
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
2.2 V, 3 V
1.62 V to 1.98 V
2.2 V, 3 V
1.62 V to 1.98 V
0
MAX
2.2 V, 3 V
tSU,STO
(1)
VCC
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
50
600
ns
In all test conditions, VIO ≤ VCC
tSU,STA
tHD,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-17. I2C Mode Timing
Specifications
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5.41 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (2)
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 00
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
VCC
MIN
TYP
MAX
UNIT
1.8
3.6
V
0
AVCC
V
2.2 V
60
100
3V
75
110
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 1, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 01
3V
113
150
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 10,
VEREF = 2.5 V
3V
105
140
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 11,
VEREF = 2.5 V
3V
70
110
µA
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
(2)
µA
pF
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC
36
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. See ().
5.42 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.2
4.8
5.4
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
3.0
µs
External fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
(2)
Turn on settling time of
the ADC
See
tSample
Sampling time
RS = 1000 Ω, RI = 96 k Ω, CI = 3.5 pF (4)
tADC10ON
(1)
(2)
(3)
(4)
40
(3)
100
ns
1.8 V
3
µs
3.0 V
1
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
12 × ADC10DIV × 1/fADC10CLK
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
5.43 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF
VCC
MIN
TYP
MAX
±1.0
UNIT
EI
Integral
linearity error
ED
Differential
linearity error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EO
Offset error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
Internal impedance of source RS < 100 Ω
2.2 V, 3 V
±1.0
LSB
EG
Gain error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
2.2 V, 3 V
±1.0
LSB
ET
Total unadjusted
error
1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
2.2 V, 3 V
±2.0
LSB
1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
±1.0
LSB
5.44 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
MIN
MAX
UNIT
VeREF+ > VeREF–
(2)
1.4
AVCC
V
Negative external reference
voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
Differential external reference
voltage input
VeREF+ > VeREF–
(4)
1.4
AVCC
V
VeREF+
Positive external reference
voltage input
VeREF–
(VeREF+ –
VeREF–)
IVeREF+,
IVeREF–
CVREF+,
CVREF(1)
(2)
(3)
(4)
(5)
Static input current
Capacitance at VeREF+ or
VeREF- terminal
TEST CONDITIONS
VCC
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
–26
26
µA
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
–1
1
µA
See
(5)
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
Specifications
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5.45 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VREF+
Positive built-in reference voltage
AVCC minimum voltage, Positive
built-in reference active
AVCC(min)
Operating supply current into
AVCC terminal (2)
IREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V
REFON = 1
3V
2.445
2.486
2.527
REFVSEL = {1} for 2.0 V
REFON = 1
3V
1.94
1.97
2.01
REFVSEL = {0} for 1.5 V
REFON = 1
2.2 V, 3 V
1.461
1.485
1.511
REFVSEL = {0} for 1.5 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
V
V
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
18
24
µA
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
3V
15.5
21
µA
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
3V
13.5
21
µA
TCREF+
Temperature coefficient of built-in IVREF+ = 0 A
reference (3)
REFVSEL = {0, 1, 2}, REFON = 1
ISENSOR
Operating supply current into
AVCC terminal (4)
VSENSOR
See
VMID
AVCC divider at channel 11
(5)
UNIT
30
50 ppm/ °C
REFON = 0, INCH = 0Ah,
ADC10ON = N/A, TA = 30°C
2.2 V
20
22
3V
20
22
ADC10ON = 1, INCH = 0Ah,
TA = 30°C
2.2 V
770
3V
770
ADC10ON = 1, INCH = 0Bh,
VMID is approximately 0.5 × VAVCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
µA
mV
V
tSENSOR(sample Sample time required if
channel 10 is selected (6)
)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
µs
tVMID(sample)
Sample time required if
channel 11 is selected (7)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
1
µs
PSRR_DC
Power supply rejection ratio (dc)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1
120
µV/V
PSRR_AC
Power supply rejection ratio (ac)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
6.4
mV/V
tSETTLE
Settling time of reference
voltage (8)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
75
µs
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
42
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
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5.46 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
IAVCC_COMP
VREF
IAVCC_REF
CBPWRMD = 00, CBON = 1, CBRSx = 00
Comparator operating
supply current into
AVCC, Excludes
CBPWRMD = 01, CBON = 1, CBRSx = 00
reference resistor ladder
Reference voltage level
Quiescent current of
resistor ladder into
AVCC, Includes REF
module current
VIC
Common mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
tPD
tPD,filter
Series input resistance
Propagation delay,
response time
Propagation delay with
filter active
MAX
V
38
2.2 V
31
38
3V
32
39
2.2 V,
3V
10
17
CBPWRMD = 10, CBON = 1, CBRSx = 00
2.2 V,
3V
0.2
0.85
CBREFLx = 01, CBREFACC = 0
≥ 1.8V
1.400
1.43
1.472
CBREFLx = 10, CBREFACC = 0
≥ 2.2V
1.864
1.90
1.960
CBREFLx = 11, CBREFACC = 0
≥ 3.0V
2.32
2.37
2.44
CBREFACC = 0, CBREFLx = 01, CBRSx = 10,
REFON = 0, CBON = 0
2.2 V,
3V
33
40
CBREFACC = 1, CBREFLx = 01, CBRSx = 10,
REFON = 0, CBON = 0
2.2 V,
3V
17
22
µA
V
µA
0
VCC–1
CBPWRMD = 00
–20
20
CBPWRMD = 01, 10
–10
10
5
ON - switch closed
OFF - switch opened
UNIT
3
V
mV
pF
4
50
kΩ
MΩ
CBPWRMD = 00, CBF = 0
450
CBPWRMD = 01, CBF = 0
600
CBPWRMD = 10, CBF = 0
50
ns
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.5
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.8
3.4
6.5
1
2
µs
1.0
1.5
µs
50
ppm/
°C
tEN_CMP
Comparator enable time
CBON = 0 to CBON = 1, CBPWRMD = 00, 01
tEN_REF
Resistor reference
enable time
CBON = 0 to CBON = 1
TCREF
Temperature coefficient
reference
VCB_REF
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
µs
VIN ×
(n+0.5)
/32
VIN ×
(n+1)
/32
VIN ×
(n+1.5)
/32
Specifications
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5.47 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
11
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank
erase
6
11
mA
16
ms
tCPT
Cumulative program time
See
(1)
4
Program and erase endurance
10
5
10
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
tErase
Erase time for segment, mass erase, and bank erase when
available
See
(2)
23
32
ms
fMCLK,MRG
MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)
0
1
MHz
tBlock,
(1)
(2)
N
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write mode and block write mode.
These values are hardwired into the state machine of the flash controller.
5.48 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
VIO
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
1.62 V to 1.98 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
1.62 V to 1.98 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first
clock edge) (1)
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
µs
TCK input frequency for 4-wire JTAG (2)
fTCK
Rinternal
(1)
(2)
44
Internal pulldown resistance on TEST
1.62 V to 1.98 V
2.2 V, 3 V
1.62 V to 1.98 V
15
100
2.2 V
1.62 V to 1.98 V
0
5
3V
1.62 V to 1.98 V
0
10
2.2 V, 3 V
1.62 V to 1.98 V
45
60
80
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
5.49 DVIO BSL Entry
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
(1)
tSU, BSLEN
Setup time, BSLEN to RST/NMI
tHO,
Hold time, BSLEN to RST/NMI (2)
(1)
(2)
BSLEN
VCC
VIO
MIN
MAX
UNIT
2.2 V, 3 V
1.62 V to 1.98 V
100
ns
2.2 V, 3 V
1.62 V to 1.98 V
350
µs
AVCC, DVCC, DVIO stable and within specification.
BSLEN must remain logically high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold
time is achieved, BSLEN is a don't care.
BSLEN
VIT+
VITtHO,BSLEN
VIT+
VITRST/NMI
(DVIO domain)
tSU,BSLEN
t
Figure 5-18. DVIO BSL Entry Timing
Specifications
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6 Detailed Description
6.1
CPU (Link to user's guide)
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
46
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.2
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up signal from RST/NMI, P1, or P2
Detailed Description
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6.3
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
System Reset
Power-Up
External Reset
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
PMM Password Violation
INTERRUPT FLAG
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Maskable
0FFF8h
60
Maskable
0FFF6h
59
Maskable
0FFF4h
58
Maskable
0FFF2h
57
COMP_B
UCA0RXIFG, UCA0TXIFG (UCA0IV)
USCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV) (1)
USCI_A1 Receive or Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV) (1)
UCB1RXIFG, UCB1TXIFG (UCB1IV)
ADC10_A
ADC10IFG0 (1)
(3)
Maskable
0FFF0h
56
(1) (3)
Maskable
0FFEEh
55
Maskable
0FFECh
54
Maskable
0FFEAh
53
Maskable
0FFE8h
52
(3) (4)
(1) (3)
USCI_A2 Receive or Transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV)
USCI_B2 Receive or Transmit
UCB2RXIFG, UCB2TXIFG (UCB2IV) (1)
(3)
TA0
TA0CCR0 CCIFG0 (3)
Maskable
0FFE6h
51
TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1) (3)
Maskable
0FFE4h
50
Maskable
0FFE2h
49
Maskable
0FFE0h
48
Maskable
0FFDEh
47
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
Maskable
0FFD0h
40
Maskable
0FFCEh
39
Maskable
0FFCCh
38
(5)
Reserved
Reserved
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)
(1) (3)
USCI_A3 Receive or Transmit
UCA3RXIFG, UCA3TXIFG (UCA3IV)
USCI_B3 Receive or Transmit
UCB3RXIFG, UCB3TXIFG (UCB3IV) (1)
TB0
TB0CCR0 CCIFG0
TA1
TA1
I/O Port P1
TA2
TA2
I/O Port P2
48
(3)
WDTIFG
USCI_B1 Receive or Transmit
TB0
(3)
(4)
(5)
(3)
(1) (3)
USCI_A0 Receive or Transmit
Watchdog Timer_A Interval Timer
Mode
(1)
(2)
Comparator B interrupt flags (CBIV) (1)
(3)
(3)
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1) (3)
TA1CCR0 CCIFG0
(3)
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1) (3)
P1IFG.0 to P1IFG.7 (P1IV) (1)
TA2CCR0 CCIFG0
(3)
(3)
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1) (3)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
(3)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are in the module.
Only on devices with ADC, otherwise reserved
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 6-1. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
RTC_A
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
I/O Port P6
P6IFG.0 to P6IFG.7 (P6IV)
WORD
ADDRESS
PRIORITY
Maskable
0FFCAh
37
Maskable
0FFC8h
36
0FFC6h
35
(1) (3)
Reserved (5)
Reserved
6.4
SYSTEM
INTERRUPT
⋮
⋮
0FF80h
0, lowest
Memory Organization
Table 6-2 lists the memory organization of the devices.
Table 6-2. Memory Organization (1)
Memory (flash)
Main: interrupt vector
MSP430F5259, MSP430F5258,
MSP430F5255, MSP430F5254
MSP430F5257, MSP430F5256,
MSP430F5253, MSP430F5252
128KB
00FFFFh-00FF80h
128KB
00FFFFh-00FF80h
Bank D
32KB
002A3FFh-0022400h
32KB
002A3FFh-0022400h
Bank C
32KB
00223FFh-001A400h
32KB
00223FFh-001A400h
Bank B
32KB
001A3FFh-0012400h
32KB
001A3FFh-0012400h
Bank A
32KB
00123FFh-00A400h
32KB
00123FFh-00A400h
Sector 7
4KB
00A3FFh-009400h
n/a
Sector 6
4KB
0093FFh-008400h
n/a
Sector 5
4KB
0083FFh-007400h
n/a
Sector 4
4KB
0073FFh-006400h
n/a
Sector 3
4KB
0063FFh-005400h
4KB
0063FFh-005400h
Sector 2
4KB
0053FFh-004400h
4KB
0053FFh-004400h
Sector 1
4KB
0043FFh-003400h
4KB
0043FFh-003400h
Sector 0
4KB
0033FFh-002400h
4KB
0033FFh-002400h
A
128 B
001BFFh-001B80h
128 B
001BFFh-001B80h
B
128 B
001B7Fh-001B00h
128 B
001B7Fh-001B00h
C
128 B
001AFFh-001A80h
128 B
001AFFh-001A80h
D
128 B
001A7Fh-001A00h
128 B
001A7Fh-001A00h
Total Size
Main: code memory
RAM
TI factory memory (ROM)
(1)
N/A = Not available
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Table 6-2. Memory Organization(1) (continued)
Information memory (flash)
Bootloader (BSL) memory (flash)
MSP430F5257, MSP430F5256,
MSP430F5253, MSP430F5252
Info A
128 B
0019FFh-001980h
128 B
0019FFh-001980h
Info B
128 B
00197Fh-001900h
128 B
00197Fh-001900h
Info C
128 B
0018FFh-001880h
128 B
0018FFh-001880h
Info D
128 B
00187Fh-001800h
128 B
00187Fh-001800h
BSL 3
512 B
0017FFh-001600h
512 B
0017FFh-001600h
BSL 2
512 B
0015FFh-001400h
512 B
0015FFh-001400h
BSL 1
512 B
0013FFh-001200h
512 B
0013FFh-001200h
BSL 0
512 B
0011FFh-001000h
512 B
0011FFh-001000h
4KB
000FFFh-0h
4KB
000FFFh-0h
Size
Peripherals
6.5
MSP430F5259, MSP430F5258,
MSP430F5255, MSP430F5254
Bootloader (BSL)
NOTE
Devices from TI come factory programmed with either an I2C-based BSL or a timer-based
UART BSL. See Table 3-1 to determine which BSL type is implemented.
6.5.1
Bootloader – I2C
The I2C BSL enables users to program the flash memory or RAM using a I2C serial interface. Access to
the device memory through the BSL is protected by an user-defined password.
When using the BSL, it requires a specific entry sequence on the RST/NMI and BSLEN pins. Table 6-3
shows the required pins and their functions. For further details on interfacing to development tools and
device programmers, see the MSP430™ Hardware Tools User's Guide (SLAU278). For a complete
description of the features of the BSL and its implementation, see the MSP430 Programming With the
Bootloader User's Guide (SLAU319).
NOTE
To invoke the BSL from the DVIO domain, the RST/NMI pin and BSLEN pins must be used
for the entry sequence. It is critical not to confuse the RST/NMI pin with the
RSTDVCC/SBWTDIO pin. In many other MSP430 devices, SBWTDIO is shared with the
RST/NMI pin, and RSTDVCC does not exist. Additional information can be found in
Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
50
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 6-3. BSL Pin Requirements and Functions
6.5.2
DEVICE SIGNAL
BSL FUNCTION
RST/NMI
External reset
BSLEN
Enable BSL
P4.1/PM_UCB1SDA
I2C data
P4.2/ PM_UCB1SCL
I2C clock
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
Bootloader – UART
The UART BSL enables users to program the flash memory or RAM using a UART serial interface.
Access to the device memory through the BSL is protected by an user-defined password. Because the
F525x have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO
supply domains. This is useful when the MSP430 is interfacing to a host on the DVIO supply domain. The
BSL interface on the DVIO supply domain (Table 6-5) uses the USCI_A0 module configured as a UART.
The BSL interface on the DVCC supply domain (Table 6-4) uses a timer-based UART.
For applications in which it is desirable to have BSL communication based on the DVCC supply domain,
entry to the BSL requires a specific sequence on the RSTDVCC/SBWTDIO and TEST/SBWTCK pins.
Table 6-4 lists the required pins and their function.
NOTE
Devices that are factory programmed with an UART BSL use the DVCC power supply
domain pin configuration per default (see Table 6-4).
NOTE
To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO pin and
TEST/SBWTCK pin must be used for the entry sequence. It is critical not to confuse the
RST/NMI pin with the RSTDVCC/SBWTDIO pin. In many other MSP430 devices, SBWTDIO
is shared with the RST/NMI pin, and RSTDVCC does not exist. Additional information can be
found in Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
Table 6-4. DVCC BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RSTDVCC/SBWTDIO
External reset
TEST/SBWTCK
Enable BSL
P6.1
Data transmit
P6.2
Data receive
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
When using the DVIO supply domain for the BSL, entry to the BSL requires a specific sequence on the
RST/NMI and BSLEN pins. Table 6-5 lists the required pins and their functions. For further details on
interfacing to development tools and device programmers, see the MSP430™ Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the BSL and its implementation, see the
MSP430 Programming With the Bootloader User's Guide (SLAU319). The BSL on the DVIO supply
domain uses the USCI_A0 module configured as a UART.
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NOTE
To invoke the BSL from the DVIO domain, the RST/NMI pin and the BSLEN pin must be
used for the entry sequence (see Section 5.49). It is critical not to confuse the RST/NMI pin
with the RSTDVCC/SBWTDIO pin. In many other MSP430 devices, SBWTDIO is shared with
the RST/NMI pin, and RSTDVCC does not exist. Additional information can be found in
Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
Table 6-5. DVIO BSL Pin Requirements and Functions
6.6
6.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI
External reset
BSLEN
Enable BSL
P3.3
Data transmit
P3.4
Data receive
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RSTDVCC/SBWTDIO is required to interface
with MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430™ Hardware
Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its
implementation, see MSP430™ Programming Via the JTAG Interface (SLAU320). Additional information
can be found in Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
NOTE
All JTAG I/O pins are supplied by DVCC.
NOTE
Traditionally, on other MSP430 devices, the RST/NMI pin is used for SBWTDIO, so care
must be taken not to mistakenly use the incorrect pin. On the F525x series of devices, it is
required to use RSTDVCC for SBWTDIO as shown in Table 6-6. Additional information can
be found in Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
52
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 6-6. JTAG Pin Requirements and Functions
6.6.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RSTDVCC/SBWTDIO
IN
External reset
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
Table 6-7 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to
development tools and device programmers, see the MSP430™ Hardware Tools User's Guide
(SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430™ Programming Via the JTAG Interface (SLAU320). Additional information can be found in
Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
NOTE
All SBW I/O pins are supplied by DVCC.
NOTE
Traditionally, on other MSP430 devices, the RST/NMI pin is used for SBWTDIO, so care
must be taken not to mistakenly use the incorrect pin. On the F525x series of devices, it is
required to use RSTDVCC for SBWTDIO as shown in Table 6-7. Additional information can
be found in Designing With MSP430F522x and MSP430F521x Devices (SLAA558).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RSTDVCC/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
Detailed Description
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6.7
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Flash Memory (Link to user's guide)
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
6.8
RAM (Link to user's guide)
The RAM is made up of n sectors. Each sector can be completely powered down to reduce leakage;
however, all data are lost during power down.
Features of the RAM include:
• RAM memory has n sectors. The sizes of the sectors can be found in Section 6.4, Memory
Organization.
• Each sector 0 to n can be complete disabled; however, all data in a sector are lost when it is disabled.
• Each sector 0 to n automatically enters low-power retention mode when possible.
54
Detailed Description
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6.9
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
6.9.1
Digital I/O (Link to user's guide)
•
•
•
•
•
•
•
•
6.9.2
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1, P2.
Edge-selectable interrupt capability is available for all bits of port P6.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Port Mapping Controller (Link to user's guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 6-8. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT0
–
COMP_B output
1
2
OUTPUT PIN FUNCTION
PM_TB0CLK
TB0 clock input
–
PM_ADC10CLK
–
ADC10CLK
PM_DMAE0
DMAE0 input
–
SVM output
PM_SVMOUT
–
PM_TB0OUTH
TB0 high-impedance input TB0OUTH
–
4
PM_TB0CCR0A
TB0 CCR0 capture input CCI0A
TB0 CCR0 compare output Out0
5
PM_TB0CCR1A
TB0 CCR1 capture input CCI1A
TB0 CCR1 compare output Out1
6
PM_TB0CCR2A
TB0 CCR2 capture input CCI2A
TB0 CCR2 compare output Out2
7
PM_TB0CCR3A
TB0 CCR3 capture input CCI3A
TB0 CCR3 compare output Out3
8
PM_TB0CCR4A
TB0 CCR4 capture input CCI4A
TB0 CCR4 compare output Out4
9
PM_TB0CCR5A
TB0 CCR5 capture input CCI5A
TB0 CCR5 compare output Out5
10
PM_TB0CCR6A
TB0 CCR6 capture input CCI6A
TB0 CCR6 compare output Out6
3
11
12
13
14
15
16
PM_UCA1RXD
USCI_A1 UART RXD (direction controlled by USCI – input)
PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD
USCI_A1 UART TXD (direction controlled by USCI – output)
PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK
USCI_A1 clock input/output (direction controlled by USCI)
PM_UCB1STE
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
PM_UCB1SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
PM_UCB1SCL
USCI_B1 I2C clock (open drain and direction controlled by USCI)
PM_UCB1SIMO
USCI_B1 SPI slave in master out (direction controlled by USCI)
PM_UCB1SDA
USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1CLK
USCI_B1 clock input/output (direction controlled by USCI)
PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17
PM_CBOUT1
None
18
PM_MCLK
None
COMP_B output
MCLK
19
PM_RTCCLK
None
RTCCLK output
Detailed Description
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Table 6-8. Port Mapping Mnemonics and Functions (continued)
VALUE
20
21
22
23
24
25
26
27
28
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCA0RXD
USCI_A0 UART RXD (direction controlled by USCI – input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (direction controlled by USCI – output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
PM_UCA3RXD
USCI_A3 UART RXD (direction controlled by USCI – input)
PM_UCA3SOMI
USCI_A3 SPI slave out master in (direction controlled by USCI)
PM_UCA3TXD
USCI_A3 UART TXD (direction controlled by USCI – output)
PM_UCA3SIMO
USCI_A3 SPI slave in master out (direction controlled by USCI)
PM_UCB3SIMO
USCI_B3 SPI slave in master out (direction controlled by USCI)
PM_UCB3SDA
USCI_B3 I2C data (open drain and direction controlled by USCI)
PM_UCB3SOMI
USCI_B3 SPI slave out master in (direction controlled by USCI)
PM_UCB3SCL
USCI_B3 I2C clock (open drain and direction controlled by USCI)
30
Reserved
Reserved
31 (0FFh) (1)
PM_ANALOG
Disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals
29
(1)
PxMAPy MNEMONIC
The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored,
which results in a read out value of 31.
Table 6-9. Default Mapping
PIN
56
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P4.0/P4MAP0
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.1/P4MAP1
PM_UCB1SIMO/PM_UCB1SDA
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.2/P4MAP2
PM_UCB1SOMI/PM_UCB1SCL
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
P4.3/P4MAP3
PM_UCB1CLK/PM_UCA1STE
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
P4.4/P4MAP4
PM_UCA1TXD/PM_UCA1SIMO
USCI_A1 UART TXD (Direction controlled by USCI - output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
P4.5/P4MAP5
PM_UCA1RXD/PM_UCA1SOMI
USCI_A1 UART RXD (Direction controlled by USCI - input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6
PM_UCA3TXD/PM_UCA3SIMO
USCI_A3 UART TXD (Direction controlled by USCI - output)
USCI_A3 SPI slave in master out (direction controlled by USCI)
P4.7/P4MAP7
PM_UCA3RXD/PM_UCA3SOMI
USCI_A3 UART RXD (Direction controlled by USCI - input)
USCI_A3 SPI slave out master in (direction controlled by USCI)
Detailed Description
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6.9.3
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Oscillator and System Clock (Link to user's guide)
The clock system is supported by the Unified Clock System (UCS) module, which includes support for a
32-kHz watch crystal oscillator (XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power
low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is
designed to meet the requirements of both low system cost and low power consumption. The UCS module
features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The
internal DCO provides a fast turnon clock source and stabilizes in 3.5 µs (typical). The UCS module
provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.9.4
Power-Management Module (PMM) (Link to user's guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The
brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary
supply and core supply.
6.9.5
Hardware Multiplier (Link to user's guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.9.6
Real-Time Clock (RTC_A) (Link to user's guide)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit
timers that can be cascaded to form a 16-bit timer or counter. Both timers can be read and written by
software. Calendar mode integrates an internal calendar that compensates for months with less than
31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offsetcalibration hardware.
6.9.7
Watchdog Timer (WDT_A) (Link to user's guide)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
Detailed Description
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System Module (SYS) (Link to user's guide)
The SYS module handles many of the system functions within the device. These functions include poweron reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader (BSL) entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism using JTAG that is called a
JTAG mailbox and that can be used in the application.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
58
Detailed Description
ADDRESS
019Eh
019Ch
019Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (BOR)
04h
PMMSWBOR (BOR)
06h
Wakeup from LPMx.5
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT password violation (PUC)
18h
KEYV flash password violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM password violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
06h
SVSMHDLYIFG
08h
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
04h
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
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6.9.9
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
DMA Controller (Link to user's guide)
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Table 6-11. DMA Trigger Assignments (1)
TRIGGER
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
TA2CCR2 CCIFG
TA2CCR2 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
9
UCA2RXIFG
UCA2RXIFG
UCA2RXIFG
10
UCA2TXIFG
UCA2TXIFG
UCA2TXIFG
11
UCB2RXIFG
UCB2RXIFG
UCB2RXIFG
12
UCB2TXIFG
UCB2TXIFG
UCB2TXIFG
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
UCB1TXIFG
UCB1TXIFG
UCB1TXIFG
24
(1)
(2)
CHANNEL
0
ADC10IFG0
(2)
ADC10IFG0
(2)
ADC10IFG0 (2)
25
UCA3RXIFG
UCA3RXIFG
26
UCA3TXIFG
UCA3TXIFG
UCA3RXIFG
UCA3TXIFG
27
UCB3RXIFG
UCB3RXIFG
UCB3RXIFG
28
UCB3TXIFG
UCB3TXIFG
UCB3TXIFG
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
If a reserved trigger source is selected, no trigger is generated.
Only on devices with ADC; reserved on devices without ADC
Detailed Description
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6.9.10 Universal Serial Communication Interface (USCI) (Links to user's guide: UART
Mode,SPI Mode, I2C Mode)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI
module contains two portions, A and B.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430F525x include four complete USCI modules (n = 0, 1, 2, 3).
6.9.11 TA0 (Link to user's guide)
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple
captures or compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-12. TA0 Signal Connections
INPUT PIN
NUMBER
RGC, ZQE
18, H2 - P1.0
18, H2 - P1.0
19, H3 - P1.1
20, J3 - P1.2
21, G4 - P1.3
22, H4 - P1.4
23, J4 - P1.5
60
DEVICE INPUT
SIGNAL
MODULE
INPUT SIGNAL
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK
(internal)
SMCLK
TA0CLK
TACLK
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
TA0.1
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
RGC, ZQE
19, H3 - P1.1
CCR0
TA0
TA0.0
CCI1A
20, J3 - P1.2
CBOUT
(internal)
CCI1B
ADC10 (internal)
ADC10SHSx = {1}
DVSS
GND
DVCC
VCC
TA0.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
TA0.3
CCI3A
DVSS
CCI3B
DVSS
GND
DVCC
VCC
TA0.4
CCI4A
DVSS
CCI4B
DVSS
GND
DVCC
VCC
Detailed Description
CCR1
TA1
TA0.1
21, G4 - P1.3
CCR2
TA2
TA0.2
22, H4 - P1.4
CCR3
TA3
TA0.3
23, J4 - P1.5
CCR4
TA4
TA0.4
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.9.12 TA1 (Link to user's guide)
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
captures or compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-13. TA1 Signal Connections
INPUT PIN
NUMBER
RGC, ZQE
24, G5 - P1.6
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
24, G5 - P1.6
TA1CLK
TACLK
25, H5 - P1.7
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
26, J5 - P2.0
27, G6 - P2.1
DVCC
VCC
TA1.1
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PIN
NUMBER
RGC, ZQE
NA
25, H5 - P1.7
CCR0
TA0
TA1.0
26, J5 - P2.0
CCR1
TA1
TA1.1
27, G6 - P2.1
CCR2
TA2
TA1.2
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
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6.9.13 TA2 (Link to user's guide)
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
captures or compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-14. TA2 Signal Connections
INPUT PIN
NUMBER
RGC, ZQE
1, A1 - P6.0
MODULE INPUT
SIGNAL
TA2CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
1, A1 - P6.0
TA2CLK
TACLK
2, B2 - P6.1
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
3, B1 - P6.2
4, C2 - P6.3
62
DEVICE INPUT
SIGNAL
DVCC
VCC
TA2.1
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2.2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
Detailed Description
MODULE BLOCK
Timer
MODULE
DEVICE OUTPUT
OUTPUT SIGNAL
SIGNAL
NA
OUTPUT PIN
NUMBER
RGC, ZQE
NA
2, B2 - P6.1
CCR0
TA0
TA2.0
3, B1 - P6.2
CCR1
TA1
TA2.1
4, C2 - P6.3
CCR2
TA2
TA2.2
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6.9.14 TB0 (Link to user's guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
captures or compares, PWM outputs, and interval timing. TB0 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-15. TB0 Signal Connections
INPUT PIN NUMBER
RGC, ZQE
(1)
MODULE INPUT
SIGNAL
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
(1)
TB0CLK
TBCLK
(1)
TB0.0
CCI0A
(1)
TB0.0
CCI0B
DVSS
GND
(1)
DVCC
VCC
TB0.1
CCI1A
CBOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
(1)
TB0.2
CCI2A
(1)
TB0.2
CCI2B
DVSS
GND
DVCC
VCC
(1)
TB0.3
CCI3A
(1)
TB0.3
CCI3B
DVSS
GND
(1)
(1)
(1)
(1)
(1)
(1)
DEVICE INPUT
SIGNAL
DVCC
VCC
TB0.4
CCI4A
TB0.4
CCI4B
DVSS
GND
DVCC
VCC
TB0.5
CCI5A
TB0.5
CCI5B
DVSS
GND
DVCC
VCC
TB0.6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
RGC, ZQE
(1)
CCR0
TB0
TB0.0
ADC10 (internal)
ADC10SHSx = {2}
(1)
CCR1
TB1
TB0.1
ADC10 (internal)
ADC10SHSx = {3}
(1)
CCR2
TB2
TB0.2
(1)
CCR3
TB3
TB0.3
(1)
CCR4
TB4
TB0.4
(1)
CCR5
TB5
TB0.5
(1)
CCR6
TB6
TB0.6
Timer functions can be selected by the port mapping controller.
Detailed Description
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6.9.15 Comparator_B (Link to user's guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.9.16 ADC10_A (Link to user's guide)
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion result buffer. A window
comparator with lower and upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.
6.9.17 CRC16 (Link to user's guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.9.18 REF Voltage Reference (Link to user's guide)
The reference module (REF) is responsible for generation of all critical reference voltages that can be
used by the various analog peripherals in the device.
6.9.19 Embedded Emulation Module (EEM) (S Version) (Link to user's guide)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
64
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.9.20 Peripheral File Map
Table 6-16. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-17)
0100h
000h-01Fh
PMM (see Table 6-18)
0120h
000h-010h
Flash Control (see Table 6-19)
0140h
000h-00Fh
CRC16 (see Table 6-20)
0150h
000h-007h
RAM Control (see Table 6-21)
0158h
000h-001h
Watchdog (see Table 6-22)
015Ch
000h-001h
UCS (see Table 6-23)
0160h
000h-01Fh
SYS (see Table 6-24)
0180h
000h-01Fh
Shared Reference (see Table 6-25)
01B0h
000h-001h
Port Mapping Control (see Table 6-26)
01C0h
000h-002h
Port Mapping Port P4 (see Table 6-26)
01E0h
000h-007h
Port P1, P2 (see Table 6-27)
0200h
000h-01Fh
Port P3, P4 (see Table 6-28)
0220h
000h-00Bh
Port P5, P6 (see Table 6-29)
0240h
000h-01Fh
Port P7 (see Table 6-30)
0260h
000h-00Bh
Port PJ (see Table 6-31)
0320h
000h-01Fh
TA0 (see Table 6-32)
0340h
000h-02Eh
TA1 (see Table 6-33)
0380h
000h-02Eh
TB0 (see Table 6-34)
03C0h
000h-02Eh
TA2 (see Table 6-35)
0400h
000h-02Eh
Real-Time Clock (RTC_A) (see Table 6-36)
04A0h
000h-01Bh
32-Bit Hardware Multiplier (see Table 6-37)
04C0h
000h-02Fh
DMA General Control (see Table 6-38)
0500h
000h-00Fh
DMA Channel 0 (see Table 6-38)
0510h
000h-00Ah
DMA Channel 1 (see Table 6-38)
0520h
000h-00Ah
DMA Channel 2 (see Table 6-38)
0530h
000h-00Ah
USCI_A0 (see Table 6-39)
05C0h
000h-01Fh
USCI_B0 (see Table 6-40)
05E0h
000h-01Fh
USCI_A1 (see Table 6-41)
0600h
000h-01Fh
USCI_B1 (see Table 6-42)
0620h
000h-01Fh
USCI_A2 (see Table 6-39)
0640h
000h-01Fh
USCI_B2 (see Table 6-40)
0660h
000h-01Fh
USCI_A3 (see Table 6-41)
0680h
000h-01Fh
USCI_B3 (see Table 6-42)
06A0h
000h-01Fh
ADC10_A (see Table 6-47)
0740h
000h-01Fh
Comparator_B (see Table 6-48)
08C0h
000h-00Fh
Detailed Description
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Table 6-17. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-18. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control
PM5CTL0
10h
Table 6-19. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-20. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-21. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 6-23. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
66
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 6-23. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 8
UCSCTL8
10h
UCS control 9
UCSCTL9
12h
Table 6-24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-26. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping key/ID register
PMAPKEYID
00h
Port mapping control register
PMAPCTL
02h
Port P4.0 mapping register
P4MAP0
00h
Port P4.1 mapping register
P4MAP1
01h
Port P4.2 mapping register
P4MAP2
02h
Port P4.3 mapping register
P4MAP3
03h
Port P4.4 mapping register
P4MAP4
04h
Port P4.5 mapping register
P4MAP5
05h
Port P4.6 mapping register
P4MAP6
06h
Port P4.7 mapping register
P4MAP7
07h
Detailed Description
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Table 6-27. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup or pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup or pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 6-28. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup or pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup or pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
68
Detailed Description
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Table 6-29. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup or pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup or pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Port P6 interrupt vector word
P6IV
1Eh
Port P6 interrupt edge select
P6IES
19h
Port P6 interrupt enable
P6IE
1Bh
Port P6 interrupt flag
P6IFG
1Dh
Table 6-30. Port P7 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup or pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Table 6-31. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup or pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Detailed Description
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Table 6-32. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0 counter
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
Capture/compare register 3
TA0CCR3
18h
Capture/compare register 4
TA0CCR4
1Ah
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-33. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
70
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Table 6-34. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 counter
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
Capture/compare register 3
TB0CCR3
18h
Capture/compare register 4
TB0CCR4
1Ah
Capture/compare register 5
TB0CCR5
1Ch
Capture/compare register 6
TB0CCR6
1Eh
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
Table 6-35. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
Capture/compare register 2
TA2CCR2
16h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Detailed Description
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Table 6-36. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds/counter register 1
RTCSEC/RTCNT1
10h
RTC minutes/counter register 2
RTCMIN/RTCNT2
11h
RTC hours/counter register 3
RTCHOUR/RTCNT3
12h
RTC day of week/counter register 4
RTCDOW/RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Table 6-37. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
72
Detailed Description
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Table 6-38. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-39. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
USCI control 0
UCA0CTL0
01h
USCI baud rate 0
UCA0BR0
06h
USCI baud rate 1
UCA0BR1
07h
USCI modulation control
UCA0MCTL
08h
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
USCI interrupt enable
UCA0IE
1Ch
USCI interrupt flags
UCA0IFG
1Dh
USCI interrupt vector word
UCA0IV
1Eh
Detailed Description
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Table 6-40. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB0CTL1
00h
USCI synchronous control 0
UCB0CTL0
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
USCI synchronous status
UCB0STAT
0Ah
USCI synchronous receive buffer
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
USCI interrupt enable
UCB0IE
1Ch
USCI interrupt flags
UCB0IFG
1Dh
USCI interrupt vector word
UCB0IV
1Eh
Table 6-41. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
USCI control 0
UCA1CTL0
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
UCA1MCTL
08h
USCI status
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
UCA1IE
1Ch
USCI interrupt flags
UCA1IFG
1Dh
USCI interrupt vector word
UCA1IV
1Eh
Table 6-42. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB1CTL1
00h
USCI synchronous control 0
UCB1CTL0
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
USCI interrupt enable
UCB1IE
1Ch
USCI interrupt flags
UCB1IFG
1Dh
USCI interrupt vector word
UCB1IV
1Eh
74
Detailed Description
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Table 6-43. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA2CTL1
00h
USCI control 0
UCA2CTL0
01h
USCI baud rate 0
UCA2BR0
06h
USCI baud rate 1
UCA2BR1
07h
USCI modulation control
UCA2MCTL
08h
USCI status
UCA2STAT
0Ah
USCI receive buffer
UCA2RXBUF
0Ch
USCI transmit buffer
UCA2TXBUF
0Eh
USCI LIN control
UCA2ABCTL
10h
USCI IrDA transmit control
UCA2IRTCTL
12h
USCI IrDA receive control
UCA2IRRCTL
13h
USCI interrupt enable
UCA2IE
1Ch
USCI interrupt flags
UCA2IFG
1Dh
USCI interrupt vector word
UCA2IV
1Eh
Table 6-44. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB2CTL1
00h
USCI synchronous control 0
UCB2CTL0
01h
USCI synchronous bit rate 0
UCB2BR0
06h
USCI synchronous bit rate 1
UCB2BR1
07h
USCI synchronous status
UCB2STAT
0Ah
USCI synchronous receive buffer
UCB2RXBUF
0Ch
USCI synchronous transmit buffer
UCB2TXBUF
0Eh
USCI I2C own address
UCB2I2COA
10h
USCI I2C slave address
UCB2I2CSA
12h
USCI interrupt enable
UCB2IE
1Ch
USCI interrupt flags
UCB2IFG
1Dh
USCI interrupt vector word
UCB2IV
1Eh
Table 6-45. USCI_A3 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA3CTL1
00h
USCI control 0
UCA3CTL0
01h
USCI baud rate 0
UCA3BR0
06h
USCI baud rate 1
UCA3BR1
07h
USCI modulation control
UCA3MCTL
08h
USCI status
UCA3STAT
0Ah
USCI receive buffer
UCA3RXBUF
0Ch
USCI transmit buffer
UCA3TXBUF
0Eh
USCI LIN control
UCA3ABCTL
10h
USCI IrDA transmit control
UCA3IRTCTL
12h
USCI IrDA receive control
UCA3IRRCTL
13h
USCI interrupt enable
UCA3IE
1Ch
USCI interrupt flags
UCA3IFG
1Dh
USCI interrupt vector word
UCA3IV
1Eh
Detailed Description
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Table 6-46. USCI_B3 Registers (Base Address: 06A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
UCB3CTL1
00h
USCI synchronous control 0
UCB3CTL0
01h
USCI synchronous bit rate 0
UCB3BR0
06h
USCI synchronous bit rate 1
UCB3BR1
07h
USCI synchronous status
UCB3STAT
0Ah
USCI synchronous receive buffer
UCB3RXBUF
0Ch
USCI synchronous transmit buffer
UCB3TXBUF
0Eh
USCI I2C own address
UCB3I2COA
10h
USCI I2C slave address
UCB3I2CSA
12h
USCI interrupt enable
UCB3IE
1Ch
USCI interrupt flags
UCB3IFG
1Dh
USCI interrupt vector word
UCB3IV
1Eh
Table 6-47. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A Control register 0
ADC10CTL0
00h
ADC10_A Control register 1
ADC10CTL1
02h
ADC10_A Control register 2
ADC10CTL2
04h
ADC10_A Window Comparator Low Threshold
ADC10LO
06h
ADC10_A Window Comparator High Threshold
ADC10HI
08h
ADC10_A Memory Control Register 0
ADC10MCTL0
0Ah
ADC10_A Conversion Memory Register
ADC10MEM0
12h
ADC10_A Interrupt Enable
ADC10IE
1Ah
ADC10_A Interrupt Flags
ADC10IGH
1Ch
ADC10_A Interrupt Vector Word
ADC10IV
1Eh
Table 6-48. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
76
Detailed Description
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6.10 Input/Output Schematics
6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
From module
1
P1OUT.x
0
From module
1
0
DVIO
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
To module
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Detailed Description
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Table 6-49. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.0/TA0CLK/ACLK
x
0
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
I: 0; O: 1
0
TA0CLK
0
1
ACLK
P1.1/TA0.0
1
P1.1 (I/O)
TA0.CCI0A
TA0.0
P1.2/TA0.1
2
P1.2 (I/O)
TA0.CCI1A
TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
78
Detailed Description
3
4
5
6
7
CONTROL BITS AND SIGNALS
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
TA0.CCI2A
0
1
TA0.2
1
1
P1.3 (I/O)
P1.4 (I/O)
I: 0; O: 1
0
TA0.CCI3A
0
1
TA0.3
1
1
P1.5 (I/O)
I: 0; O: 1
0
TA0.CCI4A
0
1
TA0.4
1
1
P1.6 (I/O)
I: 0; O: 1
0
TA1CLK
0
1
CBOUT comparator B
1
1
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.0
1
1
P1.7 (I/O)
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6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
0
From module
1
P2OUT.x
0
From module
1
0
DVIO
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
To module
DVSS
P2.0/TA1.1
P2.1/TA1.2
P2.2/UCB3SIMO/UCB3SDA
P2.3/UCB3SOMI/UCB3SCL
P2.4/UCB3CLK/UCA3STE
P2.5/UCB3STE/UCA3CLK
P2.6/RTCCLK/DMAE0
P2.7/UB0STE/UCA0CLK
D
P2IE.x
EN
To module
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Detailed Description
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Table 6-50. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
P2.0/TA1.1
P2.1/TA1.2
P2.2/UCB3SIMO/UCB3SDA
x
0
1
2
FUNCTION
P2DIR.x
P2SEL.x
I: 0; O: 1
0
TA1.CCI1A
0
1
TA1.1
1
1
I: 0; O: 1
0
TA1.CCI2A
0
1
TA1.2
1
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
P2.0 (I/O)
P2.1 (I/O)
P2.2 (I/O)
UCB3SIMO/UCB3SDA
P2.3/UCB3SOMI/UCB3SCL
3
P2.3 (I/O)
UCB3SOMI/UCB3SCL
P2.4/UCB3CLK/UCA3STE
4
P2.4 (I/O)
UCB3CLK/UCA3STE
P2.5/UCB3STE/UCA3CLK
5
(2) (3)
P2.5 (I/O)
UCB3STE/UCA3CLK (2)
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
6
7
(4)
(5)
80
(4)
P2.6 (I/O)
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
DMAE0
0
1
RTCCLK
1
1
P2.7 (I/O)
I: 0; O: 1
0
X
1
UCB0STE/UCA0CLK
(1)
(2)
(3)
CONTROL BITS AND
SIGNALS (1)
(2) (5)
X = Don't care
The pin direction is controlled by the USCI module.
UCB3CLK function takes precedence over UCA3STE function. If the pin is required as UCB3CLK input or output, USCI A3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Detailed Description
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6.10.3 Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
0
From module
1
P3OUT.x
0
From module
1
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
EN
To module
D
Table 6-51. Port P3 (P3.0 to P3.4) Pin Functions
PIN NAME (P3.x)
x
P3.0/UCB0SIMO/UCB0SDA
0
FUNCTION
P3.0 (I/O)
UCB0SIMO/UCB0SDA (2)
P3.1/UCB0SOMI/UCB0SCL
1
P3.1 (I/O)
UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
2
(2) (3)
P3.2 (I/O)
UCB0CLK/UCA0STE (2)
P3.3/UCA0TXD/UCA0SIMO
3
(4)
P3.3 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.4/UCA0RXD/UCA0SOMI
4
P3.4 (I/O)
UCA0RXD/UCA0SOMI
(1)
(2)
(3)
(4)
(3)
(2)
CONTROL BITS AND
SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
The pin direction is controlled by the USCI module.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Detailed Description
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6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
from Port Mapping Control
1
P4OUT.x
0
from Port Mapping Control
1
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
D
to Port Mapping Control
Table 6-52. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.x)
P4.0/P4MAP0
x
0
FUNCTION
P4.0 (I/O)
Mapped secondary digital function
P4.1/P4MAP1
1
P4.1 (I/O)
Mapped secondary digital function
P4.2/P4MAP2
2
P4.3/P4MAP3
3
P4.2 (I/O)
Mapped secondary digital function
P4.3 (I/O)
Mapped secondary digital function
P4.4/P4MAP4
4
P4.4 (I/O)
Mapped secondary digital function
P4.5/P4MAP5
5
P4.5 (I/O)
Mapped secondary digital function
P4.6/P4MAP6
6
P4.6 (I/O)
Mapped secondary digital function
P4.7/P4MAP7
7
P4.7 (I/O)
Mapped secondary digital function
(1)
(2)
82
CONTROL BITS AND SIGNALS (1)
P4DIR.x (2)
P4SEL.x
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
≤ 30
P4MAPx
X
1
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
I: 0; O: 1
0
X
X
1
≤ 30
X = Don't care
The direction of some mapped secondary functions are controlled directly by the module. See Table 6-8 for specific direction control
information of mapped secondary functions.
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
to/from Reference
(1)
to ADC10
(1)
INCHx = x
(1)
Pad Logic
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
From module
1
P5.0/(A8/VeREF+)
P5.1/(A9/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
To module
D
(1) not available for MSPF430F5258
MSPF430F5256
MSPF430F5254
MSPF430F5252
Table 6-53. Port P5 (P5.0 and P5.1) Pin Functions
PIN NAME (P5.x)
P5.0/A8/VeREF+
x
0
FUNCTION
P5.0 (I/O) (3)
A8/VeREF+
P5.1/A9/VeREF–
1
(4)
P5.1 (I/O) (3)
A9/VeREF– (5)
(1)
(2)
(3)
(4)
(5)
CONTROL BITS AND SIGNALS (1)
P5DIR.x
P5SEL.x
REFOUT (2)
I: 0; O: 1
0
X
X
1
0
I: 0; O: 1
0
X
X
1
0
X = Don't care
REFOUT resides in the REF module.
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A. Channel A8, when selected with
the INCHx bits, is connected to the VeREF+ pin.
Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A. Channel A9, when selected with the
INCHx bits, is connected to the VeREF- pin.
Detailed Description
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6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.2
P5DIR.2
DVSS
0
DVCC
1
1
0
1
P5OUT.2
0
Module X OUT
1
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5.2/XT2IN
P5IN.2
EN
Module X IN
84
Detailed Description
Bus
Keeper
D
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.3
P5DIR.3
DVSS
0
DVCC
1
1
0
1
P5OUT.3
0
Module X OUT
1
P5SEL.2
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
XT2BYPASS
P5SEL.3
P5IN.3
Bus
Keeper
EN
Module X IN
D
Table 6-54. Port P5 (P5.2, P5.3) Pin Functions
PIN NAME (P5.x)
P5.2/XT2IN
x
2
FUNCTION
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
I: 0; O: 1
0
0
X
XT2OUT crystal mode (3)
X
1
X
0
P5.3 (I/O) (3)
X
1
0
1
P5.2 (I/O)
XT2IN crystal mode
(2)
XT2IN bypass mode (2)
P5.3/XT2OUT
(1)
(2)
(3)
3
CONTROL BITS AND SIGNALS (1)
P5.3 (I/O)
X = Don't care
Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
Detailed Description
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6.10.8 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.4
P5DIR.4
DVSS
0
DVCC
1
1
0
1
P5OUT.4
0
Module X OUT
1
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5.4/XIN
P5IN.4
EN
Module X IN
86
Detailed Description
Bus
Keeper
D
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Pad Logic
to XT1
P5REN.5
P5DIR.5
DVSS
0
DVCC
1
1
0
1
P5OUT.5
0
Module X OUT
1
P5.5/XOUT
P5SEL.4
P5DS.5
0: Low drive
1: High drive
XT1BYPASS
P5SEL.5
P5IN.5
Bus
Keeper
EN
Module X IN
D
Table 6-55. Port P5 (P5.4 and P5.5) Pin Functions
PIN NAME (P5.x)
P5.4/XIN
4
P5.5/XOUT
(1)
(2)
(3)
x
5
FUNCTION
P5.4 (I/O)
CONTROL BITS AND SIGNALS (1)
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
I: 0; O: 1
0
X
X
XIN crystal mode (2)
X
1
X
0
XIN bypass mode (2)
X
1
X
1
P5.5 (I/O)
I: 0; O: 1
0
0
X
XOUT crystal mode (3)
X
1
X
0
P5.5 (I/O) (3)
X
1
0
1
X = Don't care
Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
Detailed Description
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6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Pad Logic
to ADC10
(1)
INCHx = x
(1)
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
P6DIR.x
0
0
From module
1
0
DVCC
1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
EN
To module
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.0/TA2CLK/CB0/(A0)
P6.1/TA2.0/CB1/(A1)
P6.2/TA2.1/CB2/(A2)
P6.3/TA2.2/CB3/(A3)
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
D
P6IE.x
EN
P6IRQ.x
Q
P6IFG.x
P6SEL.x
P6IES.x
88
Detailed Description
Set
Interrupt
Edge
Select
(1) not available for MSPF430F5258
MSPF430F5256
MSPF430F5254
MSPF430F5252
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Table 6-56. Port P6 (P6.0 to P6.7) Pin Functions
PIN NAME (P6.x)
x
P6.0/TA2CLK/SMCLK/C
B0/(A0)
0
P6.1/TA2.0/CB1/(A1)
P6.2/TA2.1/CB2/(A2)
1
2
FUNCTION
P6SEL.x
CBPD
P6.0 (I/O)
I: 0; O: 1
0
0
TA2CLK
0
1
0
SMCLK
1
1
0
A0
X
X
1
CB0 (1)
X
X
1
P6.1 (I/O)
I: 0; O: 1
0
0
TA2.CCI0A
0
1
0
TA2.0
1
1
0
A1
X
X
1
CB1 (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
P6.2 (I/O)
TA2.CCI1A
P6.3/TA2.1/CB3/(A3)
P6.4/CB4/(A4)
3
4
TA2.1
1
1
0
A2
X
X
1
CB2 (1)
X
X
1
P6.3 (I/O)
I: 0; O: 1
0
0
TA2.CCI2A
0
1
0
TA2.2
1
1
0
A3
X
X
1
CB3 (1)
X
X
1
I: 0; O: 1
0
0
X
X
1
P6.4 (I/O)
A4
CB4
P6.5/CB5/(A5)
5
(1)
P6.5 (I/O)
A5
CB5
P6.6/CB6/(A6)
6
(1)
P6.6 (I/O)
A6
CB6
P6.7/CB7/(A7)
(1)
7
CONTROL BITS AND SIGNALS
P6DIR.x
(1)
X
X
1
I: 0; O: 1
0
0
X
X
1
X
X
1
I: 0; O: 1
0
0
X
X
1
X
X
1
I: 0; O: 1
0
0
A7
X
X
1
CB7 (1)
X
X
1
P6.7 (I/O)
Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input buffer
for that pin, regardless of the state of the associated CBPD.x bit.
Detailed Description
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6.10.10 Port P7, P7.0 to P7.5, Input/Output With Schmitt Trigger
Pad Logic
P7REN.x
P7DIR.x
0
From module
1
P7OUT.x
0
DVSS
0
DVIO
1
1
Direction
0: Input
1: Output
1
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
P7.0/UCA2TXD/UCA2SIMO
P7.1/UCA2RXD/UCA2SOMI
P7.2/UCB2CLK/UCA2STE
P7.3/UCB2SIMO/UCB2SDA
P7.4/UCB2SOMI/UCB2SCL
P7.5/UCB2STE/UCA2CLK
EN
D
To module
Table 6-57. Port P7 (P7.0 to P7.5) Pin Functions
PIN NAME (P7.x)
x
P7.0/UCA2TXD/UCA2SIMO
(
1)
0
FUNCTION
P7.0 (I/O)
UCA2TXD/UCA2SIMO (2)
P7.1/UCA2RXD/UCA2SOMI (
1)
1
P7.1 (I/O)
UCA2RXD/UCA2SOMI
P7.2/UCB2CLK/UCA2STE (1)
2
(2)
P7.2 (I/O)
UCB2CLK/UCA2STE (2)
P7.3/UCB2SIMO/UCB2SDA (
1)
3
P7.3 (I/O)
UCB2SIMO/UCB2SDA
P7.4/UCB2SOMI/UCB2SCL (
1)
4
(2) (4)
P7.4 (I/O)
UCB2SOMI/UCB2SCL (2)
P7.5/UCB2STE/UCA2CLK
(1)
5
P7.5 (I/O)
UCB2STE/UCA2CLK (2)
(1)
(2)
(3)
(4)
90
(3)
(4)
CONTROL BITS AND SIGNALS
P7DIR.x
P7SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
The pin direction is controlled by the USCI module.
Setting P7SEL.x bit disables the output driver and the input Schmitt trigger.
UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI_A2 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.10.11 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
6.10.12 Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
PJDS.x
0: Low drive
1: High drive
From JTAG
1
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJIN.x
EN
To JTAG
D
Detailed Description
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Table 6-58. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS
AND SIGNALS (1)
FUNCTION
PJDIR.x
PJ.0/TDO
0
PJ.0 (I/O) (2)
I: 0; O: 1
TDO (3)
PJ.1/TDI/TCLK
1
X
PJ.1 (I/O) (2)
TDI/TCLK (3)
PJ.2/TMS
2
PJ.2 (I/O)
TMS (3)
PJ.3/TCK
3
92
(4)
X
(2)
I: 0; O: 1
(4)
X
PJ.3 (I/O) (2)
TCK (3)
(1)
(2)
(3)
(4)
I: 0; O: 1
I: 0; O: 1
(4)
X
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
Detailed Description
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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
6.11 Device Descriptors
Table 6-59 and Table 6-60 list the complete contents of the device descriptor tag-length-value (TLV)
structure for each device type.
Table 6-59. MSP430F5259, MSP430F5257, MSP430F5255, MSP430F5253 Device Descriptor Table (1)
Info Block
Die Record
ADC10
Calibration
REF Calibration
(1)
VALUE
DESCRIPTION
ADDRESS
SIZE
(BYTES)
F5259
F5257
F5255
F5253
Info length
01A00h
1
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
Device ID
01A04h
1
FF
01
03
05
Device ID
01A05h
1
81
82
82
82
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
ADC10 Calibration Tag
01A14h
1
13h
13h
13h
13h
ADC10 Calibration length
01A15h
1
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
per unit
per unit
per unit
per unit
REF Calibration Tag
01A26h
1
12h
12h
12h
12h
REF Calibration length
01A27h
1
06h
06h
06h
06h
REF 1.5-V Reference Factor
01A28h
2
per unit
per unit
per unit
per unit
REF 2.0-V Reference Factor
01A2Ah
2
per unit
per unit
per unit
per unit
REF 2.5-V Reference Factor
01A2Ch
2
per unit
per unit
per unit
per unit
NA = Not applicable, blank = unused and reads FFh.
Detailed Description
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
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93
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
www.ti.com
Table 6-60. MSP430F5258, MSP430F5256, MSP430F5254, MSP430F5252 Device Descriptor Table (1)
ADDRESS
SIZE
(BYTES)
F5258
F5256
F5254
F5252
Info length
01A00h
1
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
Device ID
01A04h
1
00
02
04
06
Device ID
01A05h
1
82
82
82
82
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
ADC10 Calibration Tag
01A14h
1
13h
13h
13h
13h
ADC10 Calibration length
01A15h
1
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
blank
blank
blank
blank
Info Block
Die Record
ADC10
Calibration
REF Calibration
(1)
94
VALUE
DESCRIPTION
ADC Offset
01A18h
2
blank
blank
blank
blank
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
blank
blank
blank
blank
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
blank
blank
blank
blank
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
blank
blank
blank
blank
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
blank
blank
blank
blank
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
blank
blank
blank
blank
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
blank
blank
blank
blank
12h
REF Calibration Tag
01A26h
1
12h
12h
12h
REF Calibration length
01A27h
1
06h
06h
06h
06h
REF 1.5-V Reference Factor
01A28h
2
per unit
per unit
per unit
per unit
REF 2.0-V Reference Factor
01A2Ah
2
per unit
per unit
per unit
per unit
REF 2.5-V Reference Factor
01A2Ch
2
per unit
per unit
per unit
per unit
NA = Not applicable, blank = unused and reads FFh.
Detailed Description
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
7 Device and Documentation Support
7.1
Device Support
7.1.1
Development Support
7.1.1.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.1.1.2
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
7.1.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
7.1.1.2.2 Recommended Hardware Options
7.1.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards can be ordered individually or as a kit with
the JTAG programmer and debugger included. The following table shows the compatible target boards
and the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
64-pin RCG (QFN)
MSP-FET430U64C
MSP-TS430RGC64C
7.1.1.2.2.2 Experimenter Boards
Experimenter boards and evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
7.1.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
7.1.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
Features
Program up to eight devices at a time. Works with PC or standalone.
Provider
Texas Instruments
7.1.1.2.3 Recommended Software Options
7.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
Copyright © 2013–2015, Texas Instruments Incorporated
95
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
www.ti.com
This device is supported by Code Composer Studio™ IDE (CCS).
7.1.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
7.1.1.2.3.3 SYS/BIOS
SYS/BIOS is an advanced real-time operating system for the MSP430 microcontrollers. It features
preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time
analysis. SYS/BIOS is available free of charge and is provided with full source code.
7.1.1.2.3.4 Command-Line Programmer
MSP430 Flasher is an open-source shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 without the need for an IDE.
7.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend
for reading the complete device name for any family member.
96
Device and Documentation Support
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
Copyright © 2013–2015, Texas Instruments Incorporated
97
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
7.2
www.ti.com
Documentation Support
The following documents describe the MSP430F525x devices. Copies of these documents are available
on the Internet at www.ti.com.
7.3
SLAU208
MSP430x5xx and MSP430x6xx Family User's Guide. Detailed information on the modules
and peripherals available in this device family.
SLAZ532
MSP430F5259 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ533
MSP430F5258 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ534
MSP430F5257 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ535
MSP430F5256 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ536
MSP430F5255 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ537
MSP430F5254 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ538
MSP430F5253 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
SLAZ539
MSP430F5252 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of the device.
Related Links
Table 7-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
98
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F5259
Click here
Click here
Click here
Click here
Click here
MSP430F5258
Click here
Click here
Click here
Click here
Click here
MSP430F5257
Click here
Click here
Click here
Click here
Click here
MSP430F5256
Click here
Click here
Click here
Click here
Click here
MSP430F5255
Click here
Click here
Click here
Click here
Click here
MSP430F5254
Click here
Click here
Click here
Click here
Click here
MSP430F5253
Click here
Click here
Click here
Click here
Click here
MSP430F5252
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2013–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
www.ti.com
7.4
SLAS903B – MAY 2013 – REVISED NOVEMBER 2015
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.5
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254
MSP430F5253 MSP430F5252
Copyright © 2013–2015, Texas Instruments Incorporated
99
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F5252IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5252
MSP430F5252IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5252
MSP430F5252IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5252
MSP430F5252IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5252
MSP430F5253IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5253
MSP430F5253IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5253
MSP430F5253IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5253
MSP430F5253IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5253
MSP430F5254IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5254
MSP430F5254IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5254
MSP430F5254IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5254
MSP430F5254IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5254
MSP430F5255IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5255
MSP430F5255IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5255
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
9-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F5255IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5255
MSP430F5255IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5255
MSP430F5256IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5256
MSP430F5256IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5256
MSP430F5256IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5256
MSP430F5256IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5256
MSP430F5257IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5257
MSP430F5257IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5257
MSP430F5257IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5257
MSP430F5257IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5257
MSP430F5258IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5258
MSP430F5258IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5258
MSP430F5258IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5258
MSP430F5258IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5258
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
9-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F5259IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5259
MSP430F5259IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
F5259
MSP430F5259IZQE
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5259
MSP430F5259IZQER
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
F5259
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430F5252IRGCR
MSP430F5252IRGCT
MSP430F5252IZQER
Package Package Pins
Type Drawing
VQFN
RGC
64
VQFN
RGC
ZQE
BGA MI
CROSTA
R JUNI
OR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5253IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5253IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5253IZQER
BGA MI
CROSTA
R JUNI
OR
MSP430F5254IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5254IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5254IZQER
BGA MI
CROSTA
R JUNI
OR
MSP430F5255IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5255IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5255IZQER
BGA MI
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2015
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CROSTA
R JUNI
OR
MSP430F5256IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5256IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5256IZQER
BGA MI
CROSTA
R JUNI
OR
MSP430F5257IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5257IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5257IZQER
BGA MI
CROSTA
R JUNI
OR
MSP430F5258IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5258IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5258IZQER
BGA MI
CROSTA
R JUNI
OR
MSP430F5259IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
MSP430F5259IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
ZQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
MSP430F5259IZQER
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F5252IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5252IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5252IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5253IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5253IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5253IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5254IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5254IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5254IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5255IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5255IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5255IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5256IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5256IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5256IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5257IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5257IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F5257IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5258IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5258IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5258IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
MSP430F5259IRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
MSP430F5259IRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
MSP430F5259IZQER
BGA MICROSTAR
JUNIOR
ZQE
80
2500
338.1
338.1
20.6
Pack Materials-Page 4
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