ETC2 ML610Q485 8-bit microcontroller Datasheet

FEDL610Q485-01
Issue Date Aug. 25, 2014
ML610Q485
8-bit Microcontroller
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as synchronous serial port, UART, melody driver, and Analog compartor.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash
memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher)
and low-power consumption (typically 5uA at low-speed operation), enabling volume production by the MTP version. For
industrial use, ML610Q485P with the extended operating ambient temperature ranging from -40°C to 85°C are available.
FEATURES
• CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- On-Chip debug function
- Minimum instruction execution time
30.5 μs (@ 32.768 kHz system clock)
2 μs (@ 500 kHz system clock)
0.25 μs (@ 4 MHz system clock)
• Internal memory
- Internal 32KByte flash memory (16K x 16 bits) (including unusable 1K Byte TEST area)
- Internal 2KByte RAM (2048 x 8 bits)
• Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 28 maskable interrupt sources:
Internal source: 16 (SSIO0, Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, Melody 0, PWM0,
TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz, Analog Comparator, RTC)
External source: 12 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
• Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
• Real time clock
− Year, month, day, hour, minute, and second registers
− Adjustable to compensate for crystal variations
− Automatic leap year correction
− Regular interrupts (0.5 sec, 1 sec, 1 minute)
1/25
FEDL610Q485-01
ML610Q485
• Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
• Timers
- 8 bits x 6 channels [also available is 16-bit x 3 configuration (using Timers 0-1, 2-3, or C-D) ]
- Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only)
- The timer C and timer D are controlled by the external trigger.
- The timer C and timer D are used for the one-shot timer mode.
• PWM
- Resolution 16 bits × 1 channel
• Capture
- Time base capture x 2 channels (4096 Hz to 32 Hz)
•
-
Synchronous serial port
Master/slave selectable × 1 channel
LSB first/MSB first selectable
8-bit length/16-bit length selectable
• UART
- TXD/RXD × 1 channel
- Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
- Positive logic/negative logic selectable
- Built-in baud rate generator
• Melody driver
- Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
- Tone length: 63 types
- Tempo: 15 types
- Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• Analog Comparator
- Operating voltage:
VDD=1.8V～3.6V
- Common mode input voltage:
0.2V～VDD－0.2V
- Input offset voltage:
30mV(max)
- Interrupt allow edge selection and sampling selection
- The RC discharged type A/D convertor is configured with the timers C and D.
- The temperature measurement function using built-in temperature sensor.
Temperature measurement range: -20°C to +70°C (P version:-40°C to +85°C)
- The reference voltage can be switched between CMPP0, CMPP1, CMPM0, CMPM1, 1/4VDD, 1/2VDD, temperature
sensor and the internal 0.7V voltage source.
• General-purpose ports
- Input-only port: 4 channels (including secondary functions)
- Output-only port: 6 channels (including secondary functions)
- Input/output port: 16 channels (including secondary functions)
2/25
FEDL610Q485-01
ML610Q485
• Random Number Generator
- Ring oscillator based entropy source
• Reset
- Reset through the RESET_N pin
- Power-on reset generation when powered on
- Reset by the watchdog timer (WDT) overflow
- Reset by the low-speed oscillation stop detection
• Clock
- Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation
clock)
Crystal oscillation (32.768 kHz)
- High-speed clock
Built-in RC oscillation (500 kHz, 4 MHz)
• Power management
- HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)
- STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
- High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
- Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and
stops clock)
- When LSCLK is selected for system clock, the power consumption can be reduced by using halver circuit.
• Shipment
- Chip (Die) -
Low-speed
oscillation
stop detect reset
ML610Q485-ｘｘｘWA
Yes
ML610Q485P-ｘｘｘWA
Yes
- 48 pin plastic TQFP
-
Low-speed
oscillation
stop detect reset
Operating
temperature
Product
availability
ML610Q485-ｘｘｘTB
Yes
-20°C to
+70°C
-
ML610Q485P-ｘｘｘTB
Yes
-40°C to
+85°C
-
Operating
temperature
-20°C to
+70°C
-40°C to
+85°C
xxx: ROM code number (xxx of the blank product is NNN)
Q: MTP version
P: Wide range temperature version (P version)
WA: Chip (Die)
TB: TQFP
• Guaranteed Operation Range
− Operating temperature: -20°C to +70°C (P version: -40°C to +85°C)
− Operating voltage: VDD = 1.25V to 3.6V (2.4V to 3.6V used halver circuit)
3/25
Product
availability
Yes
Yes
FEDL610Q485-01
ML610Q485
BLOCK DIAGRAM
Block Diagram of ML610Q485
CPU (nX-U8/100)
EPSW1−3
GREG
0−15
PSW
Timing
Controller
On-Chip
ICE
ELR1−3
ECSR1−3
LR
DSR/CSR
EA
PC
ALU
SP
Instruction
Decoder
Instruction
Register
Program
Memory
(Flash)
32Kbyte
BUS
Controller
VPP
Data-bus
INT
1
VSS
RESET_N
TEST0
TEST1_N
XT0
XT1
LSCLK*
VDD
VHF
VDDL
VDDX
CH1, CH2
RAM
2K byte
RESET &
TEST
Interrupt
Controller
OSC
INT
1
Power
INT
4
CMPP0*
CMPM0*
CMPP1*
CMPM1*
INT
6
Analog
Comparator
INT
1
SCK0*
SIN0*
SOUT0*
UART
RXD0*
TXD0*
Melody/
Buzzer
MD0*
INT
1
WDT
TBC
Capture
×2
INT
1
SSIO
INT
1
INT
1
PWM
8bit Timer
×6
INT
5
P00 to P03
P20, P21
RTC
GPIO
RNG
* Secondary
function or Tertiary function
Figure 1 ML610Q485 Block Diagram
4/25
PWM0*
P40 to P47
P50 to P57
P60 to P63
FEDL610Q485-01
ML610Q485
CHIP PAD LAYOUT
P62
P61
P60
23
22
21
15
P02
P54
40
14
P01
13
P00
11
39
12
P55
TEST0
P03
RESET_N
16
9
38
10
P56
RESET_N
P50
8
17
XT1
37
VDDX
P57
7
P51
XT0
18
6
36
VHF
P44
5
P52
4
19
CH2
35
CH1
P45
3
P53
VDDL
20
2
34
VSS
P46
1
33
VDD
P47
2.00mm
Chip size: 2.00mm × 2.08mm
PAD count: 40 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 2 ML610Q485 Chip Pin Layout & Dimension
5/25
2.08mm
P40
P41
26
P63
P42
27
24
P43
28
25
P20
VSS
29
P21
31
30
VPP
32
ML610Q485 Chip Pad Layout & Dimension
y
x
FEDL610Q485-01
ML610Q485
PAD COORDINATES
ML610Q485 Pad Coordinates
Table 1 ML610Q485 Pad Coordinates
PAD
No.
Pad
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
VSS
VDDL
CH1
CH2
VHF
XT0
XT1
VDDX
RESET_N
TEST0
TEST1_N
P00
P01
P02
P03
P50
P51
P52
P53
ML610Q485
X (μm)
Y (μm)
-193
-934
-113
-934
-33
-934
47
-934
127
-934
207
-934
287
-934
447
-934
527
-934
607
-934
687
-934
767
-934
879
-934
879
-699
879
-464
879
-229
879
6
879
241
879
476
879
711
PAD
No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
6/25
Pad
Name
P60
P61
P62
P63
P40
P41
P42
P43
VSS
P20
P21
VPP
P47
P46
P45
P44
P57
P56
P55
P54
Chip Center: X=0,Y=0
ML610Q485
X (μm)
Y (μm)
230
934
150
934
70
934
-10
934
-90
934
-170
934
-250
934
-330
934
-410
934
-490
934
-570
934
-650
934
-879
934
-879
699
-879
464
-879
229
-879
-6
-879
-241
-879
-476
-879
-711
FEDL610Q485-01
ML610Q485
PIN LIST
Primary function
Secondary function or Tertiary function
PAD
No.
Pin name
I/O
Function
2,29
1
VSS
VDD
⎯
⎯
6
VHF
⎯
3
VDDL
⎯
9
VDDX
⎯
32
VPP
⎯
4
CH1
⎯
5
CH2
⎯
11
12
10
7
8
TEST0
TEST1_N
RESET_N
XT0
XT1
I/O
I
I
I
O
13
P00/EXI0/
CAP0/TPRUN0
I
14
P01/EXI1/
CAP1/TPRUN1
I
15
P02/EXI2/
RXD0/TPRUN2
I
16
P03/EXI3/
TPRUN3
I
30
31
P20/LED0
P21/LED1
O
O
Negative power supply pin
Positive power supply pin
Power supply pin for halver
circuit (internally generated)
Power supply pin for internal
logic (internally generated)
Power supply pin for low-speed
oscillation
(internally generated)
Power supply pin for Flash ROM
Capacitor connection pin for
halver circuit
Capacitor connection pin for
halver circuit
Test pin
Test pin
Reset input pin
Low-speed clock oscillation pin
Low-speed clock oscillation pin
Input port, External interrupt,
Capture 0 input
Timer C/Timer D external trigger
input
Input port, External interrupt,
Capture 1 input
Timer C/Timer D external trigger
input
Input port, External interrupt,
UART0 received data
Timer C/TimerD external trigger
input
Input port, External interrupt
Timer C/Timer D external trigger
input
Output port
Output port
25
P40
I/O
Input/output port
26
P41
I/O
Input/output port
27
P42
I/O
Input/output port
28
P43
I/O
Input/output port
P44/T02P0CK/
TCDRUN
I/O
P45/T13CK/
TCDRUN
I/O
34
P46/TCCK
I/O
33
P47/TDCK
I/O
17
P50/EXI8
I/O
18
P51/EXI8
I/O
19
P52/EXI8
I/O
36
35
Input/output port,
Timer 0/Timer 2/PWM 0 external
clock input
Timer C/Timer D external trigger
Input
Input/output port,
Timer 1/Timer 3 external clock
input
Timer C/Timer D external trigger
input
Input/output port,
Timer C external clock input
Input/output port,
Timer D external clock input
Input/output
port,
External
interrupt
Input/output
port,
External
interrupt
Input/output
port,
External
interrupt
7/25
Secondary/
Tertiary
⎯
⎯
Pin name
I/O
Function
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Secondary
Secondary
⎯
Tertiary
⎯
LSCLK
OUTCLK
⎯
SIN0
⎯
O
O
⎯
I
⎯
Tertiary
SCK0
I/O
Secondary
Tertiary
Secondary
Tertiary
RXD0
SOUT0
TXD0
PWM0
I
O
O
O
Low-speed clock output
High-speed clock output
⎯
SSIO0 data input
⎯
SSIO0 synchronous
clock input/output
UART data input
SSIO0 data output
UART data output
PWM output
⎯
⎯
⎯
⎯
Tertiary
SIN0
I
⎯
⎯
⎯
Tertiary
SCK0
I/O
SSIO0 synchronous
clock input/output
⎯
Tertiary
⎯
SOUT0
⎯
O
⎯
SSIO0 data output
⎯
⎯
⎯
Secondary
MD0
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SSIO0 data input
⎯
⎯
Melody 0 output
FEDL610Q485-01
ML610Q485
PAD
No.
Primary function
Pin name
I/O
20
P53/EXI8
I/O
40
P54/EXI8/
CMPP0
I/O
39
P55/EXI8/
CMPP1
I/O
38
P56/EXI8/
CMPM0
I/O
37
P57/EXI8/
CMPM1
I/O
21
22
23
24
P60
P61
P62
P63
O
O
O
O
Secondary function or Tertiary function
Function
Input/output
port,
External
interrupt
Input/output
port,
External
interrupt
Analog comparator noninverting
input0 pin
Input/output
port,
External
interrupt
Analog comparator noninverting
Input1 pin
Input/output
port,
External
interrupt
Analog comparator inverting
input0 pin
Input/output
port,
External
interrupt
Analog comparator inverting
Input1 pin
Output port
Output port
Output port
Output port
8/25
Secondary/
Tertiary
Pin name
I/O
Function
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
FEDL610Q485-01
ML610Q485
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Secondary/
Logic
Tertiary
System
RESET_N
I
Reset input pin. When this pin is set to a “L” level, system reset
mode is set and the internal section is initialized. When this pin is
set to a “H” level subsequently, program execution starts. A pull-up
resistor is internally connected.
—
Negative
—
—
—
—
I
Crystal connection pin for low-speed clock.
XT1
O
A 32.768 kHz crystal resonator is connected to this pin. Capacitors
CDL and CGL are connected across this pin and VSS. (see appendix
C measuring circuit 1)
LSCLK
O
Low-speed clock output. Assigned to the secondary function of the
P20 pin.
Secondary
—
OUTCLK
O
High-speed clock output pin. This pin is used as the secondary
function of the P21 pin.
Secondary
—
Primary
Positive
This cannot be used as the general output port when used as the
secondary function.
Primary
Positive
General-purpose output port.
Primary
Positive
Primary
Positive
Primary
Positive
XT0
General-purpose input port
P00 to P03
I
General-purpose input port.
General-purpose output port
P20, P21
P60 to P63
O
O
General-purpose output port.
General-purpose input/output port
P40 to P47
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as
the secondary or tertiary function.
P50 to P57
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as
the secondary function.
9/25
FEDL610Q485-01
ML610Q485
Primary/
Pin name
I/O
Description
Secondary/
Logic
Tertiary
UART
TXD0
O
UART data output pin. This pin is used as the secondary function of
the P43 pin.
RXD0
I
UART data input pin. This pin is used as the secondary function of
the P42 or the primary function of the P02 pin.
Secondary
Primary/
Secondary
Positive
Positive
Synchronous serial (SSIO)
SCK0
I/O Synchronous serial clock input/output pin. This pin is used as the
tertiary function of the P41 or P45 pin.
Tertiary
—
SIN0
I
Synchronous serial data input pin. This pin is used as the tertiary
function of the P40 or P44 pin.
Tertiary
Positive
SOUT0
O
Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
Tertiary
Positive
I
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are
used as the primary functions of the P00 to P03 pins.
Primary
Positive/
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. Assigned to
the primary function of the P50 to P57 pins.
Primary
Capture trigger input pins. The value of the time base counter is
captured in the register synchronously with the interrupt edge
selected by software. These pins are used as the primary functions
of the P00 pin(CAP0) and P01 pin(CAP1).
Primary
External interrupt
EXI0-3
EXI8
I
negative
Positive/
negative
Capture
CAP0
CAP1
I
I
Positive/
negative
Primary
Positive/
negative
Timer
T02P0CK
I
External clock input pin used for both Timer 0 and Timer 2. This pin
is used as the primary function of the P44 pin.
Primary
T13CK
I
External clock input pin used for both Timer 1 and Timer 3. This pin
is used as the primary function of the P45 pin.
Primary
TCCK
I
External clock input pin used for Timer C. This pin is used as the
primary function of the P46 pin.
Primary
TDCK
I
External clock input pin used for Timer D. This pin is used as the
primary function of the P47 pin.
Primary
TCDRUN
I
External trigger input pin used for Timer C or Timer D. This pin is
used as the primary function of the P44 pin or the P45 pin.
Primary
TPRUN0
I
External trigger input pin used for Timer C or Timer D. This pin is
used as the primary function of the P00 pin.
Primary
TPRUN1
I
External trigger input pin used for Timer C or Timer D. This pin is
used as the primary function of the P01 pin.
Primary
TPRUN2
I
External trigger input pin used for Timer C or Timer D. This pin is
used as the primary function of the P02 pin.
Primary
TPRUN3
I
External trigger input pin used for Timer C or Timer D. This pin is
used as the primary function of the P03 pin.
Primary
O
N-channel open drain output pins to drive LED. This pin is used as
the primary function of the P20 and the P21 pins.
Primary
—
—
—
—
—
—
—
—
—
LED drive
LED0, LED1
10/25
Positive
/negative
FEDL610Q485-01
ML610Q485
Primary/
Pin name
I/O
Description
Secondary/
Logic
Tertiary
Melody
MD0
O
PWM
PWM0
O
T02P0CK
I
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P50 pin.
Secondary
Positive/
PWM0 output pin. This pin is used as the tertiary function of the
P43 pin.
PWM0 external clock input pin. This pin is used as the primary
function of the P44 pin.
Tertiary
Positive
Primary
—
negative
Analog Comparator
CMPP0
I
Analog comparator noninverting input0 pin. This pin is used as the
primary function of the P54.
Primary
CMPP1
I
Analog comparator noninverting input1 pin. This pin is used as the
primary function of the P55.
Primary
CMPM0
I
Analog comparator inverting input0 pin. This pin is used as the
primary function of the P56.
Primary
CMPM1
I
Analog comparator inverting input1 pin. This pin is used as the
primary function of the P57.
Primary
—
—
—
—
Test
TEST0
TEST1_N
I/O Pin for testing. A pull-down resistor is internally connected.
I
Pin for testing. A pull-up resistor is internally connected.
—
Positive
—
Negative
Power supply
VSS
— Negative power supply pin.
—
—
VDD
— Positive power supply pin.
— Positive power supply pin (internally generated) for Halver.
Capacitor CHF (see measuring circuit 1) should be connected
between this pin and VSS.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VHF
VDDL
VDDX
CH1
CH2
VPP
— Positive power supply pin (internally generated) for internal logic.
Capacitors CL (see measuring circuit 1) are connected between this
pin and VSS.
— Positive power supply pin (internally generated) for low-speed
oscillation.
Capacitor CX (see measuring circuit 1) should be connected
between this pin and VSS.
— Capacitor connection pin for halver circuit.
Capacitor CH12 (see measuring circuit 1) are connected between
— CH1 and CH2.
— Power supply pin for programming Flash ROM. A pull-down resistor
is internally connected.
11/25
FEDL610Q485-01
ML610Q485
TERMINATION OF UNUSED PINS
Table 2 shows methods of terminating the unused pins.
Table 2 Termination of Unused Pins
Pin
VPP
RESET_N
TEST0
TEST1_N
P00 to P03
P20, P21
P40 to P47
P50 to P57
P60 to P63
Recommended pin handling
Open
Open
Open
Open
VDD or VSS
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
12/25
FEDL610Q485-01
ML610Q485
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS= 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta=25°C
-0.3 to +4.6
V
Power supply voltage 2
VPP
Ta=25°C
-0.3 to +9.5
V
Power supply voltage 3
VDDL
Ta=25°C
-0.3 to +3.6
V
Input voltage
VIN
Ta=25°C
-0.3 to VDD+0.3
V
Output voltage
VOUT
Ta=25°C
-0.3 to VDD+0.3
V
Output current 1
IOUT1
Port 4 to 6, Ta=25°C
-12 to +11
mA
Output current 2
IOUT2
Port 2, Ta=25°C
-12 to +20
mA
Power dissipation
PD
Ta=25°C
0.9
W
Storage temperature
TSTG
―
-55 to +150
°C
Recommended Operating conditions
(VSS= 0V)
Parameter
Symbol
Operating temperature
TOP
Operating voltage
Operating frequency
(CPU)
Low-speed crystal
oscillation frequency
Low-speed crystal
oscillation
external capacitance
VDDL pin external
capacitance
VDDX pin external
capacitance
VHF pin external
capacitance
Pin-to-pin (CH1 to CH2)
external capacitance
VDD
Condition
Range
without P version
-20 to +70
P version
-40 to +85
fOP=30k to 625kHz
1.25 to 3.6
Unit
°C
V
fOP=30k to 5MHz
1.8 to 3.6
fOP=30k to 36kHz, Used Halver
VDD=1.25 to 3.6V
VDD=1.8 to 3.6V
VDD=2.4 to 3.6V, Used Halver
2.4 to 3.6
30k to 625k
30k to 5.0M
30k to 36k
fXTL
―
32.768k
CDL
―
3 to 18
CGL
―
3 to 18
CL
―
2.2±30%
μF
CX
―
0.1±30%
μF
CHF
―
0.1±30%
μF
CH12
―
0.1±30%
μF
fOP
13/25
Hz
Hz
pF
FEDL610Q485-01
ML610Q485
Operating conditions of FlashROM
(VSS= 0V)
Parameter
Operating temperature
Operating voltage
Rewrite count
Data retention
Symbol
TOP
VDD
VDDL
VPP
CEP
YDR
Condition
At write/erase
At write/erase
At write/erase*1
At write/erase
―
―
Range
0 to +40
2.75 to 3.6
2.5 to 2.75
7.7 to 8.3
80
10
Unit
°C
V
cycles
years
*1
: When writing to and erasing on the flash Memory, the voltage in the specified range needs to be supplied to the VDDL pin.
The VPP pin has an internal pull-down resistor.
Operation conditions of Comparator
(VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Measurement
Parameter
Symbol
Condition
Unit
circuit
Max.
Min.
Typ.
Common-mode
―
0.2
―
VDD-0.2
V
CMVIN
input voltage
Analog Comparator
Ta=25°C
-30
―
30
mV
VCMPOF
Input offset voltage
Ta=25°C,
Analog Comparator
TCMP
―
―
1
μs
Overdrive=100mV
Response time
Analog Comparator
―
―
―
5
μs
TCMPW
Wakeup time
Analog Comparator
Ta=25°C
―
33
45
μA
ICMP
supply current
Temperature sensor
Ta=25°C
―
1355
―
mV
VTMP
output voltage through x2
1
Temperature sensor
Ta = -40 to +25°C
―
-3.585
―
mV/°C
ΔVTMP
output voltage through x2
Ta = 25 to 85°C
―
-3.718
―
(Temperature property)
0.7V voltage source
Ta=25°C
1.386
1.400
1.414
V
VREF
output voltage through x2
0.7V voltage source
―
0
―
%/°C
―
ΔVREF
temperature deviation
0.7V voltage source
Ta=25°C
―
20
40
μA
IREF
supply current
VDD/2
VDD/2
1/2 VDD voltage source
VDD2
―
VDD/2
V
x 0.96
x 1.04
VDD/4
VDD/4
1/4 VDD voltage source
VDD4
―
VDD/4
V
x 0.96
x 1.04
14/25
FEDL610Q485-01
ML610Q485
DC Characteristics (1/4)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Symbol
Condition
Ta=25°C
VDD=1.25
to 3.6V
500kHz/4MHz RC
oscillation frequency
*
fRC
Ta=25°C
VDD=1.8 to
3.6V
Low-speed crystal
oscillation start time*1
500kHz/4MHz RC
oscillation start time
Reset pulse width
Reset noise elimination
pulse width
Power-on reset generated
power rise time
2
*
2
Min.
Typ.
-10%
Typ.
-25%
Typ.
-10%
Typ.
-25%
Rating
Typ.
500
500
4.0
4.0
Max.
Typ.
+10%
Typ.
+25%
Typ.
+10%
Typ.
+25%
Unit
kHz
kHz
MHz
MHz
TXTL
―
―
0.6
2
s
TRC
―
―
―
3
μs
PRST
―
200
―
―
PNRST
―
―
―
0.3
TPOR
―
―
―
10
1
μs
ms
* : 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF).
2
* : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
VIL1
RESET_N
VIL1
PRST
External reset sequence
0.9xVDD
VDD
0.1xVDD
TPOR
Power on reset sequence
15/25
Measure
ment
circuit
1
FEDL610Q485-01
ML610Q485
DC Characteristics (2/4)
(VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Symbol
Supply current
1
IDD1
Supply current
2
IDD2
Supply current
3-1
Supply current
3-2
IDD3-1
IDD3-2
Supply current
4-1
IDD4-1
Supply current
4-2
IDD4-2
Condition
CPU: In STOP state.
Low-speed/High-speed oscillation:
stopped.
CPU: In HALT state.
2 3
(LTBC, WDT: Operating)* * .
High-speed 500kHz/4MHz
oscillation: Stopped.
Used halver
CPU: In 32.768kHz operating
1 2
state.* *
High-speed 500kHz/4MHz
oscillation: Stopped,
Not used halver
CPU: In 32.768kHz operating
1 2
state.* *
High-speed 500kHz/4MHz
oscillation: Stopped,
Used halver
CPU: In 500kHz RC operating
state.
Not used halver
Ta=25°C
CPU: In 4MHz RC operating state.
Not used halver
Ta=25°C
1
*
4
Ta=25°C
Min.
Rating
Typ.
Max.
―
0.32
0.8
―
―
8
―
0.35
0.7
―
―
4
―
4.5
8
―
―
15
―
2.5
4
Unit
μA
μA
*
4
Ta=25°C
μA
*
4
Ta=25°C
1
μA
*
4
Ta=25°C
*
*
4
4
―
―
7.5
―
75
100
―
―
120
―
―
600
―
750
800
μA
μA
* : When the CPU operating rate is 100% (no HALT state).
2
* : 32.768KHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF)
3
* : Significant bits of BLKCON0 to BLKCON3 registers are all “1”.
4
* : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
16/25
Measur
ement
circuit
FEDL610Q485-01
ML610Q485
DC Characteristics (3/4)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Output voltage 1
(P20, P21
(N-channel open
drain output
mode is not
selected))
(P40 to P47)
(P50 to P57)
(P60 to P63)
Output voltage 2
(P20, P21
(N-channel open
drain output
mode is
selected))
Output leakage
(P20, P21)
(P40 to P47)
(P50 to P57)
(P60 to P63)
Input current 1
(RESET_N,
TEST1_N)
Input current 2
(TEST0)
Symbol
Rating
Min.
Typ.
Max.
VDD
-0.5
VDD
-0.3
―
―
―
―
IOL1=+0.5mA, VDD=1.8 to 3.6V
―
―
0.5
IOL1=+0.1mA, VDD=1.25 to 3.6V
―
―
0.3
VOL2
IOL2=+5mA, VDD=1.8 to 3.6V
―
―
0.5
IOOH
VOH=VDD (in high-impedance state)
―
―
1
IOH1=-0.5mA, VDD=1.8 to 3.6V
VOH1
IOH1=-0.03mA, VDD=1.25 to 3.6V
VOL1
IOOL
VOL=VSS (in high-impedance state)
-1
―
―
IIH1
VIH1=VDD
―
―
1
IIL1
VIL1=VSS
-600
-300
-2
IIH2
IIL2
2
-1
300
―
600
―
2
30
200
0.01
30
200
-200
-30
-2
-200
-30
-0.01
IIH3Z
VIH2=VDD
VIL2=VSS
VIH3=VDD, VDD=1.8 to 3.6V
(when pulled-down)
VIH3=VDD, VDD=1.25 to 3.6V
(when pulled-down)
VIL3=VSS, VDD=1.8 to 3.6V
(when pulled-up)
VIL3=VSS, VDD=1.25 to 3.6V
(when pulled-up)
VIH3=VDD (in high-impedance state)
―
―
1
IIL3Z
VIL3=VSS (in high-impedance state)
-1
―
―
IIH3
Input current 3
(P00 to P03)
(P40 to P47)
(P50 to P57)
Condition
IIL3
17/25
Unit
Measur
ement
circuit
V
2
μA
3
μA
4
FEDL610Q485-01
ML610Q485
DC Characteristics (4/4)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Input voltage 1
(RESET_N)
(TEST1_N)
(TEST0)
(P00 to P03)
(P40 to P47)
(P50 to P57)
Input pin
capacitance
(P00 to P03)
(P40 to P47)
(P50 to P57)
Symbol
Condition
VIH1
―
Rating
Min.
Typ.
Max.
0.7
×VDD
―
VDD
VIL1
VDD=1.25 to 3.6V
0
―
0.2
×VDD
CIN
f=10kHz
Vrms=50mV
Ta=25°C
―
―
5
18/25
Unit
Measur
ement
circuit
V
5
pF
―
FEDL610Q485-01
ML610Q485
Measuring Circuits
Measuring Circuit 1
CGL
XT0
CDL
XT1
32.768kHz
crystal
resonator
CH2
CH12
CH1
VDD
VHF
VDDL
VDDX
VSS
A
CV
CHF
CL
CX
CV
: 2.2μF
: 2.2uF
CL
Cx
: 0.1μF
CHF
: 0.1μF
: 0.1μF
CH12
32.768kHz crystal resonator
: DT-26 (Load capacitance 6pF)
(Made by KDS:DAISHINKU CORP.)
CGL, CDL
: 6pF
Measuring Circuit 2
(Note 2)
VIH
Output pin
VIL
Input pin
(Note 1)
VDD
VDDL VDDX
V
VSS
(Note 1): Input logic circuit to determine the specified measuring conditions.
(Note 2) Repeats for the specified output pin
19/25
FEDL610Q485-01
ML610Q485
Measuring Circuit 3
(Note 2)
VIH
Output pin
VIL
Input pin
(Note 1)
VDD
VDDL VDDX
A
VSS
(Note 1): Input logic circuit to determine the specified measuring conditions.
(Note 2) Repeats for the specified output pin
Measuring Circuit 4
(Note 3)
Output pin
Input pin
A
VDD
VDDL VDDX
VSS
(Note 3) Repeats for the specified input pin
20/25
FEDL610Q485-01
ML610Q485
Measuring Circuit 5
VIH
VDD
VDDL VDDX
Waveform observation
Output pin
VIL
Input pin
(Note 1)
VSS
(Note 1): Input logic circuit to determine the specified measuring conditions.
21/25
FEDL610Q485-01
ML610Q485
AC Characteristics (External Interrupt)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Symbol
Rating
Condition
Min.
Typ.
Max.
76.8
―
106.8
Unit
Interrupt: Enabled (MIE = 1),
External interrupt disable
period
TNUL
CPU: NOP operation
μs
System clock: 32.768kHz
P00 to P03
(Rising-edge interrupt)
tNUL
P00 to P03
(Falling-edge interrupt)
tNUL
P00–P03
(Both-edge interrupt)
tNUL
AC Characteristics (UART)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Parameter
Symbol
Condition
Transmit baud rate
tTBRT
―
Receive baud rate
tRBRT
―
1
Rating
Min.
Typ.
Max.
―
BRT*1
―
BRT*1
-3%
1
BRT*
BRT*1
+3%
Unit
s
s
* : Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and
the UART mode register 0 (UA0MOD0).
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
22/25
FEDL610Q485-01
ML610Q485
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
When RC oscillation is 500kHz
10
⎯
⎯
*2 (VDD = 1.25 to 3.6V)
SCLK0 input cycle
μs
tSCYC
(slave mode)
When RC oscillation is 4MHz
2
⎯
⎯
3
* (VDD = 1.8 to 3.6V)
SCLK0 output cycle
tSCYC
⎯
⎯
SCLK0*1
⎯
s
(master mode)
When RC oscillation is 500kHz
4
⎯
⎯
*2 (VDD = 1.25 to 3.6V)
SCLK0 input pulse width
tSW
μs
(slave mode)
When RC oscillation is 4MHz
04
⎯
⎯
*3 (VDD = 1.8 to 3.6V)
1
1
1
SCLK0*
SCLK0*
SCLK0*
SCLK0 output pulse width
s
⎯
tSW
(master mode)
×0.4
×0.5
×0.6
When RC oscillation is 500kHz
*2 (VDD = 1.25 to 3.6V)
⎯
⎯
500
output load 10pF
SOUT0 output delay time
ns
tSD
(slave mode)
When RC oscillation is 4MHz
3
* (VDD = 1.8 to 3.6V)
⎯
⎯
240
output load 10pF
When RC oscillation is 500kHz
*2 (VDD = 1.25 to 3.6V)
⎯
⎯
500
output
load
10pF
SOUT0 output delay time
tSD
ns
(master mode)
When RC oscillation is 4MHz
*3 (VDD = 1.8 to 3.6V)
⎯
⎯
240
output load 10pF
SIN0 input setup time
tSS
⎯
80
⎯
⎯
ns
(slave mode)
When RC oscillation is 500kHz
500
⎯
⎯
*2 (VDD = 1.25 to 3.6V)
SIN0 input setup time
tSS
ns
(master mode)
When RC oscillation is 4MHz
240
⎯
⎯
3
* (VDD = 1.8 to 3.6V)
When RC oscillation is 500kHz
300
⎯
⎯
*2 (VDD = 1.25 to 3.6V)
SIN0 input hold time
ns
tSH
When RC oscillation is 4MHz
80
⎯
⎯
*3 (VDD = 1.8 to 3.6V)
*1: Clock period selected with S0CK3–0 of the serial port n mode register (SIO0MOD1)
2
* : When 500kHz RC oscillation is selected by OSCM3 of the frequency control register (FCON0)
3
* : When 4MHz RC oscillation is selected by OSCM3 of the frequency control register (FCON0)
tSW
tSCYC
tSW
SCLK0*
tSD
tSD
SOUT0*
tSS
tSH
SIN0*
*: Indicates the secondary function of the port
23/25
FEDL610Q485-01
ML610Q485
REVISION
HISTORY
Document No.
FEDL610Q485-01
Date
Aug.25,2014
Page
Previous Current
Edition
Edition
–
–
Description
Final edition 1
24/25
FEDL610Q485-01
ML610Q485
NOTES
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25/25