ETC2 ML9472 Static,1/2duty 60 output lcd driver Datasheet

Semiconductor
ML9472
FEDL9472-02
Issue Date: Feb. 1, 2008
Static,1/2Duty 60 Output LCD Driver
GENERAL DESCRIPTION
The ML9472 is a LCD driver which can directly drive up to 60 segments in the static display mode and up to 120
segments in the 1/2 duty dynamic display mode.
FEATURES
• Operating range
Supply voltage
: 3.0 to 5.5 V
Operating temperature range
: 40 to  105C
• Segment output
Static display mode
: Up to 60 segments can be displayed.
1/2 duty
: Up to 120 segments can be displayed.
• Simple interface with microcomputer
• Built-in common signal generator
• One-to-one correspondence between input data and output data
When input data is at “H” level
: Display goes on.
When input data is at “L” level
: Display goes off.
• Test pin for all-on (SEG_TEST) and all-off (BLANK)
• Can be cascade-connected
• Can be synchronized with the external common signal
• Applicable as an output expander
• Package
80-pin plastic TQFP (TQFP80-P-1212-0.50-K) (Product name: ML9472TB)
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ML9472
BLOCK DIAGRAM
SEG1
SEG60
SEG_TEST
60-Dot Segment Driver
BLANK
60-Ch Data Selector
60
LOAD
60-Bit Latch (A)
60-Bit Latch (B)
60
60
60-Stage Shift Register (A)
60-Stage Shift Register (B)
CLOCK
DATA_IN
60
DATA_OUT2
DATA_OUT1
D/S
EXT/INT
VLC1
1/4 or 1/8
OSC_OUT
OSC_OUT
OSC
OSC_IN
VLC2
1/2
Common
Driver
COM_A
COM_B
COM_OUT
SYNC
SYNC Circuit
VDD
GND
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PIN CONFIGURATION (TOP VIEW)
80-Pin Plastic TQFP
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PIN DESCRIPTION
Symbol
Type
Description
OSC_IN
OSC_OUT
OSC_OUT
I
O
O
Pins for oscillation. The oscillator circuit is configured by externally connecting two
resistors and a capacitor. Make the wiring length as short as possible, because the
resistor connected to the OSC_IN pin has a higher value and the circuit is susceptible to
external noise.
DATA_IN
I
CLOCK
I
LOAD
I
BLANK
l
SEG_TEST
l
D/S
l
EXT/INT
I
SYNC
I/O
DATA_OUT1
O
DATA_OUT2
O
COM_OUT
O
Serial data input pin. The display goes on when input data is at a “H” level, and it goes
off when input data is at a “L” level.
Shift clock input pin. Data from the DATA pin is transferred in synchronization with the
rising edge of the shift clock.
Load signal input pin. Serially input data is transferred to the 60-bit latch at a “H” level of
this load signal, then held at a “L” level.
Input pin that turns off all segments. The entire display goes off when a “L” level is
applied to this pin. The display returns to the previous state when a “H” level is applied.
When SEG_TEST pin is at a “H” level, the input on this pin is disabled.
Input pin is used to test the segment outputs (SEG1 to SEG60). All displays are turned
on when “H” is applied to this pin. The display returns to the previous state when a “L”
level is applied. When this pin is at a “H” level, the input on the BLANK pin is disabled.
When “H” is applied to this pin, the ML9472 operates in the 1/2 duty dynamic display
mode. When this pin is set at a “L” level, the ML9472 operates in the static display
mode.
When the external common signal is used, fix this pin at a “H” level and input the
external common signal from the OSC_IN pin. The input common signal is used as the
internal common signal and is output from the COM_OUT pin through the buffer. When
the built-in common signal generator is used, fix this pin at a “L” level. When the
ML9472 is used as an output expander, fix this pin at a “H” level and the OSC_IN pin at
a “L” level. The output logic can be reversed with respect to the input data by setting
OSC_IN to a “H” level.
This pin is an input/output pin which is used when two or more ML9472s are connected
in series (cascade connection) in the 1/2 duty dynamic display mode. All of the involved
ML9472’s SYNC pins should be connected by the common line and they should be
pulled up with a common resistor, which makes a phase level of all involved ML9472’s
COM_A and COM_B pins equal. When a single ML9472 is used in the dynamic display
mode, SYNC should be pulled up with a resistor.
Connect this pin to GND if any of the following conditions is true:
- The ML9472 is operated in the static display mode.
- The ML9472 is used as an output expander.
th
The 60 stage data of the shift register is output from this pin.
When two or more ML9472s are connected in series (cascade connection) in the static
display mode, this pin should be connected to the next ML9472’s DATA_IN Pin.
th
The 120 stage data of the shift register is output from this pin.
When two or more ML9472s are connected in series (cascade connection) in the 1/2
duty dynamic display mode, this pin should be connected to the next ML9472’s
DATA_IN pin.
When tow or more ML9472s are connected in series (cascade connection), this pin
should be connected with all of the slave ML9472’s OSC_IN pins.
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Symbol
ML9472
Type
COM_A
COM_B
O
O
SEG1 to
SEG60
O
VLC1, VLC2
—
VDD, GND
—
Description
LCD driving common signals is output from these pins. These pins should be
connected to the COMMON side of the LCD panel.
- In the static display mode
A pulse in phase with the COM_OUT is output from both COM_A and COM_B. In
this case, the high level is VDD, and the low level is VLC2.
- In the 1/2 duty dynamic display mode
The COM_A and COM_B output signals are alternately changed within each
COM_OUT output cycle, resulting in alternate repetition of select and non-select
modes.
Display output pins for LCD. Theses pins are connected to the SEGMENT side of the
LCD panel. For the correspondence between the output of these pins and input data,
see Section, “Data Structure”.
Bias pins for LCD driver. Through these pins, bias voltages for the LCD are externally
supplied.
In the static display mode, VLC1 should be open.
VLC1 = VDD /2
VDD > VLC1 > VLC2 = GND
Supply voltage pin and ground pin.
Note: Built-in schmitt circuit is used for all input pins.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Power Dissipation
Output Current
Symbol
Condition
Rating
Unit
VDD
VI
TSTG
PD
IO1
IO2
Ta = 25C
Ta = 25C
—
Ta  105C
Driver Outputs
Logic Outputs
0.3 to 6.5
0.3 to VDD0.3
55 to 150
650
2.0 to 2.0
2.0 to 2.0
V
V
C
mW
mA
mA
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Range
Unit
Supply Voltage
VDD
—
3 to 5.5
V
LCD Driving Voltage
VLCD
VDD - VLC2
3 to VDD
V
CLOCK Frequency
fCP
—
0.3 to 4
MHz
Operating Temperature
Ta
—
40 to 105
C
OSCILLATOR CIRCUIT
Parameter
Symbol
Applicable pin
Condition
Min.
Typ.
Max.
Unit
Oscillator Resistance
R0
OSC_OUT
56
100
220
k
Oscillator Capacitance
C0
OSC_OUT
0.001
—
0.047
F
Current Limiting Resistance
R1
560
1000
2220
k
Common Signal Frequency
fCOM
OSC_IN
COM_A
COM_B
—
Film
capacitor
R1  10R0
—
25
—
150
Hz
Note: See Section, “Reference Data”, for the resistor and capacitor values in the table.
Example of an oscillator circuit:
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Symbol
“H” Input Voltage
VIH
“L” Input Voltage
VIL
“H” Input Current
IIH
“L” Input Current
IIL
VOH1
“H” Output Voltage
VOH2
VOL1
“L” Output Voltage
VOL2
VOL3
COMMON
Output Voltage
Segment
Voltage
Output
Current
Output
DATA_OUT1
DATA_OUT2
COM_OUT
OSC_OUT
OSC_OUT
DATA_OUT1
DATA_OUT2
COM_OUT
OSC_OUT
OSC_OUT
SYNC
Leakage
Common
Output
Impedance
Static
Supply
Current
Supply
IO = 100 A, VDD = 5.0 V
4.5
—
V
IO = 200 A, VDD = 5.0 V
4.5
—
V
IO = 100 A, VDD = 5.0 V
—
0.5
V
IO = 200 A, VDD = 5.0V
—
0.5
V
IO = 250 A, VDD = 5.0 V
—
0.8
V
VOCH
COM_A
COM_B
VDD = 5.0 V, VLC1 = 2.5 V, VLC2 = 0 V,
IO = 150 A
4.8
—
V
VOCM
COM_A
COM_B
VDD = 5.0 V, VLC1 = 2.5 V, VLC2 = 0 V,
IO = 150 A
2.3
2.7
V
VOCL
COM_A
COM_B
VDD = 5.0 V, VLC1 = 2.5 V, VLC2 = 0 V,
IO = 150 A
—
0.2
V
IO = 30 A
4.8
—
V
IO = 30 A
—
0.2
V
VDD = 5.0 V and VO = 5 V when
internal Tr is off
—
5
A
VOSH
SEG1 - SEG60
VOSL
Segment
Output
Impedance
Dynamic
Current
(VDD = 3.0 to 5.5 V, Ta = 40 to 105C, unless otherwise specified)
Applicable pin
Condition
Min.
Max.
Unit
SEG_TEST,
—
0.8 VDD
VDD
V
BLANK, LOAD,
—
GND
0.2 VDD
V
DATA_IN,
CLOCK, D/S, VI = VDD
—
1
A
EXT/INT,
VI = 0 V
1
—
A
OSC_IN
VDD = 5.0 V,
VLC1 = 2.5 V
VLC2 =0 V
ILO
SYNC
RSEG
SEG1 – SEG60
VDD = 5.0 V, VLC1 = 2.5V, VLC2 = 0V
—
10
k
RCOM
COM_A
COM_B
VDD = 5.0 V, VLC1 = 2.5V, VLC2 = 0V
—
1.5
k
IDD1
VDD
Fix all input levels at either VDD or
GND
—
100
A
IDD2
VDD
VDD = 5.0V, No load.
R0 = 100 k,
C0 = 0.01 F, R1 = 1 M
—
0.5
mA
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AC Characteristics
(VDD = 3 to 5.5 V, Ta = 40 to 105C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Clock “H” Time
Clock “L” Time
Data Set-up Time
Data Hold Time
Load “H” Time
Clock-to-load Time
Load-to-Clock Time
tWHC
tWLC
tDS
tDH
tWHL
tCL
tLC
70
70
50
50
100
100
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
“H”, “L” Propagation Delay
Time
tPHL
tPLH
—
—
0.14
s
—
0.2
—
—
50
—
ns
s
—
—
5
kHz
Clock Rise time, Fall time
SYNC Pulse “L” Time
tr1, tf1
tS
—
—
—
—
—
—
—
Load capacitance of
DATA_OUT1, DATA_OUT2:
15 pF
—
—
OSC_IN Input Frequency
fOSC
—
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POWER-ON/OFF TIMING
[Voltage]
VDD Terminal Voltage
VLC1 Terminal Voltage
[Time]
t
t0
t
* Please start up VLC1 after turning on the VDD power supply. Or, please start up at the same time.
INITIAL SIGNAL TIMING
VDD
BLANK
SEG_TEST
Low Level
* After VDD is applied, BLANK and SEG_TEST should be applied to ‘L’ level to make all SEGMENTS off
until first group of display data is latched.
FUNCTIONAL DESCRIPTION
Operation Description
The ML9472 consists of a 120-stage shift register, 120-bit data latch, and 60 pairs of LCD drivers. The display
data is input from the DATA_IN pin to the 120-stage shift register at the rising edge of the CLOCK pulse and it is
shifted to the 120-bit data latch when the LOAD signal is set at “H” level, then it is directly output from the 60
pairs of LCD drivers to the LCD panel. Input the display data in the order of SEG60, SEG59, SEG58, …, SEG2,
SEG1.
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COM_A, COM_B
In the select mode, a signal in phase with the COM_OUT signal is output at “H” (VDD) and “L” (VLC2).
In the non-select mode a voltage is output at “M” (VLC1). In the select mode of COM_A (non-select mode of
COM_B), signals that correspond to the 1st-to 60th-bit data of the data latch are output to the segment outputs.
In the select mode of COM_B (non-select mode of COM_A), signals that correspond to the 61st- to 120th-bit data
of the data latch are output to the segment outputs.
SEGn Truth Table
Mode
Display data
in LatchA
Display data
in LatchB
COMA
COMB
SEGn
—
“H”
“H”
0
—
—
—
“L”
“H”
“L”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“L”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“H”
“L”
“M”
“M”
“H”
“L”
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
Static
0
1
1
1
0
0
1
0
0
1/2 duty
Dynamic
*Note: “H” = VDD; “M” = VLC1; “L” = VLC2.
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SEG1-SEG60
LCD segmnet driving signals are outputfrom these pins and they should be connected to the segment side of the
LCD panel.
“H” level: VDD, “L” level: VLC2
In the static display mode, the nth bit data of the data latch (A) corresponds to the SEGn. The data of the data latch
(B) is invalid.
A signal out of phase with the COM_OUT signal is output to the segment outputs when the display is turned on,
while a signal in phase with it is output when the display is turned off.
In the 1/2 duty dynamic mode, the output of the SEGn corresponds to the nth bit data of the data latch (A) when
COM_A is in select mode and corresponds to the nth bit data of the data latch (B) when COM_B is in select mode.
When the display is turned on, a signal out of phase with the common signal corresponding to the data is output,
while a signal in phase with the common signal is output when the display is turned off.
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APPLICATION CIRCUITS
1) Single ML9472 operation in the static display mode
2) Single ML9472 operation in the 1/2 duty dynamic display mode
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3) Cascade connections for ML9472s in the static display mode
4) Cascade connections for ML9472s in the 1/2 duty dynamic display mode
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5) Output-expander
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REFERENCE CHARACTERISTICS
·Fcom — R0,C0
Fcom--R0,C0
1000
0.001uF
0.0022uF
0.0047uF
100
0.01uF
0.022uF
Fcom(Hz)
0.047uF
spec_min(25Hz)
10
spec_max(150Hz)
1
56
68
82
100
120
150
180
R0(K)
220
Condition:D/S=“L”
EXT/INT=“L”
VDD=5V
25C
R1=10R0
Theoretical Value:
Fcom=1/8Fosc
·Fosc — VDD,C0
Fosc--VDD,C0
395
393
Fosc 391
(Hz)
389
0.01uF
387
385
2
3
4
5
6
Condition：
25C
C0=0.01uF
R1=10R0
R1=1M
VDD(V)
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PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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REVISION HISTORY
Document No.
FEDL9472-01
FEDL9472-02
Date
July. 2, 2007
Feb. 1,2008
Page
Previous
Current
Edition
Edition
Description
–
–
Final edition 1
2
2
BLOCK DIAGRAM
6
6
Power Dissipation 794mW→650mW
7
7
Segment Output Impedance Condition
Common Output Impedance Condition
9
9
POWER-ON/OFF TIMING
10
10
SEGn Truth Table
14
14
Output-expander
–
15
Reference Characteristics
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