AD ADP5301ACBZ-2-R7 50 ma/500 ma, high efficiency,ultralow power step-down regulator Datasheet

FEATURES
TYPICAL APPLICATION CIRCUIT
Input start-up voltage range: 2.15 V to 6.50 V
Operates down to 2.00 V voltage
Ultralow 180 nA quiescent current with no load
Selectable output voltage of 1.2 V to 3.6 V or 0.8 V to 5.0 V
±1.5% output accuracy over full temperature range in
PWM mode
Selectable hysteresis mode or PWM operation mode
Output current
Up to 50 mA in hysteresis mode
Up to 500 mA in PWM mode
VOUTOK flag monitors the output voltage
100% duty cycle operation mode
2 MHz switching frequency with optional synchronization
input from 1.2 MHz to 2.5 MHz
QOD option
UVLO, OCP, and TSD protection
9-ball, 1.65 mm × 1.87 mm WLCSP
−40°C to +125°C junction temperature
VIN = 3.6V
2.2µH
VOUT
SW
PVIN
10µF
ADP5301
10µF
(9-BALL WLCSP)
ON
EN
OFF
PWM
HYS
PGND
SYNC/
MODE
13169-001
Data Sheet
50 mA/500 mA, High Efficiency,
Ultralow Power Step-Down Regulator
ADP5301
FB
VOUTOK
VID
RVID
AGND
VID0: 1.2V
VID1: 1.5V
VID2: 1.8V
VID3: 2.0V
VID4: 2.1V
VID5: 2.2V
VID6: 2.3V
VID7: 2.4V
VID8: 2.5V
VID9: 2.6V
VID10: 2.7V
VID11: 2.8V
VID12: 2.9V
VID13: 3.0V
VID14: 3.3V
VID15: 3.6V
Figure 1.
APPLICATIONS
Energy (gas and water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supplies
GENERAL DESCRIPTION
The ADP5301 is a high efficiency, ultralow quiescent current
step-down regulator that draws only a 180 nA quiescent current
to regulate the output at no load.
The ADP5301 runs from an input startup voltage range of 2.15 V
to 6.50 V, allowing the use of multiple alkaline/NiMH, Li-Ion
cells, or other power sources. The output voltage is selectable from
0.8 V to 5.0 V by an external VID resistor and factory fuse. The
total solution requires only four tiny external components.
The ADP5301 can operate between hysteresis mode and PWM
mode via the SYNC/MODE pin. The regulator in hysteresis mode
achieves excellent efficiency at a power of less than 1 mW and
provides up to 50 mA of output current. The regulator in PWM
mode produces a lower output ripple and supplies up to 500 mA
of output current. The flexible configuration capability during
operation of the device enables very efficient power management
to meet both the longest battery life and low system noise
requirements.
Rev. A
The ADP5301 contains a VOUTOK flag, which monitors the
output voltage and runs at a 2 MHz switching frequency in
PWM mode. SYNC/MODE can synchronize to an external
clock from 1.2 MHz to 2.5 MHz.
Other key features in the ADP5301 include separate enabling,
quick output discharge (QOD), and safety features such as
overcurrent protection (OCP), thermal shutdown (TSD), and
input undervoltage lockout (UVLO).
The ADP5301 is available in a 9-ball, 1.65 mm × 1.87 mm
WLCSP rated for a −40°C to +125°C junction temperature range.
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ADP5301
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Short-Circuit Protection............................................................ 15
Applications ....................................................................................... 1
Soft Start ...................................................................................... 15
Typical Application Circuit ............................................................. 1
Startup with a Precharged Output ........................................... 15
General Description ......................................................................... 1
100% Duty Cycle Operation ..................................................... 15
Revision History ............................................................................... 2
Active Discharge ......................................................................... 15
Functional Block Diagram .............................................................. 3
VOUTOK Function ................................................................... 15
Specifications..................................................................................... 4
Thermal Shutdown .................................................................... 15
Absolute Maximum Ratings ............................................................ 6
Applications Information .............................................................. 16
Thermal Resistance ...................................................................... 6
External Component Selection ................................................ 16
ESD Caution .................................................................................. 6
Selecting the Inductor ................................................................ 16
Pin Configuration and Function Descriptions ............................. 7
Output Capacitor........................................................................ 16
Typical Performance Characteristics ............................................. 8
Input Capacitor ........................................................................... 17
Theory of Operation ...................................................................... 14
Efficiency ..................................................................................... 17
Buck Regulator Operation Modes............................................ 14
Printed Circuit Board (PCB) Layout Recommendations ..... 18
Oscillator and Synchronization ................................................ 14
Typical Application Circuits ......................................................... 19
Adjustable and Fixed Output Voltages .................................... 14
Factory Programmable Options ................................................... 20
Undervoltage Lockout (UVLO) ............................................... 15
Outline Dimensions ....................................................................... 21
Enable/Disable ............................................................................ 15
Ordering Guide .......................................................................... 21
Current Limit .............................................................................. 15
REVISION HISTORY
12/15—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 21
6/15—Revision 0: Initial Version
Rev. A | Page 2 of 21
Data Sheet
ADP5301
FUNCTIONAL BLOCK DIAGRAM
VOUTOK
PVIN
PVIN
90%
87%
DRIVER
ILIM_PWM
FB
SW
ILIM_HYS
–0.6A(PWM)
0A(HYS)
CONTROL
LOGIC
PWM
PVIN
Σ
SLOPE
COMPENSATION
DRIVER
PGND
STANDBY
0.808V
0.8V
FB
INTERNAL
FEEDBACK
RESISTOR
DIVIDER
0.8V
V TO I
VID
MODE
1.2V
0.4V
SOFT
START
EN
PVIN
UVLO
AGND
BAND GAP BIAS
AND
HOUSEKEEPING
2.06V
2.00V
SYNC/
MODE
SYNC
KEEP ALIVE BLOCK
MODE
Figure 2.
Rev. A | Page 3 of 21
2MHz
OSC
13169-002
1.2V
0.4V
ADP5301
Data Sheet
SPECIFICATIONS
VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter
INPUT SUPPLY VOLTAGE RANGE
SHUTDOWN CURRENT
Symbol
VIN
ISHUTDOWN
QUIESCENT CURRENT
Operating Quiescent Current in Hysteresis Mode
Operating Quiescent Current in PWM Mode
UNDERVOLTAGE LOCKOUT
UVLO Threshold
Rising
Falling
OSCILLATOR CIRCUIT
Switching Frequency in PWM Mode
FB Threshold of Frequency Fold
SYNCHRONIZATION THRESHOLD
SYNC Clock Range
SYNC High Level Threshold
SYNC Low Level Threshold
SYNC Duty Cycle Range
SYNC/MODE Leakage Current
MODE TRANSITION
Transition Delay from Hysteresis Mode to
PWM Mode
EN PIN
Input Voltage Threshold
High
Low
Input Leakage Current
FB PIN
Output Options by VID Resistor
PWM Mode
Fixed VID Code Voltage Accuracy
Adjustable VID Code Voltage Accuracy
Hysteresis Mode
Fixed VID Code Threshold Accuracy from
Active Mode to Standby Mode
Adjustable VID Code Threshold Accuracy
from Active Mode to Standby Mode
Hysteresis of Threshold Accuracy from
Active Mode to Standby Mode
Feedback Bias Current
Min
2.15
18
18
Max
6.50
40
130
Unit
V
nA
nA
IQ_HYS
180
180
570
260
350
1400
nA
nA
nA
IQ_PWM
UVLO
425
630
µA
2.06
2.00
2.14
V
V
2.0
0.3
2.3
MHz
V
2.5
MHz
V
V
ns
VUVLO_RISING
VUVLO_FALLING
1.90
fSW
VOSC_FOLD
1.7
SYNCCLOCK
SYNCHIGH
SYNCLOW
SYNCDUTY
1.2
1.2
Typ
100
ISYNC_LEAKAGE
50
tHYS_TO_PWM
20
VIH
VIL
IEN_LEAKAGE
1.2
VOUT_OPT
0.4
1/fSW −
150
150
Test Conditions/Comments
VEN = 0 V, −40°C ≤ TJ ≤ +85°C
VEN = 0 V, −40°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +85°C
−40°C ≤ TJ ≤ +125°C
100% duty cycle operation, VIN = 3.0 V,
VOUT set to 3.3 V
nA
VSYNC/MODE = 3.6 V
Clock
cycles
SYNC/MODE goes logic high from
logic low
0.4
25
V
V
nA
0.8
5.0
V
0.8 V to 5.0 V in various factory options
VFB_PWM_FIX
−0.6
+0.6
%
VFB_PWM_ADJ
−1.2
−1.5
+1.2
+1.5
%
%
TJ = 25°C, output voltage setting via
factory fuse
−40°C ≤ TJ ≤ +125°C
Output voltage setting via VID resistor
VFB_HYS_FIX
−0.75
+0.75
%
TJ = 25°C
VFB_HYS_ADJ
−2.5
−3
+2.5
+3
%
%
−40°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
VFB_HYS (HYS)
1
IFB
66
25
Rev. A | Page 4 of 21
%
95
45
nA
nA
Output Option 0, VOUT = 2.5 V
Output Option 1, VOUT = 1.3 V
Data Sheet
Parameter
SW PIN
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
Current-Limit in PWM Mode
Peak Current in Hysteresis Mode
Minimum On Time
VOUTOK PIN
Monitor Threshold
Monitor Hysteresis
Monitor Rising Delay
Monitor Falling Delay
Leakage Current
Output Low Voltage
SOFT START
Default Soft Start Time
Start-Up Delay
COUT DISCHARGE SWITCH ON RESISTANCE
THERMAL SHUTDOWN
Threshold
Hysteresis
ADP5301
Symbol
RDS (ON) H
RDS (ON) L
ILIM_PWM
ILIM_HYS
tMIN_ON
VOUTOK (RISE)
VOUTOK (HYS)
tVOUTOK_RISE
tVOUTOK_FALL
IVOUTOK_LEAKAGE
VOUTOK_LOW
Min
Typ
Max
Unit
Test Conditions/Comments
800
324
196
1000
265
40
470
320
1200
mΩ
mΩ
mA
mA
ns
Pin to pin measurement
Pin to pin measurement
SYNC/MODE = high
SYNC/MODE = low
90
3
40
10
0.1
50
93
87
70
1
80
%
%
µs
µs
µA
mV
tSS
tSTART_DELAY
RDIS
350
2
290
µs
ms
Ω
TSHDN
THYS
142
127
°C
°C
Rev. A | Page 5 of 21
IVOUTOK = 100 µA
Factory trim, 1 bit (350 µs and 2800 µs)
Delay from the EN pin being pulled high
ADP5301
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
PVIN to PGND
SW to PGND
FB to AGND
VID to AGND
EN to AGND
VOUTOK to AGND
SYNC/MODE to AGND
PGND to AGND
Storage Temperate Range
Operational Junction Temperature Range
Rating
−0.3 V to +7 V
−0.3 V to PVIN + 0.3 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−65°C to +150°C
−40°C to +125°C
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
9-Ball WLCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 21
θJA
132
Unit
°C/W
Data Sheet
ADP5301
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1
A2
A3
SW
PVIN
EN
B1
B2
B3
PGND
AGND
SYNC/
MODE
C1
C2
C3
VOUTOK
FB
VID
13169-003
ADP5301
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
A1
A2
A3
B1
B2
B3
Mnemonic
SW
PVIN
EN
PGND
AGND
SYNC/MODE
C1
C2
C3
VOUTOK
FB
VID
Description
Switching Node Output for the Regulator.
Power Input for the Regulator.
Enable Input for the Regulator. Set this pin to logic low to disable the regulator.
Power Ground.
Analog Ground.
Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external
clock, connect this pin to an external clock with a frequency from 1.2 MHz to 2.5 MHz.
PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM
mode. When this pin is logic low, the regulator operates in hysteresis mode.
Output Power-Good Signal. This open-drain output is the power-good signal for the output voltage.
Feedback Sensing Input for the Regulator.
Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the
output voltage of the regulator (see Table 5).
Rev. A | Page 7 of 21
ADP5301
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, VOUT = 2.5 V, L = 2.2 µH, CIN = COUT = 10 μF, fSW = 2 MHz, TA = 25°C, unless otherwise noted.
100
100
90
90
60
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
50
40
0.010
0.100
1.000
LOAD CURRENT (mA)
10.000
40
0.001
0.010
0.100
1.000
LOAD CURRENT (mA)
10.000
Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V
100
100
90
90
EFFICIENCY (%)
80
70
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
60
50
0.010
0.100
1.000
LOAD CURRENT (mA)
10.000
80
70
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
60
13169-005
EFFICIENCY (%)
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
60
50
Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V
40
0.001
70
50
0.001
Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V
0.010
0.100
1.000
LOAD CURRENT (mA)
13169-008
30
0.001
80
13169-007
EFFICIENCY (%)
70
13169-004
EFFICIENCY (%)
80
10.000
Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V
100
100
90
90
80
60
50
40
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
30
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
60
50
0.001
0.010
0.100
1.000
LOAD CURRENT (mA)
10.000
20
10
0
0
Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V
100
200
300
LOAD CURRENT (mA)
400
Figure 9. PWM Efficiency vs. Load Current, VOUT = 1.2 V
Rev. A | Page 8 of 21
500
13169-009
EFFICIENCY (%)
70
13169-006
EFFICIENCY (%)
70
80
ADP5301
100
90
90
80
80
70
70
40
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
30
20
10
100
200
300
LOAD CURRENT (mA)
400
40
20
10
500
0
90
80
80
70
70
EFFICIENCY (%)
90
60
50
40
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
100
200
300
LOAD CURRENT (mA)
400
40
500
0
0
100
200
300
LOAD CURRENT (mA)
400
Figure 14. PWM Efficiency vs. Load Current, VOUT = 3.3 V
350
QUIESCENT CURRENT (nA)
–40ºC
+25ºC
+85ºC
+125ºC
100
80
60
40
300
–40ºC
+25ºC
+85ºC
+125ºC
250
200
150
20
0
2.3
2.9
3.5
4.1
4.7
VIN (V)
5.3
5.9
6.5
13169-012
SHUTDOWN CURRENT (nA)
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
10
160
120
6.5
50
Figure 11. PWM Efficiency vs. Load Current, VOUT = 2.5 V
140
500
60
20
0
0
400
200
300
LOAD CURRENT (mA)
30
13169-011
EFFICIENCY (%)
100
10
100
Figure 13. PWM Efficiency vs. Load Current, VOUT = 1.8 V
100
20
500
0
Figure 10. PWM Efficiency vs. Load Current, VOUT = 1.5 V
30
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
30
0
0
60
50
13169-013
50
13169-014
60
13169-015
EFFICIENCY (%)
100
13169-010
EFFICIENCY (%)
Data Sheet
100
2.3
2.9
3.5
4.1
4.7
VIN (V)
5.3
5.9
Figure 15. Hysteresis Quiescent Current vs. VIN, SYNC/MODE = Low
Figure 12. Shutdown Current vs. VIN, EN = Low
Rev. A | Page 9 of 21
ADP5301
Data Sheet
810
801
808
FEEDBACK VOLTAGE (mV)
FEEDBACK VOLTAGE (mV)
ACTIVE TO STANDBY
800
799
798
806
804
STANDBY TO ACTIVE
802
800
798
796
797
–40
+25
+85
TEMPERATURE (°C)
+125
792
–40
Figure 16. Feedback Voltage vs. Temperature, PWM Mode
–40ºC
+25ºC
+125ºC
–40ºC
+25ºC
+125ºC
350
LOW-SIDE RDS (ON) L (mΩ)
500
400
300
200
300
250
200
3.5
4.1
4.7
VIN (V)
5.3
5.9
6.5
100
2.3
2.9
Figure 17. High-Side RDS (ON) H vs. VIN
3.5
4.1
4.7
VIN (V)
5.3
5.9
6.5
13169-020
2.9
13169-017
150
5.9
6.5
13169-021
HIGH-SIDE RDS (ON) H (mΩ)
+125
400
600
Figure 20. Low-Side RDS (ON) L vs. VIN
1090
1200
1150
PEAK CURRENT LIMIT (mA)
1040
990
940
1100
–40ºC
+25ºC
+125ºC
1050
1000
950
900
890
850
840
–40
+25
+85
TEMPERATURE (°C)
+125
13169-018
PEAK CURRENT LIMIT (mA)
+25
+85
TEMPERATURE (°C)
Figure 19. Feedback Voltage vs. Temperature, Hysteresis Mode
700
100
2.3
13169-019
13169-016
794
Figure 18. Peak Current Limit vs. Temperature
800
2.3
2.9
3.5
4.1
4.7
VIN (V)
5.3
Figure 21. Peak Current Limit vs. VIN
Rev. A | Page 10 of 21
Data Sheet
ADP5301
2.10
2.3
SWITCHING FREQUENCY (kHz)
2.08
2.04
2.02
FALLING
2.00
2.1
2.0
1.9
13169-022
1.96
–40
+25
+85
TEMPERATURE (°C)
+125
1.7
2.3
2.9
Figure 22. UVLO Threshold, Rising and Falling vs. Temperature
3.5
4.1
4.7
VIN (V)
5.3
5.9
6.5
Figure 25. Switching Frequency vs. VIN
1
VOUT
VOUT (AC)
1
SW
IL
2
4
IL
4
2
140mA
B
CH1 10.0mV
Figure 23. Steady Waveform of Hysteresis Mode, ILOAD = 1 mA
(IL is the Inductor Current)
W
CH2 2.00V
M 400ns A CH2
CH4 200mA Ω BW T 90.60%
2.72V
13169-026
M 200µs A CH4
T 39.60%
13169-023
SW
CH2 2.00V
CH4 500mA Ω
CH1 100mV
Figure 26. Steady Waveform of PWM Mode, ILOAD = 300 mA
VIN
VIN
VOUT
3
VOUT
1
1
IL
IL
4
4
SW
SW
2
CH1 1.00V
CH3 2.00V
B
B
W
W
CH2 5.00V
M 200µs A CH1
CH4 500mA Ω BW T 50.60%
1.22V
CH1 500mV
CH3 2.00V
Figure 24. Soft Start, ILOAD = 300 mA
B
W
B
W
CH2 5.00V
M 100µs A CH1
CH4 500mA Ω BW T 40.00%
Figure 27. Soft Start with Precharge Function
Rev. A | Page 11 of 21
1.05V
13169-027
2
13169-025
1.8
1.98
13169-024
UVLO THRESHOLD (V)
RISING
2.06
–40ºC
+25ºC
+125ºC
2.2
ADP5301
Data Sheet
VOUT (AC)
1
1
VOUT (AC)
IOUT
IOUT
4
B
W
M 200µs A CH4
CH4 50.0mA Ω BW T 20.80%
111mA
CH1 50.0mV
B
W
CH4 200mA Ω
Figure 28. Load Transient of Hysteresis Mode, ILOAD from 0 mA to 50 mA
B
W
M 200µs A CH4
T 20.40%
308mA
13169-031
CH1 50.0mV
13169-028
4
Figure 31. Load Transient of PWM Mode, ILOAD from 125 mA to 375 mA
1
1
VOUT (AC)
VOUT (AC)
VIN
VIN
IL
4
3
IL
4
2
SW
2
B
W
B
W
CH2 5.00V
CH4 500mA Ω
B
W
M 2.00ms A CH3
T 30.00%
4.72V
B
CH1 10.0mV
CH3 2.00V
Figure 29. Line Transient of Hysteresis Mode, ILOAD = 10 µA, VIN from 2.5 V to 6 V
B
W
W
CH2 5.00V
CH4 500mA Ω
B
W
M 2.00ms A CH3
T 30.20%
4.28V
13169-032
CH1 50.0mV
CH3 2.00V
13169-029
SW
Figure 32. Line Transient of PWM Mode, ILOAD = 500 mA, VIN from 2.5 V to 6 V
VIN
VOUT
VOUT
1
VOUTOK
3
1
IL
SW
4
B
W
B
W
CH4 200mA Ω
B
W
M 10.0ms A CH3
T 40.20%
4.80V
CH1 1.00V
CH3 1.00V
Figure 30. Input Voltage Ramp Up and Ramp Down in Hysteresis Mode
Rev. A | Page 12 of 21
B
W
B
W
CH2 2.00V
B
W
M 200µs A CH1
T 40.00%
Figure 33. VOUTOK Function
1.32V
13169-033
CH1 1.00V
CH3 1.00V
13169-030
2
Data Sheet
ADP5301
VOUT
VOUT
1
1
IL
IL
4
4
SW
SW
W
CH2 2.00V
CH4 500mA Ω
M 10.0µs A CH1
T 40.20%
1.44V
B
CH1 2.00V
W
Figure 34. Output Short Protection
CH2 2.00V
CH4 500mA Ω
M 1.00ms A CH1
T 40.20%
1.44V
13169-036
B
13169-034
CH1 2.00V
1.64V
13169-037
2
2
Figure 36. Output Short Recovery
EN
1
SYNC/
MODE
3
VOUT
SW
2
1
2
CH1 2.00V
B
W
CH2 2.00V
M 400ns A CH2
T 50.00%
1.40V
13169-035
SW
CH1 1.00V
CH3 2.00V
Figure 35. Synchronized to 2.5 MHz
B
W
B
W
CH2 2.00V
B
W
M 4.00ms A CH3
T 40.00%
Figure 37. Quick Output Discharge Function
Rev. A | Page 13 of 21
ADP5301
Data Sheet
THEORY OF OPERATION
The ADP5301 is a high efficiency, ultralow quiescent current
step-down regulator in a 9-ball WLCSP to meet demanding
performance and board space requirements. The device enables
direct connection to the wide input voltage range of 2.15 V to
6.50 V, allowing the use of multiple alkaline/NiMH or Li-Ion
cells and other power sources.
BUCK REGULATOR OPERATION MODES
The user can alternate between hysteresis mode and PWM mode
during operation. The flexible configuration capability during
operation of the device enables efficient power management to
meet high efficiency and low output ripple requirements when
the system switches between active mode and standby mode.
OSCILLATOR AND SYNCHRONIZATION
The ADP5301 operates at a 2 MHz switching frequency typical
in PWM operation mode.
PWM Mode
In PWM mode, the buck regulator in the ADP5301 operates at
a fixed frequency that is set by an internal oscillator. At the start
of each oscillator cycle, the high-side MOSFET switch turns on and
sends a positive voltage across the inductor. The inductor current
increases until the current sense signal exceeds the peak inductor
current threshold, which turns off the high-side MOSFET switch.
This threshold is set by the error amplifier output. During the highside MOSFET off time, the inductor current decreases through
the low-side MOSFET until the next oscillator clock pulse starts
a new cycle.
Hysteresis Mode
In hysteresis mode, the buck regulator in the ADP5301 charges
the output voltage slightly higher than its nominal output voltage
with PWM pulses by regulating the constant peak inductor current.
When the output voltage increases until the output sense signal
exceeds the hysteresis upper threshold, the regulator enters standby
mode. In standby mode, the high-side and low-side MOSFETs and
a majority of the circuitry are disabled to allow a low quiescent
current as well as high efficiency performance.
During standby mode, the output capacitor supplies energy into
the load and the output voltage decreases until it falls below the
hysteresis comparator lower threshold. The buck regulator wakes
up and generates the PWM pulses to charge the output again.
Because the output voltage occasionally enters standby mode
and then recovers, the output voltage ripple in hysteresis mode
is larger than the ripple in PWM mode.
Mode Selection
The ADP5301 includes the SYNC/MODE pin to allow flexible
configuration in hysteresis mode or PWM mode.
When a logic high level is applied to the SYNC/MODE pin, the
buck regulator is forced to operate in PWM mode. In PWM mode,
the regulator can supply up to 500 mA of output current. The
regulator can provide lower output ripple and output noise in
PWM mode, which is useful for noise sensitive applications.
When a logic low level is applied to the SYNC/MODE pin, the buck
regulator is forced to operate in hysteresis mode. In hysteresis mode,
the regulator draws only 180 nA of quiescent current typical to
regulate the output under zero load, which allows the regulator to
act as a keep-alive power supply in a battery-powered system. In
hysteresis mode, the regulator supplies up to 50 mA of output current with a relatively large output ripple compared to PWM mode.
The switching frequency of the ADP5301 can be synchronized to
an external clock with a frequency range from 1.2 MHz to
2.5 MHz. The ADP5301 automatically detects the presence of an
external clock applied to the SYNC/MODE pin, and the switching
frequency transitions to the frequency of the external clock. When
the external clock signal stops, the device automatically switches
back to the internal clock.
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
The ADP5301 provides adjustable output voltage settings by
connecting one resistor through the VID pin to AGND. The
VID detection circuitry works in the start-up period, and the
voltage ID code is sampled and held into the internal register
and does not change until the next power recycle. Furthermore,
the ADP5301 provides a fixed output voltage programmed via
the factory fuse. In this condition, connect the VID pin to the
PVIN pin.
For the output voltage settings, the feedback resistor divider is
built into the ADP5301, and the feedback pin (FB) must be tied
directly to the output. An ultralow power voltage reference and
an integrated high impedance (50 MΩ typical) feedback divider
network contribute to the low quiescent current. Table 5 lists
the output voltage options by the VID pin configurations.
Table 5. Output Voltage (VOUT) Options Using the VID Pin
VID Configuration
Short to Ground
Short to PVIN
RVID = 499 kΩ
RVID = 316 kΩ
RVID = 226 kΩ
RVID = 174 kΩ
RVID = 127 kΩ
RVID = 97.6 kΩ
RVID = 76.8 kΩ
RVID = 56.2 kΩ
RVID = 43 kΩ
RVID = 32.4 kΩ
RVID = 25.5 kΩ
RVID = 19.6 kΩ
RVID = 15 kΩ
RVID = 11.8 kΩ
Rev. A | Page 14 of 21
VOUT (V)
Factory Option 0
Factory Option 1
3.0
3.1
2.5
1.3
3.6
5.0
3.3
4.5
2.9
4.2
2.8
3.9
2.7
3.4
2.6
3.2
2.4
1.9
2.3
1.7
2.2
1.6
2.1
1.4
2.0
1.1
1.8
1.0
1.5
0.9
1.2
0.8
Data Sheet
ADP5301
UNDERVOLTAGE LOCKOUT (UVLO)
STARTUP WITH A PRECHARGED OUTPUT
The undervoltage lockout circuitry monitors the input voltage
level on the PVIN pin. If input voltage falls below 2.00 V (typical),
the regulator turns off. After the input voltage rises above 2.06 V
(typical), the soft start period is initiated, and the regulator is
enabled when the EN pin is high.
The buck regulator in the ADP5301 includes a precharged
start-up feature to protect the low-side MOSFET from damage
during startup. If the output voltage is precharged before the
regulator turns on, the regulator prevents reverse inductor
current—which discharges the output capacitor—until the
internal soft start reference voltage exceeds the precharged
voltage on the feedback pin.
ENABLE/DISABLE
The ADP5301 includes a separate enable pin (EN). A logic high
in the EN pin starts the regulator. Due to the low quiescent current
design, it is typical for the regulator to start switching after a delay
of a few milliseconds from the EN pin being pulled high.
A logic low on the EN pin immediately disables the regulator
and brings the regulator into extremely low current consumption.
CURRENT LIMIT
The buck regulator in the ADP5301 has protection circuitry
that limits the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-side
MOSFET in cycle-by-cycle mode. The positive current limit on
the high-side MOSFET limits the amount of current that can flow
from the input to the output. The negative current limit on the
low-side MOSFET prevents the inductor current from reversing
direction and flowing out of the load.
SHORT-CIRCUIT PROTECTION
The buck regulator in ADP5301 includes frequency foldback to
prevent current runaway on a hard short. When the output voltage
at the FB pin falls below 0.3 V typical, indicating the possibility
of a hard short at the output, the switching frequency (in PWM
mode) is reduced to one-fourth of the internal oscillator frequency.
The reduction in the switching frequency allows more time for the
inductor to discharge, preventing a runaway of output current.
SOFT START
The ADP5301 has an internal soft start function that ramps up
the output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This feature prevents possible input
voltage drops when a battery or a high impedance power source
is connected to the input of the device. The default typical soft
start time is 350 µs for the regulator.
A different soft start time (2800 µs) can be programmed for
ADP5301 by the factory fuse.
100% DUTY CYCLE OPERATION
When the input voltage approaches the output voltage, the
ADP5301 stops switching and enters 100% duty cycle operation. It
connects the output via the inductor and the internal high-side
power switch to the input. When the input voltage is charged
again and the required duty cycle falls to 95% typical, the buck
immediately restarts switching and regulation without allowing
overshoot on the output voltage. In hysteresis mode, the ADP5301
draws an ultralow quiescent current of only 570 nA typical during
100% duty cycle operation
ACTIVE DISCHARGE
The ADP5301 integrates an optional, factory programmable
discharge switch from the switching node to ground. This switch
turns on when its associated regulator is disabled, which helps
discharge the output capacitor quickly. The typical value of the
discharge switch is 290 Ω for the regulator.
By default, the discharge function is not enabled. The active
discharge function can be enabled by the factory fuse.
VOUTOK FUNCTION
The ADP5301 includes an open-drain power-good output
(VOUTOK pin) that is active high when the buck regulator is
operating normally. By default, the VOUTOK pin monitors the
output voltage. A logic high on the VOUTOK pin indicates that
the regulated output voltage of the buck regulator is above 90%
(typical) of its nominal output. When the regulated output voltage
of the buck regulator falls below 87% (typical) of its nominal output
for a delay time greater than approximately 10 µs, the VOUTOK
pin goes low.
THERMAL SHUTDOWN
If the ADP5301 junction temperature exceeds 142°C, the thermal
shutdown circuit turns off the IC except for the internal linear
regulator. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15°C hysteresis is included so that the ADP5301
does not return to operation after thermal shutdown until the
junction temperature falls below 127°C. When the device exits
thermal shutdown, a soft start is initiated for the buck regulator.
Rev. A | Page 15 of 21
ADP5301
Data Sheet
APPLICATIONS INFORMATION
This section describes the external components selection for the
ADP5301. A typical application circuit is shown in Figure 38.
VIN =
2.15V TO 6.50V
2.2µH
PVIN
10µF
MLCC
SW
ADP5301
10µF
MLCC
(9-BALL WLCSP)
EN
VOUT = 1.8V
A minimum requirement of the dc current rating of the inductor
is for it to be equal to the maximum load current plus half of the
inductor current ripple (ΔIL), as shown by the following equations:
PGND
SYNC/
MODE
I L  VOUT
R1
1MΩ
FB






 I 
I PK  I LOAD ( MAX )   L 
 2 
VOUTOK
Use the inductor series from different vendors shown in Table 6.
VID
RVID
20kΩ
13169-038
AGND
 VOUT
1 –
VIN

 L  f SW


Figure 38. Typical Application Circuit
EXTERNAL COMPONENT SELECTION
The ADP5301 is optimized for operation with a 2.2 μH inductor
and 10 μF output capacitors for various output voltages using
the closed-loop compensation and adaptive slope compensation
circuits. The selection of components depends on the efficiency,
the load current transient, and other application requirements. The
trade-offs among performance parameters, such as efficiency and
transient response, are made by varying the choice of external
components.
SELECTING THE INDUCTOR
The high switching frequency of the ADP5301 allows the use of
small surface-mount power inductors. The dc resistance (DCR)
value of the selected inductor affects efficiency. In addition, it is
recommended to select a multilayer inductor rather than a
magnetic iron inductor because the high switching frequency
increases the core temperature rise and enlarges the core loss.
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage overshoot,
the voltage undershoot, and the ripple voltage present on the
output. Capacitors with low equivalent series resistance (ESR)
values produce the lowest output ripple. Furthermore, use
capacitors such as X5R and X7R dielectric capacitors. Do not
use Y5V and Z5U capacitors, which are unsuitable choices due
to their large capacitance variation over temperature and their dc
bias voltage changes. Because ESR is important, select the capacitor
using the following equation:
ESRCOUT 
VRIPPLE
ΔI L
where:
ESRCOUT is the ESR of the chosen capacitor.
VRIPPLE is the peak-to-peak output voltage ripple.
Increasing the output capacitor value has no effect on stability and
may reduce output ripple and enhance load transient response.
When choosing the output capacitor value, it is important to
account for the loss of capacitance due to output voltage dc bias.
Use the capacitor series from different vendors shown in Table 7.
Table 6. Recommended Inductors
Vendor
TDK
Wurth
Coilcraft
1
Model
MLP2016V2R2MT0S1
74479889222
LPS3314-222MR
Inductance (μH)
2.2
2.2
2.2
Dimensions (mm)
2.0 × 1.6 × 0.85
2.5 × 2.0 × 1.2
3.3 × 3.3 × 1.3
DCR (mΩ)
280
250
100
ISAT1 (A)
1.0
1.7
1.5
ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 7. Input and Output Capacitors
Vendor
Murata
Murata
Murata
Model
GRM188D71A106MA73
GRM21BR71A106KE51
GRM31CR71A106KA01
Capacitance (μF)
10
10
10
Rev. A | Page 16 of 21
Size
0603
0805
1206
Data Sheet
ADP5301
INPUT CAPACITOR
An input capacitor is required to reduce the input voltage
ripple, input ripple current, and source impedance. Place the
input capacitor as close as possible to the PVIN pin. A low ESR
X7R or X5R capacitor is highly recommended to minimize the
input voltage ripple. Use the following equation to determine
the rms input current:
I RMS ≥ I LOAD ( MAX )
VOUT (VIN − VOUT )
VIN
For most applications, a 10 μF capacitor is sufficient. The input
capacitor can be increased without any limit for better input
voltage filtering.
EFFICIENCY
Efficiency is the ratio of output power to input power. The high
efficiency of the ADP5301 has two distinct advantages. First, only a
small amount of power is lost in the dc-to-dc converter package,
which in turn reduces thermal constraints. Second, the high
efficiency delivers the maximum output power for the given
input power, thereby extending battery life in portable
applications.
Power Switch Conduction Losses
Power switch dc conduction losses are caused by the flow of
output current through the high-side P-channel power switch
and the low-side N-channel synchronous rectifier, which have
internal resistances (RDS (ON)) associated with them. The amount
of power loss is approximated by
To estimate the total amount of power lost in the inductor, use
the following equation:
PL = DCR × IOUT2 + Core Losses
Driver Losses
Driver losses are associated with the current drawn by the driver to
turn on and turn off the power devices at the switching frequency.
Each time a power device gate is turned on and turned off, the
driver transfers a charge from the input supply to the gate, and
then from the gate to ground.
Estimate driver losses using the following equation:
PDRIVER = (CGATE_H + CGATE_L) × VIN2 × fSW
where:
CGATE_H is the gate capacitance of the internal high-side switch.
CGATE_L is the gate capacitance of the internal low-side switch.
fSW is the switching frequency in PWM mode.
The typical values for the gate capacitances are 69 pF for CGATE_H
and 31 pF for CGATE_L.
Transition Losses
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of a switch
node transition, the power switch provides all of the inductor
current. The source to drain voltage of the power switch is half
of the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Use the following equation to estimate transition losses:
PSW_COND = (RDS (ON) H × D + RDS (ON) L × (1 − D)) × IOUT2
PTRAN = VIN/2 × IOUT × (tR + tF) × fSW
where:
where:
tR is the rise time of the SW node.
tF is the fall time of the SW node.
V
D = OUT
VIN
The typical value for the rise and fall times, tR and tF, is 2 ns.
The internal resistance of the power switches increases with
temperature and with the input voltage decrease.
Inductor Losses
Inductor conduction losses are caused by the flow of current
through the inductor, which has an internal DCR associated with
it. Larger size inductors have smaller DCR, which can decrease
inductor conduction losses. Inductor core losses relate to the
magnetic permeability of the core material. Because the ADP5301
is a high switching frequency dc-to-dc regulator, shielded ferrite
core material is recommended because of its low core losses and
low electromagnetic interference (EMI).
Rev. A | Page 17 of 21
ADP5301
Data Sheet
PRINTED CIRCUIT BOARD (PCB) LAYOUT RECOMMENDATIONS
VOUT
VIN
L1 – 2.2µH
0603
A2
A3
PVIN
EN
ADP5301
B1
B2
B3
PGND
AGND
SYNC/
MODE
C1
C2
C3
VOUTOK
FB
VID
10µF
10V/XR5
0603
3.00
GND
100kΩ
0201
3.60
Figure 39. Typical PCB Layout
Rev. A | Page 18 of 21
13169-039
10µF
6.3V/XR5
0603
A1
SW
Data Sheet
ADP5301
TYPICAL APPLICATION CIRCUITS
The ADP5301 can be used as a keep-alive, ultralow step-down power regulator to extend the battery life (see Figure 40) and as a batterypowered equipment or wireless sensor network controlled by a microcontroller or a processor (see Figure 41).
VIN = 3.0V TO 4.2V
2.2µH
PVIN
10µF
Li-Ion BATTERY
SW
ADP5301
RVID
20kΩ
1%
VOUT = 1.8V
10µF
EN
PGND
VID
FB
VOUTOK
SYNC/MODE
13169-040
AGND
Figure 40. Typical ADP5301 Application with Li-Ion Battery
VIN = 2.0V TO 3.0V
2.2µH
10µF
ADP5301
EN
RVID
20kΩ
1%
VOUT = 1.8V
SW
PVIN
ADC/RF/AFE
10µF
PGND
FB
VID
R1
1MΩ
VOUTOK
MCU
(ALWAYS ON)
SYNC/MODE
AGND
13169-041
TWO ALKALINE
OR NiMH
BATTERIES
Figure 41. Typical ADP5301 Application with Two Alkaline/NiMH Batteries
Rev. A | Page 19 of 21
ADP5301
Data Sheet
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative.
Table 8. Output Voltage VID Setting Options
Option
Option 0
Option 1
Description
VID resistor to set the output voltage as: 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, or
3.6 V (default)
VID resistor to set the output voltage as: 0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V, 3.1 V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, or 5.0 V
Table 9. Output Discharge Functionality Options
Option
Option 0
Option 1
Description
Output discharge function disabled for buck regulator (default)
Output discharge function enabled for buck regulator
Table 10. Soft Start Time Options
Option
Option 0
Option 1
Description
350 µs (default)
2800 µs
Rev. A | Page 20 of 21
Data Sheet
ADP5301
OUTLINE DIMENSIONS
1.690
1.650
1.610
0.455
0.435
0.415
3
2
1
A
BALL A1
IDENTIFIER
1.910
1.870
1.830
1.00
REF
B
C
0.50
BSC
BOTTOM VIEW
TOP VIEW
(BALL SIDE DOWN)
0.660
0.600
0.540
0.390
0.360
0.330
END VIEW
0.345
0.325
0.305
(BALL SIDE UP)
SEATING
PLANE
PKG-003773
0.360
0.320
0.280
0.270
0.240
0.210
05-20-2014-A
COPLANARITY
0.04
Figure 42. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5301ACBZ-1-R7
ADP5301ACBZ-2-R7
ADP5301ACBZ-3-R7
ADP5301-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
9-Ball WLCSP, Output Voltage Option 0 with Output Discharge
9-Ball WLCSP, Output Voltage Option 0 Without Output Discharge
9-Ball WLCSP, Output Voltage Option 1 with Output Discharge
Evaluation Board
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13169-0-12/15(A)
Rev. A | Page 21 of 21
Package Option
CB-9-6
CB-9-6
CB-9-6