ON MPTE-22RL4G 1500 watt peak power mosorb tm zener transient voltage suppressor Datasheet

1N6373 − 1N6381 Series
(ICTE−5 − ICTE−36,
MPTE−5 − MPTE−45)
1500 Watt Peak Power
Mosorbt Zener Transient
Voltage Suppressors
Unidirectional*
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Cathode
Mosorb devices are designed to protect voltage sensitive
components from high voltage, high−energy transients. They have
excellent clamping capability, high surge capability, low zener
impedance and fast response time. These devices are
ON Semiconductor’s exclusive, cost-effective, highly reliable
Surmetict axial leaded package and are ideally-suited for use in
communication systems, numerical controls, process controls,
medical equipment, business machines, power supplies and many
other industrial/consumer applications, to protect CMOS, MOS and
Bipolar integrated circuits.
AXIAL LEAD
CASE 41A
PLASTIC
MARKING DIAGRAMS
A
MPTE
−xx
1N
63xx
YYWWG
G
Specification Features
•
•
•
•
•
•
•
Anode
Working Peak Reverse Voltage Range − 5.0 V to 45 V
Peak Power − 1500 Watts @ 1 ms
ESD Rating of Class 3 (>16 KV) per Human Body Model
Maximum Clamp Voltage @ Peak Pulse Current
Low Leakage < 5 mA Above 10 V
Response Time is Typically < 1 ns
Pb−Free Packages are Available*
A
ICTE
−xx
YYWWG
G
A
= Assembly Location
MPTE−xx = ON Device Code
1N63xx = JEDEC Device Code
ICTE−xx = ON Device Code
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Mechanical Characteristics
CASE: Void-free, transfer-molded, thermosetting plastic
FINISH: All external surfaces are corrosion resistant and leads are
readily solderable
MAXIMUM LEAD TEMPERATURE FOR SOLDERING PURPOSES:
230°C, 1/16″ from the case for 10 seconds
POLARITY: Cathode indicated by polarity band
MOUNTING POSITION: Any
ORDERING INFORMATION
Package
Shipping†
MPTE−xx, G
Axial Lead
(Pb−Free)
500 Units/Box
MPTE−xxRL4, G
Axial Lead
(Pb−Free)
1500/Tape & Reel
ICTE−xx, G
Axial Lead
(Pb−Free)
500 Units/Box
ICTE−xxRL4, G
Axial Lead
(Pb−Free)
1500/Tape & Reel
1N63xx, G
Axial Lead
(Pb−Free)
500 Units/Box
1N63xxRL4, G
Axial Lead
(Pb−Free)
1500/Tape & Reel
Device
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 4
1
Publication Order Number:
1N6373/D
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Peak Power Dissipation (Note 1)
@ TL ≤ 25°C
PPK
1500
W
Steady State Power Dissipation @ TL ≤ 75°C, Lead Length = 3/8″
Derated above TL = 75°C
PD
5.0
20
W
mW/°C
Thermal Resistance, Junction−to−Lead
RqJL
20
°C/W
Forward Surge Current (Note 2)
@ TA = 25°C
IFSM
200
A
TJ, Tstg
− 65 to +175
°C
Operating and Storage Temperature Range
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Nonrepetitive current pulse per Figure 5 and derated above TA = 25°C per Figure 2.
2. 1/2 sine wave (or equivalent square wave), PW = 8.3 ms, duty cycle = 4 pulses per minute maximum.
*Please see 1N6382 – 1N6389 (ICTE−10C − ICTE−36C, MPTE−8C − MPTE−45C) for Bidirectional Devices.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless
I
otherwise noted, VF = 3.5 V Max. @ IF (Note 3) = 100 A)
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
QVBR
IF
Parameter
VC VBR VRWM
Working Peak Reverse Voltage
IR VF
IT
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
Test Current
Maximum Temperature Variation of VBR
IF
Forward Current
VF
Forward Voltage @ IF
IPP
Uni−Directional TVS
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2
V
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 3.5 V Max. @ IF (Note 3) = 100 A)
VRWM
(Note 4)
IR @
VRWM
(Volts)
(mA)
1N6373
MPTE−5
5.0
1N6374, G
(MPTE−8, G)
1N6374
MPTE−8
1N6375, G
(MPTE−10,G)
JEDEC
Device†
(ON Device)
Device
Marking
1N6373, G
(MPTE−5, G)
Breakdown Voltage
VC @ IPP (Note 6)
5)
(Volts)
@ IT
VC
IPP
Min
Nom
Max
(mA)
(Volts)
300
6.0
−
−
1.0
8.0
25
9.4
−
−
1N6375
MPTE−10
10
2.0
11.7
−
1N6376, G
(MPTE−12, G)
1N6376
MPTE−12
12
2.0
14.1
1N6377, G
(MPTE−15, G)
1N6377
MPTE−15
15
2.0
1N6379, G
(MPTE−22, G)
1N6379
MPTE−22
22
1N6380, G
(MPTE−36, G)
1N6380
MPTE−36
1N6381, G
(MPTE−45, G)
ICTE−5, G
ICTE−10, G
ICTE−12, G
VBR (Note
VC (Volts) (Note 6)
QVBR
(A)
@ IPP =
1A
@ IPP =
10 A
(mV/°C)
9.4
160
7.1
7.5
4.0
1.0
15
100
11.3
11.5
8.0
−
1.0
16.7
90
13.7
14.1
12
−
−
1.0
21.2
70
16.1
16.5
14
17.6
−
−
1.0
25
60
20.1
20.6
18
2.0
25.9
−
−
1.0
37.5
40
29.8
32
26
36
2.0
42.4
−
−
1.0
65.2
23
50.6
54.3
50
1N6381
MPTE−45
45
2.0
52.9
−
−
1.0
78.9
19
63.3
70
60
ICTE−5
ICTE−10
ICTE−12
5.0
10
12
300
2.0
2.0
6.0
11.7
14.1
−
−
−
−
−
−
1.0
1.0
1.0
9.4
16.7
21.2
160
90
70
7.1
13.7
16.1
7.5
14.1
16.5
4.0
8.0
12
ICTE−15, G
ICTE−15
15
2.0
17.6
−
−
1.0
25
60
20.1
20.6
14
ICTE−18, G
ICTE−18
18
2.0
21.2
−
−
1.0
30
50
24.2
25.2
18
ICTE−22, G
ICTE−22
22
2.0
25.9
−
−
1.0
37.5
40
29.8
32
21
ICTE−36, G
ICTE−36
36
2.0
42.4
−
−
1.0
65.2
23
50.6
54.3
26
3. Square waveform, PW = 8.3 ms, non−repetitive duty cycle.
4. A transient suppressor is normally selected according to the maximum working peak reverse voltage (VRWM), which should be equal to or
greater than the dc or continuous peak operating voltage level.
5. VBR measured at pulse test current IT at an ambient temperature of 25°C and minimum voltage in VBR is to be controlled.
6. Surge current waveform per Figure 5 and derate per Figures 1 and 2.
†The “G’’ suffix indicates Pb−Free package available.
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3
100
PPK , PEAK POWER (kW)
NONREPETITIVE
PULSE WAVEFORM
SHOWN IN FIGURE 5
PEAK PULSE DERATING IN % OF
PEAK POWER OR CURRENT @ TA = 25°C
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
100
10
1
0.1ms
1ms
10ms
1 ms
100ms
80
60
40
20
0
10 ms
0
25
50
tP, PULSE WIDTH
Figure 1. Pulse Rating Curve
75
100 125 150 175 200
TA, AMBIENT TEMPERATURE (°C)
Figure 2. Pulse Derating Curve
1N6373, ICTE-5, MPTE-5,
through
1N6389, ICTE-45, C, MPTE-45, C
10,000
MEASURED @
ZERO BIAS
C, CAPACITANCE (pF)
1000
MEASURED @ VRWM
100
10
1
10
100
1000
VBR, BREAKDOWN VOLTAGE (VOLTS)
3/8″
PEAK VALUE − IPP
100
3/8″
5
PULSE WIDTH (tP) IS DEFINED AS
THAT POINT WHERE THE PEAK
CURRENT DECAYS TO 50% OF IPP.
tr ≤ 10 ms
IPP, VALUE (%)
PD , STEADY STATE POWER DISSIPATION (WATTS)
Figure 3. Capacitance versus Breakdown Voltage
4
3
HALF VALUE −
50
IPP
2
2
tP
1
0
0
25
50
75
100 125 150 175
TL, LEAD TEMPERATURE (°C)
0
200
0
1
2
3
t, TIME (ms)
Figure 4. Steady State Power Derating
Figure 5. Pulse Waveform
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4
4
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
1N6373, ICTE-5, MPTE-5,
through
1N6389, ICTE-45, C, MPTE-45, C
1000
500
200
IT , TEST CURRENT (AMPS)
VBR(MIN)=6.0 to 11.7V
19V
42.4V
21.2V
TL=25°C
tP=10ms
100
50
20
10
5
2
1
VBR(NOM)=6.8 to 13V
20V
24V
TL=25°C
tP=10ms
200
43V
75V
100
50
20
180V
10
120V
5
2
1
0.3
0.5 0.7 1
2
3
5 7 10
20 30
DVBR, INSTANTANEOUS INCREASE IN VBR ABOVE VBR(NOM) (VOLTS)
0.3
0.5 0.7 1
2
3
5 7 10
20 30
DVBR, INSTANTANEOUS INCREASE IN VBR ABOVE VBR(NOM) (VOLTS)
Figure 6. Dynamic Impedance
1
0.7
0.5
0.3
DERATING FACTOR
IT , TEST CURRENT (AMPS)
1000
500
1.5KE6.8CA
through
1.5KE200CA
0.2
PULSE WIDTH
10 ms
0.1
0.07
0.05
1 ms
0.03
100 ms
0.02
10 ms
0.01
0.1
0.2
0.5
1
2
5
10
D, DUTY CYCLE (%)
20
50
Figure 7. Typical Derating Factor for Duty Cycle
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5
100
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
APPLICATION NOTES
RESPONSE TIME
circuit layout, minimum lead lengths and placing the
suppressor device as close as possible to the equipment or
components to be protected will minimize this overshoot.
Some input impedance represented by Zin is essential to
prevent overstress of the protection device. This impedance
should be as high as possible, without restricting the circuit
operation.
In most applications, the transient suppressor device is
placed in parallel with the equipment or component to be
protected. In this situation, there is a time delay associated
with the capacitance of the device and an overshoot
condition associated with the inductance of the device and
the inductance of the connection method. The capacitance
effect is of minor importance in the parallel protection
scheme because it only produces a time delay in the
transition from the operating voltage to the clamp voltage as
shown in Figure 8.
The inductive effects in the device are due to actual
turn-on time (time required for the device to go from zero
current to full current) and lead inductance. This inductive
effect produces an overshoot in the voltage across the
equipment or component being protected as shown in
Figure 9. Minimizing this overshoot is very important in the
application, since the main purpose for adding a transient
suppressor is to clamp voltage spikes. These devices have
excellent response time, typically in the picosecond range
and negligible inductance. However, external inductive
effects could produce unacceptable overshoot. Proper
DUTY CYCLE DERATING
The data of Figure 1 applies for non-repetitive conditions
and at a lead temperature of 25°C. If the duty cycle increases,
the peak power must be reduced as indicated by the curves
of Figure 7. Average power must be derated as the lead or
ambient temperature rises above 25°C. The average power
derating curve normally given on data sheets may be
normalized and used for this purpose.
At first glance the derating curves of Figure 7 appear to be
in error as the 10 ms pulse has a higher derating factor than
the 10 ms pulse. However, when the derating factor for a
given pulse of Figure 7 is multiplied by the peak power value
of Figure 1 for the same pulse, the results follow the
expected trend.
TYPICAL PROTECTION CIRCUIT
Zin
LOAD
Vin
V
V
Vin (TRANSIENT)
VL
OVERSHOOT DUE TO
INDUCTIVE EFFECTS
Vin (TRANSIENT)
VL
VL
Vin
td
tD = TIME DELAY DUE TO CAPACITIVE EFFECT
t
t
Figure 8.
Figure 9.
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6
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
MOSORB
CASE 41A−04
ISSUE D
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. LEAD FINISH AND DIAMETER UNCONTROLLED
IN DIMENSION P.
4. 041A−01 THRU 041A−03 OBSOLETE, NEW
STANDARD 041A−04.
D
K
P
P
DIM
A
B
D
K
P
A
K
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7
INCHES
MIN
MAX
0.335
0.374
0.189
0.209
0.038
0.042
1.000
−−−
−−−
0.050
MILLIMETERS
MIN
MAX
8.50
9.50
4.80
5.30
0.96
1.06
25.40
−−−
−−−
1.27
1N6373 − 1N6381 Series (ICTE−5 − ICTE−36, MPTE−5 − MPTE−45)
Mosorb and Surmetic are trademarks of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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