TI LM10010SDX/NOPB Lm10010 vid voltage programmer for point of load regulator Datasheet

LM10010
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LM10010 VID Voltage Programmer for Point of Load Regulator
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FEATURES
DESCRIPTION
•
•
•
The LM10010 is a precision, digitally programmed
device used to control the output voltage of a DC/DC
converter. The LM10010 outputs a DC current
inversely proportional to a 6-bit input word. This
current DAC output connects to the feedback pin of a
regulator in order to adjust its output voltage to a
desired range and resolution set by the user. As the
6-bit word counts up, the output voltage is adjusted
higher based on the setting of the feedback resistors
in the converter.
1
2
•
•
•
Output Current Accuracy (-40°C to +125°C)
Input Voltage Range: 3V to 5.5V
6-Bit Current DAC That Connects Directly to
the Feedback Node of an External Regulator to
Provide Output Voltage Control
Precision Enable to Support Custom UVLO
WSON-10 3 mm x 3 mm Footprint, 0.5 mm
Pitch
Compatible With the TMS320C66XX DSP Smart
Reflex Technology
The LM10010 is designed to program point of load
regulators with adjustable resistor feedback networks
for VID (Voltage Identification).
APPLICATIONS
•
•
•
•
•
Broadband, Networking, and Wireless
Communications
Notebook and Palmtop Computers, PDAs
Portable Instruments
Battery-Powered Equipment
Powering Digital Loads With a 6-Bit, 4 Pin VID
Interface
Typical Application Circuit
HTSSOP-20
3V to 5.5V
LF
5,6,7
VIN
PVIN
CIN
RF
3
4
SW
CC3
AVIN
RFB1
LM21215A-1
FB
CSS
VOUT
COUT
EN
CF
optional
11-16
2 SS/
TRK
COMP
RC2
19
18
CC1 RC1
RFB2
CC2
1
PGOOD
SYNC
17
PGND AGND
20
8,9,10
3
CVDD
4
EN
VDD
IDAC_OUT
LM10010
VIDS
VIDC
VIDB
GND
1
VIDA
0 - 59.2 PA
2
VCORE
10
9
8
VID
Interface
7
WSON-10
3 mm x 3 mm
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM10010
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Connection Diagram
GND
1
10
VIDS
IDAC_OUT
2
9
VIDC
VDD
3
8
VIDB
EN
4
7
VIDA
NC
5
6
NC
DAP
Figure 1. Top View
WSON-10 3mm x 3mm
0.5mm pitch
Pin Descriptions
2
Pin No.
Name
Description
1
GND
Ground.
2
IDAC_OUT
3
VDD
4
EN
Precision enable input.
5
NC
No Connect.
6
NC
No Connect.
7
VIDA
VID digital input: Bit 0 when VIDS transitions low; Bit 3 when VID transitions high.
8
VIDB
VID digital input: Bit 1 when VIDS transitions low; Bit 4 when VID transitions high.
Output current DAC that connects to the feedback node of the regulator.
Positive supply input.
9
VIDC
VID digital input: Bit 2 when VIDS transitions low; Bit 5 when VID transitions high.
10
VIDS
VID select line: Transition low selects lower 3 bits, Transition high selects upper 3 bits.
DAP
DAP
Die Attach Pad. Not electrically connected to device, connect to system ground plane for reduced thermal
resistance.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
VDD, EN, IDAC_OUT
-0.3V to 6V
VIDA, VIDB, VIDC, VIDS
-0.3V to 6V
ESD Rating (3)
Human Body Model
2 kV
Storage Temperature
-65°C to +150°C
Junction Temperature
+150°C
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and conditions,
see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Operating Ratings
VDD
3.0V to 5.5V
IDAC_OUT
-0.3V to VDD-1.75V
VIDA, VIDB, VIDC, VIDS
-0.3V to 5.5V
EN
-0.3V to 5.5V
Junction Temperature
−40°C to +125°C
Ambient Temperature
−40°C to +125°C
WSON-10 Thermal Resistance (θJA) (1)
(1)
40°C/W
Junction to ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the
package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used.
Electrical Characteristics
Limits in standard type are for TJ = 25°C only. Limits appearing in boldface type apply over the full operating junction
temperature range (-40°C < TJ < +125°C). Unless otherwise noted, specifications apply to the Typical Application Circuit. See
(1)
.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD=5.0V, VEN=2.0V
250
280
µA
VDD=5.0V, VEN=2.0V, IFS
340
VDD=5.0V, VEN=0.0V
45
70
µA
2.65
2.95
V
Supply, UVLO, and Enable
IQ
UVLO
VEN
Quiescent current
Under voltage rising threshold
Under voltage falling threshold
2.2
2.45
Hysteresis
100
200
300
mV
Enable rising threshold
1.20
1.34
1.45
V
50
100
180
mV
Enable hysteresis
IEN
µA
Enable pullup current
V
2
µA
IDAC
ACC
LSB
Measured at full scale
2
6
-2
%
DAC step size
IFS /(2 -1)
940
nA
Output code
At startup
46d
Code
Output current
At startup
16
µA
IFS
Full-scale output current
VID[5:0] = 000000b
INL
Integral non-linearity
Default
(1)
Accuracy
59.2
-1
0.15
µA
1
LSB
All limits are ensured. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and
cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only. Limits appearing in boldface type apply over the full operating junction
temperature range (-40°C < TJ < +125°C). Unless otherwise noted, specifications apply to the Typical Application Circuit. See
(1)
.
Symbol
Parameter
DNL
Offset
VOUT_MAX
VID Logic Inputs
(2)
Conditions
Differential non-linearity
Min.
Typ.
Max.
Units
-0.25
0.06
0.25
LSB
Offset current
VID[5:0] = 111111b
60
Output compliance
VDD-VIDAC_OUT, VDD=3V
1.3
nA
1.75
V
0.4
V
(2)
VIL
Input voltage low
VIH
Input voltage high
1.1
V
IIL
Input current low
-5
µA
IIH
Input current high
tDEGLITCH
Input deglitch time
5
3.4
µA
µs
t1
VIDS delay time to VID latch
VIDS rising edge
1
µs
t2
Input hold time VIDA, VIDB, VIDC valid
VIDS edge
20
µs
t3
VIDS delay time to VID latch
VIDS falling edge
1
µs
t4
Input hold time VIDA, VIDB, VIDC valid
VIDS edge
20
t5
Delay to beginning of IDAC_OUT
transition
Measured from VIDS rising edge
10
t6
IDAC_OUT transition time
Time constant for exponential rise
40
µs
17
µs
µs
For VID timing, see Figure 2
Timing Diagram
IDAC_OUT Update
IDAC_OUT Update
t6
IDAC_OUT
Current
t6
t5
t5
VID[2:0] Capture
VID[5:3] Capture
t2
VID[5:3] Capture
t4
t3
VIDS
t1
t1
VIDA,
VIDB,
VIDC
Figure 2. Timing Diagram for LM10010 Communications
4
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Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5V. All graphs show junction temperature.
Supply Current
(Default Startup)
Supply Current
(Max IDAC Current)
270
360
350
VDD=5V
CURRENT ( A)
CURRENT ( A)
260
250
240
VDD=3V
VDD=5V
340
330
VDD=3V
230
320
220
310
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 3.
Figure 4.
Supply Current
(EN Low)
Output Compliance to Positive Rail
(VDD-VIDAC_OUT)
60
1.6
VDD=5V
50
VDD=5V
VOLTAGE (V)
CURRENT ( A)
1.5
40
1.4
1.3
VDD=3V
VDD=3V
1.2
30
-40 -20
1.1
-40 -20
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 5.
Figure 6.
Gain Error
IDAC Offset Current
1.0
65
0.8
64
0.6
63
0.4
62
CURRENT (nA)
GAIN ERROR (%)
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
0.2
0.0
-0.2
-0.4
61
60
59
58
-0.6
57
-0.8
56
-1.0
55
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 7.
-40 -20
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5V. All graphs show junction temperature.
UVLO Thresholds
EN (Enable) Threshold
1.45
1.40
Rising
Rising
VOLTAGE (V)
VOLTAGE (V)
2.7
2.6
2.5
2.4
Falling
2.3
-40 -20
1.35
1.30
1.25
1.20
Falling
1.15
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 9.
Figure 10.
Differential Non-Linearity
DIFFERENTIAL NON-LINEARITY (LSB)
INTEGRAL NON-LINEARITY (LSB)
Integral Non-Linearity
125°C
0.10
85°C
0.05
0.00
-0.05
25°C
-0.10
-40°C
-0.15
0
10
20
30 40
CODES
50
60
0.08
0.06
125°C
25°C
0.04
0.02
0.00
-0.02
-0.04
70
Figure 11.
6
-40°C
85°C
0
10
20
30 40
CODES
50
60
70
Figure 12.
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BLOCK DIAGRAM
Edge-Detector
VIDS
Logic
Receiver
Logic
Receiver
3 Ps
deglitch
Update DAC
fall
D
VIDC
3 Ps
deglitch
rise
6 Ps
deglitch
rise
Q
VID[5]
R Q
UVLO
D
fall
Q
VID[2]
R Q
UVLO
D
VIDB
Logic
Receiver
3 Ps
deglitch
rise
Q
VID[4]
R Q
UVLO
D
fall
Q
VID[1]
R Q
UVLO
D
VIDA
Logic
Receiver
3 Ps
deglitch
rise
VID[3]
R Q
UVLO
D
fall
VDD
Q
UVLO
(VDD > 2.65V)
Q
VID[0]
6 bit
IDAC
R Q
PRECISION
ENABLE
(1.34V)
IDAC_OUT
(0 - 59.2 uA)
UVLO
DISABLE
EN
Slew
Limit
Bandgap
Core
IREF
+
-
GND
Figure 13. LM10010 Block Diagram
FUNCTIONAL DESCRIPTION
General
The LM10010 is a precision current DAC used for controlling any point of load regulator with an adjustable
resistor feedback network. Four communication lines are used to write to a 6-bit IDAC value. The output of the
IDAC is used to send current to the feedback node of a regulator, adjusting the output voltage. With this method,
it is possible to precisely control the output voltage of the regulator.
An enable pin (EN) is provided to allow for a reduced quiescent current when not in use. Also, the VDD line is
monitored so that an under-voltage event will shut down the device.
The device is available in a 10-pad No-Pullback Leadless Leadframe Package (WSON-10). The LM10010 can
be used in numerous applications with regulators from 3.0V to 5.5V supplies. A block diagram of the LM10010 is
shown in Figure 13 above.
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Theory of Operation
The LM10010 can be thought of as a D/A converter, converting the VID communication to analog outputs. In this
device, the output is a current DAC (IDAC_OUT), which is connected to the feedback node of a slave regulator.
Therefore, all VID data words are decoded into a 6-bit current DAC output. The impedance of the feedback node
at DC appears as the top feedback resistor. This is because the control loop of the slave regulator effectively
maintains a constant current/voltage across the bottom feedback resistor, and creates low impedance at the
VOUT node. Therefore, as more current is sourced into the feedback node, the more the output voltage is
reduced. See Figure 14.
Slave Regulator
VOUT
+
+
FB
IRFB1
RFB1
LM10010
IDAC_OUT
LM10010
VRFB1
-
+
-
VOUT
+
RFB2
VID
IRFB2
VFB
-
-
IDAC_OUT
Figure 14. Output voltage is controlled via current injection into the feedback node
Current DAC
The LM10010 current DAC is based on a low voltage bandgap reference setting a current through a precision
adjustable resistor. This bandgap is trimmed for precision and gives excellent performance over temperature.
The output current has a maximum full-scale range of 59.2 µA and is adjustable with the 6-bit VID word. This
allows for 64 settings, with a resolution of 940 nA. The current DAC also has a slew limit to prevent abrupt
changes in the output. As the VID data lines are set for the output voltage for the regulator, deglitch filters
provide a small delay and the output current rises with a 1-e-t function that can be identified by a time constant.
VID Programming
Four pins are used to communicate with the LM10010. VIDC, VIDB, and VIDA are data lines, while VIDS is a
latching strobe that programs in the LM10010 data. As shown in the Timing Diagram in Figure 2, the falling edge
of VIDS latches in the data from VIDC, VIDB, and VIDA as the lower three LSB of the IDAC value. After a
minimum hold time, the rising edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the upper three
LSB of the IDAC value. Internally, a delay on VIDS allows for the setting of all VID lines simultaneously.
The VID data word is set so that the lowest output current is seen at the highest VID data word (59.2 µA at a
code of 0d). Conversely, the lowest current is seen at the highest VID data word (0 µA at 63d). During VID
operation with the regulator, this will translate to the lowest output voltage with the lowest VID word, and the
highest output voltage with the highest VID word. The communications pins can be used with a low voltage
microcontroller, with a maximum VIL of 0.4V and a minimum VIH of 1.1V.
Upon startup, the IDAC is set at a code of 46d, which translates to approximately 16 µA. This default startup
value is trimmed at final test. For applications with a different default output current at startup, please contact
Texas Instruments.
8
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Deglitch Time
The four digital input pins all have deglitch filters which prevent transient noise from affecting the operation of the
LM10010. These filters will also impart a small delay to the digital signal. On the VIDS latching signal, there is an
additional delay. As mentioned previously, this allows for the VID data lines and the VIDS strobe to be set
simultaneously without the need for setup time.
Enable Pin and UVLO
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.34V (typical). The EN pin
has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.24V (typical). If EN is
not used, it can be left open, and will be pulled high by an internal 2 µA current source. Since the enable pin has
a precise turn-on threshold it can be used along with an external resistor divider network from VIN to configure
the device to turn-on at a precise input voltage.
The LM10010 has a built-in under-voltage lockout (UVLO) protection circuit that keeps the device from operating
until the input voltage reaches 2.65V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the
device from responding to power-on glitches during startup. Note that the enable and the UVLO are functionally
the same as a reset. Bringing the device back from a low enable setting or from a VDD under-voltage event will
reset the device back to its startup default setting.
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APPLICATION INFORMATION
Design Example
In this example, an LM21215A-1 is used as the buck regulator to provide CVDD to the TMS320C6670 or
TMS320C6678 from 0.7V to 1.1V and an output current of up to 15A. The LM10010 in conjunction with VID
control from the DSP, provides control of the output voltage within this range with 6 bits of resolution. For this
example, the 400 mV of voltage range translates to a 6.4 mV resolution in the control of the regulator output
voltage. In this calculation, 1% resistor values are used. A schematic for this example is shown in the circuit of
Figure 15.
HTSSOP-20
VIN
3V to 5.5V
LF
5,6,7
PVIN
CIN
RF
3
4
SW
CC3
AVIN
RFB1
LM21215A-1
FB
CSS
0.7V to 1.1V
COUT
EN
CF
optional
VOUT
11-16
2 SS/
TRK
COMP
RC2
19
CC1 RC1
18
RFB2
CC2
17
1
PGOOD
SYNC
PGND AGND
20
8,9,10
CBYPASS
3
VDD
IDAC_OUT
CVDD
4
0 - 59.2 PA
2
DVDD18
EN
LM10010
VIDS
VIDC
VIDB
GND
1
VIDA
10
CVDD
RPU1:4
9
8
7
VCNTL[3]
VCNTL[2]
VCNTL[1]
TMS320C6670/
TMS320C6678
VCNTL[0]
WSON-10
3 mm x 3 mm
Figure 15. Typical Application Circuit
Setting the VOUT Range and LSB
Looking at the Typical Application Circuit in Figure 15, the following equation defines VOUT of a given regulator
(valid for VOUT > VFB):
(1)
Here, the output voltage is a function of the resistor divider from RFB1 and RFB2. Additionally, there is a current
supplied by the LM10010 that helps drive the feedback resistor RFB2, thus lowering the necessary current
supplied through RFB1, and lowering VOUT.
10
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The change in the output voltage can be analyzed based on the resolution of the current DAC from the LM10010
compared to the desired resolution of the output swing of the regulator. RFB1 is designed to provide the desired
LSB for VOUT with the equation:
(2)
Based on the desired default VOUT (with IDAC_OUT = 0 µA), RFB2 can be solved from Eq. 1 above.
Example Solution
Assuming a 400 mV output range, 64 VID codes, and an IDAC LSB of 0.940 µA, it is desired to have a VOUT with
an LSB of 6.4 mV and a default value of 1.1V using an LM21215A-1 regulator:
(3)
(4)
(5)
(6)
Using 1% resistor values, RFB1 can be set to 6.81 kΩ and RFB2 can be set to 8.06 kΩ. This will yield a regulator
output range of 0.704V to 1.107V. At startup, the code of the LM10010 will be 46d (101110b) and will output a
15.97 µA. This will give an output voltage of approximately 1.0V (0.998V) when power is applied and both the
LM10010 and the LM21215A-1 come out of UVLO. Of course, values calculated here will be dependent on the
accuracy of the regulator, the LM10010 IDAC, and the resistor values used in the circuit.
Table 1 shows the codes and some of the resultant values of the IDAC current and the corresponding regulator
output voltage for the previous example.
Table 1. VID Codes with IDAC Current and Regulator Voltage for the Example
VID Code
IDAC Current (µA)
Regulator Voltage (V)
000000b
59.20
0.7038
000001b
58.26
0.7102
000010b
57.32
0.7166
000011b
56.38
0.7230
...
111100b
2.82
1.0878
111101b
1.88
1.0941
111110b
0.94
1.1005
111111b
0.00
1.1069
PC Board Guidelines
The following guidelines should be followed when designing the PC board for the LM10010:
• Place the LM10010 close to the regulator feedback pin to minimize the FB trace length.
• Place a small capacitor, CVDD, (1 nF) directly adjacent to the VDD and GND pins of the LM10010 to help
minimize transients which may occur on the input supply line.
• The high current path from the board’s input to the load and the return path should be parallel and close to
each other to minimize loop inductance.
• The ground connections for the various components around the LM10010 should be connected directly to
each other, and to the LM10010’s GND pins, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
• For additional information about the operation of the regulator, please consult the respective datasheet and
application notes on the respective evaluation boards.
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM10010SD/NOPB
ACTIVE
WSON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L254B
LM10010SDX/NOPB
ACTIVE
WSON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L254B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM10010SD/NOPB
WSON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LM10010SDX/NOPB
WSON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM10010SD/NOPB
WSON
DSC
10
1000
210.0
185.0
35.0
LM10010SDX/NOPB
WSON
DSC
10
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
SDA10A (Rev A)
www.ti.com
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