Lyontek LY62W1024SL-55SLI.T 128k x 8 bit low power cmos sram Datasheet

®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 1.6
Rev. 1.7
Rev. 1.8
Description
Initial Issue
Revised ISB1 LL/LLI-LLE(max)= 50/100 μA => 20/50 μA
IDR LL/LLI-LLE(max)= 20/40 μA => 12/30 μA
Added SL Spec.
Revised typos in FEATURES
Revised ISB1/IDR(MAX.)
Added ISB1/IDR values when TA = 25℃ and TA = 40℃
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package available
Added packing type in ORDERING INFORMATION
Revised VTERM to VT1 and VT2
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION in page 10/11/12/13
Revised ORDERING INFORMATION in page 14
Deleted E Grade
Revised PIN CONFIGURATION in page 2
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
Issue Date
Aug.28.2005
Mar.30.2006
Nov.2.2007
May.6.2008
Mar.30.2009
May.7.2010
Aug.30.2010
Aug.9.2011
Apr.06.2012
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
FEATURES
GENERAL DESCRIPTION
„ Fast access time : 35/55/70ns
„ Low power consumption:
Operating current : 12/10/7mA (TYP.)
Standby current : 1μA (TYP.) LL-version
0.8μA (TYP.) SL-version
„ Single 2.7V ~ 5.5V power supply
„ All outputs TTL compatible
„ Fully static operation
„ Tri-state output
„ Data retention voltage : 1.5V (MIN.)
„ Green package available
„ Package : 32-pin 450 mil SOP
32-pin 600 mil P-DIP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
The LY62W1024 is a 1,048,576-bit low power
CMOS static random access memory organized as
131,072 words by 8 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The LY62W1024 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The LY62W1024 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
LY62W1024
LY62W1024(I)
Operating
Temperature
0 ~ 70℃
-40 ~ 85℃
Vcc Range
Speed
2.7 ~ 5.5V
2.7 ~ 5.5V
35/55/70ns
35/55/70ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A16
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.)
Operating(Icc,TYP.)
1µA(LL)/0.8µA(SL)
12/10/7mA
1µA(LL)/0.8µA(SL)
12/10/7mA
128Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A16
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#, CE2
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY62W1024
Rev. 1.8
128K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
PS: All pin out definition are relative with “Lyontek logo” orientation.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
Operating Temperature
TA
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
X
L
L
L
CE2
X
L
H
H
H
OE#
X
X
H
L
X
WE#
X
X
H
H
L
I/O OPERATION
High-Z
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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SUPPLY CURRENT
ISB1
ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
®
LY62W1024
Rev. 1.8
128K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
VCC
2.7
*1
Input High Voltage
VIH
0.7*Vcc
*2
Input Low Voltage
VIL
- 0.2
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
-1
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
-1
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
2.4
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min.
- 35
CE# = VIL and CE2 = VIH ,
ICC
- 55
II/O = 0mA
- 70
Other pins at VIL or VIH
Average Operating
Power supply Current
Cycle time = 1µs
CE# = 0.2V and CE2≧VCC-0.2V,
ICC1
II/O = 0mA
Other pins at 0.2V or VCC - 0.2V
LL
LLI
CE# ≧VCC-0.2V
*5
25℃
SL
Standby Power
or CE2≦0.2V
ISB1
*5
SLI
Supply Current
Others at 0.2V or
40℃
VCC - 0.2V
SL
SLI
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
*4
MAX.
5.5
VCC+0.3
0.6
1
UNIT
V
V
V
µA
-
1
µA
2.7
12
0.4
80
V
V
mA
10
60
mA
7
50
mA
1
10
mA
1
1
0.8
1
0.8
0.8
15
30
2
2
7
10
µA
µA
µA
µA
µA
µA
TYP.
3.0
-
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM. LY62W1024-35 LY62W1024-55 LY62W1024-70 UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
tRC
35
55
70
ns
tAA
35
55
70
ns
tACE
35
55
70
ns
tOE
25
30
35
ns
tCLZ*
10
10
10
ns
tOLZ*
5
5
5
ns
tCHZ*
15
20
25
ns
tOHZ*
15
20
25
ns
tOH
10
10
10
ns
SYM. LY62W1024-35 LY62W1024-55 LY62W1024-70
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
tWC
35
55
70
tAW
30
50
60
tCW
30
50
60
tAS
0
0
0
tWP
25
45
55
tWR
0
0
0
tDW
20
25
30
tDH
0
0
0
tOW*
5
5
5
tWHZ*
15
20
25
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
CE2
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
LL
LLI
VCC = 1.5V
CE# ≧ VCC - 0.2V
SL
IDR
or CE2 ≦ 0.2V
SLI
Other pins at 0.2V or VCC-0.2V SL
SLI
See Data Retention
tCDR
Waveforms (below)
tR
25℃
40℃
MIN.
1.5
-
TYP.
0.5
0.5
0.4
0.5
0.4
0.4
MAX.
5.5
12
30
2
2
5
8
UNIT
V
µA
µA
µA
µA
µA
µA
0
-
-
ns
tRC*
-
-
ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE2
tR
CE2 ≦ 0.2V
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
Θ
INCH.(BASE)
0.120(MAX)
0.004(MIN)
0.116(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
0.445±0.006
0.555±0.025
0.050(TYP)
0.033±0.017
0.055±0.008
0.026(MAX)
0.004(MAX)
o
o
0 -10
MM(REF)
3.048(MAX)
0.102(MIN)
2.946(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
11.303±0.152
14.097±0.635
1.270(TYP)
0.838±0.432
1.397±0.203
0.660(MAX)
0.101(MAX)
o
o
0 -10
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
32 pin 600 mil P-DIP Package Outline Dimension
UNIT
SYM.
A1
A2
B
D
E
E1
e
eB
L
S
Q1
INCH(BASE)
MM(REF)
0.015(MIN)
0.155±0.005
0.018±0.005
1.650±0.01
0.600±0.010
0.545±0.005
0.100(TYP)
0.650±0.020
0.158±0.043
0.075±0.010
0.070±0.005
0.381(MIN)
3.937±0.127
0.457±0.127
41.910±0.254
15.240±0.254
13.843±0.127
2.540(TYP)
16.510±0.508.
4.013±1.092
1.905±0.254
1.778±0.127
Note : D/E1/S dimension do not include mold flash.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.047 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.724 ±0.008
0.315 ±0.008
0.020 (TYP)
0.787 ±0.008
0.024 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.20 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
18.40 ±0.20
8.00 ±0.20
0.50 (TYP)
20.00 ±0.20
0.60 ±0.10
0.08 ±0.10
0.08 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY62W1024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.8
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.049 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.465 ±0.008
0.315 ±0.008
0.020 (TYP)
0.528±0.008
0.02 ±0.008
0.031 ±0.005
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.25 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
11.80 ±0.20
8.00 ±0.20
0.50 (TYP)
13.40 ±0.20.
0.50 ±0.20
0.8 ±0.125
0.076 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
LY62W1024
Rev. 1.8
128K X 8 BIT LOW POWER CMOS SRAM
36 ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
®
LY62W1024
Rev. 1.8
128K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14
®
LY62W1024
Rev. 1.8
128K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
15
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