Semiconductor ML9471 FEDL9471-01 Issue Date: Aug. 21, 2008 1/3, 1/4, 1/5 Duty 80 Output LCD Driver GENERAL DESCRIPTION The ML9471 is a LCD driver for dynamic display providing 3-duty-switchable pins (1/3, 1/4, 1/5 duty). It can directly drive LCDs of up to 400, 320 and 240 segments when 1/5, 1/4 and 1/3 duty are selected respectively. FEATURES • Operating range Supply voltage : 3.0 to 5.5 V Operating temperature range : 40 to + 105C • Segment output : 80 pins 1/5 duty : Up to 400 segments can be displayed. 1/4 duty : Up to 320 segments can be displayed. 1/3 duty : Up to 240 segments can be displayed. • Serial transfer clock frequency : 4 MHz • Serical interface with CPU :Through three input pins (DATA_IN, LOAD, and CLOCK) • Built-in oscillator circuit for COMMON signals • One-to-one correspondence between input data and output data When input data is at “H” level : Display goes on. When input data is at “L” level : Display goes off. • The entire display can be turned off. (BLANK pin) • Package options 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: ML9471TB) 1/20 FEDL9471-01 LAPIS Semiconductor ML9471 BLOCK DIAGRAM SEG1 SEG80 80-Dot Segment Driver BLANK 80-Ch Data Selector LOAD 80 80 80 80 80 80-Bit Latch 5 80-Bit Latch 4 80-Bit Latch 3 80-Bit Latch 2 80-Bit Latch 1 LATCH SELECTOR 80 DATA_IN 88-Stage Shift Register CLOCK OSC_OUT OSC_OUT OSC_IN OSC TIMING GENERATOR VLC1 VLC2 VLC3 DSEL1 DSEL2 COMMON Driver COM1 COM2 COM3 COM4 VDD COM5 GND 2/20 FEDL9471-01 LAPIS Semiconductor ML9471 SEG28 SEG 27 SEG 26 78 77 76 SEG 31 81 SEG 30 SEG32 82 SEG29 SEG33 83 79 SEG34 84 80 SEG36 SEG35 87 85 SEG37 88 86 SEG39 SEG38 89 92 SEG 41 SEG42 93 SEG40 SEG43 94 90 SEG44 95 91 SEG46 SEG45 96 SEG48 SEG47 97 99 98 SEG50 SEG49 100 PIN CONFIGURATION (TOP VIEW) 18 58 SEG8 SEG69 19 57 SEG7 SEG70 20 56 SEG6 SEG71 21 55 SEG5 SEG72 22 54 SEG4 SEG73 23 53 SEG3 SEG74 24 52 SEG2 SEG75 25 51 SEG1 50 SEG9 SEG68 COM1 59 49 17 48 SEG10 SEG67 COM2 60 COM3 16 47 SEG11 SEG66 COM4 61 46 15 COM5 SEG12 SEG65 45 62 V LC1 14 44 SEG13 SEG64 VLC2 63 43 13 42 SEG14 SEG63 VLC3 64 GND 12 41 SEG15 SEG62 OS C_IN 65 40 11 39 SEG16 SEG61 OSC_OUT 66 OSC_OUT 10 38 SEG17 SEG60 37 67 DSEL2 9 DSEL1 SEG18 SEG59 36 68 BLANK 8 35 SEG19 SEG58 DATA_IN 69 34 7 CLO CK SEG20 SEG57 33 70 32 6 VDD SEG21 SEG56 LOA D 71 31 5 30 SEG22 SEG55 NC 72 SEG80 4 29 SEG23 SEG54 28 73 SEG79 3 SEG78 SEG24 SEG53 27 SEG25 74 26 75 2 SEG77 1 SEG52 SEG76 SEG51 100-Pin Plastic TQFP 3/20 FEDL9471-01 LAPIS Semiconductor ML9471 PIN DESCRIPTION Symbol Type Description OSC_IN OSC_OUT OSC_OUT I O O Pins for oscillation. The oscillator circuit is configured by externally connecting two resistors and a capacitor. Make the wiring length as short as possible, because the resistor connected to the OSC_IN pin has a higher value and the circuit is susceptible to external noise. DATA_IN I Serial data input pin. The display goes on when input data is at a “H” level, and it goes off when input data is at “L” level. CLOCK I Shift clock input pin. Data from the DATA_IN pin is transferred in synchronization with the rising edge of the shift clock. LOAD I Load signal input pin. Serially input data is transferred to the 80-bit latch at “H” level of this load signal, then held at “L” level. BLANK l Input pin that turns off all segments. The entire display goes off when “L” level is applied to this pin. The display returns to the previous state when “H” level is applied. DSEL1 DSEL2 I I Input pins to select 1/3, 1/4, or 1/5 duty. Following shows how each duty is selected. DSEL2 DSEL1 Duty selected L L 1/3 L H 1/4 H X 1/5 X: Don’t care COM1 to COM5 O Display output pins for LCD. These pins are connected to the COMMON side of the LCD panel. SEG1 to SEG80 O Display output pins for LCD. Theses pins are connected to the SEGMENT side of the LCD panel. For the correspondence between the output of these pins and input data, see the “Data Structure” Section. VLC1, VLC2, VLC3 — Bias pins for LCD driver. Through these pins, bias voltages for the LCD are externally supplied. The bias potential must meet the following condition: VDD > VLC1 VLC2 > VLC3 =GND VDD, GND — Supply voltage pin and ground pin. Note: Built-in schmitt circuit is used for all input pins. 4/20 FEDL9471-01 LAPIS Semiconductor ML9471 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD Ta = 25°C –0.3 to 6.5 V VI Ta = 25°C –0.3 to VDD+0.3 V TSTG — –55 to 150 °C Power Dissipation PD Ta < 105°C 700 mW Output Current IO — –2.0 to 2.0 mA Supply Voltage Input Voltage Storage Temperature RECOMMENDED OPERATING CONDITIONS Symbol Condition Range Unit Supply Voltage Parameter VDD VLC3 = GND 3.0 to 5.5 V CLOCK Frequency fCP — 1 to 4 MHz Operating Temperature Ta — –40 to 105 °C Oscillator Circuit Parameter Symbol Applicable pin Condition Min. Max. Unit Oscillator Resistance R0 OSC_OUT — 20 120 k Oscillator Capacitance C0 OSC_OUT — 0.00047 0.01 F Current Limiting Resistance R1 OSC_IN — 62 360 k 25 250 Hz Common Signal Frequency fCOM COM1 to COM5 — Note: See Section, “Reference Data”, for the resistor and capacitor values in the table. RC Values in Oscillator Circuit Symbol Applicable pin 1/3 duty 1/4 duty 1/5 duty Unit Oscillator Resistance Parameter R0 OSC_OUT 68 51 43 k Oscillator Capacitance C0 OSC_OUT 0.001 0.001 0.001 F Current Limiting Resistance R1 OSC_IN 220 160 130 k Example of an oscillator circuit: 5/20 FEDL9471-01 LAPIS Semiconductor ML9471 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 3.0 to 5.5 V, Ta = –40 to +105°C, unless otherwise specified) Parameter Symbol Applicable pin Condition Min. Max. Unit “H” Input Voltage 1 VIH1 CLOCK, OSC_IN — 0.85 VDD VDD V “L” Input Voltage 1 VIL1 CLOCK, OSC_IN — GND 0.15 VDD V “H” Input Voltage 2 VIH2 *1 — 0.8 VDD VDD V “L” Input Voltage 2 VIL2 *1 — GND 0.2 VDD V “H” Input Current IIH All input pins VDD = 5.5 V, VI = VDD — 10 A IIL All input pins VDD = 5.5 V, VI = 0 V “L” Input Current IO = 100 A VOC0a COMMON Output Voltage VOC1 VOC2 COM1 - COM5 VDD = 3.0 V VOC3 Segment Output Voltage VOS1 VOS2 SEG1 - SEG80, VDD = 3.0 V VOS3 Supply Current *1 *2 *3 *4 *5 IDD VDD — A — V IO = 100 A *3 VLC1 1 VLC1 +1 V IO = 100 A *4 VLC2 1 VLC2 +1 V IO = +100 A *5 — VLC3 +1 V VDD 1 — V IO = 10 A VOS0 10 VDD 1 IO = 10 A *3 VLC1 1 VLC1 +1 V IO = 10 A *4 VLC2 1 VLC2 +1 V IO = +10 A *5 — VLC3 +1 V — 0.5 mA VDD = 5.0 V, no load. *2 Applies to all input pins excluding CLOCK and OSC_IN. R0 = 51 k R1 = 160 k C0 = 0.001 F VLC1 = 2.0V VLC2 = 1.0V VLC3 = 0V 6/20 FEDL9471-01 LAPIS Semiconductor ML9471 AC Characteristics (VDD =3.0 to 5.5V, Ta = –40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Clock “H” Time tWHC — 70 — — ns Clock “L” Time tWLC — 70 — — ns Data Set-up Time tDS — 50 — — ns Data Hold Time tDH — 50 — — ns Load “H” Time tWHL — 100 — — ns Clock-to-load Time tCL — 100 — — ns Load-to-Clock Time tLC — 100 — — ns Clock Rise time, Fall time tR1, tF1 — — — 50 ns OSC_IN Input Frequency fOSC — — — 20 kHz OSC_IN “H” Time tWHO — 20 — — s OSC_IN “L” Time tWLO — 20 — — s tR2, tF2 — — — 100 ns OSC_IN Rise time, Fall time 7/20 FEDL9471-01 LAPIS Semiconductor ML9471 POWER-ON/OFF TIMING * VLC1, VLC2 are applied when VDD is applied to external bias resistor. INITIAL SIGNAL TIMING VDD BLANK * Once VDD is applied, BLANK should be applied to ‘L’ level to make all SEGMENTs off until first group of display data is latched. 8/20 FEDL9471-01 LAPIS Semiconductor ML9471 FUNCTIONAL DESCRIPTION Operation As shown in “Data Structure”, the display data consists of the data field corresponding to the output for turning the segments on or off and the select field that selects field that selects the input block of data. Data input to the DATA_IN pin is loaded into the 88-bit shift register, transferred to the 80-bit latch while the load signal is at “H” level, and then output via the 80-dot segment driver. Data Structure Input data Correspondence between select bits and COM1 to COM5 C5 C4 C3 C2 C1 Description 0 0 0 0 1 Display data corresponding to COM1 0 0 0 1 0 Display data corresponding to COM2 0 0 1 0 0 Display data corresponding to COM3 0 1 0 0 0 Display data corresponding to COM4 0 0 0 0 Display data corresponding to COM5 1 Notes: 1. 2. Arbitrary data can be set for the dummy bits. Select bit, C1 to C5, selects 80-bit latches that correspond to COM1 to COM5, respectively. Therefore, if “1” is set for more than one select bit, data is set to all the corresponding 80-bit latches. Example: If “1” is set to all the select bits C1 to C5, the display data of D1 to D80 is set to all the 80-bit latches that correspond to COM1 to COM5. 9/20 FEDL9471-01 LAPIS Semiconductor ML9471 COM1 – COM5 Timing Chart: VDD COM1 VLC1 VLC2 VLC3 VDD COM2 VLC1 VLC2 VLC3 VDD COM3 VLC1 VLC2 VLC3 1/3 DUTY COM TIMING 10/20 FEDL9471-01 LAPIS Semiconductor ML9471 SEGn True Value Table: LATCH1 LATCH2 LATCH3 LATCH4 LATCH5 COM1 COM2 COM3 COM4 COM5 SEGn 0 0 0 0 1 “H” “L” “M2” “M1” “M2” “M1” “M2” “M1” “M2” “M1” “M1” “M2” “M2” “M1” “H” “L” “M2” “M1” “M2” “M1” “M2” “M1” “M1” “M2” “M2” “M1” “M2” “M1” “H” “L” “M2” “M1” “M2” “M1” “M1” “M2” “M2” “M1” “M2” “M1” “M2” “M1” “H” “L” “M2” “M1” “M1” “M2” “M2” “M1” “M2” “M1” “M2” “M1” “M2” “M1” “H” “L” “L” “H” *Note: “H” = VDD; “M1” = VLC1; “M2” = VLC2; “L” = VLC3=GND 11/20 FEDL9471-01 LAPIS Semiconductor ML9471 Timing Chart FOR 1/3 DUTY DRIVE MODE: 12/20 FEDL9471-01 LAPIS Semiconductor ML9471 Timing Chart FOR 1/4 DUTY DRIVE MODE: VDD COM1 VLC1 VLC2 VLC3 COM1 COM2 COM3 COM4 VDD VLC1 COM2 VLC2 VLC3 VDD COM3 VLC1 VLC2 VLC3 VDD COM4 VLC1 VLC2 VLC3 VDD SEG1 VLC1 VLC2 VLC3 VDD SEG2 VLC1 VLC2 VLC3 13/20 FEDL9471-01 LAPIS Semiconductor ML9471 VDD COM1 VLC1 VLC2 VLC3 VDD SEG2 SEG1 Timing Chart FOR 1/5 DUTY DRIVE MODE: COM1 COM2 COM3 COM4 COM5 VLC1 COM2 VLC2 VLC3 VDD COM3 VLC1 VLC2 VLC3 VDD COM4 VLC1 VLC2 VLC3 VDD COM5 VLC1 VLC2 VLC3 VDD SEG1 VLC1 VLC2 VLC3 VDD SEG2 VLC1 VLC2 VLC3 14/20 FEDL9471-01 LAPIS Semiconductor ML9471 APPLICATION CIRCUITS (For 1/4 duty) 15/20 FEDL9471-01 LAPIS Semiconductor ML9471 REFERENCE DATA The data shown in this section is for reference (a metal film resistor and a film capacitor are used). Resistor and capacitor values must be determined based on experiments. Use the following expression to convert oscillation frequency to COMMON frame frequency (or vice versa): fCOM=fOSC × Duty/16 fCOM fOSC Duty : COMMON frame frequency : Oscillation frequency : e.g., 1/4 for 1/4 duty For example, if fCOM=100Hz at 1/5 duty, the oscillation frequency is fOSC =8000Hz. Ta=25°C R0=51k R1=160k C0=0.001µF 1/4 duty I DD vs. VDD 0.7 0.6 IDD [mA] 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VDD [V] 16/20 FEDL9471-01 LAPIS Semiconductor ML9471 fOSC---R0,C0 ML9471 Oscillator Frequency Result VDD=3V 25°C fOSC[kHz] 100.00 10.00 0.00047µF | 62k 0.00047µF | 360k 0.01µF | 62k 0.01µF | 360k 1.00 0.10 0 25 50 75 100 125 150 R0[k] ML9471 Oscillator Frequency Result VDD=5.5V 25°C 100.00 fOSC[kHz] 10.00 0.00047µF | 62k 0.00047µF | 360k 0.01µF | 62k 0.01µF | 360k 1.00 0.10 0 25 50 75 100 125 150 R0[k] 17/20 FEDL9471-01 LAPIS Semiconductor ML9471 PACKAGE DIMENSIONS (Unit: mm) TQFP100-P-1414-0.50-K Mirror finish 5 Package material Lead frame material Lead finish Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Sn-2Bi (Bi 2% typ.) Solder plating (t5μm) 0.55 TYP. 1/Jul. 18, 2007 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/20 FEDL9471-01 LAPIS Semiconductor ML9471 REVISION HISTORY Document No. Date Page Previous Current Edition Edition Description PEDL9471-01 Dec. 15, 2006 – – Preliminary edition 1 PEDL9471-02 Jan. 15, 2007 – – Preliminary edition 2 PEDL9471-03 Jan. 9, 2008 – – Preliminary edition 3 FEDL9471-01 Aug. 21, 2008 – – Final edition 1 19/20 FEDL9471-01 LAPIS Semiconductor ML9471 NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. 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