ON NCP439FCT2G 2a very low ron switches at low vin voltage Datasheet

NCP439
2A Very Low Ron Switches
at Low Vin Voltage
The NCP439 is a very low Ron MOSFET controlled by external
logic pin, allowing optimization of battery life, and portable device
autonomy.
This load switch is a best in class in term of RDS(on) optimization at
low VIN voltage.
Due to a current consumption optimization with PMOS structure,
leakage currents are eliminated by isolating connected IC’s on the
battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output.
Proposed in wide input voltage range from 1.0 V to 3.6 V, and a very
small 0.96 x 0.96 mm WLCSP4, 0.5 mm pitch.
http://onsemi.com
MARKING
DIAGRAM
1
XX
WLCSP4
CASE 567FG
XX
A
WL
YY
WW
G
Features
•
•
•
•
•
•
•
1 V – 3.6 V Operating Range
37 mW P MOSFET at 1.8 V
DC Current Up to 2 A
Output Auto−Discharge
Active High EN Pin
WLCSP4 0.96 x 0.96 mm
This is a Pb−Free Device
PIN DIAGRAM
Typical Applications
•
•
•
•
•
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
1
2
A
OUT
IN
B
GND
EN
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
DCDC Converter
A2
or
LDO
ENx
B2
IN
OUT
EN
GND
A1
IC’n
B1
EN
0
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 0
1
Publication Order Number:
NCP439/D
NCP439
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2
POWER
Load−switch input voltage; connect a 0.1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND
B1
POWER
Ground connection.
EN
B2
INPUT
OUT
A1
OUTPUT
Enable input, logic high turns on power switch.
Load−switch output; connect a 0.1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2
OUT: Pin A1
Gate driver and soft
start control
Control
logic
EN: Pin B2
EN block
GND: Pin B1
Figure 2. Block Diagram
http://onsemi.com
2
NCP439
MAXIMUM RATINGS
Symbol
VEN, VIN,
VOUT
VIN, VOUT
Rating
IN, OUT, EN, Pins
Unit
V
0 to + 4.0
V
ESD HBM
Human Body Model (HBM) ESD Rating are (Notes 1 and 2)
2500
V
ESD MM
Machine Model (MM) ESD Rating are (Notes 1 and 2)
250
V
2000
V
100
mA
Maximum Junction Temperature
−40 to + 125
°C
TSTG
Storage Temperature Range
−40 to + 150
°C
MSL
Moisture Sensitivity (Note 4)
Level 1
ESD CDM
LU
TJ
From IN to OUT Pins: Input/Output
Value
−0.3 to + 4.0
Charge Device Model (CDM) ESD Rating are (Notes 1 and 2)
Latch−up protection (Note 3)
− Pins IN, OUT, EN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.5 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins.
3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
Parameter
VIN
Operational Power Supply
VEN
Enable Voltage
Conditions
Min
Typ
1.0
0
Max
Unit
3.6
V
3.6
TA
Ambient Temperature Range
−40
CIN
Decoupling input capacitor
0.1
mF
COUT
Decoupling output capacitor
0.1
mF
RqJA
Thermal Resistance Junction to Air
IOUT
Maximum DC current
PD
Power Dissipation Rating (Note 6)
WLCSP package (Note 5)
25
+ 85
100
°C/W
2
TA ≤ 25°C
WLCSP package
0.5
TA = 85°C
WLCSP package
0.2
5. The RqJA is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (PD) is given by the following formula:
PD +
http://onsemi.com
3
T JMAX * T A
R qJA
°C
A
W
NCP439
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V
(Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VIN = 3.3 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
27
34
Unit
POWER SWITCH
VIN = 3.6 V
TA = 25°C
TJ = 125°C
VIN = 3.3 V
38
TA = 25°C
28
TJ = 125°C
VIN = 2.5 V
RDS(on)
40
TA = 25°C
Static drain−source on−state
resistance
31
TJ = 125°C
VIN = 1.8 V
37
TJ = 125°C
TA = 25°C
RDIS
Output discharge path
TA = 25°C
EN = low
VIN = 3.3 V
mW
45
52
54
TJ = 125°C
VIN = 1.0 V
39
45
TA = 25°C
VIN = 1.2 V
35
70
76
73
95
55
67
95
W
TIMINGS
TR
Output rise time
CLOAD = 1 mF,
RLOAD = 25 W From 10%
to 90% of VOUT
40
75
160
ms
TF
Output fall time
CLOAD = 1 mF,
RLOAD = 25 W (Note 7)
10
50
80
ms
Tdis
Disable time
Ton
Gate turn on
Enable time + Output rise
time
70
166
280
ms
Ten
Enable time
From EN low to high to
VOUT = 10% of fully on
30
66
120
ms
VIN = 3.3 V
From EN vil to 90% VOUT
8.7
ms
LOGIC PIN
VIH
High−level input voltage
VIN = 3.3 V
VIL
Low−level input voltage
VIN = 3.3 V
V
0.90
0.5
V
QUIESCENT CURRENT
IQ
Current consumption
VIN = 3.3 V,
EN = low, No
load
0.02
VIN = 3.3 V,
EN = high,
No load
1.6
1
mA
7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground
8. Guaranteed by design and characterization, not production tested.
http://onsemi.com
4
4
NCP439
TIMINGS
VIN
EN
VOUT
TEN
TDIS
TR
TOFF
TON
Figure 3. Enable, Rise and fall time
http://onsemi.com
5
TF
NCP439
TYPICAL CHARACTERISTICS
60
100
55
90
80
50
70
RDS(on) (mW)
RDS(on) (mW)
−40°C
0°C
25°C
85°C−
125°C
45
40
35
30
60
50
40
30
20
25
10
10
1.0
1.5
2.0
2.5
3.0
VIN (V)
3.5
4.0
0
1.0
5.0
Figure 4. RDS(on) (mW) vs VIN (V), No Load
4.0
3.0
2.5
3.0
VIN (V)
3.5
4
4.5
0.8
−40°C
25°C
85°C
0.7
0.6
2.5
IIN (mA)
0.5
2.0
1.5
0.4
0.3
1.0
0.2
0.5
0.1
0
1.0
1.5
2.0
2.5
3.0
VIN (V)
3.5
4.0
4.5
0
5.0
1
Figure 6. Quiescent Current (mA) vs VIN (V), In
Temperature
1.2
2
3
VIN (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0
1
4
5
Figure 7. Standby Current (mA) vs VIN (V), In
Temperature
Vih
Vil
1.1
VEN (V)
IIN (mA)
2.0
Figure 5. RDS(on) (mW) vs VIN (V) In
Temperature (5C), No Load
−40°C
25°C
85°C
3.5
1.5
2
3
4
VIN (V)
Figure 8. Enable Logic Threshold vs VIN
http://onsemi.com
6
5
NCP439
FUNCTIONAL DESCRIPTION
Overview
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path ( Pull down NMOS) stays activated as
long as EN pin is set at low level and VIN > 1.0 V.
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at 65 W.
The NCP439 is high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a range of battery from 1.0 V to 3.6 V.
Enable input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of VIN of
1.0 V and EN forced to high level.
CIN and COUT Capacitors
IN and OUT, 100 nF, at least, capacitors must be placed as
close as possible the part for stability improvement.
Auto Discharge
N−MOSFET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
APPLICATION INFORMATION
Power Dissipation
TJ + PD
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
P D + R DS(on)
PD
RDS(on)
IOUT
ǒIOUTǓ
TJ
RqJA
TA
R qJA ) T A
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
PCB Recommendations
2
The NCP439 integrates an up to 2 A rated PMOS FET, and
the PCB design rules must be respected to properly evacuate
the heat out of the silicon. By increasing PCB area,
especially around IN and OUT pins, the RqJA of the package
can be decreased, allowing higher power dissipation.
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current (A)
Figure 9. Routing Example 1 oz, 2 Layers, 1005C/W
http://onsemi.com
7
NCP439
Figure 10. Routing Example 2 oz, 4 Layers, 605C/W
ORDERING INFORMATION
Device
Auto Discharge
Marking
Package
Shipping†
NCP439FCT2G
Yes
AY
WLCSP 0.96 x 0.96 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
8
NCP439
PACKAGE DIMENSIONS
WLCSP4, 0.96x0.96
CASE 567FG
ISSUE O
ÈÈ
ÈÈ
D
PIN A1
REFERENCE
2X
0.05 C
2X
0.05 C
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
e
TOP VIEW
A2
0.05 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
A1
0.05 C
NOTE 3
4X
0.03 C
SEATING
PLANE
e
b
0.05 C A B
C
SIDE VIEW
A1
MILLIMETERS
MIN
MAX
0.54
0.63
0.22
0.28
0.33 REF
0.29
0.34
0.96 BSC
0.96 BSC
0.50 BSC
0.50
PITCH
e
B
PACKAGE
OUTLINE
4X
0.50
PITCH
0.25
DIMENSIONS: MILLIMETERS
A
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP439/D
Similar pages