TI1 ADS8506IDWG4 12-bit 40-ksps low power sampling analog-to-digital converter with internal reference and parallel/serial interface Datasheet

ADS8506
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH
INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
FEATURES
APPLICATIONS
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2
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40-kHz Min Sampling Rate
4-V, 5-V, and ±10-V Input Ranges
73.9-dB SINAD with 10-kHz Input
±0.45 LSB Max INL
±0.45 LSB Max DNL, 12-Bit No Missing Codes
±5-mV BPZ, ±0.5 PPM/°C BPZ Drift
SPI Compatible Serial Output With
Daisy-Chain (TAG), SPI Master/Slave Feature
Single 5-V Analog Supply
Pin-Compatible With ADS7806 and 16-Bit
ADS7807/8507
Uses Internal or External 2.5-V Reference
Low Power Dissipation
– 24 mW Typ, 30 mW Max at 40 KSPS
50-µW Max Power Down Mode
28-Pin SO Package
Full Parallel Interface
2's Comp or BTC Output Code
Industrial Process Control
Test Equipment
Medical Equipment
Data Acquisition Systems
Digital Signal Processing
Instrumentation
DESCRIPTION
The ADS8506 is a complete low power, single 5-V
supply, 12-bit sampling analog-to-digital (A/D)
converter.
It
contains
a
complete
12-bit
capacitor-based, successive approximation register
(SAR) A/D converter with sample and hold, clock,
reference, and data interface. The converter can be
configured for a variety of input ranges including ±10
V, 4 V, and 5 V. For most input ranges, the input
voltage can swing to 25 V or –25 V without damage
to the converter.
A SPI compatible serial interface allows data to be
synchronized to an internal or external clock. A full
parallel interface with BYTE select is also provided to
allow the maximum system design flexibility. The
ADS8506 is specified at 40 kHz sampling rate over
the industrial -40°C to 85°C temperature range.
Successive Approximation Register
Clock
CDAC
39.8 kΩ
Parallel
Data
R1IN
9.9 kΩ
R2IN
20 kΩ
40 kΩ
Comparator
CAP
Buffer
6 kΩ
REF
EXT/IN
Internal
+2.5 V Ref
Parallel
and
Serial
Data
Out
&
Control
PWRD
BYTE
BUSY
CS
R/C
SB/BTC
TAG
SDATA
DATACLK
REFD
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
QSPI, SPI are trademarks of Motorola.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ADS8506
www.ti.com
SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
INL
(LSB)
NO
MISSING
CODE
FULLSCALE
ERROR
(%)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ADS8506IB
±0.45
12
±0.25
-40°C to 85°C
SO-28
DW
ADS8506I
(1)
±0.9
12
±0.5
-40°C to 85°C
SO-28
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
ADS8506IBDW
Tube, 20
ADS8506IBDWR
ADS8506IDW
DW
Tape and Reel, 1000
Tube, 20
ADS8506IDWR
Tape and Reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Analog inputs
R1IN
±25 V
R2IN
±25 V
REF
+VANA + 0.3 V to AGND2 - 0.3 V
DGND, AGND2
Ground voltage differences
±0.3 V
VANA
6V
VDIG to VANA
0.3 V
VDIG
6V
Digital inputs
-0.3 V to +VDIG + 0.3 V
Maximum junction temperature
165°C
Storage temperature range
–65°C to 150°C
Internal power dissipation
700 mW
Lead temperature (soldering, 1.6 mm from case 10 seconds)
(1)
260°C
All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless
otherwise specified.
PARAMETER
TEST CONDITIONS
ADS8506IB
MIN
TYP
Resolution
ADS8506I
MAX
MIN
TYP
12
MAX
12
UNIT
Bits
ANALOG INPUT
Voltage ranges
See Table 1
-10
10
-10
10
0
5
0
5
0
4
0
4
V
Impedance
Capacitance
45
45
pF
THROUGHPUT SPEED
Conversion time
Complete cycle
Acquire and convert
Throughput rate
15
15
25
25
40
µs
kHz
DC ACCURACY
INL
(1)
2
Integral linearity error
-0.45
±0.15
0.45
-0.9
±0.15
0.9
LSB (1)
LSB means Least Significant Bit. One LSB for the ±10-V input range is 305 µV.
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SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless
otherwise specified.
PARAMETER
DNL
TEST CONDITIONS
Differential linearity error
No missing codes
ADS8506IB
ADS8506I
MIN
TYP
MAX
MIN
TYP
MAX
-0.45
±0.15
0.45
-0.9
±0.15
0.9
12
Transition noise (2)
12
0.1
Gain Error
-0.25
Full scale error drift
-0.5
±5
Full scale error (3) (4)
Ext. 2.5-V Ref
Full scale error drift
Ext. 2.5-V Ref
Bipolar zero error (3)
±10 V Range
Bipolar zero error drift
±10 V Range
Unipolar zero error (3)
0 V to 5 V, 0 V to 4 V Ranges
Unipolar zero error drift
0 V to 5 V, 0 V to 4 V Ranges
Recovery time to rated accuracy
from power down (5)
2.2-µF Capacitor to CAP
Power supply sensitivity
(VDIG = VANA = VS)
+4.75 V < VS < +5.25 V
-0.25
0.25
-0.5
10
0.5
-10
3
10
-3
3
mV
ppm/°C
1
±0.5
mV
ppm/°C
±0.5
1
%
ppm/°C
±0.5
±0.5
%
ppm/°C
±0.5
±0.5
-3
%
0.5
±7
±0.5
-10
LSB
±0.2
0.25
LSB
Bits
0.1
±0.1
Full scale error (3) (4)
UNIT
ms
±0.5
LSB
AC ACCURACY
SFDR
Spurious-free dynamic range
fIN = 10 kHz, ±10 V
THD
Total harmonic distortion
fIN = 10 kHz, ±10 V
SINAD
Signal-to-(noise+distortion)
SNR
Signal-to-noise
fIN = 10 kHz, ±10 V
80
98
72
73.9
-96
-60 dB Input
80
98
70
73.9
-80
-96
32
-80
dB
32
74
dB
130
kHz
600
600
kHz
Aperture delay
40
40
ns
Aperture jitter
20
20
fIN = 10 kHz, ±10 V
Full-power bandwidth (-3 dB)
74
70
dB
130
Usable bandwidth (7)
72
dB (6)
SAMPLING DYNAMICS
Transient response
FS Step
5
Overvoltage recovery (8)
ps
5
750
750
µs
ns
REFERENCE
Internal reference voltage
No load
2.48
2.5
Internal reference source current
(must use external buffer)
1
Internal reference drift
8
External reference voltage range
for specified linearity
External reference current drain
2.3
2.5
Ext. 2.5-V Ref
2.52
2.7
2.48
2.3
100
2.5
2.52
V
1
µA
8
ppm/°C
2.5
2.7
V
100
µA
V
DIGITAL INPUTS
VIL
Low-level input voltage
-0.3
+0.8
-0.3
+0.8
VIH
High-level input voltage
2.0
VD +0.3 V
2.0
VD +0.3 V
V
IIL
Low-level input current
VIL = 0 V
±10
±10
µA
IIH
High-level input current
VIH = 5 V
±10
±10
µA
DIGITAL OUTPUTS
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Typical rms noise at worst case transitions.
As measured with fixed resistors, see Figure 43. Adjustable to zero with external potentiometer.
Full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by
the transition voltage (not divided by the full-scale range) and includes the effect of offset error.
This is the time delay after the ADS8506 is brought out of Power-Down mode until all internal settling occurs and the analog input is
acquired to rated accuracy. A Convert command after this delay will yield accurate results.
All specifications in dB are referred to a full-scale input.
Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
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SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless
otherwise specified.
PARAMETER
ADS8506IB
TEST CONDITIONS
MIN
TYP
ADS8506I
MAX
MIN
TYP
MAX
UNIT
Data format - Parallel 12-bits in
2-bytes
Data coding - Serial binary 2s
complement or straight binary
VOL
Low-level output voltage
ISINK = 1.6 mA
VOH
High-level output voltage
ISOURCE = 500 µA
0.4
Leakage Current
High-Z state,
VOUT = 0 V to VDIG
±5
±5
µA
Output capacitance
High-Z state
15
15
pF
Bus access time
RL = 3.3 kΩ, CL = 50 pF
83
83
ns
Bus relinquish time
RL = 3.3 kΩ, CL = 10 pF
83
83
ns
4
0.4
4
V
V
DIGITAL TIMING
POWER SUPPLIES
Must be ≤ VANA
VDIG
Digital I/O voltage
VANA
ADC core voltage
IDIG
Digital current
0.6
0.6
mA
IANA
Analog current
4.2
4.2
mA
Power dissipation
4.75
5
5.25
4.75
5
5.25
V
4.75
5
5.25
4.75
5
5.25
V
VANA = VDIG = 5 V,
fS = 40 kHz
24
REFD High
20
20
mW
PWRD and REFD High
50
50
µW
30
24
30
mW
TEMPERATURE RANGE
SO
Specified performance
-40
85
-40
85
°C
Derated performance
-55
125
-55
125
°C
Storage temperature
-65
150
-65
150
Thermal resistance (ΘJA)
46
46
°C
°C/W
DEVICE INFORMATION
28 VDIG
R1IN 1
AGND1 2
27 VANA
R2IN 3
26 REFD
CAP 4
25 PWRD
REF 5
24 BUSY
23 CS
AGND2 6
SB/BTC 7
EXT/INT 8
4
ADS8506
22 R/C
21 BYTE
D7 9
20 TAG
D6 10
19 SDATA
D5 11
18 DATACLK
D4 12
17 D0
D3 13
16 D1
DGND 14
15 D2
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SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
Terminal Functions
TERMINAL
NO.
NAME
DIGITAL
I/O
DESCRIPTION
1
R1IN
Analog Input.
2
AGND1
Analog sense ground. Used internally as ground reference point. Minimal current flow
3
R2IN
Analog Input.
4
CAP
Reference buffer output. 2.2-µF Tantalum capacitor to ground.
5
REF
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.
6
AGND2
7
SB/BTC
I
Selects straight binary or binary 2's complement for output data format. if high, data is output in a
straight binary format. If low, data is output in a binary 2's complement format.
8
EXT/INT
I
Selects external/Internal data clock for transmitting data. If high, data is output synchronized to
the clock input on DATACLK. If low, a convert command initiates the transmission of the data
from the previous conversion, along with 12-clock pulses output on DATACLK.
9
D7
O
Data bit 3 if BYTE is high. Data bit 11 (MSB) if BYTE is low. Hi-Z when CS is high and/or R/C is
low. Leave unconnected when using serial output.
10
D6
O
Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
11
D5
O
Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
12
D4
O
Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. Hi-Z when CS is high and/or R/C is
low.
13
D3
O
Ground if BYTE is high. Data bit 7 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
14
DGND
15
D2
O
Ground if BYTE is high. Data bit 6 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
16
D1
O
Ground if BYTE is high. Data bit 5 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
17
D0
O
Ground if BYTE is high. Data bit 4 if BYTE is low. Hi-Z when CS is high and/or R/C is low.
18
DATACLK
I/O
Either an input or an output depending on the EXT/INT level. Output data is synchronized to this
clock. If EXT/INT is low, DATACLK transmits 12 pulses after each conversion, and then remains
low between conversions.
19
SDATA
O
Serial data output. Data is synchronized to DATACLK, with the format determined by the level of
SB/BTC. In the external clock mode, after 12 bits of data, the ADC outputs the level input on
TAG as long as CS is low and R/C is high. If EXT/INT is low, data is valid on both the rising and
falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG input
when the conversion was started.
20
TAG
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that is dependent on the external clock mode.
21
BYTE
I
Selects 8 most significant bits (low) or 8 least significant bits (high) on parallel output pins.
22
R/C
I
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of
the data results from the previous conversion.
23
CS
I
Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new conversion. If
EXT/INT is low, this same falling edge will start the transmission of serial data results from the
previous conversion.
24
BUSY
O
At the start of a conversion, BUSY goes low and stays low until the conversion is completed and
the digital outputs have been updated.
25
PWRD
I
Power down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
26
REFD
I
REFD High shuts down the internal reference. External reference will be required for
conversions.
27
VANA
ADC Core Supply. Nominally +5 V. Decouple with 0.1-µF ceramic and 10-µF tantalum
capacitors.
28
VDIG
Digital Interface Supply. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA.
Analog ground
Digital ground
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SLAS484B – SEPTEMBER 2007 – REVISED DECEMBER 2007
Table 1. Input Range Connections (see Figure 42 and Figure 43)
ANALOG INPUT
RANGE
CONNECT R1IN VIA 200 Ω TO
CONNECT R2IN VIA 100 Ω TO
IMPEDANCE
±10 V
VIN
CAP
45.7 kΩ
0 V to 5 V
AGND
VIN
20.0 kΩ
0 V to 4 V
VIN
VIN
21.4 kΩ
TYPICAL CHARACTERISTICS
POWER SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
INTERNAL REFERENCE
vs
FREE-AIR TEMPERATURE
4.5
4
2.510
2.505
2.500
2.495
2.490
2.485
5
4.5
4
3.5
10
2.480
-40 -25 -10 5 20 35 50 65 80 95 110 125
TA - Free-Air Temperature - ºC
20
30
fs - Sampling Frequency - kHz
40
Figure 2.
Figure 3.
BIPOLAR OFFSET ERROR
vs
FREE-AIR TEMPERATURE
BIPOLAR POSITIVE FULL-SCALE
ERROR
vs
FREE-AIR TEMPERATURE
BIPOLAR NEGATIVE FULL-SCALE
ERROR
vs
FREE-AIR TEMPERATURE
2
1
0
-1
-2
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
Figure 4.
0
0.2
20 V Bipolar Range
0.15
0.1
0.05
0
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
Figure 5.
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Bipolar Negative Full-Scale Error - %FSR
20 V Bipolar Range
Bipolar Positive Full-Scale Error - %FSR
Figure 1.
3
Bipolar Offset Error - mV
2.515
ICC - Power Supply Current - mA
5
3.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TA - Free-Air Temperature - ºC
6
5.5
2.520
Vref - Internal Reference Voltage - V
ICC - Power Supply Current - mA
5.5
POWER SUPPLY CURRENT
vs
SAMPLING FREQUENCY
-0.05
-0.1
-0.15
-0.2
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
UNIPOLAR OFFSET ERROR
vs
FREE-AIR TEMPERATURE
UNIPOLAR FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
3
1
0
-1
Unipolar Range,
4 V Input Range
Unipolar Full-Scale Error - %FSR
Unipolar Full-Scale Error - %FSR
0.1
0
-0.1
Unipolar Range,
5 V Input Range
-0.1
-0.2
-0.3
-0.4
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
-0.2
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
Figure 7.
Figure 8.
Figure 9.
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
110
100
95
90
85
-25
0
25
50
75 100
TA - Free-Air Temperature - ºC
fi = 10 kHz, 0 dB
SNR - Signal-to-Noise Ratio - dB
THD - Total Harmonic Distortion - dB
105
80
-50
90
-80
fi = 10 kHz, 0 dB
-85
-90
-95
-100
-105
-110
-50
125
-25
0
25
50
75 100
TA - Free-Air Temperature - ºC
fi = 10 kHz, 0 dB
85
80
75
70
65
60
-50
125
-25
0
25
50
75 100
TA - Free-Air Temperature - ºC
125
Figure 11.
Figure 12.
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND DISTORTION
vs
FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
90
90
85
fi = 10 kHz, 0 dB
85
80
75
70
65
60
-50
-25
0
25
50
75 100
TA - Free-Air Temperature - ºC
125
Figure 13.
SINAD - Signal-to-Noise and Distortion - dB
Figure 10.
80
G = 0 dB
70
G = -20 dB
60
50
40
30
G = -60 dB
20
10
0
0
2
4
6 8 10 12 14 16 18 20
f - Frequency - kHz
Figure 14.
SINAD - Signal-to-Noise and Distortion - dB
Unipolar Offset Error - mV
2
-2
-45 -30 -15 0 15 30 45 60 75 90 105120
TA - Free-Air Temperature - ºC
SFDR - Spurious Free Dynamic Range - dB
0
0.2
Unipolar Range
SINAD - Signal-to-Noise and Distortion - dB
UNIPOLAR FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
fi = 10kHz, 0 dB
80
fs = 10 kHz
fs = 20 kHz
75
70
fs = 40 kHz
fs = 30 kHz
65
60
-50
-25
0
25
50
75
100
TA - Free-Air Temperature - ºC
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
90
80
70
60
50
0
1
100
10
f - Frequency - kHz
1000
70
60
50
0
1
10
100
f - Frequency - kHz
1000
fi = 0 dB
90
80
70
60
0
1
10
100
f - Frequency - kHz
1000
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
EQUIVALENT SERIES RESISTOR
TOTAL HARMONIC DISTORTION
vs
EQUIVALENT SERIES RESISTOR
-80
-90
-100
-110
0
1
10
100
f - Frequency - kHz
1000
fi = 10 kHz, 0 dB
THD - Total Harmonic Distortion - dB
-70
-80
115
110
105
100
95
90
85
80
fi = 10 kHz, 0 dB
-85
-90
-95
-100
-105
-110
75
0
1
2
3
4 5 6
ESR - W
7
8
9
0
10
1
2
3
4
5 6
ESR - W
7
8
9
Figure 19.
Figure 20.
Figure 21.
SIGNAL-TO-NOISE RATIO
vs
EQUIVALENT SERIES RESISTOR
SIGNAL-TO-NOISE AND DISTORTION
vs
EQUIVALENT SERIES RESISTOR
OUTPUT REJECTION
vs
POWER-SUPPLY RIPPLE
FREQUENCY
SINAD - Signal-to-Noise and Distortion - dB
95
fi = 10 kHz, 0 dB
90
85
80
75
70
65
60
55
0
1
2
3
4
5 6
ESR - W
7
8
9
10
Figure 22.
95
10
-20
fi = 10 kHz, 0 dB
90
-30
85
Output Rejection - dB
THD - Total Harmonic Distortion - dB
80
100
Figure 18.
fi = 0 dB
SNR - Signal-to-Noise Ratio - dB
fi = 0 dB
Figure 17.
-60
8
90
Figure 16.
SFDR - Spurious Free Dynamic Range - dB
SNR - Signal-to-Noise Ratio - dB
fi = 0 dB
SPURIOUS FREE DYNAMIC RANGE
vs
FREQUENCY
SFDR - Spurious Free Dynamic Range - dB
SIGNAL-TO-NOISE AND DISTORTION
vs
FREQUENCY
SINAD - Signal-to-Noise and Distortion - dB
SIGNAL-TO-NOISE RATIO
vs
FREQUENCY
80
75
70
65
Silicon Tested Under
5 V Unipolar Range
-40
-50
-60
-70
60
55
0
1
2
3
4
5 6
ESR - W
7
8
9
Figure 23.
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10
-80
10
100
1k
10 k
100 k
1M
Power-Supply Ripple Frequency - Hz
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
CONVERSION TIME
vs
FREE-AIR TEMPERATURE
tCONVERT - Conversion Time - ms
13.6
13.5
13.4
13.3
13.2
13.1
13
-50
-25
0
25
50
75 100
TA - Free-Air Temperature - ºC
125
Figure 25.
INL
0.3
0.2
INL - LSBs
0.1
0
-0.1
-0.2
-0.3
0
512
1024
1536
2048
2560
3072
3584
4095
2560
3072
3584
4095
Code
Figure 26.
DNL
0.3
0.2
DNL - LSBs
0.1
0
-0.1
-0.2
-0.3
0
512
1024
1536
2048
Code
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
FFT
0
-10
8192 Point FFT,
fi = 10 kHz, 0 dB
Amplitude - dB
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10
f - Frequency - kHz
15
20
15
20
Figure 28.
FFT
0
-10
-20
8192 Point FFT,
fi = 20 kHz, 0 dB
Amplitude - dB
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10
f - Frequency - kHz
Figure 29.
FFT
0
-10
8192 Point FFT,
fi = 1 kHz, 0 dB
-20
Amplitude - dB
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10
f - Frequency - kHz
15
20
Figure 30.
BASIC OPERATION
PARALLEL OUTPUT
Figure 31 shows a basic circuit to operate the ADS8506 with a ±10-V input range and parallel output. Taking R/C
(pin 22) LOW for a minimum of 40 ns (12 µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay
10
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LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight
most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the four least significant bits (LSBs)
will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY going HIGH
can be used to latch the data. After the first byte has been read, BYTE can be toggled allowing the remaining
byte to be read. All convert commands will be ignored while BUSY is LOW.
The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the
Calibration section).
Parallel Output
200 Ω
± 10 V
66.5 kΩ
100 Ω
2.2 µF
+5 V
+
2.2 µF
1
28
2
27
3
26
4
25
5
24
6
23
7
Pin 21
LOW
Pin 21
HIGH
B11 B10 B9 B8 B7
(MSB)
B3 B2 B1 B0
(LSB)
+
0.1 µF
+
+5 V
10 µF
BUSY
Convert Pulse
22
R/C
8
21
BYTE
9
20
10
19 NC(1)
11
18
12
17
13
16
14
15
ADS8506
40 ns Min
B6 B5 B4
B2
Figure 31. Basic ±10-V Operation, Both Parallel and Serial Output
SERIAL OUTPUT
Figure 32 shows a basic circuit to operate the ADS8506 with a ±10-V input range and serial output. Taking R/C
(pin 22) LOW for 40 ns (12 µs max) will initiate a conversion and output valid data from the previous conversion
on SDATA (pin 19) synchronized to 12 clock pulses output on DATACLK (pin 18). BUSY (pin 24) will go LOW
and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in
BTC format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH
can be used to latch the data. All convert commands will be ignored while BUSY is LOW.
The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
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Serial Output
200 Ω
± 10 V
66.5 kΩ
+5V
100 Ω
2.2 µF
22 µF
+
+
1
28
2
27
3
26
4
25
5
24
6
23
7
22
ADS8506
+
0.1 µF
+
+5 V
10 µF
BUSY
Convert Pulse
R/C
8
21
NC(1) 9
20
NC(1) 10
19
SDATA
DATACLK
NC(1) 11
18
NC(1) 12
17 NC(1)
NC(1) 13
16 NC(1)
14
15 NC(1)
40 ns Min
Figure 32. Basic ±10-V Operation With Serial Output
STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) low for a minimum of 40 ns puts the sample-and-hold of the
ADS8506 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N is
completed and the internal output register has been updated. All new convert commands during BUSY low are
ignored. CS and/or R/C must go high before BUSY goes high, or a new conversion is initiated without sufficient
time to acquire a new signal.
The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,
R/C, and BUSY states, and Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, and Figure 39 for
timing diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High)
(1)
CS
R/C
BUSY
1
X
X
None. Data bus is in Hi-Z state.
OPERATION
↓
0
1
Initiates conversion N. Data bus remains in Hi-Z state.
0
↓
1
Initiates conversion N. Databus enters Hi-Z state.
0
1
↑
Conversion N completed. Valid data from conversion N on the databus.
↓
1
1
Enables databus with valid data from conversion N.
↓
1
0
Enables databus with valid data from conversion N–1 (1). Conversion N in progress.
0
↑
0
Enables databus with valid data from conversion N–1 (1). Conversion N in progress.
0
0
↑
New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C
must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion N in progress.
See Figure 33 and Figure 34 for constraints on data valid from conversion N–1.
CS and R/C are internally ORed and level triggered. It is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical
input is low at least tsu2 ≥ 10 ns prior to the initiating input. If EXT/INT (pin 8) is low when initiating conversion N,
serial data from conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal
Data Clock in the Reading Data section.
12
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To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This
has no effect when using the internal data clock in the serial output mode. The parallel output and the serial
output (only when using an external data clock), however, is affected whenever R/C goes high and the external
clock is active. Refer to the Reading Data section. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high
therefore, data always represents the conversion previously completed even when it is read during a conversion.
READING DATA
The ADS8506 outputs serial or parallel data in straight binary (SB) or binary 2's complement data output format.
If SB/BTC (pin 7) is high, the output is in SB format, and if low, the output is in BTC format. Refer to Table 4 for
ideal output codes. The first conversion immediately following a power-up does not produce a valid conversion
result.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on the
parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port
prior to reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output (1)
CS
R/C
BUSY
EXT/INT
DATACLK
↓
0
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
0
↓
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
↓
0
1
1
Input
0
↓
1
1
↓
1
1
1
Input
Conversion N completed. Valid data from conversion N clocked out on SDATA
synchronized to external data clock.
↓
1
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
↑
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
0
↑
X
Input
New conversion initiated without acquisition of a new signal. Data will be invalid. CS
and/or R/C must be HIGH when BUSY goes HIGH.
X
X
0
X
X
(1)
OPERATION
Initiates conversion N. Internal clock still runs conversion process.
Initiates conversion N. Internal clock still runs conversion process.
New convert commands ignored. Conversion N in progress..
See Figure 37, Figure 38, and Figure 39 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
Full-scale range
Least significant bit (LSB)
+Full-Scale (FS - 1LSB)
Midscale
One LSB Below Midscale
-Full-Scale
ANALOG INPUT
BINARY 2's COMPLEMENT
(SB/BTC LOW)
±10
0 V to 5 V
0 V to 4 V
305 µV
76 µV
61 µV
9.999695 V
4.999924 V
0V
2.5 V
305 µV
-10 V
STRAIGHT BINARY (SB/BTC HIGH)
BINARY CODE
HEX
CODE
BINARY CODE
HEX CODE
3.999939 V
0111 1111 1111
7FF
1111 1111 1111
FFF
2V
0000 0000 0000
000
1000 0000 0000
800
2.499924 V
1.999939 V
1111 1111 1111
FFF
0111 1111 1111
7FF
0V
0V
1000 0000 0000
800
0000 0000 0000
000
PARALLEL OUTPUT
To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left
unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other
combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on
D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the 8 most significant bits will be valid with the MSB
on D7. When BYTE is high, the 4 least significant bits are valid with the LSB on D4. BYTE can be toggled to
read both bytes within one conversion cycle.
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Upon initial power up, the parallel output contains indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N is available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5 and Figure 33 and Figure 34 for timing specifications.
t1
t1
R/C
t3
t3
t4
BUSY
t6
t5
t6
t7
MODE
Acquire
t8
Convert
Acquire
Convert
t12
Parallel
Data Bus
Previous
High Byte Valid
Previous High Previous Low
Byte Valid
Byte Valid
Hi-Z
t12
t10
t11
Not Valid
High Byte
Valid
Low Byte
Valid
t2
t9
Hi-Z
t9
t12
t12
t12
High Byte
Valid
t12
BYTE
Figure 33. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)
t21
t21
t1
t21
t21
R/C
t21
t21
CS
t3
t4
BUSY
t21
t21
BYTE
t21
Data Bus
Hi-Z State
High Byte
t21
t9
t21
Hi-Z State
t21
Low Byte
Hi-Z State
t9
Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs
14
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PARALLEL OUTPUT (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after
the start of conversion N. Do not attempt to read data beyond 12 µs after the start of conversion N until BUSY
(pin 24) goes high; this may result in reading invalid data. Refer to Table 5 and Figure 33 and Figure 34 for
timing constraints.
Table 5. Parallel Conversion and Data Timing, TA = -40°C to 85°C
SYMBOL
DESCRIPTION
MIN
TYP
UNITS
12
µs
15
µs
85
ns
15
µs
t1
Convert pulse width
t2
Data valid delay after R/C low
t3
BUSY delay from start of conversion
t4
BUSY Low
t5
BUSY delay after end of conversion
90
ns
t6
Aperture delay
40
ns
t7
Conversion time
13.5
t8
Acquisition time
11.5
t9
Bus relinquish time
10
t10
BUSY delay after data valid
20
t11
Previous data valid after start of conversion
t12
Bus access time and BYTE delay
t21
R/C to CS setup time
t7 + t8
0.04
MAX
13.5
13.5
15
µs
83
60
ns
ns
13.5
15
µs
10
83
ns
10
Throughput time
µs
ns
25
µs
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an external data clock. When using serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state whenever CS
(pin 23) is low and R/C (pin 22) is high. The serial output cannot be 3-stated and is always active. Refer to the
Applications Information section for specific serial interfaces. If external clock is used, the TAG input can be used
to daisy-chain multiple ADS8506 data pins together.
INTERNAL DATA CLOCK (During a Conversion)
To use the internal data clock, tie EXT/INT (pin 8) low. The combination of R/C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically 900-kHz clock rate). The ADS8506 outputs
12 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 12 clock pulses output
on DATACLK (pin 18). The data is valid on both the rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After the 12th clock pulse, DATACLK remains low until the
next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the start of
transmission. Refer to Table 6 and Figure 36.
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8506, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between DC and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N is completed or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/C to initiate conversions.
While this is perfectly acceptable, there is a possible problem when using an external data clock. At an
indeterminate point from 12 µs after the start of conversion N until BUSY rises, the internal logic shifts the results
of conversion N into the output register. If CS is low, R/C high, and the external clock is high at this point, data is
lost. So, with CS low, either R/C and/or DATACLK must be low during this period to avoid losing valid data.
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EXTERNAL DATA CLOCK (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/C high, valid data from conversion N is output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 12th falling edge and 13th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 13th
falling edge and the 14th rising edge of DATACLK; the second input bit is valid on the 14th falling edge and the
15th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 38.
EXTERNAL DATA CLOCK (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after
the start of conversion N. Do not attempt to clock out data from 12 µs after the start of conversion N until BUSY
(pin 24) rises; this results in data loss. NOTE: For the best possible performance when using an external data
clock, data should not be clocked out during a conversion. The switching noise of the asynchronous data clock
can cause digital feedthrough degrading the converter's performance. Refer to Table 6 and Figure 39.
16
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Table 6. Serial Timing Requirements, TA = –40°C to 85°C
PARAMETER
tw1
Pulse duration, convert
td1
Delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td2
Delay time, BUSY, after end of conversion
td3
Delay time, aperture
tconv
Conversion time
tacq
Acquisition time
tconv + tacq
MIN
TYP
MAX
0.04
12
µs
12
20
ns
13.5
15
µs
5
ns
5
ns
13.5
10
UNIT
15
µs
µs
11.5
Cycle time
25
204
µs
td4
Delay time, R/C low to internal DATACLK output
tc1
Cycle time, internal DATACLK
600
820
ns
td5
Delay time, data valid to internal DATACLK high
150
204
ns
td6
Delay time, data valid after internal DATACLK low
150
208
ns
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
850
ns
tw4
Pulse duration, external DATACLK low
15
ns
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
ns
tsu2
Setup time, R/C transition to CS transition
10
ns
td8
Delay time, data valid from external DATCLK high
td9
Delay time, CS rising edge to external DATACLK rising edge
10
ns
td10
Delay time, previous data available after CS, R/C low
12
µs
5
2
20
ns
tsu4
Setup time, BUSY transition to first external DATACLK
td11
Delay time, final external DATACLK to BUSY rising edge
ns
tsu3
Setup time, TAG valid to rising DATACLK
0
ns
th1
Hold time, TAG valid after rising edge of DATACLK
2
ns
2
CS
R/C
R/C
CS
µs
td9
tsu1
tsu1
tsu1
External
DATACLK
tsu1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
CS
tsu2
R/C
tsu2
tsu3
External
DATACLK
1
2
CS Set Low, Discontinuous Ext DATACLK
Figure 35. Critical Timing
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tw1
tw1
R/C
td1
td1
tw2
tw2
(N+1)th
BUSY
(N+2)th
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td11
td3
td11
Error
(N+1)th Conversion Correction
(N+1)th Accquisition
tconv
tconv
tacq
tc1
td4
(N+2)th Accquisition
tacq
td4
Internal
1
DATACLK
2
12
12
td6
td5
SDATA
2
1
D11
TAG = 0
TAG = 0
D0
D11
D0
TAG = 0
Nth Conversion Data
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
8 starts READ
Figure 36. Basic Conversion Timing - Internal DATACLK (Read Previous Data During Conversion)
tw1
tw1
R/C
td1
td1
tw2
BUSY
tw2
(N+1)th
(N+2)th
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td3
td11
td11
(N+1)th Accquisition
(N+1)th Conversion
tacq
tconv
(N+2)th Accquisition
tacq
tconv
tsu3
tsu1
Error
Correction
tsu3
tsu1
External
1
DATACLK
SDATA
TAG = 0
12
No more
data to
shift out
1
TAG = 0
EXT/INT tied high, CS and TAG are tied low
2
1
12
Nth Data
TAG = 0
12
No more
data to
shift out
1
TAG = 0
2
12
(N+1)th Data
TAG = 0
tw1 + tsu1 starts READ
Figure 37. Basic Conversion Timing - External DATACLK
18
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tw1
R/C
td1
tsu1
tw2
td1
BUSY
td2
td3
td3
td11
STATUS
Nth Conversion
Error
Correction
(N+1) th Accquisition
tsu3
tconv
tacq
tc2
External
tsu1
tw4
tw3
DATACLK
0
1
2
3
4
5
8
td8
10
11
12
td8
Nth Conversion Data
D11
SDATA
D10
D9
D8
D7
D6
D03
D02
D01
D00
Null
T00
Txx
T02
T03
T04
T05
T06
T8
T9
T10
T11
Null
T13
Tyy
th1
tsu4
TAG
9
T00
T01
EXT/INT tied high, CS tied low
tw1 + tsu1 starts READ
Figure 38. Read After Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
tw2
BUSY
td2
td3
Error
Correction
Nth Conversion
STATUS
tsu3
tconv
tc2
External
tsu1
tw3
1
0
DATACLK
td11
tw4
2
3
4
5
7
8
9
10
11
td10
td8
(N − 1)th Conversion Data
D11
SDATA
EXT/INT tied high, CS and TAG tied low
D10
D9
D8
D7
D6
D03
D02
td8
D01
D00
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 39. Read During Conversion (Discontinuous External DATACLK)
TAG FEATURE
The TAG feature allows the data from multiple ADS8506 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 40. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
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The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 40, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in the internal clock
mode the state of the TAG pin determines the state of the DATA pin after all 12 bits have shifted out. When
multiple converters are cascaded together this state forms the NULL bit that separates the words. Thus, with the
TAG pin of the first converter grounded as shown in Figure 40 the NULL bit becomes a zero between each data
word.
Processor
ADS8506A
DATA
CS
R/C
DATACLK
TAG
SCLK
ADS8506B
TAG(A)
DATA
CS
R/C
DATACLK
TAG
TAG(B)
GPIO
GPIO
SDI
Null
D
A00
Q
D
Q
D
Null
D
A11
Q
D
Q
D
B00
SDATA (A)
A12
Q
D
Q
D
B11
Q
B12
SDATA (B)
Q
DATACLK
R/C
(both A & B)
Nth Conversion
BUSY
(both A & B)
External
DATACLK
1
2
3
4
12
13
SDATA ( A )
A11
A10
A9
A01
A00
SDATA ( B )
B11
B10
B9
B01
B00
14
15
16
17
Null
TAG(A) = 0
A
Nth Conversion Data
Null A11
A10 A9
B
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
26
A01
27
28
A00
Null
A
TAG(A) = 0
.
Figure 40. Timing of TAG Feature With Single Conversion (Using External DATACLK)
INPUT RANGES
The ADS8506 offers three input ranges: standard ±10-V and 0-V to 5-V ranges, and a 0-V to 4-V range for
complete, single-supply systems. See Figure 42 and Figure 43 for the necessary circuit connections for
implementing each input range and optional offset and gain adjust circuitry. Offset and full-scale error
specifications are tested with the fixed resistors, see Figure 43 (full-scale error includes offset and gain errors
measured at both +FS and -FS). Adjustments for offset and gain are described in the Calibration section of this
data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The input impedance, summarized in Table 1, results from the combination of the internal resistor network (see
the front page of this product data sheet) and the external resistors used for each input range (see Figure 44).
The input resistor divider network provides inherent over-voltage protection to at least ±5.5 V for R2IN and ±12 V
for R1IN.
Analog inputs above or below the expected range yields either positive full-scale or negative full-scale digital
outputs, respectively. Wrapping or folding over for analog inputs outside the nominal range does not occur.
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+15V
2.2 mF
22 pF
ADS8506
200 W
100 nF
GND
R1IN
2 kW
Pin 7
2 kW
Vin
Pin 2
22 pF
Pin3
AGND1
Pin 1
100 W
−
OPA 627
or
OPA 132
+
R2IN
Pin 6
33.2 kW
GND
R3IN
Pin4
CAP
2.2 mF
GND
REF
2.2 mF
GND
100 nF
DGND
2.2 mF
GND
AGND2
−15 V
GND
Figure 41. Typical Driving Circuit (±10 V, No Trim)
CALIBRATION
Hardware Calibration
To calibrate the offset and gain of the ADS8506 in hardware, install the resistors shown in Figure 42. Table 7
lists the hardware trim ranges relative to the input for each input range.
Table 7. Offset and Gain Adjust Ranges for Hardware Calibration (see Figure 42)
INPUT RANGE
OFFSET ADJUST RANGE (mV)
GAIN ADJUST RANGE (mV)
±10 V
±15
±60
0 V to 5 V
±4
±30
0 V to 4 V
±3
±30
±10 V
VIN
0 V to 5 V
200 Ω 1
2
3
100 Ω
33.2 kΩ
4
+
+ 5 V 2.2 µF
5
50 kΩ
50 kΩ
+5V
1 MΩ
2.2 µF
+
200 Ω
R1IN
AGND1
33.2 kΩ
R2IN
VIN
2
3
+5 V
CAP
50 kΩ
REF
AGND2
33.2 kΩ
1
R1IN
50 kΩ
6
0 V to 4 V
100 Ω
2.2 µF
+
+
1 MΩ
2.2 µF
4
5
R1IN
2
AGND1
VIN
3
R2IN
+5 V
100 Ω
CAP
50 kΩ
REF
50 kΩ
6
1
200 Ω
AGND2
2.2 µF
+
+
1 MΩ
2.2 µF
4
5
6
AGND1
R2IN
CAP
REF
AGND2
Figure 42. Circuit Diagrams (With Hardware Trim)
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Software Calibration
To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet
specifications for offset and gain, the resistors shown in Figure 43 are necessary. See the No Calibration section
for more details on the external resistors. Refer to Table 8 for the range of offset and gain errors with and without
the external resistors.
±10 V
VIN
0 V to 5 V
200 Ω 1
2
66.5 kΩ
200 Ω
100 Ω
4
+
2.2 µF
5
+
2.2 µF
6
33.2 kΩ
1
R1IN
R1IN
AGND1
2
33.2 kΩ
3
3
+5V
0 V to 4 V
R2IN
VIN
100 Ω
CAP
2.2 µF
4
+
REF
5
+
2.2 µF
AGND2
6
1
R1IN
200 Ω
2
AGND1
VIN
3
R2IN
100 Ω
CAP
2.2 µF
4
+
5
REF
+
2.2 µF
AGND2
6
AGND1
R2IN
CAP
REF
AGND2
Figure 43. Circuit Diagrams (Without Hardware Trim)
Table 8. Range of Offset and Gain Errors With and Without External Resistors
INPUT
RANGE
(V)
OFFSET ERROR
WITH RESISTORS
(1)
WITHOUT RESISTORS
RANGE (mV)
RANGE (mV)
-10 ≤ BPZ ≤ 10
±10
GAIN ERROR
0 ≤ BPZ ≤ 35
TYP (mV)
15
0 to 5
-3 ≤ UPO ≤ 3
-12 ≤ UPO ≤ -3
-7.5
0 to 4
-3 ≤ UPO ≤ 3
-10.5 ≤ UPO ≤ -1.5
-6
WITH RESISTORS
WITHOUT RESISTORS
RANGE (% FS)
RANGE (% FS)
TYP
-0.4 ≤ G ≤ 0.4
-0.3 ≤ G ≤ 0.5
0.05
0.15 ≤ G
(1)
≤ 0.15
-0.1 ≤ G
(1)
≤ 0.2
0.05
-0.4 ≤ G ≤ 0.4
-1.0 ≤ G ≤ 0.1
-0.2
0.15 ≤ G (1)≤ 0.1
-0.55 ≤ G (1)≤ -0.05
-0.2
-0.4 ≤ G ≤ 0.4
-1.0 ≤ G ≤ 0.1
-0.2
-0.15 ≤ G (1)≤ 0.15
-0.55 ≤ G (1)≤ -0.05
-0.2
High grade
No Calibration
Figure 43 shows circuit connections. Note that the actual voltage dropped across the external resistors is at least
two orders of magnitude lower than the voltage dropped across the internal resistor divider network. This should
be considered when choosing the accuracy and drift specifications of the external resistors. In most applications,
1% metal-film resistors are sufficient.
The external resistors, see Figure 43, may not be necessary in some applications. These resistors provide
compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not
using the external resistors results in offset and gain errors in addition to those listed in the electrical
characteristics section. Offset refers to the equivalent voltage of the digital output when converting with the input
grounded. A positive gain error occurs when the equivalent output voltage of the digital output is larger than the
analog input. Refer to Table 8 for nominal ranges of gain and offset errors with and without the external resistors.
Refer to Figure 44 for typical shifts in the transfer functions which occur when the external resistors are removed.
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(a) Bipolar
(b) Unipolar
Digital Output
Digital Output
+ Full-Scale
+ Full-Scale
Analog Input
− Full-Scale
Analog Input
− Full-Scale
Typical Transfer Functions With External Resistors.
Typical Transfer Functions Without External Resistors.
Figure 44. Typical Transfer Functions With and Without External Resistors
To further analyze the effects of removing any combination of the external resistors, consider Figure 45. The
combination of the external and the internal resistors form a voltage divider which reduces the input signal to a
0.3125-V to 2.8125-V input range at the capacitor digital-to-analog converter (CDAC). The internal resistors are
laser trimmed to high relative accuracy to meet full-scale specifications. The actual input impedance of the
internal resistor network looking into pin 1 or pin 3 however, is only accurate to ±20% due to process variations.
This should be taken into account when determining the effects of removing the external resistors.
200 Ω
39.8 kΩ
CDAC
(0.3125 V to 2.8125 V)
VIN
33.5 kΩ
9.9 kΩ
20 kΩ
40 kΩ
+5V
+ 2.5 V
100 Ω
+ 2.5 V
200 Ω
33.5 kΩ
VIN
39.8 kΩ
CDAC
(0.3125 V to 2.8125 V)
9.9 kΩ
100 Ω
+ 2.5 V
200 Ω
20 kΩ
40 kΩ
+ 2.5 V
39.8 kΩ
VIN
33.5 kΩ
100 Ω
+ 2.5 V
CDAC
(0.3125 V to 2.8125 V)
9.9 kΩ
20 kΩ
40 kΩ
+ 2.5 V
Figure 45. Circuit Diagrams Showing External and Internal Resistors
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REFERENCE
The ADS8506 can operate with its internal 2.5-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
The ADS8506 also has an internal buffer for the reference voltage. Figure 46 shows characteristic impedances at
the input and output of the buffer with all combinations of powerdown and reference down.
ZCAP
CAP
(Pin 4)
CDAC
Buffer
ZREF
Internal
Reference
REF
(Pin 5)
ZCAP Ω
ZREF Ω
PWRD 0
REFD 0
1
6k
PWRD 0
REFD 1
1
100 M
PWRD 1
REFD 0
200
6k
PWRD 1
REFD 1
200
100 M
Figure 46. Characteristic Impedances of the Internal Buffer
REF
REF (pin 5) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF tantalum
capacitor should be connected as close as possible to the REF pin from ground. This capacitor and the output
resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor will
introduce more noise to the reference, degrading the SNR and SINAD. The REF pin should not be used to drive
external AC or DC loads, as shown in Figure 46.
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF tantalum capacitor should be placed as close
as possible to the CAP pin from ground to provide optimum switching currents for the CDAC throughout the
conversions cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any
smaller than 1 µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC.
Capacitor values larger than 2.2 µF have little affect on improving performance. ESR is the total equivalent series
resistance of the compensation capacitor (CAP pin). See Figure 46 and Figure 47.
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7000
Power−Up Time − ms
6000
5000
4000
3000
2000
1000
0
0.1
1
10
CAP − Pin Value − mF
100
Figure 47. Power-Down to Power-Up Time vs Capacitor Value on CAP
The output of the buffer is capable of driving up to 1 mA of current to a DC load. Using an external buffer allows
the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load
with the output voltage on CAP. This causes performance degradation of the converter.
REFERENCE AND POWER-DOWN
The ADS8506 has analog power-down and reference power down capabilities via PWRD (pin 25) and REFD (pin
26), respectively. PWRD and REFD high powers down all analog circuitry maintaining data from the previous
conversion in the internal registers, provided that the data has not already been shifted out through the serial
port. Typical power consumption in this mode is 50 µW. Power recovery is typically 1 ms, using a 2.2-µF
capacitor connected to CAP. Figure 47 shows power-down to power-up recovery time relative to the capacitor
value on CAP. With +5 V applied to VDIG, the digital circuitry of the ADS8506 remains active at all times,
regardless of PWRD and REFD states.
PWRD
PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversion
is maintained in the internal registers and can still be read. With PWRD high, a convert command yields
meaningless data.
REFD
REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, is
active. REFD should be high when using an external reference to minimize power consumption and the loading
effects on the external reference. See Figure 46 for the characteristic impedance of the reference buffer's input
for both REFD high and low. The internal reference consumes approximately 5 mW.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical characteristics, the ADS8506 uses 90% of its
power for the analog circuitry. The ADS8506 should be considered as an analog component.
The +5-V power for the A/D converter should be separate from the +5 V used for the system's digital logic.
Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise
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from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is
used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V
regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and
VANA should be tied to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8506. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is
more susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system's
digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to
the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground
currents from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the
sampling FET switch on the ADS8506 is approximately 5% to 10% of the amount on similar A/D converters with
the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front end
which attenuates any charge which is released. The end result is a minimal requirement for the drive capability
on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will
be sufficient to drive the ADS8506.
The resistive front end of the ADS8506 also provides a specified ±25-V overvoltage protection. In most cases,
this eliminates the need for external over-voltage protection circuitry.
INTERMEDIATE LATCHES
The ADS8506 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolate
the A/D converter from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8506 has an internal LSB size of
38 µV. Transients from fast switching signals on the parallel port, even when the A/D converter is 3-stated, can
be coupled through the substrate to the analog circuitry causing degradation of converter performance.
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APPLICATION INFORMATION
AVERAGING
The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results,
transition noise is reduced by a factor of 1/√Hz where n is the number of averages. For example, averaging four
conversion results reduces the TN by to 0.4 LSBs. Averaging should only be used for input signals with
frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a
similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves 3 dB.
QSPI™ INTERFACE
Figure 48 shows a simple interface between the ADS8506 and any QSPI equipped microcontroller. This interface
assumes that the convert pulse does not originate from the microcontroller and that the ADS8506 is the only
serial peripheral.
Convert Pulse
QSPI
ADS8506
R/C
PCS0/SS
MOSI
SCK
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data Valid on Falling Edge)
QSPI Port is in Slave Mode
The ADC is the SPI master
Figure 48. QSPI Interface to the ADS8506
Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line. When
a transition from high to low occurs on slave select (SS) from BUSY (indicating the end of the current
conversion), the port can be enabled. If this is not done, the microcontroller and the A/D converter may be
out-of-sync.
SPI™ INTERFACE
The SPI interface is generally only capable of 8-bit data transfers. For some microcontrollers with SPI interfaces,
it might be possible to receive data in a similar manner as shown for the QSPI interface in Figure 48. The
microcontroller needs to fetch the 8 most significant bits before the contents are overwritten by the least
significant bits.
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Revision History
Changes from Revision A (OCTOBER 2007) to Revision B ........................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
28
Changed minimum INL for ADS8506I from ±0.45 to ±0.9 LSB in ordering information table ............................................... 2
Changed INL min value for ADS8506I from -0.45 to -0.9 LSB in the electrical characteristics ........................................... 2
Changed INL max value for ADS8506I from 0.45 to 0.9 LSB in the electrical characteristics.............................................. 2
Added DNL min value for ADS8506I of -0.9 LSB in the electrical characteristics ................................................................ 3
Changed DNL max value for ADS8506I from 0.45 to 0.9 LSB in the electrical characteristics ............................................ 3
Changed gain error typ value for ADS8506I from ±0.1% to ±0.2%....................................................................................... 3
Changed full scale error drift typ value for ADS8506I from ±5 to ±7..................................................................................... 3
Changed power supply sensitivity value for ADS8506I from typ to max ............................................................................... 3
Added spurious-free dynamic range min value for ADS8506IB of 80 dB.............................................................................. 3
Added spurious-free dynamic range min value for ADS8506I of 80 dB ................................................................................ 3
Changed SINAD min value for ADS8506I from 72 to 70 dB ................................................................................................. 3
Changed SNR min value for ADS8506I from 72 to 70 dB..................................................................................................... 3
Changed delay time td10 min value from 2 to 12 µs............................................................................................................. 17
Changed delay time td11 max value from 1 to 2 µs.............................................................................................................. 17
Changed tsu3 to tsu4 and tsu4 description ............................................................................................................................... 17
Changed th1 description........................................................................................................................................................ 17
Added td9 to critical timing diagram ...................................................................................................................................... 17
Changed tsu3 to tsu4 in Figure 38 .......................................................................................................................................... 19
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8506IBDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
B
ADS8506IBDWG4
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
B
ADS8506IBDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
B
ADS8506IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
ADS8506IDWG4
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
ADS8506IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8506I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8506IBDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
ADS8506IDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8506IBDWR
SOIC
DW
28
1000
367.0
367.0
55.0
ADS8506IDWR
SOIC
DW
28
1000
367.0
367.0
55.0
Pack Materials-Page 2
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