WS57C49C HIGH SPEED 8K x 8 CMOS PROM/RPROM KEY FEATURES • Ultra-Fast Access Time • Pin Compatible with Bipolar PROMs • Immune to Latch-UP — t ACC = 25 ns — t CS = 12 ns — Up to 200 mA • Low Power Consumption • Fast Programming • ESD Protection Exceeds 2000 V • Available in 300 Mil DIP and PLDCC GENERAL DESCRIPTION The WS57C49C is a High Performance 64K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology which enables it to operate at Bipolar PROM speeds while consuming only 25% of the power required by its Bipolar counterparts. A further advantage of the WS57C49C over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology. This enables the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike devices which cannot be erased, every WS57C49C in a windowed package is 100% tested with worst case test patterns both before and after assembly. The WS57C49C is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems which are currently using Bipolar PROMs, or its predecessor, the WS57C49B. BLOCK DIAGRAM PIN CONFIGURATION TOP VIEW 8 A5 - A12 ROW ADDRESSES ROW DECODER EPROM ARRAY Chip Carrier 65,536 BITS CERDIP/Plastic DIP Flatpack NC A5 A 6 A 7 5 4 3 2 COLUMN DECODER A0 - A4 COLUMN ADDRESSES VCC A8 A9 SENSE AMPLIFIERS A4 A3 A2 A1 A0 NC O0 CS1/ VPP 28 27 26 1 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 O1 O2 NC O3 O4 O5 A7 A6 A5 A10 A4 CS1/VPP A3 A11 A2 A12 A1 NC A0 O7 O0 O6 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 A10 CS1/VPP A11 A12 O7 O6 O5 O4 O3 GND 8 OUTPUTS PRODUCT SELECTION GUIDE PARAMETER 57C49C-25 57C49C-35 57C49C-45 57C49C-55 57C49C-70 Address Access Time (Max) 25 ns 35 ns 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 12 ns 20 ns 25 ns 25 ns 25 ns Return to Main Menu 2-39 WS57C49C ABSOLUTE MAXIMUM RATINGS* MODE SELECTION Storage Temperature............................–65° to + 150°C PINS CS1/VPP VCC OUTPUTS Read VIL VCC DOUT ESD Protection ..................................................> 2000V Output Disable VIH VCC High Z *NOTICE: Program VPP VCC DIN Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Program Verify VIL VCC DOUT Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V VPP with Respect to Ground...................–0.6V to + 13V MODE OPERATING RANGE RANGE TEMPERATURE VCC 0°C to +70°C +5V ± 10% Industrial –40°C to +85°C +5V ± 10% Military –55°C to +125°C +5V ± 10% Commercial DC READ CHARACTERISTICS Over Operating Range. (See Above) SYMBOL TEST CONDITIONS MIN MAX UNITS VIL Input Low Voltage (Note 3) –0.1 0.8 V VIH Input High Voltage (Note 3) 2.0 VCC + 0.3 V VOL Output Low Voltage IOL = 16 mA 0.4 V VOH Output High Voltage IOH = –4 mA ICC1 ICC2 ILI ILO NOTES: 2-40 PARAMETER VCC Active Current (CMOS) VCC Active Current (TTL) 2.4 V VCC = 5.5 V, f = 0 MHz (Note 1), Comm'l 30 mA Output Not Loaded Industrial 35 mA Add 3 mA/MHz for AC Operation Military 35 mA VCC = 5.5 V, f = 0 MHz (Note 2), Comm'l 40 mA Output Not Loaded Industrial 50 mA Add 3 mA/MHz for AC Operation Military 50 mA Input Leakage Current VIN = 5.5V or Gnd –10 10 µA Output Leakage Current VOUT = 5.5 V or Gnd –10 10 µA 1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V. 2. TTL inputs: VIL ≤ 0.8V, VIH ≥ 2.0V. 3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. WS57C49C AC READ CHARACTERISTICS Over Operating Range. (See Above) PARAMETER SYMBOL 57C49C-25 57C49C-35 57C49C-45 57C49C-55 57C49C-70 MIN MAX MIN MAX MIN MAX MIN MAX MIN UNITS MAX Address to Output Delay tACC 25 35 45 55 70 CS1 to Output Delay tCS 12 20 25 25 25 ns Output Disable to Output Float* tDF Address to Output Hold tOH 12 0 25 0 25 25 0 0 25 0 *Sampled, Not 100% Tested. AC READ TIMING DIAGRAM ADDRESSES VALID tACC tOH CS tCS OUTPUTS VALID tDF 2-41 WS57C49C CAPACITANCE (4) TA = 25°C, f = 1 MHz PARAMETER CONDITIONS TYP (5) MAX UNITS Input Capacitance VIN = 0V 4 6 pF C OUT Output Capacitance VOUT = 0V 8 12 pF C VPP VPP Capacitance VPP = 0 V 18 25 pF SYMBOL C IN NOTES: 4. This parameter is only sampled and is not 100% tested. 5.Typical values are for TA = 25°C and nominal supply voltages. TEST LOAD (High Impedance Test Systems) 98 Ω A.C. TESTING INPUT/OUTPUT WAVEFORM 3.0 2.01 V 1.5 0.0 D.U.T. TEST POINTS 1.5 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 1.5 V for input and output transitions in both directions. NOTE: 6. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters. A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures. 2-42 WS57C49C NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.60 40.0 35.0 1.40 DELTA Taa (ns) NORMALIZED I CC 30.0 1.20 1.00 25.0 20.0 15.0 10.0 0.80 5.0 0.60 0.0 4.0 4.5 5.0 5.5 6.0 0.0 200 SUPPLY VOLTAGE ( V ) 400 600 800 1000 CAPACITANCE ( pF ) NORMALIZED Taa vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.6 1.2 1.4 NORMALIZED I CC NORMALIZED Taa 1.1 1.2 1.0 1.0 0.9 0.8 0.6 0.8 -55 -35 -15 5 25 45 65 85 AMBIENT TEMPERATURE (°C ) 105 125 -55 -35 -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (°C) 2-43 WS57C49C PROGRAMMING INFORMATION DC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER MIN MAX UNITS –10 10 µA ILI Input Leakage Current (VIN = VCC or Gnd) IPP VPP Supply Current During Programming Pulse 60 mA ICC VCC Supply Current 35 mA VOL Output Low Voltage During Verify (IOL = 16 mA) 0.45 V VOH Output High Voltage During Verify (IOH = –4 mA) 2.4 V NOTES: 7. VPP must not be greater than 13 volts including overshoot. AC CHARACTERISTICS (TA = 25 ± 5°C, VCC = 6.25 V ± 0.25 V, VPP = 12.75 ± 0.25 V) SYMBOLS PARAMETER tAS Address Setup Time tDF Chip Disable Setup Time tDS Data Setup Time tPW Program Pulse Width tDH Data Hold Time tCS Chip Select Delay tRF VPP Rise and Fall Time MIN TYP MAX UNITS 2 µs 30 2 µs 100 200 2 1 VIH ADDRESS STABLE VIL tAS VIH DATA IN DATA OUT VIL tDF tPW tDS tDH VPP VIH CS1/VPP VIL 2-44 tRF tRF ns µs PROGRAMMING WAVEFORM DATA µs µs 30 ADDRESSES ns tCS WS57C49C ORDERING INFORMATION PART NUMBER SPEED (ns) WS57C49C-25D WS57C49C-25J WS57C49C-25S WS57C49C-25T WS57C49C-35CMB WS57C49C-35D WS57C49C-35DMB WS57C49C-35J WS57C49C-35L WS57C49C-35S WS57C49C-35T WS57C49C-35TI WS57C49C-35TMB WS57C49C-45CMB* WS57C49C-45D WS57C49C-45DMB* WS57C49C-45J WS57C49C-45JI WS57C49C-45L WS57C49C-45S WS57C49C-45T WS57C49C-45TI WS57C49C-45TMB* WS57C49C-55CMB* WS57C49C-55D WS57C49C-55DMB* WS57C49C-55FMB* WS57C49C-55J WS57C49C-55T WS57C49C-55TMB* WS57C49C-70CMB* WS57C49C-70D WS57C49C-70TMB* 25 25 25 25 35 35 35 35 35 35 35 35 35 45 45 45 45 45 45 45 45 45 45 55 55 55 55 55 55 55 70 70 70 PACKAGE TYPE 24 Pin CERDIP, 0.6" 28 Pin PLDCC 24 Pin Plastic DIP, 0.3" 24 Pin CERDIP, 0.3" 28 Pad CLLCC 24 Pin CERDIP, 0.6" 24 Pin CERDIP, 0.6" 28 Pin PLDCC 28 Pin CLDCC 24 Pin Plastic DIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 28 Pad CLLCC 24 Pin CERDIP, 0.6" 24 Pin CERDIP, 0.6" 28 Pin PLDCC 28 Pin PLDCC 28 Pin CLDCC 24 Pin Plastic DIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 28 Pad CLLCC 24 Pin CERDIP, 0.6" 24 Pin CERDIP, 0.6" 24 Pin Ceramic Flatpack 28 Pin PLDCC 24 Pin CERDIP, 0.3" 24 Pin CERDIP, 0.3" 28 Pad CLLCC 24 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.3" WSI PACKAGE OPERATING TEMPERATURE MANUFACTURING DRAWING RANGE PROCEDURE D1 J3 S1 T1 C1 D1 D1 J3 L2 S1 T1 T1 T1 C1 D1 D1 J3 J3 L2 S1 T1 T1 T1 C1 D1 D1 F1 J3 T1 T1 C1 D1 T1 Comm’l Comm’l Comm'l Comm’l Military Comm’l Military Comm’l Comm’l Comm'l Comm’l Industrial Military Military Comm’l Military Comm’l Industrial Comm’l Comm'l Comm’l Industrial Military Military Comm’l Military Military Comm’l Comm’l Military Military Comm’l Military Standard Standard Standard Standard MIL-STD-883C Standard MIL-STD-883C Standard Standard Standard Standard Standard MIL-STD-883C MIL-STD-883C Standard MIL-STD-883C Standard Standard Standard Standard Standard Standard MIL-STD-883C MIL-STD-883C Standard MIL-STD-883C MIL-STD-883C Standard Standard MIL-STD-883C MIL-STD-883C Standard MIL-STD-883C NOTE: The actual part marking will not include the initials "WS." *SMD product. See section 4 for SMD number. PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C49C is programmed using Algorithm D shown on page 5-9. Return to Main Menu 2-45