ON MMSF3350 Single nâ channel field effect transistor Datasheet

MMSF3350
WaveFET™ HDTMOS™
Single N−Channel Field
Effect Transistor
Power Surface Mount Products
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WaveFET devices are an advanced series of power MOSFETs
which utilize ON Semiconductor’s latest MOSFET technology
process to achieve the lowest possible on−resistance per silicon area.
They are capable of withstanding high energy in the avalanche and
commutation modes and the drain−to−source diode has a very low
reverse recovery time. WaveFET devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
• Characterized Over a Wide Range of Power Ratings
• Ultralow RDS(on) Provides Higher Efficiency and
Extends Battery Life in Portable Applications
• Logic Level Gate Drive − Can Be Driven by
Logic ICs
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Miniature SO−8 Surface Mount Package − Saves Board Space
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 3
1
SINGLE TMOS
POWER MOSFET
30 VOLTS
RDS(on) = 11 mW
D
G
S
MARKING
DIAGRAM
8
XXXXXX
ALYW
SO−8
CASE 751
Style 12
1
XXX
A
L
Y
W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Publication Order Number:
MMSF3350/D
MMSF3350
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
Vdc
Drain−to−Gate Voltage
VDGR
30
Vdc
Gate−to−Source Voltage
VGS
± 20
Vdc
Gate−to−Source Operating Voltage
VGS
± 16
Vdc
TJ, Tstg
−55 to 150
°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, L = 20 mH, IL(pk) = 10 A, VDS = 30 Vdc)
EAS
1000
mJ
POWER RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp ≤ 10 ms)
Mounted on 1 inch square
FR−4 or G10 board
VGS = 10 Vdc
Continuous Source Current (Diode Conduction)
t ≤ 10 seconds
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Thermal Resistance
− Junction−to−Ambient
Parameter
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp ≤ 10 ms)
Mounted on 1 inch square
FR−4 or G10 board
VGS = 10 Vdc
Continuous Source Current (Diode Conduction)
Steady State
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Thermal Resistance
− Junction−to−Ambient
Parameter
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp ≤ 10 ms)
Mounted on minimum recommended
FR−4 or G10 board
VGS = 10 Vdc
Continuous Source Current (Diode Conduction)
t ≤ 10 seconds
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Thermal Resistance
− Junction−to−Ambient
Parameter
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp ≤ 10 ms)
Mounted on minimum recommended
FR−4 or G10 board
VGS = 10 Vdc
Continuous Source Current (Diode Conduction)
Steady State
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Thermal Resistance
− Junction−to−Ambient
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2
Symbol
Value
Unit
ID
ID
IDM
13
9.2
50
Adc
Adc
Adc
IS
3.6
Adc
PD
2.7
22.2
Watts
mW/°C
RqJA
46
°C/W
Symbol
Value
Unit
ID
ID
IDM
9.4
6.7
50
Adc
Adc
Adc
IS
2.0
Adc
PD
1.5
11.8
Watts
mW/°C
RqJA
85
°C/W
Symbol
Value
Unit
ID
ID
IDM
10
7.4
50
Adc
Adc
Adc
IS
2.4
Adc
PD
1.8
14.3
Watts
mW/°C
RqJA
70
°C/W
Symbol
Value
Unit
ID
ID
IDM
7.4
5.2
50
Adc
Adc
Adc
IS
1.2
Adc
PD
0.9
7.1
Watts
mW/°C
RqJA
140
°C/W
MMSF3350
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Characteristic
Symbol
Min
Typ
Max
Unit
30
−
33
23
−
−
−
−
0.003
0.4
1.0
10
−
2.0
100
1.0
−
2.0
4.6
−
−
−
−
9.4
14.4
11
17
gFS
12
17
−
Mhos
Ciss
−
1680
−
pF
Coss
−
540
−
Crss
−
185
−
td(on)
−
21
40
tr
−
50
90
td(off)
−
42
80
tf
−
44
80
td(on)
−
12
20
tr
−
15
30
td(off)
−
60
100
tf
−
44
80
QT
−
46
60
Q1
−
4.5
−
Q2
−
12.8
−
Q3
−
9.8
−
−
−
0.76
0.58
1.0
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
ON
Vdc
mV/°C
mAdc
nAdc
CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 4.5 Vdc, ID = 5.0 Adc)
RDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc)
Vdc
mV/°C
mW
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING
CHARACTERISTICS(2)
Turn−On Delay Time
Rise Time
(VDD = 25 Vdc, ID = 1.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 W)
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
(VDD = 25 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc,
RG = 6.0 W)
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 15 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
ns
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
(IS = 2.3 Adc, VGS = 0 Vdc)
(IS = 2.3 Adc, VGS = 0 Vdc, TJ =
125°C)
VSD
Reverse Recovery Time
(IS = 3.5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
trr
−
41
−
ta
−
21
−
tb
−
20
−
QRR
−
0.049
−
Reverse Recovery Stored Charge
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperatures.
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3
Vdc
ns
mC
MMSF3350
25
20
14
4.1 V 3.9 V
10 V
6.0 V
4.5 V
TJ = 25°C
VGS = 3.7 V
4.3 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
TYPICAL ELECTRICAL CHARACTERISTICS
15
3.5 V
10
3.3 V
3.1 V
5
0.25
0.5
0.75
1.0
1.25
1.75
1.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.3
ID = 5.0 A
TJ = 25°C
0.2
0.1
2
3
4
5
6
7
TJ = 125°C
4
−55°C
8
9
2
2.5
4
3.5
10
0.020
TJ = 25°C
0.018
0.016
VGS = 4.5 V
0.014
0.012
10 V
0.010
0.008
0.006
0.004
0.002
0
0
Figure 3. On−Resistance versus
Gate−To−Source Voltage
5
20
10
15
ID, DRAIN CURRENT (AMPS)
25
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
1000
VGS = 0 V
VGS = 10 V
ID = 10 A
1.5
IDSS, LEAKAGE (nA)
RDS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
3
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.0
0.5
0
−50
25°C
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
0
8
0
2.0
RDS(on)
, DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on)
, DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
10
2
2.9 V
0
VDS . 10 V
12
−25
0
25
50
75
100
125
150
TJ = 125°C
100
100°C
10
25°C
1
0.1
5
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
20
25
10
15
30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MMSF3350
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
C, CAPACITANCE (pF)
4000
3500
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Ciss
3000
2500
TJ = 25°C
VDS = 0 V
VGS = 0 V
Crss
2000
Ciss
1500
1000
0
−10
Coss
Crss
500
−5
0
VGS
5
VDS
10
15
20
25
30
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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5
18
QT
10
15
VGS
8
12
6
9
4 Q1
2
0
TJ = 25°C
ID = 2 A
Q2
6
3
Q3
VDS
0
10
20
30
40
50
0
Qg, TOTAL GATE CHARGE (nC)
1000
t, TIME (ns)
12
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS
MMSF3350
100
10
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse
recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise
generated. In addition, power dissipation incurred from
switching the diode will be less due to the shorter recovery
time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 16. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
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MMSF3350
IS, SOURCE CURRENT (AMPS)
12
VGS = 0 V
TJ = 25°C
10
8
6
4
2
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
di/dt = 300 A/ms
I S, SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
ta
tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RqJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
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EAS, SINGLE PULSE DRAIN−TO−SOURC
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
MMSF3350
100
10 ms
10
1 ms
100 ms
dc
1
0.1
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
10
100
1000
ID = 10 A
900
800
700
600
500
400
300
200
100
0
25
50
75
100
125
15
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MMSF3350
Rthja(t)
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
TYPICAL ELECTRICAL CHARACTERISTICS
100
0
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
DUTY CYCLE
D = 0.5
10
0
0.2
0.1
0.05
10
RqJA(t) = r(t) RqJA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TA = P(pk) RqJA(t)
0.02
0.01
1
t2
0.1
SINGLE PULSE
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (seconds)
1E+00
1E+02
1E+01
1E+0
Figure 14. Thermal Response − Various Duty Cycles
Rthja(t)
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10,000
1
2
3
4
5
1000
100
MIN PAD, jl
MIN PAD, ja 1 INCH PAD,
R
C
R
C
R ja C
0.0758 1.07 0.0707 0.417 0.0866 0.0142
1.12 16.9
0.456 3.10 0.558 0.106
276
6.61 1.59
11.0
4.95 46.7
5.64 289
60.8 1090
31.6 318
63.8 13,600 45.4 12,500 3.95 9,580
R1
CHIP
JUNCTION C1
R2
C2
R3
C3
R4
C4
C5
AMBIENT
Rthja, MIN PAD
Rthja, 1 INCH PAD
Rthjl, MIN PAD
10
1
R5
1E−03
1E−02
1E−01
1E+00
t, TIME (seconds)
1E+01
1E+02
1E+
Figure 15. Thermal Response − Various
Mounting/Measurement Conditions
80
MOUNTED ON 2, SQ. FR4 BOARD (1, SQ. 2
OZ. CU 0.06, THICK SINGLE SIDED).
POWER (W)
60
40
trr
tb
20
0
tp
0.01
0.1
1
10
t, TIME (seconds)
Figure 17. Diode Reverse Recovery Waveform
Figure 16. Single Pulse Power
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MMSF3350
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self−align when subjected to a
solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
SO−8 POWER DISSIPATION
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RqJA, the thermal resistance from the
device junction to ambient; and the operating temperature,
TA. Using the values provided on the data sheet for the SO−8
package, PD can be calculated as follows:
PD =
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 2.7 Watts.
PD =
150°C − 25°C
46°C/W
= 2.7 Watts
The 46°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.7 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Clad™. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
TJ(max) − TA
RqJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
•
•
•
•
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
*Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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MMSF3350
TYPICAL SOLDER HEATING PROFILE
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177−189°C. When this type of furnace is used
for solder reflow work, the circuit boards and solder joints
tend to heat first. The components on the board are then
heated by conduction. The circuit board, because it has a
large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones and
a figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 1 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems, but it is a
good starting point. Factors that can affect the profile
include the type of soldering system in use, density and types
of components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 5
STEP 1
STEP 4
STEP 2
STEP 3
HEATING
PREHEAT
HEATING
VENT
HEATING
ZONE 1
“SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“SPIKE”
“RAMP”
“SOAK”
“RAMP”
200°C
170°C
DESIRED CURVE FOR HIGH
160°C
MASS ASSEMBLIES
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
150°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
140°C(DEPENDING ON
MASS OF ASSEMBLY)
100°C
100°C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TMAX
TIME (3 TO 7 MINUTES TOTAL)
Figure 18. Typical Solder Heating Profile
DEVICE MARKING
S3350
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
13″
12 mm embossed tape
2500 units
MMSF3350R2
http://onsemi.com
11
MMSF3350
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AA
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 12:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0_
8_
0.010
0.020
0.228
0.244
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
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HDTMOS is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
Thermal Clad is a registered trademark of the Bergquist Company.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MMSF3350/D