SUTEX HV9123NG-G High-voltage, current-mode pwm controller Datasheet

Supertex inc.
HV9123
High-Voltage,
Current-Mode PWM Controller
Features
► 10 to 450V input voltage range
► <1.3mA supply current
► >1.0MHz clock
► >20:1 dynamic range @ 500KHz
►► 99% Maximum duty cycle version
► Low internal noise
Applications
►
►
►
►
►
Off-line high frequency power supplies
Universal input power supplies
High density power supplies
Very high efficiency power supplies
Extra wide load range power supplies
General Description
The Supertex HV9123 is a Switch Mode Power Supply
(SMPS) controller subsystem that can start and run
directly from almost any DC input, from a 12V battery
to a rectified and filtered 240VAC line. It contains all the
elements required to build a single-switch converter except
for the switch, magnetic assembly, output rectifier(s) and
filter(s).
A unique input circuit allows the HV9123 to self-start directly
from a high voltage input, and subsequently take the power
to operate from one of the outputs of the converter it is
controlling, allowing very efficient operation while maintaining
input-to-output galvanic isolation limited in voltage only by
the insulation system of the associated magnetic assembly.
A ±2% internal bandgap reference, internal operational
amplifier, very high speed comparator, and output buffer
allow production of rugged, high performance, high efficiency
power supplies of 50W or more, which can still be over 80%
efficient at outputs of 1.0W or less. The wide dynamic range of
the controller system allows designs with extremely wide line
and load variations with much less difficulty and much higher
efficiency than usual. The exceptionally wide input voltage
range also allows better usage of energy stored in input
dropout capacitors than with other PWM ICs. Remote on/off
controls allow either latching or nonlatching remote shutdown.
During shutdown, the power required is under 6.0mW.
For detailed circuit and application information, please
refer to application notes AN-H13, AN-H21 to AN-H24.
Functional Block Diagram
15 (19)
FB
COMP DISCHARGE
OSC
OUT
8 (10)
OSC
IN
Error
Amplifier
VREF
OSC
–
11 (14)
+
2V
4V
BIAS
VDD
+VIN
Modulator
Comparator
+
REF
GEN
16 (20)
–
Current
Sources
7 (9)
R
S
+
To
Internal
Circuits
To VDD
5 (6)
OUTPUT
Q
Current Limit
Comparator
–
6 (8)
-VIN
1.2V
VDD
1 (3)
–
–
+
8.1V
8.6V
+
Undervoltage
Comparator
Q
S
R
4 (5)
SENSE
12 (16)
SHUTDOWN
13 (17)
RESET
Pre-regulator/Startup
Note:
Pin numbers in parentheses are for PLCC package.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV9123
Ordering Information
Pin Configurations
Package Options
Device
16-Lead SOIC
16-Lead PDIP
1
.790x.250in body
.210in height (max)
.100in pitch
.353x.353in body
.180in height (max)
.050in pitch
HV9123NG-G
HV9123P-G
HV9123PJ-G
4
16-Lead SOIC (NG)
2
Absolute Maximum Ratings
16-Lead PDIP (P)
1
20
20-Lead PLCC (PJ)
Parameter
Value
Input voltage, VIN
450V
Device supply voltage, VDD
15.5V
Logic input voltage
-0.3V to VDD +0.3V
Linear input voltage
-0.3V to VDD +0.3V
Preregulator input current, IIN
(continuous)
2.5mA
Operating junction temperature (TJ)
150OC
Storage temperature
16
20-Lead PLCC
9.90x3.90mm body
1.75mm height (max)
1.27mm pitch
HV9123
1
16
-65OC to +150OC
Power dissipation:
Product Marking
Top Marking
HV9123NG
YWW
LLLLLLLL
Bottom Marking
CCCCCCCCC AAA
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead SOIC (NG)
Top Marking
YYWW
HV9123P
16-Lead SOIC
900mW
16-Lead PDIP
1000mW
20-Lead PLCC
1400mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead PDIP (P)
Top Marking
YY = Year Sealed
WW = Week Sealed
HV9123PJ
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
YYWW AAA
CCCCCCCCCCC
*May be part of top marking
Package may or may not include the following marks: Si or
20-Lead PLCC (PJ)
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
HV9123
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
3.92
4.00
4.08
3.84
4.00
4.16
Units
Conditions
Reference
V
RL = 10MΩ
VREF
Output voltage
-
ZOUT
Output impedance
#
15
30
45
KΩ
---
ISHORT
Short circuit current
-
-
125
250
μA
VREF = -VIN
ΔVREF
Change in VREF with temperature
#
-
0.25
-
mV/°C
-
1.0
3.0
-
MHz
-
80
100
120
-
160
200
240
RL = 10MΩ, TA = -55 to 125OC
TA = -55 to 125°C
Oscillator
fMAX
Oscillator frequency
fOSC
Initial accuracy1
ΔVOSC
Voltage stability
-
-
-
15
%
TCOSC
Temperature coefficient
#
-
170
-
ppm/°C
Maximum duty cycle
#
95
97
99
%
---
Deadtime
#
-
225
-
ns
---
Minimum duty cycle
-
-
-
0
%
---
Maximum pulse width before
pulse drops out
#
-
80
125
ns
---
Maximum input signal
-
1.0
1.2
1.4
V
VFB = 0V
Delay to output
#
-
80
120
ns
VSENSE = 1.5V, VCOMP ≤ 2.0V
PWM
DMAX
DMIN
KHz
ROSC = 0Ω
ROSC = 330KΩ
ROSC = 150KΩ
9.5V < VDD < 13.5V
TA = -55 to 125°C
Current Limit
VLIM
tD
Error Amplifier
VFB
Feedback voltage
-
3.92
4.00
4.08
V
VFB shorted to COMP
IIN
Input bias current
-
-
25
500
nA
VFB = 4.0V
VOS
Input offset voltage
-
nulled during trim
AVOL
Open loop voltage gain
#
60
80
GB
Unity gain bandwidth
#
1.0
1.3
ZOUT
Out impedance
#
Output source current
-
-1.4
-2.0
-
mA
VFB = 3.4V
Output sink current
-
0.12
0.15
-
mA
VFB = 4.5V
Power supply rejection
#
dB
---
ISOURCE
ISINK
PSRR
-
---
-
dB
---
-
MHz
---
Ω
---
see Fig. 1
see Fig. 2
Notes:
# Guaranteed by design.
1. Stray capacitance on OSC In pin must be ≤5pF.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV9123
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
Pre-regulator/Startup
+VIN
Input voltage
-
10
-
450
V
IIN < 10µA; VCC > 9.4V
+IIN
Input leakage current
-
-
-
10
μA
VDD > 9.4V
VTH
VDD pre-regulator turn-off
threshold voltage
-
8.0
8.7
9.4
V
IPREREG = 10µA
Undervoltage lockout
-
7.0
8.1
8.9
V
---
IDD
Supply current
-
-
0.75
1.3
mA
CL < 75pF
IQ
Quiescent supply current
-
-
0.55
-
mA
SHUTDOWN = -VIN
IBIAS
Nominal bias current
-
-
20
-
μA
---
VDD
Operating range
-
9.0
-
13.5
V
---
VLOCK
Supply
Shutdown Logic
tSD
SHUTDOWN delay
#
-
50
100
ns
CL = 500pF, VSENSE = -VIN
tSW
SHUTDOWN pulse width
#
50
-
-
ns
---
tRW
RESET pulse width
#
50
-
-
ns
---
tLW
Latching pulse width
#
25
-
-
ns
SHUTDOWN and RESET low
VIL
Input low voltage
-
-
-
2.0
V
---
VIH
Input high voltage
-
7.0
-
-
V
---
IIH
Input current, input high voltage
-
-
1.0
5.0
μA
VIN = VDD
IIL
Input current, input low voltage
-
-
-25
-35
μA
VIN = 0V
-
VDD -0.25
-
-
V
IOUT = 10mA
-
VDD -0.3
-
-
V
IOUT = 10mA,
TA = -55 to 125°C
-
-
-
0.2
V
IOUT = -10mA
-
-
-
0.3
V
IOUT = -10mA,
TA = -55 to 125°C
Pull up
-
-
15
25
Ω
Pull down
-
-
8.0
20
Ω
Pull up
-
-
20
30
Ω
Pull down
-
-
10
30
Ω
IOUT = ±10mA,
TA = -55 to 125°C
Output
VOH
Output high voltage
VOL
Output low voltage
ROUT
Output resistance
IOUT = ±10mA
tR
Rise time
#
-
30
75
ns
CL = 500pF
tF
Fall time
#
-
20
75
ns
CL = 500pF
Note:
# Guaranteed by design.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
HV9123
Test Circuits
+10V
(VDD)
Error Amp ZOUT
0.1V swept 10Hz - 1.0MHz
PSRR
1.0V swept 100Hz - 2.2MHz
100K 1%
10.0V
60.4K
(FB)
100K1%
–
+
Reference
GND
(-VIN)
V1
Tektronix
P6021
(1 turn
secondary)
4.0V
40.2K
Reference
V2
0.1µF
–
V1
+
V2
0.1µF
Note:
Set feedback voltage so that VCOMP = VDIVIDE ± 1.0mV before connecting transformer.
Detailed Description
Preregulator
The preregulator/startup circuit for the HV9123 consists of
a high-voltage n-channel depletion-mode DMOS transistor
driven by an error amplifier to form a variable current path
between the VIN terminal and the VDD terminal. Maximum
current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD
rises to somewhere between 7.8 and 9.4V, so that if VDD is
held at 10 or 12V by an external source (generally the supply the chip is controlling), no current other than leakage is
drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
CSTORAGE ≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable. A common resistor divider string
is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting
the undervoltage sense point about 0.6V lower on the string
than the FET shutoff point guarantees that the undervoltage
lockout always releases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the bias pin
and VSS is required by the HV9123 to set currents in a series of current mirrors used by the analog sections of the
chip. Nominal external bias current requirement is 15 to
Supertex inc.
20µA, which can be set by a 390 to 510KΩ resistor if a 10V
VDD is used, or a 510 to 680KΩ resistor if VDD will be 12V. A
precision resistor is not required; ± 5% is fine.
Clock Oscillator
The clock oscillator of the HV9123 consists of a ring of
CMOS inverters, timing capacitors, and a capacitor discharge FET. A single external resistor between the OSC IN
and OSC OUT pins is required to set oscillator frequency
(see graph). The discharge can either be connected to VSS
directly or connected to VSS through a resistor used to set
a dead time.
One difference exists between the Supertex HV9123 and
competitive 9123s: The oscillator is shut off when a shutoff
command is received. This saves about 150µA of quiescent
current, which aids in the construction of power supplies
to meet CCITT specification I-430, and in other situations
where an absolute minimum of quiescent power dissipation
is required.
Reference
The Reference of the HV9123 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when connected
in a gain of -1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
A ≈ 50KΩ resistor is placed internally between the output
of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
HV9123
amplifier). This allows overriding the internal reference with
a low-impedance voltage source ≤6.0V. Using an external
reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage
required. In general, because the reference voltage of the
Supertex HV9123 is not noisy, as some previous examples
have been, overriding the reference should seldom be necessary.
Because the reference of the HV9123 is a high impedance
node, and usually there will be significant electrical noise
near it, a bypass capacitor between the reference pin and
VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF.
Error Amplifier
The error amplifier in the HV9123 is a true low-power differential input operational amplifier intended for around-theamplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common-mode
range includes ground and the input impedance is very high.
This is followed by bipolar gain stages which provide high
gain without the electrical noise of all-MOS amplifiers. The
amplifier is unity-gain stable.
Current Sense Comparators
The HV9123 uses a true dual-comparator system with independent comparators for modulation and current limiting.
This allows the designer greater latitude in compensation
design, as there are no clamps (except ESD protection) on
the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction.
Remote Shutdown
The SHUTDOWN and RESET pins of the HV9123 can be
used to perform either latching or non-latching shutdown of
a converter as required. These pins have internal current
source pull-ups so they can be driven from open-drain logic.
When not used, they should be left open, or connected to
VDD.
Output Buffer
The output buffer of the HV9123 is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the
body-drain diodes of the output stage can be used for spike
clipping if necessary, and external Schottky diode clamping
of the output is not required.
Truth Table
SHUTDOWN
RESET
Output
H
H
H
H→L
L
H
Off, not latched
L
L
Off, latched
L→H
L
Off, latched, no change
Normal operation
Normal operation, no change
Shutdown Timing Waveforms
1.5V
SENSE
0
VDD
50%
SHUTDOWN
tR ≤ 10ns
tF ≤ 10ns
50%
0
tSD
tD
VDD
OUTPUT
0
VDD
SHUTDOWN
0
VDD
OUTPUT
0
90%
tSW
50%
90%
50%
tR, tF ≤ 10ns
tLW
VDD
RESET
0
Supertex inc.
50%
50%
tRW
50%
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6
HV9123
Typical Performance Curves
Error Amplifier Output Impedance (Z0)
106
Output Switching Frequency
vs. Oscillator Resistance
1M
105
104
fOUT (Hz)
Z0 (Ω)
103
102
100k
10
1.0
0.1
100
1K
10K
100K
1M
10k
10k
10M
100k
Frequency (Hz)
PSRR - Error Amplifier and Reference
80
-10
70
-20
60
-30
50
180
-50
60
40
0
20
-60
10
-70
0
10
100
1K
10K
100K
-60
-120
-180
-10
100
1M
1K
10K
1M
RDISCHARGE vs. tOFF
104
100
VDD = 10V
ROSC = 100k
VDD = 10V
tOFF (nsec)
Bias Current (µA)
100K
Frequency (Hz)
Frequency (Hz)
10
103
ROSC = 10k
ROSC = 1.0k
1.0
105
106
107
Bias Resistance (Ω)
Supertex inc.
102
10-1
10
101
102
103
104
105
106
RDISCHARGE (Ω)
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7
Phase (OC)
-40
-80
Error Amplifier Open Loop Gain/Phase
120
Gain (dB)
PSRR (dB)
0
1M
ROSC (Ω)
HV9123
Pin Descriptions
16-Lead SOIC (NG)
Pin #
Description
Pin #
Description
1
+VIN
9
OSC IN
-
-
10
DISCHARGE
-
-
11
VREF
4
SENSE
12
SHUTDOWN
5
OUTPUT
13
RESET
6
-VIN
14
COMP
7
VDD
15
FB
8
OSC OUT
16
BIAS
Pin #
Description
Pin #
Description
1
+VIN
9
OSC IN
2
NC
10
DISCHARGE
3
NC
11
VREF
4
SENSE
12
SHUTDOWN
5
OUTPUT
13
RESET
6
-VIN
14
COMP
7
VDD
15
FB
8
OSC OUT
16
BIAS
Pin #
Description
Pin #
Description
1
NC
11
OSC IN
2
NC
12
DISCHARGE
3
+VIN
13
NC
4
NC
14
VREF
5
SENSE
15
NC
6
OUTPUT
16
SHUTDOWN
7
NC
17
RESET
8
-VIN
18
COMP
9
VDD
19
FB
10
OSC OUT
20
BIAS
16-Lead PDIP (P)
20-Lead PLCC (PJ)
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
8
HV9123
16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D
16
θ1
E1 E
Note 1
(Index Area
D/2 x E1/2)
L2
1
L
Top View
View B
A
A A2
e
A1
View
B
h
h
Seating
Plane
Seating
Plane
θ
L1
Gauge
Plane
Note 1
b
Side View
View A-A
A
Note:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be:
a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
1.35*
0.10
1.25
0.31
9.80*
5.80* 3.80*
NOM
-
-
-
-
9.90
6.00
MAX
1.75
0.25
1.65*
0.51
3.90
10.00* 6.20* 4.00*
e
1.27
BSC
h
L
0.25
0.40
-
-
0.50
1.27
L1
L2
1.04 0.25
REF BSC
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-16SONG, Version G041309.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
9
θ
θ1
0
5O
O
-
-
8O
15O
HV9123
16-Lead PDIP (.300in Row Spacing) Package Outline (P)
.790x.250in body, .210in height (max), .100in pitch
D
16
Note 1
(Index Area)
E1
E
b1
1
D1
D1
b
Top View
A
View B
View B
A
Seating
Plane
A2
A1
L
eA
eB
e
A
Side View
View A - A
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
MIN
.130*
.015
.115
.014
.045
.780
.005
.290
NOM
-
-
.130
.018
.060
.790
-
.310
.250
MAX
.210
.035*
.195
.023
.070
.810
.050*
.325
.280
†
†
E1
†
.240
e
eA
.100
BSC
.300
BSC
eB
L
.300*
.115
-
.130
.430
.150
JEDEC Registration MS-001, Variation AB, Issue D, June, 1993.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-16DIPP, Version B041009.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
10
HV9123
20-Lead PLCC Package Outline (PJ)
.353x.353in body, .180in height (max), .050in pitch
.048/.042
x 45O
D
D1
1
3
.150 MAX
.056/.042
x 45O
20
Note 1
(Index Area)
18
.075 MAX
E1
E
8
Note 2
.020max
(3 Places)
13
Top View
Vertical Side View
View
B
A
b1
Base .020 MIN
Plane
A1 A2
Seating
Plane
e
b
Horizontal Side View
R
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.385
.350
.385
.350
NOM
.172
.105
-
-
-
.390
.353
.390
.353
MAX
.180
.120
.083
.021
.032
.395
.356
.395
.356
e
.050
BSC
R
.025
.035
.045
JEDEC Registration MS-018, Variation AA, Issue A, June, 1993.
Drawings not to scale.
Supertex Doc. #: DSPD-20PLCCPJ, Version C031111
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV9123
A040711
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
11
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