AD ADA8282CP-EBZ Radar receive path afe - 4-channel lna and pga Datasheet

Data Sheet
Radar Receive Path AFE:
4-Channel LNA and PGA
ADA8282
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
ADA8282
+INA
+OUTA
3nV√Hz
LNA
PGA
–INA
–OUTA
+24dB
–6dB TO +12dB
+INB
+OUTB
3nV√Hz
LNA
PGA
–INB
–OUTB
+24dB
–6dB TO +12dB
+INC
+OUTC
3nV√Hz
LNA
PGA
–INC
–OUTC
+24dB
–6dB TO +12dB
+IND
+OUTD
3nV√Hz
LNA
PGA
–IND
–OUTD
+24dB
POWER
MODE
–6dB TO +12dB
GAIN
SELECT
SPI
CS SCLK SDI SDO VIO AVDD RESET
13132-001
4 channels of low noise amplifiers (LNAs) followed by
programmable gain amplifiers (PGAs)
Minimum −3 dB bandwidth of 5 MHz
Typical –3 dB bandwidth of 42.3 MHz
Typical slew rate of 28 V/µs
Differential input and output
Gain of 18 dB to 36 dB in 6 dB steps
Selectable low noise and low power modes
Input referred noise of 4.5 nV/√Hz at 18.3 mW per channel
Input referred noise of 3.8 nV/√Hz at 26.5 mW per channel
Input referred noise of 3.6 nV/√Hz at 34.8 mW per channel
Input referred noise of 3.4 nV/√Hz at 54.8 mW per channel
Channel to channel gain matching of ±0.25 dB
Absolute gain error of ±0.5 dB
SPI programmable
Power-down mode (SPI selectable)
3.1 V p-p differential output swing when using a 3.3 V supply
32-lead, 5 mm × 5 mm LFCSP package
Specified from −40°C to +125°C
Qualified for automotive applications
Figure 1.
Automotive radar
Adaptive cruise control
Collision avoidance
Blind spot detection
Self parking
Electronic bumpers
GENERAL DESCRIPTION
The ADA8282 is designed for applications that require low cost,
low power, compact size, and flexibility. The ADA8282 has four
parallel channels, each including an LNA and a PGA. The LNA
and PGA combine to form a signal chain that features a gain range
of 18 dB to 36 dB in 6 dB increments with a guaranteed
minimum bandwidth of 5 MHz.
Using the highest power settings, the combined input referred
voltage noise of the combined LNA and PGA channel is
3.4 nV/√Hz at maximum gain.
Rev. 0
The ADA8282 can be configured in four power modes that
trade off power and noise performance to optimize the overall
performance according to the end application.
Fabricated in an advanced complementary metal-oxide
semiconductor (CMOS) process, the ADA8282 is available in a
5 mm × 5 mm, RoHS-compliant, 32-lead LFCSP. It is specified
over the automotive temperature range of −40°C to +125°C.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility isassumed by Analog Devicesfor its use,norfor any infringements of patents or other
rights of third parties thatmay resultfrom its use.Specificationssubject to changewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices .
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA8282
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
Output Swing Variation with Gain......................................... 12
Applications ................................................................................... 1
Offset Voltage Adjustments .................................................... 12
Functional Block Diagram............................................................ 1
Single-Ended or Differential Input......................................... 12
General Description ...................................................................... 1
Short-Circuit Currents............................................................ 12
Revision History ............................................................................ 2
SPI Interface ............................................................................. 12
Specifications ................................................................................. 3
Channel to Channel Phase Matching..................................... 13
Digital Specifications................................................................. 4
Applications ................................................................................. 14
Absolute Maximum Ratings ......................................................... 5
Increased Gain Using Two ADA8282 Devices in Series....... 14
Thermal Resistance ................................................................... 5
Multiplexing Inputs Using Multiple ADA8282 Devices....... 15
ESD Caution............................................................................... 5
Basic Connections for a Typical Application......................... 16
Pin Configuration and Function Descriptions............................ 6
Register Map ................................................................................ 17
Typical Performance Characteristics............................................ 7
Register Summary ................................................................... 17
Theory of Operation.................................................................... 11
Register Details ........................................................................ 17
Radar Receive Path AFE.......................................................... 11
Outline Dimensions .................................................................... 21
Default SPI Settings................................................................. 11
Ordering Guide............................................................................ 21
Input Impedance...................................................................... 11
Automotive Products............................................................... 21
Power Modes............................................................................ 11
Programmable Gain Range ..................................................... 12
REVISION HISTORY
7/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 21
Data Sheet
ADA8282
SPECIFICATIONS
AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = −40°C to +125°C, PGA_BIAS_SEL = b’10,
LNA_BIAS_SEL= b’10, unless otherwise noted.
Table 1.
Parameter
ANALOG CHANNEL CHARACTERISTICS
Gain
Gain Range
Gain Error
−3 dB Bandwidth
Channel to Channel Gain Matching
Channel to Channel Phase Matching1
Slew Rate
Input Referred Noise
Output Referred Noise
Offset Voltage
Referred to Input
Referred to Output
SPI Offset Adjustment Resolution
(Relative to Input)
SPI Offset Adjustment Range (Relative
to Input)
Harmonic Distortion
Second Harmonic (HD2)
Third Harmonic (HD3)
Intermodulation Distortion
Test Conditions/Comments
Min
Typ
Max
Unit
±0.5
dB
dB
dB
18/24/30/36
18
VOUT = 100 mV p-p, gain = 36 dB
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
Frequencies up to 5 MHz
Frequencies up to 5 MHz
Gain = 36 dB at 2 MHz
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
50 Ω impedance used for voltage to power
conversion
Gain = 18 dB
Gain = 24 dB
Gain = 30 dB
Gain = 36 dB
5
5
5
5
20.5
34.2
42.3
52.3
0.1
0.1
28
±0.25
±1
MHz
MHz
MHz
MHz
dB
Degrees
V/μs
4.5
3.8
3.6
3.4
−156
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
dBm/Hz
36
61
115
218
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Gain = 36 dB
Gain = 36 dB
LNA_BIAS_SEL = b’00
±0.8
±50
113
LNA_BIAS_SEL = b’01
LNA_BIAS_SEL = b’10
LNA_BIAS_SEL = b’11
LNA_BIAS_SEL = b’00
186
250
440
±4
μV
μV
μV
mV
LNA_BIAS_SEL = b’01
LNA_BIAS_SEL = b’10
LNA_BIAS_SEL = b’11
±6
±8
±14
mV
mV
mV
VOUT = 2 V p-p, fIN = 100 kHz
VOUT = 100 mV p-p, fIN = 2 MHz
VOUT = 2 V p-p, fIN = 100 kHz
VOUT = 100 mV p-p, fIN = 2 MHz
VOUT = 2 V p-p, fIN1 = 100 kHz, fIN2 = 150 kHz
VOUT = 100 mV p-p, fIN1 = 2 MHz, fIN2 = 2.1 MHz
−70
−85
−85
−95
−72
−83
−80
−105
dBc
dBc
dBc
dBc
dBc
dBc
dB
dBc
Common-Mode Rejection Ratio (CMRR)
Crosstalk
Rev. 0 | Page 3 of 21
±3
±200
mV
mV
μV
ADA8282
Parameter
POWER SUPPLY
Total Power Dissipation
Data Sheet
Test Conditions/Comments
Min
Typ
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
Power Dissipation per Channel
AVDD
VIO
IAVDD
IVIO
Power-Down Current
Power-Down Dissipation
Power-Up Time
Power Supply Rejection Ratio (PSRR)
INPUT
Input Resistance
Differential Input Resistance
Common-Mode Input Resistance
Differential Input Capacitance
OUTPUT
Output Voltage Swing
Output Balance
Short-Circuit Current
Capacitive Load
1
Max
Unit
73
106
139
219
mW
mW
mW
mW
mW
V
V
31
3.0
1.8
3.6
3.6
Four channels active
PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01
PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10
PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11
One channel active
19.6
29
37.7
60
9.8
10
20
0.07
5
IAVDD and IVIO
Time to operational after chip is enabled
At dc
At 1 MHz
mA
mA
mA
mA
mA
μA
μA
mW
μs
dB
dB
1.7
0.42
13.2
kΩ
kΩ
pF
−80
−80
1.45
0.37
10.8
+OUTx (−OUTx), gain = 18 dB
+OUTx (−OUTx), gain = 24 dB, 30 dB, or 36 dB
fIN = 100 kHz
Per output at 25°C
20% overshoot
22
32
42
66.3
11
12
100
0.33
1.57
0.39
12
3.1
6.3
V p-p
V p-p
dB
mA
pF
−70
205
30
Normalized to 0° phase matching at 25°C; see the Theory of Operation section for details.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
LOGIC INPUT (CS)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUTS (SDI, SCLK, RESET)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Maximum SCLK Frequency
LOGIC OUTPUT (SDO)
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
Temperature
Min
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
0
Typ
Max
Unit
VIO + 0.3
0.3
V
V
kΩ
pF
VIO + 0.3
0.3
10
V
V
kΩ
pF
MHz
0.3
V
V
15
0.5
2.5
2
Full
Full
VIO − 0.3
Rev. 0 | Page 4 of 21
Data Sheet
ADA8282
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Electrical
AVDD to EPAD
+INx, −INx, SCLK, SDI, SDO, CS, VIO, RESET,
−OUTx, +OUTx to EPAD
ESD Ratings
Human Body Model (HBM)
Charged Device Model (CDM)
Environmental
Operating Temperature Range (Ambient)
Storage Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
−0.3 V to +3.9 V
−0.3V to AVDD +
0.3 V
±4000 V
±2000 V
Table 4. Thermal Resistance
Package Type
32-Lead, 5 mm × 5 mm LFCSP
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 21
θJA
33.51
θJC
4.1
Unit
°C/W
ADA8282
Data Sheet
32
31
30
29
28
27
26
25
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADA8282
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE
PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
13132-002
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
9
10
11
12
13
14
15
16
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Mnemonic
EPAD
+INA
−INA
+INB
−INB
+INC
−INC
+IND
−IND
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
−OUTD
+OUTD
−OUTC
+OUTC
−OUTB
+OUTB
−OUTA
+OUTA
AVDD
VIO
RESET
28
29
30
31
32
SCLK
CS
SDI
SDO
AVDD
Description
Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane.
Positive LNA Analog Input for Channel A.
Negative LNA Analog Input for Channel A.
Positive LNA Analog Input for Channel B.
Negative LNA Analog Input for Channel B.
Positive LNA Analog Input for Channel C.
Negative LNA Analog Input for Channel C.
Positive LNA Analog Input for Channel D.
Negative LNA Analog Input for Channel D.
3.3 V Analog Supply.
No Internal Connection. Leave this pin floating.
No Internal Connection. Leave this pin floating.
No Internal Connection. Leave this pin floating.
No Internal Connection. Leave this pin floating.
No Internal Connection. Leave this pin floating.
No Internal Connection. Leave this pin floating.
3.3 V Analog Supply.
Negative Analog Output for Channel D.
Positive Analog Output for Channel D.
Negative Analog Output for Channel C.
Positive Analog Output for Channel C.
Negative Analog Output for Channel B.
Positive Analog Output for Channel B.
Negative Analog Output for Channel A.
Positive Analog Output for Channel A.
3.3 V Analog Supply.
Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V.
Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is
pulled to ground by default. A logic high triggers the reset.
Serial Clock.
Chip Select Bar.
Serial Data Input.
Serial Data Output.
3.3 V Analog Supply.
Rev. 0 | Page 6 of 21
Data Sheet
ADA8282
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = 25°C, PGA_BIAS_SEL = b’10, LNA_BIAS_SEL=
b’10, unless otherwise noted.
350
25000
TA = +125°C
TA = +25°C
TA = –40°C
TA = +125°C
TA = –40°C
300
20000
NUMBER OF HITS
NUMBER OF HITS
250
15000
10000
200
150
100
5000
0
2500
N: 12353
M: –7.49789
SD: 20.0841
–20
2000
N: 11292
M: 0.0246995
SD: 21.4755
–40
1500
1000
–80
500
–100
–50
0
50
100
150
VOS (mV)
Figure 4. Output Offset Voltage Distribution
3000
13132-107
0.30
0.35
0.25
0.15
0.20
0.10
30dB
–120
13132-110
–100
0.05
24dB
18dB
36dB
0
–150
0
–0.10
–60
0
1
2
3
4
5
FREQUENCY (MHz)
13132-108
THD (dB)
NUMBER OF HITS
–0.05
Figure 6. Distribution of Channel to Channel Phase Matching
N: 12199
M: –13.1269
SD: 19.535
TA = +125°C
TA = +25°C
TA = –40°C
–0.15
PHASE MISMATCH (Degrees)
Figure 3. Gain Accuracy Distribution
3000
–0.20
13132-103
–0.20
–0.19
–0.18
–0.17
–0.16
–0.15
–0.14
–0.13
–0.12
–0.11
–0.10
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
GAIN ERROR (dB)
–0.30
0
0
–0.25
50
Figure 7. Total Harmonic Distortion (THD) vs. Frequency for Various
Gains, VOUT = −10 dBm
1800
TA = +125°C
TA = +25°C
TA = –40°C
1600
2500
INPUT IMPEDANCE (Ω)
2000
1500
1000
1200
1000
800
600
400
500
DC GAIN MISMATCH (dB)
0
1k
13132-106
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 8. Input Impedance vs. Frequency
Figure 5. Distribution of Channel to Channel Gain Matching
Rev. 0 | Page 7 of 21
1G
13132-109
200
0
NUMBER OF HITS
1400
ADA8282
Data Sheet
42
GAIN = 36dB
36
30
ANALOG OUTPUT (1V/DIV)
2V
24
ANALOG OUTPUT
18
GAIN (dB)
250mV
GAIN = 30dB
GAIN = 24dB
GAIN = 18dB
12
6
0
SDI
–6
b'11
–12
TIME (80ns/DIV)
–24
100k
100M
10M
1M
13132-113
–18
13132-105
b'00
FREQUENCY (Hz)
Figure 12. Frequency Response at All Gains (Bias Mode 0)
Figure 9. Gain Step Transient Response
30
42
GAIN = 18dB
GAIN = 24dB
GAIN = 30dB
GAIN = 36dB
25
GAIN = 36dB
36
30
18
GAIN (dB)
NOISE (nV/√Hz)
24
20
15
GAIN = 30dB
GAIN = 24dB
GAIN = 18dB
12
6
0
10
–6
–12
5
100k
10M
1M
100M
FREQUENCY (Hz)
–24
100k
13132-111
10k
1M
10M
13132-114
–18
0
1k
100M
FREQUENCY (Hz)
Figure 10. Input Referred Noise vs. Frequency
Figure 13. Frequency Response at All Gains (Bias Mode 2)
40
4
35
3
30
2
AMPLITUDE (V)
25
50Ω
20
15
VOUT
1
0
–1
10
–2
5
–3
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
–4
0
100
200
300
400
500
600
TIME (ns)
Figure 11. Noise Figure vs. Frequency
Figure 14. Overdrive Recovery
Rev. 0 | Page 8 of 21
700
800
13132-115
UNTERMINATED
13132-112
NOISE FIGURE (dB)
VIN × GAIN
Data Sheet
ADA8282
200
GAIN = 36dB
29
28
SLEW RATE (V/µs)
150
VOUT (mV)
30
NO LOAD
5pF
33pF
66pF
100pF
100
50
0
GAIN = 30dB
27
GAIN = 24dB
26
25
GAIN = 18dB
24
23
22
200
400
600
800
1000
TIME (ns)
20
–40
MODE 0
MODE 1
MODE 2
MODE 3
VOUT (V)
0
–0.5
200
300
400
500
600
700
800
900
1000
TIME (ns)
13132-121
–1.0
100
65
80
95
110
125
3.4
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
–0.2
–0.6
–1.0
–1.4
–1.8
–2.2
–2.6
–3.0
–3.4
18
24
30
36
Figure 19. Maximum and Minimum Differential VOUT vs. Gain
4
500
480
3
OUTPUT VOLTAGE SWING (V)
460
440
420
400
380
360
340
2
1
0
–1
TA = +85°C
TA = +25°C
TA = –40°C
–2
–3
320
–25
10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 17. Short-Circuit Current vs. Temperature Per Channel
–4
10
13132-118
SHORT-CIRCUIT CURRENT (mA)
50
35
GAIN (dB)
Figure 16. Large Signal Pulse Response for Various LNA and PGA Bias Modes
300
–40
20
100
1k
10k
OUTPUT LOAD RESISTANCE (Ω)
100k
13132-117
VOUT (V)
0.5
0
5
Figure 18. Output Slew Rate vs. Temperature
1.5
–1.5
10
TEMPERATURE (°C)
Figure 15. Pulse Response at Various Output Capacitive Loads
1.0
–25
13132-125
0
13132-116
–50
13132-119
21
Figure 20. Differential Output Voltage Swing vs. Output Load Resistance
Rev. 0 | Page 9 of 21
ADA8282
Data Sheet
120
0
GAIN = 18dB
GAIN = 24dB
GAIN = 30dB
GAIN = 36dB
100
–20
–40
CROSSTALK (dB)
PSRR (dB)
80
60
40
–60
–80
–100
20
1M
10M
100M
FREQUENCY (Hz)
–140
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency at Various Gains
13132-124
100k
13132-122
0
10k
–120
Figure 23. Crosstalk vs. Frequency
37.85
100
90
37.80
SUPPLY CURRENT (mA)
80
60
50
40
30
GAIN = 18dB
GAIN = 24dB
GAIN = 30dB
GAIN = 36dB
10
0
100k
1M
10M
FREQUENCY (Hz)
100M
37.75
37.70
37.65
37.60
37.55
–40
–25
10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 24. Quiescent Supply Current vs. Temperature
Figure 22. CMRR vs. Frequency at Various Gains
Rev. 0 | Page 10 of 21
125
13132-120
20
13132-123
CMRR (dB)
70
Data Sheet
ADA8282
THEORY OF OPERATION
The input to the ADA8282 is typically ac-coupled. The ac
coupling capacitors operate with the input impedance of the
ADA8282 to create a high-pass filter with a pole at 1/(2π2RC),
where R = 785 Ω with a typical tolerance of ±15%.
RADAR RECEIVE PATH AFE
The primary application for the ADA8282 is a high speed ramp,
frequency modulated, continuous wave radar (HSR-FMCW radar).
Figure 25 shows a simplified block diagram of an HSR-FMCW
radar system. The signal chain requires multiple channels, each
including an LNA and a PGA. The ADA8282 provides these key
components in a single 5 mm × 5 mm LFCSP.
POWER MODES
The ADA8282 has four power modes that can be controlled
through Register 0x14 (BIAS_SEL). The power modes allow a
user to adjust the power and performance tradeoffs to suit the end
application. Use the low power mode when power savings are in
demand, and use the high power mode in applications that
require increased bandwidth and low noise.
The performance of each component is designed to meet the
demands of an HSR-FMCW radar system. Some examples of
these performance metrics are the LNA noise, PGA gain range,
and signal chain bandwidth and power. The ADA8282 also has
adjustable power modes to adjust the power and performance
level to accommodate a wide variety of applications.
Table 6 shows the power performance trade-offs of the various
SPI settings.
The ADA8282 is programmable via the SPI. Channel gain,
power mode, and offset voltage can be adjusted using the SPI port.
Table 6. Power Mode Trade-Offs
DEFAULT SPI SETTINGS
Mode
Setting
b’00
b’01
b’10
b’11
When initially powered, the ADA8282 defaults to a setting of
0x00 in Register 0x17, which disables all channels. The device is
enabled by writing 0x0F to Register 0x17.
INPUT IMPEDANCE
Power per
Channel
(mW)
18.3
26.5
34.8
54.8
Input Referred
Noise at 2 MHz
(nV/√Hz)
4.5
3.8
3.6
3.4
The input impedance to the ADA8282 is set by an internal 785 Ω
resistance at each input, biased to midsupply by an internal voltage
buffer. Both the positive and negative inputs are biased with the
same network, creating a differential input impedance of 1.57 kΩ.
TRANSMIT SIGNAL GENERATION
REF.
OSCILLATOR
CHIRP RAMP
GENERATOR
VCO
ADA8282
DSP
LNA
PGA
12-BIT
ADC
LNA
PGA
12-BIT
ADC
LNA
PGA
12-BIT
ADC
ANTENNA
Figure 25. Typical Signal Chain Overview
Rev. 0 | Page 11 of 21
13132-021
PA
Typical Bandwidth
(MHz), Gain = 36 dB
20.5
34.2
42.3
52.3
ADA8282
Data Sheet
The default setting (0x20) applies a zero offset, 0x00 applies the
maximum negative offset, and 0x3F applies the maximum
positive offset.
PROGRAMMABLE GAIN RANGE
The ADA8282 has a programmable gain to allow adjusting of
the output amplitudes of signals to accommodate a variety of
applications. The gain of the ADA8282 is programmable in 6 dB
increments from 18 dB to 36 dB. The gain is controlled using
Register 0x15. The same register controls all four channels, but
each channel can be independently controlled by utilizing the
appropriate bits in the register. Channel A is controlled with the
two LSBs of Register 0x15 (Bits[1:0]), Channel B uses Bits[3:2],
Channel C uses Bits[5:4], and Channel D uses the two MSBs,
Bits[7:6].
The range and resolution of the LNA_OFFSETx adjustments
are dependent on the LNA bias mode as described in Table 9.
Table 9. Offset Voltage Adjustments
LNA_BIAS_SEL
Setting
b’00
b’01
b’10
b’11
The gain setting and gains are listed in Table 7.
Table 7. Gain Settings
Referred to Input (RTI)
Offset Resolution (μV)
113
186
250
440
RTI Offset
Range (mV)
±4
±6
±8
±14
VIO Pin
Register 0x15 Setting
b’00
b’01
b’10
b’11
Gain (dB)
18
24
30
36
Gain (V/V)
7.9
15.9
31.6
63.1
The VIO pin sets the voltage levels used by the SPI interface. If
the VIO pin is tied to the 3.3 V supply, the SPI port functions
on 3.3 V logic.
SINGLE-ENDED OR DIFFERENTIAL INPUT
The ADA8282 operates with either a differential or single-ended
signal source. The maximum input voltage swing is the same in
either configuration. When using a single-ended signal source,
connect the unused input to ground with a capacitor. Matching
the ac coupling capacitor to the ac grounding capacitor
optimizes CMRR performance.
OUTPUT SWING VARIATION WITH GAIN
The ADA8282 gain is implemented using two internal gain stages.
The first stage is an LNA with a gain of 24 dB, and the second
stage is a PGA with a gain that varies from −6 dB to +12 dB. The
output of the LNA has a fixed output swing range, and is the
limiting factor when the channel gain is 18 dB. Because of the
limitations of the LNA swing range, the ADA8282 has an output
swing that is dependent on gain, as shown in Table 8.
SHORT-CIRCUIT CURRENTS
The ADA8282 typically has a 205 mA short-circuit current per
output pin. The thermal implications of this current during
unintended shorting of these outputs must be taken into account
when designing boards with this device.
Table 8. Output Swing at Various Gains
Gain (dB)
18
24
30
36
Output Swing (V p-p)
3.1
6.3
6.3
6.3
SPI INTERFACE
The ADA8282 SPI interface uses a 4-wire interface to deliver a
16-bit instruction header, followed by 8 bits of data. The first bit
is a read/write bit. W1 and W0 determine how many bytes are
transferred, and must both be zeros for the ADA8282 to write to a
single register. Then, a 13-bit address and an 8-bit data byte follow.
OFFSET VOLTAGE ADJUSTMENTS
Register 0x10 through Register 0x13 adjust the dc offset voltage
of each channel. The default value of 0x20 is intended to be the
setting for the offset closest to 0 V, but adjustments can be made
as required by the application.
The SPI port operates at SCLK frequencies of up to 10 MHz.
For additional SPI timing information, see the AN-877
Application Note.
CS
SDI DON’T CARE
DON’T CARE
R/W W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
16-BIT INSTRUCTION HEADER
MSB-FIRST 16-BIT INSTRUCTION
Figure 26. Serial Instruction Details
Rev. 0 | Page 12 of 21
A0
D7
D6
D5
D4
D3
D2
REGISTER (N) DATA
D1
D0
DON’T CARE
13132-022
SCLK DON’T CARE
Data Sheet
ADA8282
CHANNEL TO CHANNEL PHASE MATCHING
350
In a multichannel radar application, matching the ac performance
between channels improves the distance and angle resolution of
a detected object, particularly the phase matching in the band of
interest for the application. The ADA8282 layout and design are
optimized to increase phase matching. The ADA8282 also has
sufficient bandwidth to minimize any channel to channel phase
variation for up to 5 MHz input signals.
300
NUMBER OF HITS
250
200
150
100
The phase mismatch between channels can be calibrated at a
single temperature. However, any variation in phase matching
over temperature can still degrade system performance. The
ADA8282 is characterized to capture the maximum channel to
channel phase mismatch as the temperature varies from a
calibration temperature of 25°C.
Figure 27 shows a distribution of channel to channel phase
mismatch for signal frequencies up to 5 MHz. When the initial
phase mismatch between channels is normalized to 0° at +25°C,
the 6σ mismatch is 0.43° at −40°C and 0.6° at +125°C.
TA = +125°C
TA = –40°C
PHASE MISMATCH (Degrees)
Figure 27. Channel to Channel Phase Mismatch, Normalized to 0° at 25°C,
LNA_BIAS_SEL = PGA_BIAS_SEL = b’00, PGA_GAIN = b’11
The amount of channel to channel phase mismatch varies with
the power mode. Table 10 shows the 6σ phase mismatch up to
5 MHz over the full temperature range for all gain settings in
different power modes, when normalized to 0° at 25°C in each
power mode.
Table 10. Maximum Channel to Channel Phase Mismatch over Temperature After 25°C Calibration
PGA_BIAS_SEL
b’00
b’01
b’10
b’11
LNA_BIAS_SEL
b’00
b’01
b’10
b’11
13132-126
0.35
0.30
0.25
0.20
0.15
0.10
0
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
0
–0.30
50
6σ Channel to Channel Phase Mismatch
over Temperature (Degrees)
0.60
0.41
0.33
0.60
Rev. 0 | Page 13 of 21
Maximum Channel to Channel Phase
Mismatch (Degrees)
±1
±1
±1
±1
ADA8282
Data Sheet
APPLICATIONS INFORMATION
INCREASED GAIN USING TWO ADA8282 DEVICES
IN SERIES
Table 11. Gain Settings for Two Devices in Series
For applications that require gains greater than 36 dB, two
ADA8282 devices can be used in series with each other. To
optimize the signal swing for the path, increment the gains
according to Table 11.
GPIO: +3.3V/0V
0.1µF
0.1µF
5
25
27
28
29
26
21
20
EPAD TIED
TO GROUND
6
19
7
18
8
17
9
0.1µF
+3.3V
22
ADA8282
4
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
TO ADC
TO ADC
TO ADC
TO ADC
0.1µF
+3.3V
0.1µF
+3.3V
+3.3V
Figure 28. Using Two ADA8282 Devices in Series to Increase Gain
Rev. 0 | Page 14 of 21
13132-023
0.1µF
3
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
16
0.1µF
23
15
0.1µF
2
14
17
0.1µF
24
13
18
8
0.1µF
16
7
0.1µF
1
12
19
0.1µF
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
11
20
EPAD TIED
TO GROUND
6
0.1µF
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
5
21
0.1µF
30
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
22
ADA8282
4
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
32
25
26
27
28
29
30
31
32
3
15
0.1µF
23
14
0.1µF
2
13
INPUT D
SOURCE
0.1µF
24
12
INPUT C
SOURCE
0.1µF
0.1µF
1
11
0.1µF
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
9
INPUT B
SOURCE
0.1µF
10
0.1µF
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
INPUT A
SOURCE
0.1µF
SPI BUS
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
SPI BUS
+3.3V
10kΩ
31
0.1µF
+3.3V
+3.3V
10kΩ
A2 (Output Side
ADA8282) Gain (dB)
18
24
24
24
30
30
36
GPIO: +3.3V/0V
10
+3.3V
A1 (Input Side
ADA8282) Gain (dB)
18
18
24
30
30
36
36
Total Gain (dB)
36
42
48
54
60
66
72
Data Sheet
ADA8282
Figure 29) as long as only one device is enabled at a time. When
an ADA8282 is disabled, the outputs present a 6 kΩ load on the
output bus.
MULTIPLEXING INPUTS USING MULTIPLE
ADA8282 DEVICES
It is possible to multiplex eight differential inputs down to four
differential outputs by using two ADA8282 devices. The devices
can be connected such that the outputs are connected (see
GPIO: +3.3V/0V
+3.3V
0.1µF
+3.3V
10kΩ
0.1µF
0.1µF
25
26
27
28
29
30
31
22
ADA8282
4
5
21
20
EPAD TIED
TO GROUND
6
19
7
18
8
17
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
9
0.1µF
3
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
+3.3V
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+3.3V
0.1µF
GPIO: +3.3V/0V
+3.3V
0.1µF
16
INPUT D
SOURCE
0.1µF
23
15
0.1µF
24
2
14
INPUT C
SOURCE
0.1µF
1
13
0.1µF
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
12
INPUT B
SOURCE
0.1µF
11
0.1µF
10
INPUT A
SOURCE
32
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
SPI BUS
TO ADC
+3.3V
10kΩ
TO ADC
TO ADC
0.1µF
0.1µF
SPI BUS
0.1µF
25
26
27
28
29
30
31
22
ADA8282
4
5
21
20
EPAD TIED
TO GROUND
6
19
7
18
8
17
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+3.3V
+3.3V
Figure 29. Multiplexing by Connecting Two ADA8282 Outputs to One Output Bus
Rev. 0 | Page 15 of 21
13132-024
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
9
0.1µF
3
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
16
INPUT H
SOURCE
0.1µF
23
15
0.1µF
24
2
14
INPUT G
SOURCE
0.1µF
1
13
0.1µF
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
12
INPUT F
SOURCE
0.1µF
11
0.1µF
10
INPUT E
SOURCE
32
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
TO ADC
ADA8282
Data Sheet
series with the bypassing paths. AC couple the inputs and
outputs for each channel as shown in Figure 30. Pull the RESET pin
low with a 10 kΩ resistor and drive it with 3.3 V GPIO logic.
The SPI pins can be directly connected to the SPI bus.
BASIC CONNECTIONS FOR A TYPICAL
APPLICATION
The ADA8282 is typically configured to operate with a nominal
3.3 V power supply, using the EPAD as the analog ground
connection. Place the bypass capacitors as close as possible to
the power supply pins to minimize the length of metal traces in
GPIO: +3.3V/0V
+3.3V
0.1µF
+3.3V
10kΩ
0.1µF
25
27
28
29
30
31
26
22
ADA8282
4
5
21
20
EPAD TIED
TO GROUND
6
19
18
8
17
+OUTA
–OUTA
+OUTB
–OUTB
+OUTC
–OUTC
+OUTD
–OUTD
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
TO ADC
TO ADC
TO ADC
TO ADC
16
7
15
0.1µF
0.1µF
+3.3V
+3.3V
Figure 30. Typical Component Connections
Rev. 0 | Page 16 of 21
13132-025
0.1µF
3
14
INPUT D
SOURCE
0.1µF
0.1µF
23
13
0.1µF
24
2
12
INPUT C
SOURCE
0.1µF
1
11
0.1µF
+INA
–INA
+INB
–INB
+INC
–INC
+IND
–IND
9
INPUT B
SOURCE
0.1µF
10
0.1µF
AVDD
NIC
NIC
NIC
NIC
NIC
NIC
AVDD
INPUT A
SOURCE
32
AVDD
SDO
SDI
CS
SCLK
RESET
VIO
AVDD
SPI BUS
Data Sheet
ADA8282
REGISTER MAP
REGISTER SUMMARY
Table 12. Register Summary
Reg.
0x00
0x01
0x04
0x05
0x06
0x10
0x11
0x12
0x13
0x14
0x15
0x17
Name
INTF_CONFA
SOFT_RESET
CHIP_ID1
CHIP_ID2
Revision
LNA_OFFSET0
LNA_OFFSET1
LNA_OFFSET2
LNA_OFFSET3
BIAS_SEL
PGA_GAIN
EN_CHAN
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
[7:0]
INTF_CONFA2
LSBFIRST1
INTF_CONFA1
LSBFIRST0
[7:0]
Unused
[7:0]
CHIP_IDLOW
[7:0]
CHIP_IDHI
[7:0]
Revision
[7:0]
Unused
LNA_OFFSET0
[7:0]
Unused
LNA_OFFSET1
[7:0]
Unused
LNA_OFFSET2
[7:0]
Unused
LNA_OFFSET3
[7:0]
Unused
PGA_BIAS_SEL
[7:0]
PGA_GAIN3
PGA_GAIN2
PGA_GAIN1
[7:0]
Unused
EN_
EN_
CHANNEL3 CHANNEL2
0x18 EN_BIAS_GEN [7:0]
Unused
0x1D SPAREWR0
[7:0]
Unused
0x1E SPARERD0
[7:0]
Unused
Bit 1
Bit 0
INTF_CONFA0
SOFT_RESET
Reset
0x00
0x00
0x82
0x82
0x00
0x20
0x20
0x20
0x20
0x0A
0x00
0x00
RW
RW
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
LNA_BIAS_SEL
PGA_GAIN0
EN_
EN_
CHANNEL1 CHANNEL0
EN_BIAS_GEN 0x00 RW
GPIO_WRITE GPIO_WR_
0x00 RW
MODE
GPIO_READ
0x00 R
REGISTER DETAILS
Register 0x00: Interface Configuration Register
Bit 7
Bit 6
INTF_CONFA2
Bit 5
LSBFIRST1
Bit 4
Bit 3
INTF_CONFA1
Bit 2
LSBFIRST0
Bit 1
Bit 0
INTF_CONFA0
The INTF_CONFA configuration register is symmetric, as it is the first register written and sets the data direction (LSB first or MSB first).
Table 13. INTF_CONFA Configuration Register Bit Descriptions
Bits
[7:0]
5
[4:3]
2
[1:0]
Bit Name
INTF_CONFA2
LSBFIRST1
INTF_CONFA1
LSBFIRST0
INTF_CONFA0
Description
INTF_CONFA2 must remain b’00.
LSBFIRST1 must be set to b’1 for LSB first operation and to b’0 for MSB first operation.
INTF_CONFA1 must remain b’00.
LSBFIRST0 must be set to b’1 for LSB first operation and to b’0 for MSB first operation.
INTF_CONFA0 must remain b’00.
Reset
0x00
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
RW
Register 0x01: Soft Reset Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unused
Bit 0
SOFT_RESET
Table 14. SOFT_RESET Configuration Register Bit Descriptions
Bits
0
Bit Name
SOFT_RESET
Description
The SOFT_RESET bit resets all registers to their default values when SOFT_RESET is set to b’1.
Reset
0x00
Access
RW
Register 0x04: Chip ID Low Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHIP_IDLOW
Bit 2
Bit 1
Bit 0
Table 15. CHIP_IDLOW Configuration Register Bit Descriptions
Bits
[7:0]
Bit Name
CHIP_IDLOW
Description
The CHIP_ID1 and CHIP_ID2 registers identify the ADA8282.
Rev. 0 | Page 17 of 21
Reset
0x82
Access
R
ADA8282
Data Sheet
Register 0x05: Chip ID High Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHIP_IDHI
Bit 2
Bit 1
Bit 0
Table 16. CHIP_IDHI Configuration Register Bit Descriptions
Bits
[7:0]
Bit Name
CHIP_IDHI
Description
The CHIP_ID1 and CHIP_ID2 registers identify the ADA8282.
Reset
0x82
Access
R
Register 0x06: Revision Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Revision
Bit 2
Bit 1
Bit 0
Table 17. Revision Configuration Register Bit Descriptions
Bits
[7:0]
Bit Name
Revision
Description
The revision register identifies the silicon revision of the current die.
Reset
0x00
Access
R
Register 0x10: LNA Offset 0 Register
Bit 7
Bit 6
Unused
Bit 5
Bit 4
Bit 3
Bit 2
LNA_OFFSET0
Bit 1
Bit 0
Table 18. LNA_OFFSET0 Configuration Register Bit Descriptions
Bits
[5:0]
Bit Name
LNA_OFFSET0
Description
LNA_OFFSET0 controls the offset of Channel A. The default setting (0x20) applies the minimum
offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.
The resolution of the offset varies with the LNA bias mode as follows:
LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.
LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.
LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.
LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.
Reset
0x20
Access
RW
Register 0x11: LNA Offset 1 Register
Bit 7
Bit 6
Unused
Bit 5
Bit 4
Bit 3
Bit 2
LNA_OFFSET1
Bit 1
Bit 0
Table 19. LNA_OFFSET1 Configuration Register Bit Descriptions
Bits
[5:0]
Bit Name
LNA_OFFSET1
Description
LNA_OFFSET0 controls the offset of Channel B. The default setting (0x20) applies the minimum
offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.
The resolution of the offset varies with the LNA bias mode as follows:
LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.
LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.
LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.
LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.
Reset
0x20
Register 0x12: LNA Offset 2 Register
Bit 7
Bit 6
Unused
Bit 5
Bit 4
Bit 3
Bit 2
LNA_OFFSET2
Rev. 0 | Page 18 of 21
Bit 1
Bit 0
Access
RW
Data Sheet
ADA8282
Table 20. LNA_OFFSET2 Configuration Register Bit Descriptions
Bits
[5:0]
Bit Name
LNA_OFFSET2
Description
LNA_OFFSET0 controls the offset of Channel C. The default setting (0x20) applies the minimum
offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.
The resolution of the offset varies with the LNA bias mode as follows:
LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.
LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.
LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.
LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.
Reset
0x20
Access
RW
Register 0x13: LNA Offset 3 Register
Bit 7
Bit 6
Unused
Bit 5
Bit 4
Bit 3
Bit 2
LNA_OFFSET3
Bit 1
Bit 0
Table 21. LNA_OFFSET3 Configuration Register Bit Descriptions
Bits
[5:0]
Bit Name
LNA_OFFSET3
Description
LNA_OFFSET0 controls the offset of Channel D. The default setting (0x20) applies the minimum
offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.
The resolution of the offset varies with the LNA bias mode as follows:
LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.
LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.
LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.
LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.
Reset
0x20
Access
RW
Register 0x14: PGA Bias Register
Bit 7
Bit 6
Bit 5
Unused
Bit 4
Bit 3
Bit 2
PGA_BIAS_SEL
Bit 1
Bit 0
LNA_BIAS_SEL
The PGA bias select register allows the user to trade off power and performance (for example, bandwidth and noise).
Table 22. BIAS_SEL Configuration Register Bit Descriptions
Bits
[3:2]
[1:0]
Bit Name
PGA_BIAS_SEL
LNA_BIAS_SEL
Description
Set PGA_BIAS_SEL to b’00 for the minimum PGA bias and to b’11 for the maximum PGA bias.
Set LNA_BIAS_SEL to b’00 for the minimum LNA bias and to b’11 for the maximum LNA bias.
Reset
0x00
0x00
Access
RW
RW
Register 0x15: PGA Gain Register
Bit 7
Bit 6
PGA_GAIN3
Bit 5
Bit 4
PGA_GAIN2
Bit 3
Bit 2
PGA_GAIN1
Bit 1
Bit 0
PGA_GAIN0
The PGA gain register allows independent gain settings for each channel.
Table 23. PGA_GAIN Configuration Register Bit Descriptions
Bits
[7:6]
Bit Name
PGA_GAIN3
[5:4]
PGA_GAIN2
[3:2]
PGA_GAIN1
[1:0]
PGA_GAIN0
Description
Set PGA_GAIN3 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to
b’11 for 36 dB gain for Channel D
Set PGA_GAIN2 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to
b’11 for 36 dB gain for Channel C
Set PGA_GAIN1 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to
b’11 for 36 dB gain for Channel B
Set PGA_GAIN0 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to
b’11 for 36 dB gain for Channel A
Rev. 0 | Page 19 of 21
Reset
0x00
Access
RW
0x00
RW
0x00
RW
0x00
RW
ADA8282
Data Sheet
Register 0x17: Enable Channel Register
Bit 7
Bit 6
Bit 5
Unused
Bit 4
Bit 3
EN_CHANNEL3
Bit 2
EN_CHANNEL2
Bit 1
EN_CHANNEL1
Bit 0
EN_CHANNEL0
The enable channel register allows individual channels to be enabled or disabled. The default mode for the channel is disabled. Write 0x0F
to the EN_CHAN register to enable all channels.
When a channel is disabled but the bias generator is still enabled, the channel’s current consumption is <100 μA. When a channel is
disabled, its output pins are high-Z. The enable channel register resets at AVDD power-on to 0x00 to avoid inrush current for fast supply
ramps.
Table 24. EN_CHAN Register Bit Descriptions
Bits
3
2
1
0
Bit Name
EN_CHANNEL3
EN_CHANNEL2
EN_CHANNEL1
EN_CHANNEL0
Description
Set to b’1 to enable Channel D, and set to b’0 to disable Channel D
Set to b’1 to enable Channel C, and set to b’0 to disable Channel C
Set to b’1 to enable Channel B, and set to b’0 to disable Channel B
Set to b’1 to enable Channel A, and set to b’0 to disable Channel A
Reset
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
Register 0x18: Enable Bias Generator Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unused
Bit 0
EN_BIAS_GEN
When any channel is enabled, the bias generator is automatically enabled. The EN_BIAS_GEN register controls whether the bias
generator stays active, even when all channels are disabled. Leaving the bias generator active decreases the enable time of the device.
Table 25. EN_BIAS_GEN Register Bit Descriptions
Bits
0
Bit Name
EN_BIAS_GEN
Description
Setting EN_BIAS_GEN to 1 keeps the bias generator active, providing a faster enable time (~2 μs).
Reset
0x00
Access
RW
Register 0x1D: GPIO Write Register
Bit 7
Bit 6
Bit 5
Bit 4
Unused
Bit 3
Bit 2
Bit 1
GPIO_WRITE
Bit 0
GPIO_WR_MODE
The GPIO_WR_MODE bit reconfigures the SDO pin to a general-purpose input/output (GPIO) port that can be written by the
GPIO_WRITE register or read by the GPIO_READ register.
Table 26. SPAREWR0 Configuration Register Bit Descriptions
Bits
1
0
Bit Name
GPIO_WRITE
GPIO_WR_MODE
Description
Data bit is put onto the SDO pin when GPIO write mode is active.
Write b’1 to this register to activate GPIO write mode.
Reset
0x00
0x00
Access
RW
RW
Register 0x1E: GPIO Read Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unused
Bit 0
GPIO_READ
Table 27. SPARERD0 Configuration Register Bit Descriptions
Bits
0
Bit Name
GPIO_READ
Description
This register reflects the logic level placed on SDO when a b’0 is written to GPIO_WR_MODE.
Rev. 0 | Page 20 of 21
Reset
0x00
Access
R
Data Sheet
ADA8282
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
0.50
BSC
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.65
3.50 SQ
3.45
EXPOSED
PAD
17
TOP VIEW
PIN 1
INDICATOR
1
24
9
BOTTOM VIEW
0.25 MIN
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
04-02-2012-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADA8282WBCPZ-R7
ADA8282WBCPZ
ADA8282CP-EBZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
32-Lead LFCSP_WQ, 7” Tape and Reel
32-Lead LFCSP_WQ
Evaluation Board
Package Option
CP-32-11
CP-32-11
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADA8282W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13132-0-7/15(0)
Rev. 0 | Page 21 of 21
Similar pages