Samsung K6R1016V1C-C12 64kx16 bit high-speed cmos static ram(3.3v operating) operated at commercial and industrial temperature ranges. Datasheet

for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev. No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Aug. 5. 1998
Preliminary
Rev. 1.0
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Changed DC characteristics.
Item
ICC
12ns
15ns
20ns
Sep. 7. 1998
Final
Sep. 17. 1998
Final
Nov. 5. 1998
Final
Dec. 10. 1998
Final
Mar. 2. 1999
Final
Previous
85mA
83mA
80mA
Rev. 2.0
Added 48-fine pitch BGA.
Rev. 2.1
Changed device part name for FP-BGA.
Item
Previous
Symbol
Z
ex) K6R1016V1C-Z -> K6R1016V1C-F
Rev. 2.2
Rev. 3.0
Changed device ball name for FP-BGA.
Previous
I/O1 ~ I/O8
I/O9 ~ I/O16
Changed
95mA
93mA
90mA
Changed
F
Changed
I/O9 ~ I/O16
I/O1 ~ I/O8
1. Added 10ns speed for FP-BGA only.
2. Changed Standby Current.
Item
Previous
Standby Current(Isb1)
0.3mA
3. Added Data Retention Characteristics.
Changed
0.5mA
Rev. 3.1
Added 10ns speed for all packages(44SOJ / 44TSOP2 / 48FPBGA)
Apr. 24. 2000
Final
Rev. 3.2
Supply Voltage Change
1. Only 10ns Bin : 3.15V ~ 3.6V
2. The Rest Bin : 3.0V ~ 3.6V
Aug. 25. 2000
Final
Rev. 3.3
VIH/VIL Change
Oct. 2. 2000
Final
Item
VIH
VIL
Previous
Min
2.0
-0.5
Changed
Max
VCC+0.5
0.8
Min
2.0
-0.3
Max
VCC+0.3
0.8
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating * K6R1016V1C-10: 105mA(Max.)
K6R1016V1C-12: 95mA(Max.)
K6R1016V1C-15: 93mA(Max.)
K6R1016V1C-20: 90mA(Max.)
• Single 3.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention: L-ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
K6R1016V1C-J: 44-SOJ-400
K6R1016V1C-T: 44-TSOP2-400BF
K6R1016V1C-F: 48-Fine pitch BGA with 0.75 Ball pitch
The K6R1016V1C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016V1C uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016V1C is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-Fine pitch BGA.
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row Select
Clk Gen.
ORDERING INFORMATION
Pre-Charge Circuit
K6R1016V1C-C10/C12/C15/C20
Commercial Temp.
K6R1016V1C-I10/I12/I15/I20
Industrial Temp.
Memory Array
512 Rows
128x16 Columns
PIN FUNCTION
Pin Name
I/O1~I/O8
Data
Cont.
I/O9~I/O16
Data
Cont.
I/O Circuit &
Column Select
A0 - A15
Gen.
CLK
A9 A10 A11 A12 A13 A14 A15
Pin Function
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O1~I/O8)
UB
Upper-byte Control(I/O9~I/O16)
I/O1 ~ I/O16
Data Inputs/Outputs
WE
OE
VCC
Power(+3.3V)
VSS
Ground
UB
LB
CS
N.C
No Connection
-2-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PIN CONFIGURATION(TOP VIEW)
A0
1
44 A15
A1
2
43 A14
A2
3
42 A13
A3
4
41 OE
A4
5
40 UB
CS
6
39 LB
I/O1
7
38 I/O16
I/O2
8
37 I/O15
I/O3
9
36 I/O14
SOJ/
I/O4 10
Vcc 11
2
3
4
5
6
A
LB
OE
A0
A1
A2
N.C
B
I/O1
UB
A3
A4
CS
I/O9
C
I/O2
I/O3
A5
A6
I/O11
I/O10
D
Vss
I/O4
N.C
A7
I/O12
Vcc
E
Vcc
I/O5
N.C
N.C
I/O13
Vss
F
I/O7
I/O6
A14
A15
I/O14
I/O15
G
I/O8
N.C
A12
A13
WE
I/O16
H
N.C
A8
A9
A10
A11
N.C
35 I/O13
34 Vss
TSOP2
Vss 12
1
33 Vcc
I/O5 13
32 I/O12
I/O6 14
31 I/O11
I/O7 15
30 I/O10
I/O8 16
29 I/O9
WE 17
28 N.C
A5 18
27 A12
A6 19
26 A11
A7 20
25 A10
A8 21
24 A9
N.C 22
48-CSP
23 N.C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Symbol
Rating
Unit
VIN, VOUT
-0.5 to 4.6
V
VCC
-0.5 to 4.6
V
Voltage on VCC Supply Relative to VSS
Power Dissipation
Pd
1
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Industrial
TA
-40 to 85
°C
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70°C)
Parameter
Supply Voltage
Supply Voltage
Ground
Symbol
Min
Typ
Max
Unit
3.3
3.6
V
3.3
3.6
V
CC(1)
3.15
CC(2)
3.0
0
0
0
V
V
VSS
Input High Voltage
VIH
2.0
-
Input Low Voltage
VIL
-0.3(4)
-
VCC+0.3
0.8
V
(3)
V
V
(1) For K6R1016V1C-10 only.
(2) For all speed grades except K6R1016V1C-10.
(3) VIH(Max) = VCC + 2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA
(4) VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
-3-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
*DC
AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied)
Min
Max
Unit
Input Leakage Current
Parameter
Symbol
ILI
VIN=VSS to VCC
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
ICC
10ns
-
105
mA
12ns
-
95
15ns
-
93
20ns
-
90
-
30
mA
Normal
-
5
mA
Standby Current
Test Conditions
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
ISB
Min. Cycle, CS=VIH
ISB1
f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or VIN ≤0.2V
-
0.5
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
L-Ver.
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
Item
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
+3.3V
RL = 50Ω
DOUT
VL = 1.5V
ZO = 50Ω
319Ω
DOUT
30pF*
353Ω
* Capacitive Load consists of all components of the
test environment.
5pF*
* Including Scope and Jig Capacitance
-4-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
READ CYCLE*
Parameter
K6R1016V1C-10
Symbol
K6R1016V1C-12
K6R1016V1C-15
K6R1016V1C-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tRC
10
-
12
-
15
-
20
-
ns
Address Access Time
tAA
-
10
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
10
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
-
9
ns
UB, LB Access Time
tBA
-
5
-
6
-
7
-
9
ns
Read Cycle Time
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
3
-
ns
UB, LB Enable to Low-Z Output
tBLZ
0
-
0
-
0
-
0
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
-
7
-
9
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
-
7
-
9
ns
UB, LB Disable to High-Z Output
tBHZ
0
5
0
6
-
7
-
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
-
12
-
15
-
20
ns
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
Parameter
Symbol
K6R1016V1C-10
K6R1016V1C-12
K6R1016V1C-15
K6R1016V1C-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
7
-
8
-
9
-
10
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
9
-
10
-
ns
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
9
-
10
-
Write Pulse Width(OE Low)
tWP1
10
-
12
-
15
-
20
-
ns
UB, LB Valid to End of Write
tBW
7
-
8
-
9
-
10
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
5
-
6
-
7
-
8
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
3
-
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tRC
Address
tOH
Data Out
tAA
Valid Data
Previous Valid Data
-5-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tBHZ(3,4,5)
tBA
UB, LB
tBLZ(4,5)
tOHZ
tOE
OE
tOLZ
Data out
High-Z
VCC
ICC
Current
ISB
tOH
tLZ(4,5)
Valid Data
tPU
tPD
50%
50%
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
tWC
Address
tAW
tWR(5)
OE
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data in
High-Z
Valid Data
tDH
High-Z
tOHZ(6)
Data out
-6-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP1(2)
tAS(4)
WE
tDW
High-Z
Data in
tDH
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
High-Z
Valid Data
tLZ
Data out
tDH
tWHZ(6)
High-Z(8)
High-Z
-7-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
tAW
tCW(3)
tWR(5)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tBLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
LB
UB
I/O Pin
Mode
Supply Current
I/O1~I/O8
I/O9~I/O16
H
X
X*
X
X
Not Select
High-Z
High-Z
ISB, ISB1
L
H
H
X
X
Output Disable
High-Z
High-Z
ICC
L
X
X
H
H
L
H
L
L
H
DOUT
High-Z
ICC
H
L
High-Z
DOUT
L
L
DOUT
DOUT
L
L
X
Read
L
H
DIN
High-Z
H
L
Write
High-Z
DIN
L
L
DIN
DIN
ICC
* X means Don′t Care.
-8-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
VCC for Data Retention
VDR
CS≥VCC-0.2V
2.0
-
3.6
V
Data Retention Current
IDR
VCC=3.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V
-
-
0.4
mA
VCC=2.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V
-
-
0.3
See Data Retention
Wave form(below)
0
-
-
ns
5
-
-
ms
Data Retention Set-Up Time
tSDR
Recovery Time
tRDR
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC
tSDR
Data Retention Mode
tRDR
3.0V
VIH
VDR
CS≥VCC - 0.2V
CS
GND
-9-
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
Units:millimeters/Inches
PACKAGE DIMENSIONS
44-SOJ-400
#23
9.40 ±0.25
0.370 ±0.010
10.16
0.400
#44
11.18 ±0.12
0.440 ±0.005
0.20 +0.10
-0.05
0.008 +0.004
-0.002
#1
#22
28.98 MAX
1.141
0.69 MIN
0.027
25.58 ±0.12
1.125 ±0.005
1.19
)
0.047
3.76
1.27
MAX
( 0.050 ) 0.148
0.10 MAX
0.004
(
( 0.95 )
0.0375
0.43
0.017
+0.10
-0.05
+0.004
-0.002
+0.10
0.71 -0.05
0.028 +0.004
-0.002
1.27
0.050
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010 TYP
#23
#44
11.76 ±0.20
0.463 ±0.008
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
( 0.50 )
0.020
#1
#22
18.81
MAX
0.741
0.075
0.125 +- 0.035
+ 0.003
18.41 ±0.10
0.725 ±0.004
0.005 - 0.001
1.00 ±0.10
0.039 ±0.004
( 0.805 )
0.032
0.30 +0.10
−0.05
0.012 +0.004
−0.002
0.05
MIN
0.002
0.80
0.0315
- 10
1.20
MAX
0.047
0.10
0.004 MAX
Revision 3.3
October 2000
for AT&T
CMOS SRAM
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PACKAGE OUTLINE
(Units : millimeter)
Top View
Bottom View
B
A1 INDEX MARK
0.50
B1
B
6
5
4
3
2
0.50
1
A
B
#A1
C
C
C
C1
D
C1/2
E
F
G
H
B/2
Detail A
Side View
Y
0.80/Typ.
E1
E
0.25/Typ.
E2
0.30
A
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
1.05
1.20
E1
-
0.80
-
E2
0.20
0.25
0.30
Y
-
-
0.08
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
- 11
Revision 3.3
October 2000
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