Renesas H8/3061 Renesas 16-bit single-chip microcomputer h8 family/h8/300h sery Datasheet

REJ09B0215-0600
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/3062, H8/3062B Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Series
H8/3062
HD6433062,
HD6433061,
HD6433060
H8/3062B HD6433064B,
HD6433062B,
HD6433061B,
HD6433060B
H8/3062F HD64F3062R,
HD64F3062B
H8/3064F HD64F3064B
Rev. 6.00
Revision Date: Mar 18, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 6.00 Mar 18, 2005 page ii of xlviii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 6.00 Mar 18, 2005 page iii of xlviii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 6.00 Mar 18, 2005 page iv of xlviii
Preface
The H8/3062 Group is a high-performance single-chip microcomputer that integrates peripheral
functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal
architecture as its core.
The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
a D/A converter, an A/D converter, and I/O ports, providing an ideal configuration as a
microcomputer for embedding in sophisticated control systems. Flash memory (F-ZTAT™*) and
masked ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to
changing application specifications and the demands of the transition from initial to full-fledged
volume production.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the H8/3062 Group. Readers using this manual require a basic
knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose:
The purpose of this manual is to give users an understanding of the hardware
functions and electrical characteristics of the H8/3062 Group. Details of
execution instructions can be found in the H8/300H Series Programming
Manual, which should be read in conjunction with the present manual.
Using this Manual:
• For an overall understanding of the H8/3062 Group's functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.
• For a detailed understanding of CPU functions
Refer to the separate publication H8/300H Series Programming Manual.
Note on bit notation: Bits are shown in high-to-low order from left to right.
Related Material:
The latest information is available at our web site. Please make sure that you
have the most up-to-date information available.
http://www.renesas.com/eng/
Rev. 6.00 Mar 18, 2005 page v of xlviii
User's Manuals on the H8/3062:
Document Title
Document No.
H8/3062 Hardware Manual
This manual
H8/300H Series Software Manual
REJ09B0213
Users manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage
Editor Compiler Package User’s Manual
REJ10B0161
H8S, H8/300 Series High-performance Embedded Workshop 3 User’s
Manual
REJ10B0026
H8S, H8/300 Series High-performance Embedded Workshop 3, Tutorial
REJ10B0024
Application Note:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note
REJ05B0464
H8/300H Series On-Chip Supporting Modules Application Note
REJ05B0522
H8/300H Technical Q&A
REJ05B0521
Rev. 6.00 Mar 18, 2005 page vi of xlviii
Comparison of H8/3062 Group Product Specifications
There are 11 members of the H8/3062 Group: the H8/3062F-ZTAT R-mask version,
H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version (all with on-chip flash
memory), and the H8/3062 masked ROM version, H8/3061 masked ROM version, H8/3060
masked ROM version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask
version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version.
The specifications of these products are compared below.
H8/3062F-ZTAT
R-Mask Version
Product
specifications
H8/3062 Masked
ROM Version,
H8/3061 Masked
ROM Version,
H8/3060 Masked
ROM Version
H8/3062F-ZTAT
Masked ROM
version with address version
output functions
added
H8/3064F-ZTAT
B-Mask Version
On-chip largecapacity singlepower-supply flash
memory
H8/3062F-ZTAT
B-Mask Version
H8/3064 Masked ROM
B-Mask Version,
H8/3062 Masked ROM
B-Mask Version,
H8/3061 Masked ROM
B-Mask Version,
H8/3060 Masked ROM
B-Mask Version
H8/3062F-ZTAT
Masked ROM version
high-speed operation
version
Internal step-down
circuit
Product
code
HD64F3062R
HD6433062
HD6433061
HD6433060
Pin
arrangement
See figures 1.2 and 1.3, Pin Arrangement,
in section 1
HD64F3064B
HD64F3062B
HD6433064B
HD6433062B
HD6433061B
HD6433060B
H8/3064F-ZTAT
B-mask version has
VCL pin, and requires
connection of
external capacitor
H8/3062F-ZTAT
B-mask version has
VCL pin, and requires
connection of
external capacitor
See figures 1.4
and 1.5, Pin
Arrangement, in
section 1
See figures 1.4
and 1.5, Pin
Arrangement, in
section 1
H8/3064 masked ROM
B-mask version,
H8/3062 masked ROM
B-mask version,
H8/3061 masked ROM
B-mask version, and
H8/3060 masked ROM
B-mask version have
VCL pin, and require
connection of external
capacitor
See figures 1.4 and 1.5,
Pin Arrangement, in
section 1
RAM size
4 kbytes
H8/3062: 4 kbytes
8 kbytes
4 kbytes
H8/3064B: 8 kbytes
H8/3061: 4 kbytes
H8/3062B: 4 kbytes
H8/3060: 2 kbytes
H8/3061B: 4 kbytes
H8/3060B: 2 kbytes
Rev. 6.00 Mar 18, 2005 page vii of xlviii
H8/3062F-ZTAT
R-Mask Version
ROM size
128 kbytes
H8/3062 Masked
ROM Version,
H8/3061 Masked
ROM Version,
H8/3060 Masked
ROM Version
H8/3064F-ZTAT
B-Mask Version
H8/3062: 128 kbytes 256 kbytes
H8/3062F-ZTAT
B-Mask Version
128 kbytes
H8/3064 Masked ROM
B-Mask Version,
H8/3062 Masked ROM
B-Mask Version,
H8/3061 Masked ROM
B-Mask Version,
H8/3060 Masked ROM
B-Mask Version
H8/3064B: 256 kbytes
H8/3061: 96 kbytes
H8/3062B: 128 kbytes
H8/3060: 64 kbytes
H8/3061B: 96 kbytes
H8/3060B: 64 kbytes
Address
output
functions
Address update mode 1 or 2 selectable
See section 6.3.5, Address Output Method
Flash
memory
See section 17,
ROM
—
See section 18.1.1,
Differences from
H8/3062F-ZTAT RMask Version and
H8/3064F-ZTAT BMask Version
See section 19.1.1,
Differences from
H8/3062F-ZTAT RMask Version and
H8/3062F-ZTAT BMask Version
—
Masked
ROM
—
See section 17,
ROM
—
—
Masked ROM B-mask
version of H8/3064: see
section 18.
Masked ROM B-mask
versions of H8/3062,
H8/3061, and H8/3060:
see section 19.
Electrical See table 22.1, Comparison of H8/3062 Group Electrical Characteristics, in section 22
charac1 to 20 MHz
2 to 25 MHz
teristics
(operating
frequency)
Registers
See table B.1, Comparison of H8/3062 Group Internal I/O Register Specifications, in appendix B
See appendix B.1,
Address List
See appendix B.1,
Address List
See appendix B.2,
Address List
See appendix B.3,
Address List
Masked ROM B-mask
version of H8/3064: see
appendix B.2, Address
List.
Masked ROM B-mask
versions of H8/3062,
H8/3061, and H8/3060:
see appendix B.3,
Address List.
Usage
notes
See section 1.4, Notes on H8/3062F-ZTAT
R-Mask Version
Rev. 6.00 Mar 18, 2005 page viii of xlviii
See section 1.5, Notes on H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask
Version, H8/3062 Masked ROM B-Mask Version, H8/3061 Masked
ROM B-Mask Version, and H8/3060 Masked ROM B-Mask Version
Main Revisions for this Edition
Item
Page
Revisions (See Manual for Details)
All

All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names changed to Renesas Technology
Corp.
Designation for categories changed from “series” to “group”
All references to H8/3062F-ZTAT deleted

1.4.2 Differences 22
between H8/3062FZTAT R-Mask
Version and
H8/3064F-ZTAT BMask Version
“Product Type Names and Markings” deleted
Title amended
Table 1.5
Differences between
H8/3062F-ZTAT,
H8/3062F-ZTAT RMask Version, and
On-Chip Masked
ROM Versions
Table 1.6
24
Differences in
H8/3062F-ZTAT RMask Version,
H8/3062F-ZTAT BMask Version, and
H8/3064F-ZTAT BMask Version
Markings
9.2.5 Timer
306
Control/Status
Registers (8TCSR)
Description amended
Bit 4—Reserved (In 8TCSR2): This bit is a reserved bit, but can
be read and written.
Rev. 6.00 Mar 18, 2005 page ix of xlviii
Rev. 6.00 Mar 18, 2005 page x of xlviii
Contents
Section 1 Overview.............................................................................................................
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Overview...........................................................................................................................
Block Diagram..................................................................................................................
Pin Description .................................................................................................................
1.3.1 Pin Arrangement..................................................................................................
1.3.2 Pin Functions .......................................................................................................
1.3.3 Pin Assignments in Each Mode ...........................................................................
Notes on H8/3062F-ZTAT R-Mask Version ....................................................................
1.4.1 Pin Arrangement..................................................................................................
1.4.2 Differences between H8/3062F-ZTAT R-Mask Version and
H8/3064F-ZTAT B-Mask Version ......................................................................
Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version,
H8/3064 Masked ROM B-Mask Version, H8/3062 Masked ROM B-Mask Version,
H8/3061 Masked ROM B-Mask Version, and H8/3060 Masked ROM B-Mask Version
1.5.1 Pin Arrangement..................................................................................................
1.5.2 Product Type Names and Markings.....................................................................
1.5.3 VCL Pin.................................................................................................................
1.5.4 Notes on Changeover to On-Chip Masked ROM Versions and On-Chip Masked
ROM B-Mask Versions .......................................................................................
Setting Oscillation Settling Wait Time .............................................................................
Caution on Crystal Resonator Connection........................................................................
1
1
7
8
8
13
18
22
22
22
23
23
24
25
26
27
27
Section 2 CPU ...................................................................................................................... 29
2.1
2.2
2.3
2.4
2.5
2.6
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Differences from H8/300 CPU ............................................................................
CPU Operating Modes......................................................................................................
Address Space...................................................................................................................
Register Configuration......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers.................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial CPU Register Values.................................................................................
Data Formats.....................................................................................................................
2.5.1 General Register Data Formats............................................................................
2.5.2 Memory Data Formats.........................................................................................
Instruction Set...................................................................................................................
29
29
30
31
32
33
33
34
35
36
37
37
38
40
Rev. 6.00 Mar 18, 2005 page xi of xlviii
2.7
2.8
2.9
2.6.1 Instruction Set Overview .....................................................................................
2.6.2 Instructions and Addressing Modes.....................................................................
2.6.3 Tables of Instructions Classified by Function......................................................
2.6.4 Basic Instruction Formats ....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions ...................................................
Addressing Modes and Effective Address Calculation.....................................................
2.7.1 Addressing Modes ...............................................................................................
2.7.2 Effective Address Calculation .............................................................................
Processing States ..............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Program Execution State .....................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Exception Handling Operation ............................................................................
2.8.5 Bus-Released State ..............................................................................................
2.8.6 Reset State ...........................................................................................................
2.8.7 Power-Down State ...............................................................................................
Basic Operational Timing .................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory Access Timing........................................................................
2.9.3 On-Chip Supporting Module Access Timing ......................................................
2.9.4 Access to External Address Space.......................................................................
40
41
42
51
52
54
54
56
60
60
60
61
62
63
64
64
65
65
65
66
67
Section 3 MCU Operating Modes .................................................................................. 69
3.1
3.2
3.3
3.4
3.5
3.6
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Mode Control Register (MDCR) ......................................................................................
System Control Register (SYSCR) ...................................................................................
Operating Mode Descriptions ...........................................................................................
3.4.1 Mode 1.................................................................................................................
3.4.2 Mode 2.................................................................................................................
3.4.3 Mode 3.................................................................................................................
3.4.4 Mode 4.................................................................................................................
3.4.5 Mode 5.................................................................................................................
3.4.6 Mode 6.................................................................................................................
3.4.7 Mode 7.................................................................................................................
Pin Functions in Each Operating Mode ............................................................................
Memory Map in Each Operating Mode ............................................................................
3.6.1 Comparison of H8/3062 Group Memory Maps...................................................
3.6.2 Reserved Areas ....................................................................................................
Rev. 6.00 Mar 18, 2005 page xii of xlviii
69
69
70
71
72
75
75
75
75
75
75
76
76
76
77
77
78
Section 4 Exception Handling ......................................................................................... 87
4.1
4.2
4.3
4.4
4.5
4.6
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation ............................................................................
4.1.3 Exception Vector Table .......................................................................................
Reset90
4.2.1 Overview..............................................................................................................
4.2.2 Reset Sequence ....................................................................................................
4.2.3 Interrupts after Reset............................................................................................
Interrupts...........................................................................................................................
Trap Instruction ................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Stack Usage .......................................................................................................
87
87
87
88
90
90
93
94
94
95
96
Section 5 Interrupt Controller .......................................................................................... 99
5.1
5.2
5.3
5.4
5.5
Overview...........................................................................................................................
5.1.1 Features................................................................................................................
5.1.2 Block Diagram.....................................................................................................
5.1.3 Pin Configuration ................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
5.2.1 System Control Register (SYSCR)......................................................................
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................
5.2.3 IRQ Status Register (ISR)....................................................................................
5.2.4 IRQ Enable Register (IER) ..................................................................................
5.2.5 IRQ Sense Control Register (ISCR) ....................................................................
Interrupt Sources...............................................................................................................
5.3.1 External Interrupts ...............................................................................................
5.3.2 Internal Interrupts ................................................................................................
5.3.3 Interrupt Exception Handling Vector Table.........................................................
Interrupt Operation ...........................................................................................................
5.4.1 Interrupt Handling Process ..................................................................................
5.4.2 Interrupt Exception Handling Sequence ..............................................................
5.4.3 Interrupt Response Time......................................................................................
Usage Notes ......................................................................................................................
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction......................
5.5.2 Instructions that Inhibit Interrupts .......................................................................
5.5.3 Interrupts during EEPMOV Instruction Execution..............................................
99
99
100
101
101
101
101
102
108
109
110
111
111
112
112
116
116
121
122
123
123
124
124
Rev. 6.00 Mar 18, 2005 page xiii of xlviii
Section 6 Bus Controller ................................................................................................... 125
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
6.1.2 Block Diagram.....................................................................................................
6.1.3 Pin Configuration ................................................................................................
6.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
6.2.1 Bus Width Control Register (ABWCR)...............................................................
6.2.2 Access State Control Register (ASTCR) .............................................................
6.2.3 Wait Control Registers H and L (WCRH, WCRL)..............................................
6.2.4 Bus Release Control Register (BRCR) ................................................................
6.2.5 Bus Control Register (BCR) ................................................................................
6.2.6 Chip Select Control Register (CSCR)..................................................................
6.2.7 Address Control Register (ADRCR) ...................................................................
Operation ..........................................................................................................................
6.3.1 Area Division.......................................................................................................
6.3.2 Bus Specifications ...............................................................................................
6.3.3 Memory Interfaces...............................................................................................
6.3.4 Chip Select Signals ..............................................................................................
6.3.5 Address Output Method.......................................................................................
Basic Bus Interface ...........................................................................................................
6.4.1 Overview..............................................................................................................
6.4.2 Data Size and Data Alignment.............................................................................
6.4.3 Valid Strobes .......................................................................................................
6.4.4 Memory Areas .....................................................................................................
6.4.5 Basic Bus Control Signal Timing ........................................................................
6.4.6 Wait Control ........................................................................................................
Idle Cycle..........................................................................................................................
6.5.1 Operation .............................................................................................................
6.5.2 Pin States in Idle Cycle........................................................................................
Bus Arbiter .......................................................................................................................
6.6.1 Operation .............................................................................................................
Register and Pin Input Timing..........................................................................................
6.7.1 Register Write Timing .........................................................................................
6.7.2 BREQ Pin Input Timing ......................................................................................
125
125
126
127
128
129
129
130
131
135
137
139
140
141
141
145
146
147
148
150
150
150
151
152
153
160
162
162
164
165
165
167
167
168
Section 7 I/O Ports .............................................................................................................. 169
7.1
7.2
Overview........................................................................................................................... 169
Port 1................................................................................................................................. 173
7.2.1 Overview.............................................................................................................. 173
Rev. 6.00 Mar 18, 2005 page xiv of xlviii
7.2.2 Register Descriptions...........................................................................................
Port 2.................................................................................................................................
7.3.1 Overview..............................................................................................................
7.3.2 Register Descriptions...........................................................................................
7.4 Port 3.................................................................................................................................
7.4.1 Overview..............................................................................................................
7.4.2 Register Descriptions...........................................................................................
7.5 Port 4.................................................................................................................................
7.5.1 Overview..............................................................................................................
7.5.2 Register Descriptions...........................................................................................
7.6 Port 5.................................................................................................................................
7.6.1 Overview..............................................................................................................
7.6.2 Register Descriptions...........................................................................................
7.7 Port 6.................................................................................................................................
7.7.1 Overview..............................................................................................................
7.7.2 Register Descriptions...........................................................................................
7.8 Port 7.................................................................................................................................
7.8.1 Overview..............................................................................................................
7.8.2 Register Description ............................................................................................
7.9 Port 8.................................................................................................................................
7.9.1 Overview..............................................................................................................
7.9.2 Register Descriptions...........................................................................................
7.10 Port 9.................................................................................................................................
7.10.1 Overview..............................................................................................................
7.10.2 Register Descriptions...........................................................................................
7.11 Port A................................................................................................................................
7.11.1 Overview..............................................................................................................
7.11.2 Register Descriptions...........................................................................................
7.12 Port B................................................................................................................................
7.12.1 Overview..............................................................................................................
7.12.2 Register Descriptions...........................................................................................
7.3
174
176
176
177
180
180
180
182
182
183
186
186
187
190
190
191
194
194
195
195
195
196
201
201
202
206
206
208
218
218
220
Section 8 16-Bit Timer ...................................................................................................... 227
8.1
8.2
Overview...........................................................................................................................
8.1.1 Features................................................................................................................
8.1.2 Block Diagrams ...................................................................................................
8.1.3 Pin Configuration ................................................................................................
8.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
8.2.1 Timer Start Register (TSTR) ...............................................................................
227
227
229
232
233
234
234
Rev. 6.00 Mar 18, 2005 page xv of xlviii
8.3
8.4
8.5
8.6
8.2.2 Timer Synchro Register (TSNC) .........................................................................
8.2.3 Timer Mode Register (TMDR)............................................................................
8.2.4 Timer Interrupt Status Register A (TISRA).........................................................
8.2.5 Timer Interrupt Status Register B (TISRB) .........................................................
8.2.6 Timer Interrupt Status Register C (TISRC) .........................................................
8.2.7 Timer Counters (16TCNT) ..................................................................................
8.2.8 General Registers (GRA, GRB)...........................................................................
8.2.9 Timer Control Registers (16TCR) .......................................................................
8.2.10 Timer I/O Control Register (TIOR).....................................................................
8.2.11 Timer Output Level Setting Register C (TOLR) .................................................
CPU Interface ...................................................................................................................
8.3.1 16-Bit Accessible Registers .................................................................................
8.3.2 8-Bit Accessible Registers ...................................................................................
Operation ..........................................................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 Basic Functions....................................................................................................
8.4.3 Synchronization ...................................................................................................
8.4.4 PWM Mode .........................................................................................................
8.4.5 Phase Counting Mode..........................................................................................
8.4.6 16-Bit Timer Output Timing................................................................................
Interrupts...........................................................................................................................
8.5.1 Setting of Status Flags .........................................................................................
8.5.2 Timing of Clearing of Status Flags......................................................................
8.5.3 Interrupt Sources..................................................................................................
Usage Notes ......................................................................................................................
235
237
240
243
246
248
249
250
252
254
256
256
258
259
259
260
268
269
273
275
276
276
278
279
280
Section 9 8-Bit Timers ....................................................................................................... 293
9.1
9.2
9.3
Overview...........................................................................................................................
9.1.1 Features................................................................................................................
9.1.2 Block Diagram.....................................................................................................
9.1.3 Pin Configuration ................................................................................................
9.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
9.2.1 Timer Counters (8TCNT) ....................................................................................
9.2.2 Time Constant Registers A (TCORA).................................................................
9.2.3 Time Constant Registers B (TCORB) .................................................................
9.2.4 Timer Control Register (8TCR)...........................................................................
9.2.5 Timer Control/Status Registers (8TCSR) ............................................................
CPU Interface ...................................................................................................................
9.3.1 8-Bit Registers .....................................................................................................
Rev. 6.00 Mar 18, 2005 page xvi of xlviii
293
293
295
296
297
298
298
299
300
301
304
309
309
9.4
Operation ..........................................................................................................................
9.4.1 8TCNT Count Timing .........................................................................................
9.4.2 Compare Match Timing.......................................................................................
9.4.3 Input Capture Signal Timing ...............................................................................
9.4.4 Timing of Status Flag Setting ..............................................................................
9.4.5 Operation with Cascaded Connection..................................................................
9.4.6 Input Capture Setting...........................................................................................
Interrupt ............................................................................................................................
9.5.1 Interrupt Sources..................................................................................................
9.5.2 A/D Converter Activation....................................................................................
8-Bit Timer Application Example ....................................................................................
Usage Notes ......................................................................................................................
9.7.1 Contention between 8TCNT Write and Clear......................................................
9.7.2 Contention between 8TCNT Write and Increment ..............................................
9.7.3 Contention between TCOR Write and Compare Match ......................................
9.7.4 Contention between TCOR Read and Input Capture...........................................
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment
9.7.6 Contention between TCOR Write and Input Capture ..........................................
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)........................................................................................
9.7.8 Contention between Compare Matches A and B .................................................
9.7.9 8TCNT Operation and Internal Clock Source Switchover ..................................
311
311
312
313
314
316
318
320
320
321
321
322
322
323
324
325
326
327
Section 10 Programmable Timing Pattern Controller (TPC) .................................
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.1.2 Block Diagram.....................................................................................................
10.1.3 Pin Configuration ................................................................................................
10.1.4 Register Configuration.........................................................................................
10.2 Register Descriptions........................................................................................................
10.2.1 Port A Data Direction Register (PADDR)...........................................................
10.2.2 Port A Data Register (PADR)..............................................................................
10.2.3 Port B Data Direction Register (PBDDR) ...........................................................
10.2.4 Port B Data Register (PBDR) ..............................................................................
10.2.5 Next Data Register A (NDRA) ............................................................................
10.2.6 Next Data Register B (NDRB) ............................................................................
10.2.7 Next Data Enable Register A (NDERA)..............................................................
10.2.8 Next Data Enable Register B (NDERB)..............................................................
10.2.9 TPC Output Control Register (TPCR).................................................................
10.2.10 TPC Output Mode Register (TPMR)...................................................................
333
333
333
334
335
336
337
337
337
338
338
339
341
343
344
345
348
9.5
9.6
9.7
328
329
329
Rev. 6.00 Mar 18, 2005 page xvii of xlviii
10.3 Operation ..........................................................................................................................
10.3.1 Overview..............................................................................................................
10.3.2 Output Timing .....................................................................................................
10.3.3 Normal TPC Output.............................................................................................
10.3.4 Non-Overlapping TPC Output.............................................................................
10.3.5 TPC Output Triggering by Input Capture............................................................
10.4 Usage Notes ......................................................................................................................
10.4.1 Operation of TPC Output Pins.............................................................................
10.4.2 Note on Non-Overlapping Output .......................................................................
350
350
351
352
354
356
357
357
357
Section 11 Watchdog Timer.............................................................................................
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram.....................................................................................................
11.1.3 Pin Configuration ................................................................................................
11.1.4 Register Configuration.........................................................................................
11.2 Register Descriptions........................................................................................................
11.2.1 Timer Counter (TCNT)........................................................................................
11.2.2 Timer Control/Status Register (TCSR)................................................................
11.2.3 Reset Control/Status Register (RSTCSR)............................................................
11.2.4 Notes on Register Rewriting................................................................................
11.3 Operation ..........................................................................................................................
11.3.1 Watchdog Timer Operation .................................................................................
11.3.2 Interval Timer Operation .....................................................................................
11.3.3 Timing of Setting of Overflow Flag (OVF).........................................................
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ..................................
11.4 Interrupts...........................................................................................................................
11.5 Usage Notes ......................................................................................................................
359
359
359
360
360
361
361
361
362
364
365
367
367
368
369
370
371
371
Section 12 Serial Communication Interface ................................................................ 373
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram.....................................................................................................
12.1.3 Pin Configuration ................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions........................................................................................................
12.2.1 Receive Shift Register (RSR) ..............................................................................
12.2.2 Receive Data Register (RDR)..............................................................................
12.2.3 Transmit Shift Register (TSR).............................................................................
12.2.4 Transmit Data Register (TDR) ............................................................................
Rev. 6.00 Mar 18, 2005 page xviii of xlviii
373
373
375
376
377
378
378
378
379
379
12.2.5 Serial Mode Register (SMR) ...............................................................................
12.2.6 Serial Control Register (SCR) .............................................................................
12.2.7 Serial Status Register (SSR) ................................................................................
12.2.8 Bit Rate Register (BRR) ......................................................................................
12.3 Operation ..........................................................................................................................
12.3.1 Overview..............................................................................................................
12.3.2 Operation in Asynchronous Mode .......................................................................
12.3.3 Multiprocessor Communication ..........................................................................
12.3.4 Synchronous Operation .......................................................................................
12.4 SCI Interrupts....................................................................................................................
12.5 Usage Notes ......................................................................................................................
12.5.1 Notes on Use of SCI ............................................................................................
380
384
389
395
403
403
406
415
422
431
432
432
Section 13 Smart Card Interface ..................................................................................... 437
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram.....................................................................................................
13.1.3 Pin Configuration ................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions........................................................................................................
13.2.1 Smart Card Mode Register (SCMR)....................................................................
13.2.2 Serial Status Register (SSR) ................................................................................
13.2.3 Serial Mode Register (SMR) ...............................................................................
13.2.4 Serial Control Register (SCR) .............................................................................
13.3 Operation ..........................................................................................................................
13.3.1 Overview..............................................................................................................
13.3.2 Pin Connections...................................................................................................
13.3.3 Data Format .........................................................................................................
13.3.4 Register Settings ..................................................................................................
13.3.5 Clock....................................................................................................................
13.3.6 Transmitting and Receiving Data ........................................................................
13.4 Usage Notes ......................................................................................................................
437
437
438
439
439
440
440
442
443
444
445
445
445
446
448
450
452
460
Section 14 A/D Converter................................................................................................. 465
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram.....................................................................................................
14.1.3 Pin Configuration ................................................................................................
14.1.4 Register Configuration.........................................................................................
14.2 Register Descriptions........................................................................................................
465
465
466
467
468
469
Rev. 6.00 Mar 18, 2005 page xix of xlviii
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................
14.2.2 A/D Control/Status Register (ADCSR) ...............................................................
14.2.3 A/D Control Register (ADCR) ............................................................................
CPU Interface ...................................................................................................................
Operation ..........................................................................................................................
14.4.1 Single Mode (SCAN = 0) ....................................................................................
14.4.2 Scan Mode (SCAN = 1).......................................................................................
14.4.3 Input Sampling and A/D Conversion Time .........................................................
14.4.4 External Trigger Input Timing.............................................................................
Interrupts...........................................................................................................................
Usage Notes ......................................................................................................................
469
470
472
473
475
475
477
479
480
481
481
Section 15 D/A Converter.................................................................................................
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram.....................................................................................................
15.1.3 Pin Configuration ................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions........................................................................................................
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................
15.2.2 D/A Control Register (DACR) ............................................................................
15.2.3 D/A Standby Control Register (DASTCR)..........................................................
15.3 Operation ..........................................................................................................................
15.4 D/A Output Control ..........................................................................................................
487
487
487
488
489
489
490
490
490
492
492
494
14.3
14.4
14.5
14.6
Section 16 RAM .................................................................................................................. 495
16.1 Overview...........................................................................................................................
16.1.1 Block Diagram.....................................................................................................
16.1.2 Register Configuration.........................................................................................
16.2 System Control Register (SYSCR) ...................................................................................
16.3 Operation ..........................................................................................................................
495
496
496
497
498
Section 17 ROM [H8/3062F-ZTAT R-Mask Version,
On-Chip Masked ROM Models] ............................................................... 499
17.1 Overview........................................................................................................................... 499
17.2 Overview of Flash Memory (H8/3062F-ZTAT R-Mask Version) ................................... 500
17.2.1 Features................................................................................................................ 500
17.2.2 Block Diagram..................................................................................................... 501
17.2.3 Pin Configuration ................................................................................................ 502
17.2.4 Register Configuration......................................................................................... 502
Rev. 6.00 Mar 18, 2005 page xx of xlviii
17.3 Flash Memory Register Descriptions................................................................................
17.3.1 Flash Memory Control Register (FLMCR) .........................................................
17.3.2 Erase Block Register (EBR) ................................................................................
17.3.3 RAM Control Register (RAMCR).......................................................................
17.3.4 Flash Memory Status Register (FLMSR) ............................................................
17.4 On-Board Programming Mode .........................................................................................
17.4.1 Boot Mode ...........................................................................................................
17.4.2 User Program Mode.............................................................................................
17.5 Flash Memory Programming/Erasing...............................................................................
17.5.1 Program Mode .....................................................................................................
17.5.2 Program-Verify Mode .........................................................................................
17.5.3 Erase Mode ..........................................................................................................
17.5.4 Erase-Verify Mode ..............................................................................................
17.6 Flash Memory Protection..................................................................................................
17.6.1 Hardware Protection ............................................................................................
17.6.2 Software Protection .............................................................................................
17.6.3 Error Protection ...................................................................................................
17.6.4 NMI Input Disabling Conditions .........................................................................
17.7 Flash Memory Emulation in RAM ...................................................................................
17.8 Flash Memory PROM Mode ............................................................................................
17.8.1 Socket Adapters and Memory Map .....................................................................
17.8.2 Notes on Use of PROM Mode.............................................................................
17.9 Flash Memory Programming and Erasing Precautions.....................................................
17.10 Masked ROM (H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
H8/3060 Masked ROM Version) Overview .....................................................................
17.10.1 Block Diagram.....................................................................................................
17.11 Notes on Ordering Masked ROM Version Chips .............................................................
17.12 Notes when Converting the F-ZTAT Application Software to the Masked ROM
Versions ............................................................................................................................
503
503
507
508
510
512
515
520
522
523
524
526
526
528
528
530
531
533
534
536
536
537
538
544
544
545
546
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version,
H8/3064 Masked ROM B-Mask Version] .............................................. 547
18.1 Overview...........................................................................................................................
18.1.1 Differences from H8/3062F-ZTAT R-Mask Version and H8/3064F-ZTAT
B-Mask Version...................................................................................................
18.2 Features.............................................................................................................................
18.2.1 Block Diagram.....................................................................................................
18.2.2 Pin Configuration ................................................................................................
18.2.3 Register Configuration.........................................................................................
547
548
549
550
551
551
Rev. 6.00 Mar 18, 2005 page xxi of xlviii
18.3 Register Descriptions........................................................................................................
18.3.1 Flash Memory Control Register 1 (FLMCR1) ....................................................
18.3.2 Flash Memory Control Register 2 (FLMCR2) ....................................................
18.3.3 Erase Block Register 1 (EBR1) ...........................................................................
18.3.4 Erase Block Register 2 (EBR2) ...........................................................................
18.3.5 RAM Control Register (RAMCR).......................................................................
18.4 Overview of Operation .....................................................................................................
18.4.1 Mode Transitions .................................................................................................
18.4.2 On-Board Programming Modes...........................................................................
18.4.3 Flash Memory Emulation in RAM ......................................................................
18.4.4 Block Configuration ............................................................................................
18.5 On-Board Programming Mode .........................................................................................
18.5.1 Boot Mode ...........................................................................................................
18.5.2 User Program Mode.............................................................................................
18.6 Flash Memory Programming/Erasing...............................................................................
18.6.1 Program Mode .....................................................................................................
18.6.2 Program-Verify Mode .........................................................................................
18.6.3 Erase Mode ..........................................................................................................
18.6.4 Erase-Verify Mode ..............................................................................................
18.7 Flash Memory Protection..................................................................................................
18.7.1 Hardware Protection ............................................................................................
18.7.2 Software Protection .............................................................................................
18.7.3 Error Protection ...................................................................................................
18.8 Flash Memory Emulation in RAM ...................................................................................
18.9 NMI Input Disabling Conditions ......................................................................................
18.10 Flash Memory PROM Mode ............................................................................................
18.10.1 Socket Adapters and Memory Map .....................................................................
18.10.2 Notes on Use of PROM Mode.............................................................................
18.11 Flash Memory Programming and Erasing Precautions.....................................................
18.12 Masked ROM (H8/3064 Masked ROM B-Mask Version) Overview...............................
18.12.1 Block Diagram.....................................................................................................
18.13 Notes on Ordering Masked ROM Version Chips .............................................................
18.14 Notes when Converting the F-ZTAT Application Software to the Masked ROM
Version..............................................................................................................................
552
552
556
557
557
558
560
560
562
564
565
566
567
572
574
576
576
581
581
583
583
584
585
587
590
591
591
592
592
598
598
599
600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM
[H8/3062F-ZTAT B-Mask Version, Masked ROM B-Mask
Versions of H8/3062, H8/3061, and H8/3060] ..................................... 601
19.1 Overview........................................................................................................................... 601
Rev. 6.00 Mar 18, 2005 page xxii of xlviii
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
19.12
19.13
19.14
19.1.1 Differences from H8/3062F-ZTAT R-Mask Version and H8/3062F-ZTAT
B-Mask Version...................................................................................................
Features.............................................................................................................................
19.2.1 Block Diagram.....................................................................................................
19.2.2 Pin Configuration ................................................................................................
19.2.3 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
19.3.1 Flash Memory Control Register 1 (FLMCR1) ....................................................
19.3.2 Flash Memory Control Register 2 (FLMCR2) ....................................................
19.3.3 Erase Block Register (EBR) ................................................................................
19.3.4 RAM Control Register (RAMCR).......................................................................
Overview of Operation .....................................................................................................
19.4.1 Mode Transitions .................................................................................................
19.4.2 On-Board Programming Modes...........................................................................
19.4.3 Flash Memory Emulation in RAM ......................................................................
19.4.4 Block Configuration ............................................................................................
On-Board Programming Mode .........................................................................................
19.5.1 Boot Mode ...........................................................................................................
19.5.2 User Program Mode.............................................................................................
Flash Memory Programming/Erasing...............................................................................
19.6.1 Program Mode .....................................................................................................
19.6.2 Program-Verify Mode .........................................................................................
19.6.3 Erase Mode ..........................................................................................................
19.6.4 Erase-Verify Mode ..............................................................................................
Flash Memory Protection..................................................................................................
19.7.1 Hardware Protection ............................................................................................
19.7.2 Software Protection .............................................................................................
19.7.3 Error Protection ...................................................................................................
Flash Memory Emulation in RAM ...................................................................................
NMI Input Disabling Conditions ......................................................................................
Flash Memory PROM Mode ............................................................................................
19.10.1 Socket Adapters and Memory Map .....................................................................
19.10.2 Notes on Use of PROM Mode.............................................................................
Flash Memory Programming and Erasing Precautions.....................................................
Masked ROM (H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM
B-Mask Version, H8/3060 Masked ROM B-Mask Version) Overview ...........................
19.12.1 Block Diagram.....................................................................................................
Notes on Ordering Masked ROM Version Chips .............................................................
Notes when Converting the F-ZTAT Application Software to the Masked ROM
Versions ............................................................................................................................
602
603
604
605
605
606
606
610
611
612
614
614
616
618
619
620
621
626
628
630
630
635
635
637
637
638
639
641
643
644
644
645
645
651
651
652
653
Rev. 6.00 Mar 18, 2005 page xxiii of xlviii
Section 20 Clock Pulse Generator ..................................................................................
20.1 Overview...........................................................................................................................
20.1.1 Block Diagram.....................................................................................................
20.2 Oscillator Circuit ..............................................................................................................
20.2.1 Connecting a Crystal Resonator ..........................................................................
20.2.2 External Clock Input............................................................................................
20.3 Duty Adjustment Circuit...................................................................................................
20.4 Prescalers ..........................................................................................................................
20.5 Frequency Divider ............................................................................................................
20.5.1 Register Configuration.........................................................................................
20.5.2 Division Control Register (DIVCR) ....................................................................
20.5.3 Usage Notes.........................................................................................................
655
655
656
656
656
659
662
662
662
663
663
664
Section 21 Power-Down State ......................................................................................... 665
21.1 Overview........................................................................................................................... 665
21.2 Register Configuration...................................................................................................... 667
21.2.1 System Control Register (SYSCR)...................................................................... 667
21.2.2 Module Standby Control Register H (MSTCRH)................................................ 669
21.2.3 Module Standby Control Register L (MSTCRL) ................................................ 670
21.3 Sleep Mode ....................................................................................................................... 672
21.3.1 Transition to Sleep Mode..................................................................................... 672
21.3.2 Exit from Sleep Mode.......................................................................................... 672
21.4 Software Standby Mode.................................................................................................... 672
21.4.1 Transition to Software Standby Mode ................................................................. 672
21.4.2 Exit from Software Standby Mode ...................................................................... 673
21.4.3 Selection of Waiting Time for Exit from Software Standby Mode ..................... 673
21.4.4 Sample Application of Software Standby Mode.................................................. 675
21.4.5 Usage Note .......................................................................................................... 675
21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version .............. 676
21.5 Hardware Standby Mode .................................................................................................. 677
21.5.1 Transition to Hardware Standby Mode................................................................ 677
21.5.2 Exit from Hardware Standby Mode..................................................................... 677
21.5.3 Timing for Hardware Standby Mode................................................................... 678
21.6 Module Standby Function................................................................................................. 679
21.6.1 Module Standby Timing ...................................................................................... 679
21.6.2 Read/Write in Module Standby ........................................................................... 679
21.6.3 Usage Notes......................................................................................................... 679
21.7 System Clock Output Disabling Function ........................................................................ 680
Rev. 6.00 Mar 18, 2005 page xxiv of xlviii
Section 22 Electrical Characteristics .............................................................................
22.1 Electrical Characteristics of H8/3062 Masked ROM Version,
H8/3061 Masked ROM Version, and H8/3060 Masked ROM Version ...........................
22.1.1 Absolute Maximum Ratings ................................................................................
22.1.2 DC Characteristics ...............................................................................................
22.1.3 AC Characteristics ...............................................................................................
22.1.4 A/D Conversion Characteristics ..........................................................................
22.1.5 D/A Conversion Characteristics ..........................................................................
22.2 Electrical Characteristics of H8/3062F-ZTAT R-Mask Version ......................................
22.2.1 Absolute Maximum Ratings ................................................................................
22.2.2 DC Characteristics ...............................................................................................
22.2.3 AC Characteristics ...............................................................................................
22.2.4 A/D Conversion Characteristics ..........................................................................
22.2.5 D/A Conversion Characteristics ..........................................................................
22.2.6 Flash Memory Characteristics .............................................................................
22.3 Electrical Characteristics of H8/3064F-ZTAT B-Mask Version ......................................
22.3.1 Absolute Maximum Ratings ................................................................................
22.3.2 DC Characteristics ...............................................................................................
22.3.3 AC Characteristics ...............................................................................................
22.3.4 A/D Conversion Characteristics ..........................................................................
22.3.5 D/A Conversion Characteristics ..........................................................................
22.3.6 Flash Memory Characteristics .............................................................................
22.4 Electrical Characteristics of H8/3064 Masked ROM B-Mask Version ............................
22.4.1 Absolute Maximum Ratings ................................................................................
22.4.2 DC Characteristics ...............................................................................................
22.4.3 AC Characteristics ...............................................................................................
22.4.4 A/D Conversion Characteristics ..........................................................................
22.4.5 D/A Conversion Characteristics ..........................................................................
22.5 Electrical Characteristics of H8/3062F-ZTAT B-Mask Version ......................................
22.5.1 Absolute Maximum Ratings ................................................................................
22.5.2 DC Characteristics ...............................................................................................
22.5.3 AC Characteristics ...............................................................................................
22.5.4 A/D Conversion Characteristics ..........................................................................
22.5.5 D/A Conversion Characteristics ..........................................................................
22.5.6 Flash Memory Characteristics .............................................................................
22.6 Electrical Characteristics of H8/3062 Masked ROM B-Mask Version,
H8/3061 Masked ROM B-Mask Version, and H8/3060 Masked ROM B-Mask Version
22.6.1 Absolute Maximum Ratings ................................................................................
22.6.2 DC Characteristics ...............................................................................................
22.6.3 AC Characteristics ...............................................................................................
681
682
682
683
694
700
702
703
703
704
712
718
720
721
725
725
726
731
737
738
739
741
741
742
746
752
753
754
754
755
760
766
767
768
770
770
771
775
Rev. 6.00 Mar 18, 2005 page xxv of xlviii
22.6.4 A/D Conversion Characteristics ..........................................................................
22.6.5 D/A Conversion Characteristics ..........................................................................
22.7 Operational Timing...........................................................................................................
22.7.1 Clock Timing .......................................................................................................
22.7.2 Control Signal Timing .........................................................................................
22.7.3 Bus Timing ..........................................................................................................
22.7.4 TPC and I/O Port Timing.....................................................................................
22.7.5 Timer Input/Output Timing .................................................................................
22.7.6 SCI Input/Output Timing.....................................................................................
781
782
783
783
784
785
789
789
790
Appendix A Instruction Set .............................................................................................. 791
A.1
A.2
A.3
Instruction List.................................................................................................................. 791
Operation Code Maps ....................................................................................................... 806
Number of States Required for Execution ........................................................................ 809
Appendix B Internal I/O Registers ................................................................................. 818
B.1
B.2
B.3
B.4
Address List
(H8/3062F-ZTAT R-Mask Version, H8/3062 Masked ROM Version,
H8/3061 Masked ROM Version, H8/3060 Masked ROM Version)................................. 819
Address List
(H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version).............. 829
Address List
(H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM B-Mask Version,
H8/3061 Masked ROM B-Mask Version, and H8/3060 Masked ROM B-Mask Version) 839
Functions .......................................................................................................................... 849
Appendix C I/O Port Block Diagrams .......................................................................... 919
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
Port 1 Block Diagram .......................................................................................................
Port 2 Block Diagram .......................................................................................................
Port 3 Block Diagram .......................................................................................................
Port 4 Block Diagram .......................................................................................................
Port 5 Block Diagram .......................................................................................................
Port 6 Block Diagrams......................................................................................................
Port 7 Block Diagrams......................................................................................................
Port 8 Block Diagrams......................................................................................................
Port 9 Block Diagrams......................................................................................................
Port A Block Diagrams.....................................................................................................
Port B Block Diagrams .....................................................................................................
Rev. 6.00 Mar 18, 2005 page xxvi of xlviii
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920
921
922
923
924
929
930
934
940
943
Appendix D Pin States ........................................................................................................ 949
D.1
D.2
Port States in Each Mode.................................................................................................. 949
Pin States at Reset............................................................................................................. 954
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode ............................................................................................... 958
Appendix F Product Code Lineup .................................................................................. 959
Appendix G Package Dimensions .................................................................................. 961
Appendix H Comparison of H8/300H Series Product Specifications.................. 964
H.1
H.2
Differences between H8/3067 and H8/3062 Group, H8/3048 Group,
H8/3007 and H8/3006, and H8/3002 ................................................................................ 964
Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)........ 967
Rev. 6.00 Mar 18, 2005 page xxvii of xlviii
Figures
Section 1 Overview
Figure 1.1
Block Diagram..................................................................................................... 7
Figure 1.2
Pin Arrangement of H8/3062F-ZTAT R-Mask Version,
H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
and H8/3060 Masked ROM Version (FP-100B or TFP-100B Package,
Top View)............................................................................................................ 9
Figure 1.3
Pin Arrangement of H8/3062F-ZTAT R-Mask Version,
H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
and H8/3060 Masked ROM Version (FP-100A Package, Top View) ................. 10
Figure 1.4
Pin Arrangement of H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,
H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,
and H8/3060 Masked ROM B-Mask Version (FP-100B or TFP-100B Package,
Top View)............................................................................................................ 11
Figure 1.5
Pin Arrangement of H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,
H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,
and H8/3060 Masked ROM B-Mask Version (FP-100A Package, Top View) ... 12
Figure 1.6
H8/3062F-ZTAT B-Mask Version, H8/3064F-ZTAT B-Mask Version,
and On-Chip Masked ROM B-Mask Versions .................................................... 26
Figure 1.7
Example of Board Pattern Providing for External Capacitor............................... 27
Section 2 CPU
Figure 2.1
CPU Operating Modes.........................................................................................
Figure 2.2
Memory Map .......................................................................................................
Figure 2.3
CPU Registers......................................................................................................
Figure 2.4
Usage of General Registers..................................................................................
Figure 2.5
Stack ....................................................................................................................
Figure 2.6
General Register Data Formats............................................................................
Figure 2.7
General Register Data Formats............................................................................
Figure 2.8
Memory Data Formats.........................................................................................
Figure 2.9
Instruction Formats..............................................................................................
Figure 2.10 Memory-Indirect Branch Address Specification .................................................
Figure 2.11 Processing States .................................................................................................
Figure 2.12 Classification of Exception Sources ....................................................................
Figure 2.13 State Transitions ..................................................................................................
Figure 2.14 Stack Structure after Exception Handling............................................................
Rev. 6.00 Mar 18, 2005 page xxviii of xlviii
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32
33
34
35
37
38
39
52
56
60
61
62
63
Figure 2.15
Figure 2.16
Figure 2.17
Figure 2.18
On-Chip Memory Access Cycle ..........................................................................
Pin States during On-Chip Memory Access (Address Update Mode 1)..............
Access Cycle for On-Chip Supporting Modules..................................................
Pin States during Access to On-Chip Supporting Modules .................................
65
66
66
67
Section 3 MCU Operating Modes
Figure 3.1
Memory Map of H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM Version,
and H8/3062 Masked ROM B-Mask Version in Each Operating Mode .............
Figure 3.2
Memory Map of H8/3061 Masked ROM Version and H8/3061 Masked ROM
B-Mask Version in Each Operating Mode...........................................................
Figure 3.3
Memory Map of H8/3060 Masked ROM Version and H8/3060 Masked ROM
B-Mask Version in Each Operating Mode...........................................................
Figure 3.4
H8/3064F-ZTAT B-Mask Version and H8/3064 Masked ROM B-Mask Version
Memory Map in Each Operating Mode ...............................................................
85
Section 4 Exception Handling
Figure 4.1
Exception Sources ...............................................................................................
Figure 4.2
Reset Sequence (Modes 1 and 3).........................................................................
Figure 4.3
Reset Sequence (Modes 2 and 4).........................................................................
Figure 4.4
Reset Sequence (Mode 6) ....................................................................................
Figure 4.5
Interrupt Sources and Number of Interrupts ........................................................
Figure 4.6
Stack after Completion of Exception Handling ...................................................
Figure 4.7
Operation when SP Value is Odd ........................................................................
88
91
92
93
94
95
97
Section 5 Interrupt Controller
Figure 5.1
Interrupt Controller Block Diagram.....................................................................
Figure 5.2
Block Diagram of Interrupts IRQ0 to IRQ5 ..........................................................
Figure 5.3
Timing of Setting of IRQnF.................................................................................
Figure 5.4
Process Up to Interrupt Acceptance when UE = 1...............................................
Figure 5.5
Interrupt Masking State Transitions (Example)...................................................
Figure 5.6
Process Up to Interrupt Acceptance when UE = 0...............................................
Figure 5.7
Interrupt Exception Handling Sequence ..............................................................
Figure 5.8
Contention between Interrupt and Interrupt-Disabling Instruction......................
100
111
112
117
119
120
121
123
79
81
83
Section 6 Bus Controller
Figure 6.1
Block Diagram of Bus Controller........................................................................ 126
Figure 6.2
Access Area Map for Each Operating Mode ....................................................... 141
Rev. 6.00 Mar 18, 2005 page xxix of xlviii
Figure 6.3
Figure 6.3
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
Figure 6.21
Figure 6.22
Figure 6.23
Figure 6.24
Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM Version,
H8/3061 Masked ROM Version, H8/3062 Masked ROM B-Mask Version,
H8/3061 Masked ROM B-Mask Version) (1) .....................................................
Memory Map in 16-Mbyte Mode (H8/3060 Masked ROM Version,
H8/3060 Masked ROM B-Mask Version) (2) .....................................................
Memory Map in 16-Mbyte Mode (H8/3064F-ZTAT B-Mask Version,
H8/3064 Masked ROM B-Mask Version) (3) .....................................................
CSn Signal Output Timing (n = 0 to 7)................................................................
Sample Address Output in Each Address Update Mode (Basic Bus Interface,
3-State Space) ......................................................................................................
Example of Consecutive External Space Accesses in Address Update Mode 2..
Access Sizes and Data Alignment Control (8-Bit Access Area) .........................
Access Sizes and Data Alignment Control (16-Bit Access Area) .......................
Bus Control Signal Timing for 8-Bit, Three-State-Access Area .........................
Bus Control Signal Timing for 8-Bit, Two-State-Access Area ...........................
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address) ...........................................................................
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address).............................................................................
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access) .....................................................................................................
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address) ...........................................................................
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address).............................................................................
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access) .....................................................................................................
Example of Wait State Insertion Timing .............................................................
Example of Idle Cycle Operation (ICIS1 = 1) .....................................................
Example of Idle Cycle Operation (ICIS0 = 1) .....................................................
Example of Idle Cycle Operation ........................................................................
Example of External Bus Master Operation ........................................................
ASTCR Write Timing..........................................................................................
DDR Write Timing ..............................................................................................
BRCR Write Timing............................................................................................
142
143
144
147
148
149
150
151
153
154
155
156
157
158
159
160
161
162
163
164
166
167
167
168
Section 7 I/O Ports
Figure 7.1
Port 1 Pin Configuration...................................................................................... 173
Figure 7.2
Port 2 Pin Configuration...................................................................................... 176
Rev. 6.00 Mar 18, 2005 page xxx of xlviii
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10
Figure 7.11
Port 3 Pin Configuration......................................................................................
Port 4 Pin Configuration......................................................................................
Port 5 Pin Configuration......................................................................................
Port 6 Pin Configuration......................................................................................
Port 7 Pin Configuration......................................................................................
Port 8 Pin Configuration......................................................................................
Port 9 Pin Configuration......................................................................................
Port A Pin Configuration .....................................................................................
Port B Pin Configuration .....................................................................................
180
182
186
190
194
196
201
207
219
Section 8 16-Bit Timer
Figure 8.1
16-bit timer Block Diagram (Overall) .................................................................
Figure 8.2
Block Diagram of Channels 0 and 1 ....................................................................
Figure 8.3
Block Diagram of Channel 2 ...............................................................................
Figure 8.4
16TCNT Access Operation [CPU → 16TCNT (Word)] .....................................
Figure 8.5
Access to Timer Counter (CPU Reads 16TCNT, Word).....................................
Figure 8.6
Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte)................
Figure 8.7
Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) ................
Figure 8.8
Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte).....................
Figure 8.9
Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) .....................
Figure 8.10 16TCR Access (CPU Writes to 16TCR) .............................................................
Figure 8.11 16TCR Access (CPU Reads 16TCR) ..................................................................
Figure 8.12 Counter Setup Procedure (Example) ...................................................................
Figure 8.13 Free-Running Counter Operation ........................................................................
Figure 8.14 Periodic Counter Operation .................................................................................
Figure 8.15 Count Timing for Internal Clock Sources............................................................
Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected) ......
Figure 8.17 Setup Procedure for Waveform Output by Compare Match (Example) ..............
Figure 8.18 0 and 1 Output (TOA = 1, TOB = 0) ...................................................................
Figure 8.19 Toggle Output (TOA = 1, TOB = 0)....................................................................
Figure 8.20 Output Compare Output Timing..........................................................................
Figure 8.21 Setup Procedure for Input Capture (Example).....................................................
Figure 8.22 Input Capture (Example) .....................................................................................
Figure 8.23 Input Capture Signal Timing ...............................................................................
Figure 8.24 Setup Procedure for Synchronization (Example).................................................
Figure 8.25 Synchronization (Example) .................................................................................
Figure 8.26 Setup Procedure for PWM Mode (Example).......................................................
Figure 8.27 PWM Mode (Example 1).....................................................................................
Figure 8.28 PWM Mode (Example 2).....................................................................................
Figure 8.29 Setup Procedure for Phase Counting Mode (Example) .......................................
229
230
231
256
256
257
257
257
258
258
259
260
261
262
262
263
263
264
264
265
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266
267
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Rev. 6.00 Mar 18, 2005 page xxxi of xlviii
Figure 8.30
Figure 8.31
Figure 8.32
Figure 8.33
Figure 8.34
Figure 8.35
Figure 8.36
Figure 8.37
Figure 8.38
Figure 8.39
Figure 8.40
Figure 8.41
Figure 8.42
Figure 8.43
Figure 8.44
Operation in Phase Counting Mode (Example) ...................................................
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode...............
Timing for Setting 16-Bit Timer Output Level by Writing to TOLR ..................
Timing of Setting of IMFA and IMFB by Compare Match.................................
Timing of Setting of IMFA and IMFB by Input Capture ....................................
Timing of Setting of OVF....................................................................................
Timing of Clearing of Status Flags......................................................................
Contention between 16TCNT Write and Clear....................................................
Contention between 16TCNT Word Write and Increment ..................................
Contention between 16TCNT Byte Write and Increment....................................
Contention between General Register Write and Compare Match ......................
Contention between 16TCNT Write and Overflow.............................................
Contention between General Register Read and Input Capture...........................
Contention between Counter Clearing by Input Capture and Counter
Increment .............................................................................................................
Contention between General Register Write and Input Capture..........................
Section 9 8-Bit Timers
Figure 9.1
Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)...........................
Figure 9.2
8TCNT Access Operation (CPU Writes to 8TCNT, Word) ................................
Figure 9.3
8TCNT Access Operation (CPU Reads 8TCNT, Word) .....................................
Figure 9.4
8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)...................
Figure 9.5
8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)...................
Figure 9.6
8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)........................
Figure 9.7
8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) .......................
Figure 9.8
Count Timing for Internal Clock Input................................................................
Figure 9.9
Count Timing for External Clock Input (Both-Edge Detection)..........................
Figure 9.10 Timing of Timer Output ......................................................................................
Figure 9.11 Timing of Clear by Compare Match....................................................................
Figure 9.12 Timing of Clear by Input Capture........................................................................
Figure 9.13 Timing of Input Capture Input Signal..................................................................
Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs ...................................
Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs ....................................
Figure 9.16 Timing of OVF Setting ........................................................................................
Figure 9.17 Example of Pulse Output .....................................................................................
Figure 9.18 Contention between 8TCNT Write and Clear......................................................
Figure 9.19 Contention between 8TCNT Write and Increment ..............................................
Figure 9.20 Contention between TCOR Write and Compare Match ......................................
Figure 9.21 Contention between TCOR Read and Input Capture...........................................
Rev. 6.00 Mar 18, 2005 page xxxii of xlviii
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274
275
276
277
278
278
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281
282
283
284
285
286
287
295
309
309
310
310
310
310
311
312
312
313
313
314
314
315
315
321
322
323
324
325
Figure 9.22
Figure 9.23
Figure 9.24
Contention between Counter Clearing by Input Capture and Counter
Increment ............................................................................................................. 326
Contention between TCOR Write and Input Capture .......................................... 327
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode . 328
Section 10 Programmable Timing Pattern Controller (TPC)
Figure 10.1 TPC Block Diagram ............................................................................................
Figure 10.2 TPC Output Operation.........................................................................................
Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example) .......
Figure 10.4 Setup Procedure for Normal TPC Output (Example) ..........................................
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)...................................
Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example) ..........................
Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output) ..........................................................................
Figure 10.8 TPC Output Triggering by Input Capture (Example) ..........................................
Figure 10.9 Non-Overlapping TPC Output.............................................................................
Figure 10.10 Non-Overlapping Operation and NDR Write Timing .........................................
355
356
357
358
Section 11 Watchdog Timer
Figure 11.1 WDT Block Diagram...........................................................................................
Figure 11.2 Format of Data Written to TCNT and TCSR.......................................................
Figure 11.3 Format of Data Written to RSTCSR....................................................................
Figure 11.4 Operation in Watchdog Timer Mode...................................................................
Figure 11.5 Interval Timer Operation .....................................................................................
Figure 11.6 Timing of Setting of OVF....................................................................................
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset.............................................
Figure 11.8 Contention between TCNT Write and Count up .................................................
360
366
366
368
368
369
370
371
Section 12 Serial Communication Interface
Figure 12.1 SCI Block Diagram..............................................................................................
Figure 12.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)..............................................
Figure 12.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode) .........................................................................................
Figure 12.4 Sample Flowchart for SCI Initialization ..............................................................
Figure 12.5 Sample Flowchart for Transmitting Serial Data ..................................................
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)...........................................................
Figure 12.7 Sample Flowchart for Receiving Serial Data.......................................................
Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)..
334
350
351
352
353
354
375
406
408
409
410
411
412
415
Rev. 6.00 Mar 18, 2005 page xxxiii of xlviii
Figure 12.9
Figure 12.10
Figure 12.11
Figure 12.12
Figure 12.13
Figure 12.14
Figure 12.15
Figure 12.16
Figure 12.17
Figure 12.18
Figure 12.19
Figure 12.20
Figure 12.21
Figure 12.22
Figure 12.23
Figure 12.24
Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A) .................................................
Sample Flowchart for Transmitting Multiprocessor Serial Data .........................
Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit) .......................................................................................................
Sample Flowchart for Receiving Multiprocessor Serial Data..............................
Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit) .......................................................................................................
Data Format in Synchronous Communication.....................................................
Sample Flowchart for SCI Initialization ..............................................................
Sample Flowchart for Serial Transmitting...........................................................
Example of SCI Transmit Operation ...................................................................
Sample Flowchart for Serial Receiving ...............................................................
Example of SCI Receive Operation.....................................................................
Sample Flowchart for Simultaneous Serial Transmitting and Receiving ............
Receive Data Sampling Timing in Asynchronous Mode.....................................
Example of Synchronous Transmission...............................................................
Operation when Switching from SCK Pin Function to Port Pin Function...........
Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output) .......................................................
Section 13 Smart Card Interface
Figure 13.1 Block Diagram of Smart Card Interface ..............................................................
Figure 13.2 Smart Card Interface Connection Diagram..........................................................
Figure 13.3 Smart Card Interface Data Format.......................................................................
Figure 13.4 Timing of TEND Flag Setting .............................................................................
Figure 13.5 Sample Transmission Processing Flowchart........................................................
Figure 13.6 Relation Between Transmit Operation and Internal Registers.............................
Figure 13.7 Timing of TEND Flag Setting .............................................................................
Figure 13.8 Sample Reception Processing Flowchart.............................................................
Figure 13.9 Timing for Fixing Cock Output ...........................................................................
Figure 13.10 Procedure for Stopping and Restarting the Clock................................................
Figure 13.11 Receive Data Sampling Timing in Smart Card Interface Mode ..........................
Figure 13.12 Retransmission in SCI Receive Mode .................................................................
Figure 13.13 Retransmission in SCI Transmit Mode................................................................
416
417
418
419
421
422
424
425
426
427
429
430
433
434
435
436
438
446
447
453
454
455
455
456
457
459
460
462
462
Section 14 A/D Converter
Figure 14.1 A/D Converter Block Diagram ............................................................................ 466
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40) ................................... 474
Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ........ 476
Rev. 6.00 Mar 18, 2005 page xxxiv of xlviii
Figure 14.4
Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected) ..............................................................................................................
Figure 14.5 A/D Conversion Timing ......................................................................................
Figure 14.6 External Trigger Input Timing.............................................................................
Figure 14.7 Example of Analog Input Protection Circuit .......................................................
Figure 14.8 Analog Input Pin Equivalent Circuit....................................................................
Figure 14.9 A/D Converter Accuracy Definitions (1).............................................................
Figure 14.10 A/D Converter Accuracy Definitions (2).............................................................
Figure 14.11 Analog Input Circuit (Example) ..........................................................................
478
479
480
482
483
484
484
485
Section 15 D/A Converter
Figure 15.1 D/A Converter Block Diagram ............................................................................ 488
Figure 15.2 Example of D/A Converter Operation ................................................................. 493
Section 16 RAM
Figure 16.1 RAM Block Diagram........................................................................................... 496
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Figure 17.1 Block Diagram of Flash Memory ........................................................................
Figure 17.2 Example of ROM Area/RAM Area Overlap .......................................................
Figure 17.3 Boot Mode ...........................................................................................................
Figure 17.4 User Program Mode (Example)...........................................................................
Figure 17.5 System Configuration When Using Boot Mode ..................................................
Figure 17.6 Boot Mode Execution Procedure.........................................................................
Figure 17.7 Measurement of Low Period of Host’s Transmit Data ........................................
Figure 17.8 RAM Areas in Boot Mode...................................................................................
Figure 17.9 User Program Mode Execution Procedure (Example).........................................
Figure 17.10 FLMCR Bit Settings and State Transitions .........................................................
Figure 17.11 Program/Program-Verify Flowchart (32-byte Programming) .............................
Figure 17.12 Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................
Figure 17.13 Flash Memory State Transitions (Modes 5 and 7 (On-Chip ROM Enabled),
High Level Applied to FWE Pin) ........................................................................
Figure 17.14 Example of RAM Overlap Operation ..................................................................
Figure 17.15 Memory Map in PROM Mode.............................................................................
Figure 17.16 Power-On/Off Timing (Boot Mode)....................................................................
Figure 17.17 Power-On/Off Timing (User Program Mode) .....................................................
Figure 17.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User
Program Mode)....................................................................................................
Figure 17.19 ROM Block Diagram (H8/3062 Masked ROM Version) ....................................
Figure 17.20 Masked ROM Addresses and Data ......................................................................
501
510
513
514
515
516
517
518
521
523
525
527
532
534
537
541
542
543
544
545
Rev. 6.00 Mar 18, 2005 page xxxv of xlviii
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Figure 18.1 Block Diagram of Flash Memory ........................................................................ 550
Figure 18.2 Flash Memory Related State Transitions............................................................. 561
Figure 18.3 Reading Overlap RAM Data in User Mode/User Program Mode ....................... 564
Figure 18.4 Writing Overlap RAM Data in User Program Mode ........................................... 565
Figure 18.5 System Configuration When Using Boot Mode .................................................. 567
Figure 18.6 Boot Mode Execution Procedure......................................................................... 568
Figure 18.7 RAM Areas in Boot Mode................................................................................... 570
Figure 18.8 Example of User Program Mode Execution Procedure ....................................... 573
Figure 18.9 FLMCR1 Bit Settings and State Transitions ....................................................... 575
Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming)........................... 580
Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................ 582
Figure 18.12 Flash Memory State Transitions (When High Level is Applied to FWE Pin
in Mode 5 or 7 (On-Chip ROM Enabled))........................................................... 586
Figure 18.13 Flowchart of Flash Memory Emulation in RAM................................................. 587
Figure 18.14 Example of RAM Overlap Operation .................................................................. 588
Figure 18.15 Memory Map in PROM Mode............................................................................. 591
Figure 18.16 Power-On/Off Timing (Boot Mode).................................................................... 595
Figure 18.17 Power-On/Off Timing (User Program Mode) ..................................................... 596
Figure 18.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User
Program Mode).................................................................................................... 597
Figure 18.19 ROM Block Diagram (H8/3064 Masked ROM B-Mask Version) ...................... 598
Figure 18.20 Masked ROM Addresses and Data ...................................................................... 599
Section 19 H8/3062 Internal Voltage Step-Down Version ROM
[H8/3062F-ZTAT B-Mask Version, Masked ROM B-Mask Versions
of H8/3062, H8/3061, and H8/3060]
Figure 19.1 Block Diagram of Flash Memory ........................................................................
Figure 19.2 Example of ROM Area/RAM Area Overlap .......................................................
Figure 19.3 Flash Memory Related State Transitions.............................................................
Figure 19.4 Reading Overlap RAM Data in User Mode/User Program Mode .......................
Figure 19.5 Writing Overlap RAM Data in User Program Mode ...........................................
Figure 19.6 System Configuration When Using Boot Mode ..................................................
Figure 19.7 Boot Mode Execution Procedure.........................................................................
Figure 19.8 RAM Areas in Boot Mode...................................................................................
Figure 19.9 Example of User Program Mode Execution Procedure .......................................
Figure 19.10 FLMCR1 Bit Settings and State Transitions .......................................................
Figure 19.11 Program/Program-Verify Flowchart (128-Byte Programming)...........................
Figure 19.12 Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................
Rev. 6.00 Mar 18, 2005 page xxxvi of xlviii
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615
618
619
621
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627
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634
636
Figure 19.13 Flash Memory State Transitions (When High Level is Applied to FWE Pin
in Mode 5 or 7 (On-Chip ROM Enabled))...........................................................
Figure 19.14 Example of RAM Overlap Operation ..................................................................
Figure 19.15 Memory Map in PROM Mode.............................................................................
Figure 19.16 Power-On/Off Timing (Boot Mode)....................................................................
Figure 19.17 Power-On/Off Timing (User Program Mode) .....................................................
Figure 19.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User
Program Mode)....................................................................................................
Figure 19.19 ROM Block Diagram (H8/3062 Masked ROM B-Mask Version) ......................
Figure 19.20 Masked ROM Addresses and Data ......................................................................
Section 20 Clock Pulse Generator
Figure 20.1 Block Diagram of Clock Pulse Generator ...........................................................
Figure 20.2 Connection of Crystal Resonator (Example) .......................................................
Figure 20.3 Crystal Resonator Equivalent Circuit ..................................................................
Figure 20.4 Oscillator Circuit Block Board Design Precautions ............................................
Figure 20.5 External Clock Input (Examples) ........................................................................
Figure 20.6 External Clock Input Timing ...............................................................................
Figure 20.7 External Clock Output Settling Delay Timing.....................................................
640
641
644
648
649
650
651
652
656
656
657
658
659
661
662
Section 21 Power-Down State
Figure 21.1 NMI Timing for Software Standby Mode (Example).......................................... 675
Figure 21.2 Hardware Standby Mode Timing......................................................................... 678
Figure 21.3 Starting and Stopping of System Clock Output ................................................... 680
Section 22 Electrical Characteristics
Figure 22.1 Darlington Pair Drive Circuit (Example).............................................................
Figure 22.2 Sample LED Circuit ............................................................................................
Figure 22.3 Output Load Circuit.............................................................................................
Figure 22.4 Darlington Pair Drive Circuit (Example).............................................................
Figure 22.5 Sample LED Circuit ............................................................................................
Figure 22.6 Output Load Circuit.............................................................................................
Figure 22.7 Darlington Pair Drive Circuit (Example).............................................................
Figure 22.8 Sample LED Circuit ............................................................................................
Figure 22.9 Output Load Circuit.............................................................................................
Figure 22.10 Darlington Pair Drive Circuit (Example).............................................................
Figure 22.11 Sample LED Circuit ............................................................................................
Figure 22.12 Output Load Circuit.............................................................................................
Figure 22.13 Darlington Pair Drive Circuit (Example).............................................................
Figure 22.14 Sample LED Circuit ............................................................................................
692
693
699
710
711
717
729
730
736
745
745
751
758
759
Rev. 6.00 Mar 18, 2005 page xxxvii of xlviii
Figure 22.15
Figure 22.16
Figure 22.17
Figure 22.18
Figure 22.19
Figure 22.20
Figure 22.21
Figure 22.22
Figure 22.23
Figure 22.24
Figure 22.25
Figure 22.26
Figure 22.27
Figure 22.28
Figure 22.29
Figure 22.30
Figure 22.31
Output Load Circuit.............................................................................................
Darlington Pair Drive Circuit (Example).............................................................
Sample LED Circuit ............................................................................................
Output Load Circuit.............................................................................................
Oscillator Settling Timing....................................................................................
Reset Input Timing ..............................................................................................
Reset Output Timing............................................................................................
Interrupt Input Timing .........................................................................................
Basic Bus Cycle: Two-State Access ....................................................................
Basic Bus Cycle: Three-State Access ..................................................................
Basic Bus Cycle: Three-State Access with One Wait State.................................
Bus-Release Mode Timing ..................................................................................
TPC and I/O Port Input/Output Timing ...............................................................
Timer Input/Output Timing .................................................................................
Timer External Clock Input Timing.....................................................................
SCI Input Clock Timing ......................................................................................
SCI Input/Output Timing in Synchronous Mode.................................................
765
774
774
780
783
784
784
785
786
787
788
788
789
789
790
790
790
Appendix C I/O Port Block Diagrams
Figure C.1
Port 1 Block Diagram (Pins P10 to P17)...............................................................
Figure C.2
Port 2 Block Diagram (Pins P20 to P27)...............................................................
Figure C.3
Port 3 Block Diagram (Pins P30 to P37)...............................................................
Figure C.4
Port 4 Block Diagram (Pins P40 to P47)...............................................................
Figure C.5
Port 5 Block Diagram (Pins P50 to P53)...............................................................
Figure C.6 (a) Port 6 Block Diagram (Pin P60)...........................................................................
Figure C.6 (b) Port 6 Block Diagram (Pin P61)...........................................................................
Figure C.6 (c) Port 6 Block Diagram (Pin P62)...........................................................................
Figure C.6 (d) Port 6 Block Diagram (Pins P63 to P66)...............................................................
Figure C.6 (e) Port 6 Block Diagram (Pin P67)...........................................................................
Figure C.7 (a) Port 7 Block Diagram (Pins P70 to P75)...............................................................
Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77) ............................................................
Figure C.8 (a) Port 8 Block Diagram (Pin P80)...........................................................................
Figure C.8 (b) Port 8 Block Diagram (Pins P81 and P82) ............................................................
Figure C.8 (c) Port 8 Block Diagram (Pin P83)...........................................................................
Figure C.8 (d) Port 8 Block Diagram (Pin P84)...........................................................................
Figure C.9 (a) Port 9 Block Diagram (Pin P90)...........................................................................
Figure C.9 (b) Port 9 Block Diagram (Pin P91)...........................................................................
Figure C.9 (c) Port 9 Block Diagram (Pin P92)...........................................................................
Figure C.9 (d) Port 9 Block Diagram (Pin P93)...........................................................................
Figure C.9 (e) Port 9 Block Diagram (Pin P94)...........................................................................
919
920
921
922
923
924
925
926
927
928
929
929
930
931
932
933
934
935
936
937
938
Rev. 6.00 Mar 18, 2005 page xxxviii of xlviii
Figure C.9 (f) Port 9 Block Diagram (Pin P95)...........................................................................
Figure C.10 (a) Port A Block Diagram (Pins PA0 and PA1) .......................................................
Figure C.10 (b) Port A Block Diagram (Pins PA2 and PA3) .......................................................
Figure C.10 (c) Port A Block Diagram (Pins PA4 to PA7)..........................................................
Figure C.11 (a) Port B Block Diagram (Pins PB0 and PB2)........................................................
Figure C.11 (b) Port B Block Diagram (Pins PB1 and PB3)........................................................
Figure C.11 (c) Port B Block Diagram (Pin PB4) .......................................................................
Figure C.11 (d) Port B Block Diagram (Pin PB5) .......................................................................
Figure C.11 (e) Port B Block Diagram (Pin PB6) .......................................................................
Figure C.11 (f) Port B Block Diagram (Pin PB7) .......................................................................
939
940
941
942
943
944
945
946
947
948
Appendix D
Figure D.1
Figure D.2
Figure D.3
Figure D.4
Pin States
Reset during Memory Access (Modes 1 and 2)...................................................
Reset during Memory Access (Modes 3 and 4)...................................................
Reset during Memory Access (Mode 5) ..............................................................
Reset during Operation (Modes 6 and 7).............................................................
954
955
956
957
Appendix G
Figure G.1
Figure G.2
Figure G.3
Package Dimensions
Package Dimensions (FP-100B).......................................................................... 961
Package Dimensions (TFP-100B) ....................................................................... 962
Package Dimensions (FP-100A).......................................................................... 963
Rev. 6.00 Mar 18, 2005 page xxxix of xlviii
Tables
Section 1 Overview
Table 1.1
Features................................................................................................................
Table 1.2
Comparison of H8/3062 Group Pin Arrangements..............................................
Table 1.3
Pin Functions .......................................................................................................
Table 1.4
Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) ..................
Table 1.5
Differences between H8/3062F-ZTAT R-Mask Version and On-Chip Masked
ROM Versions.....................................................................................................
Table 1.6
Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask
Version, and H8/3064F-ZTAT B-Mask Version Markings.................................
2
8
13
18
22
24
Section 2 CPU
Table 2.1
Instruction Classification ..................................................................................... 40
Table 2.2
Instructions and Addressing Modes..................................................................... 41
Table 2.3
Data Transfer Instructions ................................................................................... 43
Table 2.4
Arithmetic Operation Instructions ....................................................................... 44
Table 2.5
Logic Operation Instructions ............................................................................... 46
Table 2.6
Shift Instructions.................................................................................................. 46
Table 2.7
Bit Manipulation Instructions .............................................................................. 47
Table 2.8
Branching Instructions......................................................................................... 49
Table 2.9
System Control Instructions................................................................................. 50
Table 2.10
Block Transfer Instruction ................................................................................... 51
Table 2.11
Addressing Modes ............................................................................................... 54
Table 2.12
Absolute Address Access Ranges........................................................................ 55
Table 2.13
Effective Address Calculation ............................................................................. 57
Table 2.14
Exception Handling Types and Priority............................................................... 61
Section 3 MCU Operating Modes
Table 3.1
Operating Mode Selection ...................................................................................
Table 3.2
Registers ..............................................................................................................
Table 3.3
Pin Functions in Each Mode................................................................................
Table 3.4
Address Maps in Mode 5.....................................................................................
69
70
76
77
Section 4 Exception Handling
Table 4.1
Exception Types and Priority .............................................................................. 87
Table 4.2
Exception Vector Table ....................................................................................... 89
Rev. 6.00 Mar 18, 2005 page xl of xlviii
Section 5 Interrupt Controller
Table 5.1
Interrupt Pins .......................................................................................................
Table 5.2
Interrupt Controller Registers ..............................................................................
Table 5.3
Interrupt Sources, Vector Addresses, and Priority...............................................
Table 5.4
UE, I, and UI Bit Settings and Interrupt Handling...............................................
Table 5.5
Interrupt Response Time......................................................................................
101
101
113
116
122
Section 6 Bus Controller
Table 6.1
Bus Controller Pins..............................................................................................
Table 6.2
Bus Controller Registers......................................................................................
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface) .....................................
Table 6.4
Data Buses Used and Valid Strobes.....................................................................
Table 6.5
Pin States in Idle Cycle........................................................................................
127
128
146
152
164
Section 7 I/O Ports
Table 7.1
Port Functions......................................................................................................
Table 7.2
Port 1 Registers....................................................................................................
Table 7.3
Port 2 Registers....................................................................................................
Table 7.4
Input Pull-Up Transistor States (Port 2) ..............................................................
Table 7.5
Port 3 Registers....................................................................................................
Table 7.6
Port 4 Registers....................................................................................................
Table 7.7
Input Pull-Up Transistor States (Port 4) ..............................................................
Table 7.8
Port 5 Registers....................................................................................................
Table 7.9
Input Pull-Up Transistor States (Port 5) ..............................................................
Table 7.10
Port 6 Registers....................................................................................................
Table 7.11
Port 6 Pin Functions in Modes 1 to 5...................................................................
Table 7.12
Port 7 Data Register.............................................................................................
Table 7.13
Port 8 Registers....................................................................................................
Table 7.14
Port 8 Pin Functions in Modes 1 to 5...................................................................
Table 7.15
Port 8 Pin Functions in Modes 6 and 7 ................................................................
Table 7.16
Port 9 Registers....................................................................................................
Table 7.17
Port 9 Pin Functions.............................................................................................
Table 7.18
Port A Registers...................................................................................................
Table 7.19
Port A Pin Functions (Modes 1, 2, 6, and 7)........................................................
Table 7.20
Port A Pin Functions (Modes 3 to 5) ...................................................................
Table 7.21
Port A Pin Functions (Modes 1 to 7) ...................................................................
Table 7.22
Port B Registers ...................................................................................................
Table 7.23
Port B Pin Functions (Modes 1 to 5) ...................................................................
Table 7.24
Port B Pin Functions (Modes 6 and 7).................................................................
169
174
177
179
180
183
185
187
189
191
193
195
196
199
200
202
204
208
210
212
215
220
222
224
Rev. 6.00 Mar 18, 2005 page xli of xlviii
Section 8 16-Bit Timer
Table 8.1
16-bit timer Functions..........................................................................................
Table 8.2
16-bit timer Pins ..................................................................................................
Table 8.3
16-bit timer Registers ..........................................................................................
Table 8.4
PWM Output Pins and Registers .........................................................................
Table 8.5
Up/Down Counting Conditions ...........................................................................
Table 8.6
16-bit timer Interrupt Sources..............................................................................
Table 8.7 (a) 16-bit Timer Operating Modes (Channel 0) ........................................................
Table 8.7 (b) 16-bit Timer Operating Modes (Channel 1) ........................................................
Table 8.7 (c) 16-bit Timer Operating Modes (Channel 2) ........................................................
228
232
233
270
274
279
289
290
291
Section 9 8-Bit Timers
Table 9.1
8-Bit Timer Pins ..................................................................................................
Table 9.2
8-Bit Timer Registers ..........................................................................................
Table 9.3
Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register....
Table 9.4
Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register....
Table 9.5
Types of 8-Bit Timer Interrupt Sources and Priority Order.................................
Table 9.6
8-Bit Timer Interrupt Sources..............................................................................
Table 9.7
Timer Output Priority Order ................................................................................
Table 9.8
Internal Clock Switchover and 8TCNT Operation ..............................................
296
297
307
307
320
320
329
330
Section 10 Programmable Timing Pattern Controller (TPC)
Table 10.1
TPC Pins .............................................................................................................. 335
Table 10.2
TPC Registers ...................................................................................................... 336
Table 10.3
TPC Operating Conditions .................................................................................. 350
Section 11 Watchdog Timer
Table 11.1
WDT Pin.............................................................................................................. 360
Table 11.2
WDT Registers .................................................................................................... 361
Table 11.3
Read Addresses of TCNT, TCSR, and RSTCSR................................................. 367
Section 12 Serial Communication Interface
Table 12.1
SCI Pins ...............................................................................................................
Table 12.2
SCI Registers .......................................................................................................
Table 12.3
Examples of Bit Rates and BRR Settings in Asynchronous Mode......................
Table 12.4
Examples of Bit Rates and BRR Settings in Synchronous Mode ........................
Table 12.5
Maximum Bit Rates for Various Frequencies (Asynchronous Mode).................
Table 12.6
Maximum Bit Rates with External Clock Input (Asynchronous Mode)..............
Table 12.7
Maximum Bit Rates with External Clock Input (Synchronous Mode) ................
Table 12.8
SMR Settings and Serial Communication Formats .............................................
Rev. 6.00 Mar 18, 2005 page xlii of xlviii
376
377
396
399
401
402
403
405
Table 12.9
Table 12.10
Table 12.11
Table 12.12
Table 12.13
SMR and SCR Settings and SCI Clock Source Selection....................................
Serial Communication Formats (Asynchronous Mode) ......................................
Receive Error Conditions ....................................................................................
SCI Interrupt Sources ..........................................................................................
SSR Status Flags and Transfer of Receive Data ..................................................
405
407
414
431
432
Section 13 Smart Card Interface
Table 13.1
Smart Card Interface Pins .................................................................................... 439
Table 13.2
Smart Card Interface Registers ............................................................................ 439
Table 13.3
Smart Card Interface Register Settings................................................................ 448
Table 13.4
n-Values of CKS1 and CKS0 Settings................................................................. 450
Table 13.5
Bit Rates (bits/s) for Various BRR Settings (When n = 0) .................................. 450
Table 13.6
BRR Settings for Typical Bit Rates (bits/s) (When n = 0)................................... 451
Table 13.7
Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode) ...... 451
Table 13.8
Smart Card Interface Mode Operating States and Interrupt Sources ................... 458
Section 14 A/D Converter
Table 14.1
A/D Converter Pins..............................................................................................
Table 14.2
A/D Converter Registers......................................................................................
Table 14.3
Analog Input Channels and A/D Data Registers (ADDRA to ADDRD).............
Table 14.4
A/D Conversion Time (Single Mode)..................................................................
Table 14.5
Analog Input Pin Ratings.....................................................................................
467
468
469
480
482
Section 15 D/A Converter
Table 15.1
D/A Converter Pins.............................................................................................. 489
Table 15.2
D/A Converter Registers...................................................................................... 489
Section 16 RAM
Table 16.1
H8/3062 Group On-Chip RAM Specifications.................................................... 495
Table 16.2
System Control Register ...................................................................................... 497
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Table 17.1
Operating Modes and ROM.................................................................................
Table 17.2
Flash Memory Pins ..............................................................................................
Table 17.3
Flash Memory Registers ......................................................................................
Table 17.4
Flash Memory Erase Blocks ................................................................................
Table 17.5
RAM Area Setting ...............................................................................................
Table 17.6
On-Board Programming Mode Settings ..............................................................
Table 17.7
System Clock Frequencies for which Automatic Adjustment of MCU Bit Rate
is Possible ............................................................................................................
499
502
502
508
509
512
517
Rev. 6.00 Mar 18, 2005 page xliii of xlviii
Table 17.8
Table 17.9
Table 17.10
Hardware Protection ............................................................................................ 528
Software Protection ............................................................................................. 530
H8/3062F-ZTAT R-Mask Version Socket Adapter Product Codes .................... 536
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Table 18.1
Operating Modes and ROM.................................................................................
Table 18.2
Differences from H8/3062F-ZTAT R-Mask Version and H8/3064F-ZTAT
B-Mask Version...................................................................................................
Table 18.3
Flash Memory Pins ..............................................................................................
Table 18.4
Flash Memory Registers ......................................................................................
Table 18.5
Flash Memory Erase Blocks ................................................................................
Table 18.6
Flash Memory Area Divisions .............................................................................
Table 18.7
On-Board Programming Mode Settings ..............................................................
Table 18.8
System Clock Frequencies for which Automatic Adjustment of
H8/3064F-ZTAT B-mask version Bit Rate is Possible........................................
Table 18.9
Hardware Protection ............................................................................................
Table 18.10 Software Protection .............................................................................................
Table 18.11 H8/3064F-ZTAT B-Mask Version Socket Adapter Product Codes ....................
Section 19 H8/3062 Internal Voltage Step-Down Version ROM
[H8/3062F-ZTAT B-Mask Version, Masked ROM B-Mask Versions
of H8/3062, H8/3061, and H8/3060]
Table 19.1
Operating Modes and ROM.................................................................................
Table 19.2
Differences from H8/3062F-ZTAT R-Mask Version and H8/3062F-ZTAT
B-Mask Version...................................................................................................
Table 19.3
Flash Memory Pins ..............................................................................................
Table 19.4
Flash Memory Registers ......................................................................................
Table 19.5
Flash Memory Erase Blocks ................................................................................
Table 19.6
RAM Area Setting ...............................................................................................
Table 19.7
On-Board Programming Mode Settings ..............................................................
Table 19.8
System Clock Frequencies for which Automatic Adjustment of
H8/3062F-ZTAT B-Mask Version Bit Rate is Possible ......................................
Table 19.9
Hardware Protection ............................................................................................
Table 19.10 Software Protection .............................................................................................
Table 19.11 H8/3062F-ZTAT B-Mask Version Socket Adapter Product Codes ....................
547
548
551
551
558
559
566
569
583
584
591
601
602
605
605
612
613
620
623
637
638
644
Section 20 Clock Pulse Generator
Table 20.1 (1) Damping Resistance Value.................................................................................. 657
Table 20.1 (2) External Capacitance Values ............................................................................... 657
Rev. 6.00 Mar 18, 2005 page xliv of xlviii
Table 20.2
Crystal Resonator Parameters..............................................................................
Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions ...........................................
Table 20.3 (2) Clock Timing for On-Chip Masked ROM Versions............................................
Table 20.4
Frequency Division Register ...............................................................................
Table 20.5
Comparison of H8/3062 Group Operating Frequency Ranges ............................
658
660
661
663
664
Section 21 Power-Down State
Table 21.1
Power-Down State and Module Standby Function..............................................
Table 21.2
Control Register...................................................................................................
Table 21.3
Clock Frequency and Waiting Time for Clock to Settle......................................
Table 21.4
φ Pin State in Various Operating States...............................................................
666
667
674
680
Section 22 Electrical Characteristics
Table 22.1
Electrical Characteristics of H8/3062 Group Products ....................................... 681
Table 22.2
Absolute Maximum Ratings ................................................................................ 682
Table 22.3
DC Characteristics (1) ......................................................................................... 683
Table 22.3
DC Characteristics (2) ......................................................................................... 686
Table 22.3
DC Characteristics (3) ......................................................................................... 689
Table 22.4
Permissible Output Currents................................................................................ 692
Table 22.5
Clock Timing ....................................................................................................... 694
Table 22.6
Control Signal Timing ......................................................................................... 695
Table 22.7
Bus Timing .......................................................................................................... 696
Table 22.8
Timing of On-Chip Supporting Modules............................................................. 698
Table 22.9
A/D Conversion Characteristics .......................................................................... 700
Table 22.10 D/A Conversion Characteristics .......................................................................... 702
Table 22.11 Absolute Maximum Ratings ................................................................................ 703
Table 22.12 DC Characteristics (1) ......................................................................................... 704
Table 22.12 DC Characteristics (2) ......................................................................................... 707
Table 22.13 Permissible Output Currents................................................................................ 710
Table 22.14 Clock Timing ....................................................................................................... 712
Table 22.15 Control Signal Timing ......................................................................................... 713
Table 22.16 Bus Timing .......................................................................................................... 714
Table 22.17 Timing of On-Chip Supporting Modules............................................................. 716
Table 22.18 A/D Conversion Characteristics .......................................................................... 718
Table 22.19 D/A Conversion Characteristics .......................................................................... 720
Table 22.20 Flash Memory Characteristics (1)........................................................................ 721
Table 22.20 Flash Memory Characteristics (2)........................................................................ 723
Table 22.21 Absolute Maximum Ratings ................................................................................ 725
Table 22.22 DC Characteristics ............................................................................................... 726
Table 22.23 Permissible Output Currents................................................................................ 729
Rev. 6.00 Mar 18, 2005 page xlv of xlviii
Table 22.24
Table 22.25
Table 22.26
Table 22.27
Table 22.28
Table 22.29
Table 22.30
Table 22.31
Table 22.32
Table 22.33
Table 22.34
Table 22.35
Table 22.36
Table 22.37
Table 22.38
Table 22.39
Table 22.40
Table 22.41
Table 22.42
Table 22.43
Table 22.44
Table 22.45
Table 22.46
Table 22.47
Table 22.48
Table 22.49
Table 22.50
Table 22.51
Table 22.52
Table 22.53
Table 22.54
Table 22.55
Table 22.56
Table 22.57
Table 22.58
Clock Timing .......................................................................................................
Control Signal Timing .........................................................................................
Bus Timing ..........................................................................................................
Timing of On-Chip Supporting Modules.............................................................
A/D Conversion Characteristics ..........................................................................
D/A Conversion Characteristics ..........................................................................
Flash Memory Characteristics .............................................................................
Absolute Maximum Ratings ................................................................................
DC Characteristics ...............................................................................................
Permissible Output Currents................................................................................
Clock Timing .......................................................................................................
Control Signal Timing .........................................................................................
Bus Timing ..........................................................................................................
Timing of On-Chip Supporting Modules.............................................................
A/D Conversion Characteristics ..........................................................................
D/A Conversion Characteristics ..........................................................................
Absolute Maximum Ratings ................................................................................
DC Characteristics ...............................................................................................
Permissible Output Currents................................................................................
Clock Timing .......................................................................................................
Control Signal Timing .........................................................................................
Bus Timing ..........................................................................................................
Timing of On-Chip Supporting Modules.............................................................
A/D Conversion Characteristics ..........................................................................
D/A Conversion Characteristics ..........................................................................
Flash Memory Characteristics .............................................................................
Absolute Maximum Ratings ................................................................................
DC Characteristics ...............................................................................................
Permissible Output Currents................................................................................
Clock Timing .......................................................................................................
Control Signal Timing .........................................................................................
Bus Timing ..........................................................................................................
Timing of On-Chip Supporting Modules.............................................................
A/D Conversion Characteristics ..........................................................................
D/A Conversion Characteristics ..........................................................................
Appendix A
Table A.1
Table A.2
Table A.2
Instruction Set
Instruction Set...................................................................................................... 793
Operation Code Map (1)...................................................................................... 806
Operation Code Map (2)...................................................................................... 807
Rev. 6.00 Mar 18, 2005 page xlvi of xlviii
731
732
733
735
737
738
739
741
742
744
746
747
748
750
752
753
754
755
758
760
761
762
764
766
767
768
770
771
773
775
776
777
779
781
782
Table A.2
Table A.3
Table A.4
Operation Code Map (3)...................................................................................... 808
Number of States per Cycle ................................................................................. 810
Number of Cycles per Instruction........................................................................ 811
Appendix B Internal I/O Registers
Table B.1
Comparison of H8/3062 Group Internal I/O Register Specifications .................. 818
Appendix D Pin States
Table D.1
Port States ............................................................................................................ 949
Appendix F Product Code Lineup
Table F.1
H8/3062 Group .................................................................................................... 959
Appendix H Comparison of H8/300H Series Product Specifications
Table H.1
Pin Arrangement of Each Product (FP-100B, TFP-100B)................................... 967
Rev. 6.00 Mar 18, 2005 page xlvii of xlviii
Rev. 6.00 Mar 18, 2005 page xlviii of xlviii
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8/3062 Group is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Renesas architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.
The 11 members of the H8/3062 Group are the H8/3062F-ZTAT R-mask version, H8/3062
(masked ROM version), H8/3061 (masked ROM version), H8/3060 (masked ROM version),
H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM Bmask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version,
and H8/3060 masked ROM B-mask version.
Seven MCU operating modes offer a choice of bus width and address space size. The modes
(modes 1 to 7) include two single-chip modes and five expanded modes.
In addition to its masked ROM versions, the H8/3062 Group has F-ZTAT™* versions with onchip flash memory that allows programs to be freely rewritten by the user. This version enables
users to respond quickly and flexibly to changing application specifications, growing production
volumes, and other conditions.
Table 1.1 summarizes the features of the H8/3062 Group.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 6.00 Mar 18, 2005 page 1 of 970
REJ09B0215-0600
Section 1 Overview
Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
High-speed operation
H8/3062F-ZTAT R-Mask version
Maximum
clock rate
Add/
subtract
Multiply/
divide
20 MHz
100 ns
700 ns
25 MHz
80 ns
560 ns
H8/3062 (masked ROM version)
H8/3061 (masked ROM version)
H8/3060 (masked ROM version)
H8/3064F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
H8/3064 masked ROM B-mask version
H8/3062 masked ROM B-mask version
H8/3061 masked ROM B-mask version
H8/3060 masked ROM B-mask version
16-Mbyte address space
Instruction features
•
8/16/32-bit data transfer, arithmetic, and logic instructions
•
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
•
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
•
Bit accumulator function
•
Bit manipulation instructions with register-indirect specification of bit positions
Rev. 6.00 Mar 18, 2005 page 2 of 970
REJ09B0215-0600
Section 1 Overview
Feature
Description
Memory
H8/3062F-ZTAT R-mask version
ROM
RAM
128 kbytes
4 kbytes
96 kbytes
4 kbytes
64 kbytes
2 kbytes
256 kbytes
8 kbytes
H8/3062F-ZTAT B-mask version
H8/3062 (masked ROM version)
H8/3062 masked ROM B-mask version
H8/3061 (masked ROM version)
H8/3061 masked ROM B-mask version
H8/3060 (masked ROM version)
H8/3060 masked ROM B-mask version
H8/3064F-ZTAT B-mask version
H8/3064 masked ROM B-mask version
Interrupt
controller
Bus controller
16-bit timer,
3 channels
•
Seven external interrupt pins: NMI, IRQ0 to IRQ5
•
27 internal interrupts
•
Three selectable interrupt priority levels
•
Address space can be partitioned into eight areas, with independent bus
specifications in each area
•
Chip select output available for areas 0 to 7
•
8-bit access or 16-bit access selectable for each area
•
Two-state or three-state access selectable for each area
•
Selection of two wait modes
•
Number of program wait states selectable for each area
•
Bus arbitration function
•
Two address update modes
•
Three 16-bit timer channels, capable of processing up to six pulse outputs or
six pulse inputs
•
16-bit timer counter (channels 0 to 2)
•
Two multiplexed output compare/input capture pins (channels 0 to 2)
•
Operation can be synchronized (channels 0 to 2)
•
PWM mode available (channels 0 to 2)
•
Phase counting mode available (channel 2)
Rev. 6.00 Mar 18, 2005 page 3 of 970
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Section 1 Overview
Feature
Description
8-bit timer,
4 channels
•
8-bit up-counter (external event count capability)
•
Two time constant registers
•
Two channels can be connected
Programmable •
timing pattern
•
controller (TPC)
•
Watchdog
timer (WDT),
1 channel
Serial
communication
interface (SCI),
2 channels
A/D converter
D/A converter
I/O ports
Maximum 16-bit pulse output, using 16-bit timer as time base
Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
Non-overlap mode available
•
Internal reset signal can be generated by overflow
•
Reset signal can be output externally (not available in on-chip flash memory
versions)
•
Usable as an interval timer
•
Selection of asynchronous or synchronous mode
•
Full duplex: can transmit and receive simultaneously
•
On-chip baud-rate generator
•
Smart card interface extended functions added
•
Resolution: 10 bits
•
Eight channels, with selection of single or scan mode
•
Variable analog conversion voltage range
•
Sample-and-hold function
•
A/D conversion can be started by an external trigger or 8-bit timer comparematch
•
Resolution: 8 bits
•
Two channels
•
D/A outputs can be sustained in software standby mode
•
70 input/output pins
•
9 input-only pins
Rev. 6.00 Mar 18, 2005 page 4 of 970
REJ09B0215-0600
Section 1 Overview
Feature
Description
Operating
modes
Seven MCU operating modes
Power-down
state
Other features
Mode
Address
Space
Address
Pins
Initial Bus
Width
Max. Bus
Width
Mode 1
1 Mbyte
A19 to A0
8 bits
16 bits
Mode 2
1 Mbyte
A19 to A0
16 bits
16 bits
Mode 3
16 Mbytes
A23 to A0
8 bits
16 bits
Mode 4
16 Mbytes
A23 to A0
16 bits
16 bits
Mode 5
16 Mbytes
A23 to A0
8 bits
16 bits
Mode 6
64 kbytes
—
—
—
Mode 7
1 Mbyte
—
—
—
•
On-chip ROM is disabled in modes 1 to 4
•
In the versions with on-chip flash memory, an on-board programming mode
is supported that allows flash memory to be programmed in modes 5 and 7.
•
Sleep mode
•
Software standby mode
•
Hardware standby mode
•
Module standby function
•
Programmable system clock frequency division
•
On-chip clock pulse generator
Rev. 6.00 Mar 18, 2005 page 5 of 970
REJ09B0215-0600
Section 1 Overview
Feature
Description
Product lineup
Product Type
H8/3062F-ZTAT
R-mask version
5 V operation
3 V operation
H8/3062 masked ROM
version
5 V operation
3 V operation
H8/3061 masked ROM
version
5 V operation
3 V operation
H8/3060 masked ROM
version
5 V operation
3 V operation
H8/3064F-ZTAT
B-mask version
5 V operation
H8/3064 masked ROM
B-mask version
5 V operation
H8/3062F-ZTAT
B-mask version
5 V operation
H8/3062 masked ROM
B-mask version
5 V operation
H8/3061 masked ROM
B-mask version
5 V operation
H8/3060 masked ROM
B-mask version
5 V operation
Rev. 6.00 Mar 18, 2005 page 6 of 970
REJ09B0215-0600
Model
Package (Package Code)
HD64F3062RF
HD64F3062RTE
HD64F3062RFP
HD64F3062RVF
HD64F3062RVTE
HD64F3062RVFP
HD6433062F
HD6433062TE
HD6433062FP
HD6433062VF
HD6433062VTE
HD6433062VFP
HD6433061F
HD6433061TE
HD6433061FP
HD6433061VF
HD6433061VTE
HD6433061VFP
HD6433060F
HD6433060TE
HD6433060FP
HD6433060VF
HD6433060VTE
HD6433060VFP
HD64F3064BF
HD64F3064BTE
HD64F3064BFP
HD6433064BF
HD6433064BTE
HD6433064BFP
HD64F3062BF
HD64F3062BTE
HD64F3062BFP
HD6433062BF
HD6433062BTE
HD6433062BFP
HD6433061BF
HD6433061BTE
HD6433061BFP
HD6433060BF
HD6433060BTE
HD6433060BFP
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100A)
Section 1 Overview
1.2
Block Diagram
Port 3
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
P30 /D8
P31 /D9
P32 /D10
P33 /D11
P34 /D12
P35 /D13
P36 /D14
P37 /D15
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCL*2
Figure 1.1 shows an internal block diagram.
Port 4
Address bus
Data bus (upper)
MD 1
Data bus (lower)
P53 /A 19
Port 5
MD 2
MD 0
P52 /A 18
P51 /A 17
P50 /A 16
EXTAL
*1
P26 /A 14
H8/300H CPU
P25 /A 13
Port 2
RES
RESO/FWE
P27 /A 15
Clock pulse
generator
XTAL
STBY
NMI
LWR/P66
RD/P64
AS/P63
Port 6
HWR/P65
ROM
(masked ROM or
flash memory)
P21 /A 9
P20 /A 8
P17 /A 7
P16 /A 6
P15 /A 5
Port 1
BACK/P62
P23 /A 11
P22 /A 10
Bus controller
Interrupt controller
φ/P67
P24 /A 12
BREQ/P61
WAIT/P60
P14 /A 4
P13 /A 3
P12 /A 2
RAM
P11 /A 1
CS0/P84
CS2/IRQ2/P82
CS3/IRQ1/P81
P10 /A 0
Watchdog timer
(WDT)
Port 8
ADTRG/CS1/IRQ3/P83
16-bit timer unit
IRQ0/P80
Serial communication
interface
(SCI) × 2 channels
8-bit timer unit
P95 /SCK 1 /IRQ 5
Programmable
timing pattern
controller (TPC)
P94 /SCK 0 /IRQ 4
Port 9
A/D converter
D/A converter
P93 /RxD1
P92 /RxD0
P91 /TxD 1
P90 /TxD 0
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AN4/P74
AN5/P75
DA0/AN6/P76
DA1/AN7/P77
AVSS
AVCC
VREF
TCLKA/TP0/PA0
TCLKB/TP1/PA1
Port 7
TCLKC/TIOCA0/TP2/PA2
A23/TIOCA1/TP4/PA4
TCLKD/TIOCB0/TP3/PA3
A22/TIOCB1/TP5/PA5
A21/TIOCA2/TP6/PA6
A20/TIOCB2/TP7/PA7
CS7/TMO0/TP8/PB0
CS6/TMIO1/TP9/PB1
Port A
CS5/TMO2/TP10/PB2
CS4/TMIO3/TP11/PB3
TP12/PB4
TP13/PB5
TP15/PB7
TP14/PB6
Port B
Notes: 1. Functions as RESO in the on-chip masked ROM versions, and as FWE in the on-chip flash memory versions.
2. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM B-mask version,
H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM
B-mask version have a VCL pin, and require the connection of an external capacitor.
Figure 1.1 Block Diagram
Rev. 6.00 Mar 18, 2005 page 7 of 970
REJ09B0215-0600
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Arrangement
The pin arrangement of the H8/3062 Group is shown in figures 1.2 to 1.5. Differences in the
H8/3062 Group pin arrangements are shown in table 1.2. The H8/3064F-ZTAT B-mask version,
H8/3062F-ZTAT B-mask version, H8/3064 masked ROM B-mask version, H8/3062 masked
ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM
B-mask version have a VCL pin. See section 1.5, Notes on H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 masked ROM B-mask version, H8/3062 masked
ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM
B-mask version. Except for the differences shown in table 1.2, the pin arrangements are the same.
Table 1.2
Package
FP-100B
(TFP-100B)
FP-100A
Package
FP-100B
(TFP-100B)
FP-100A
Comparison of H8/3062 Group Pin Arrangements
Pin
Number
H8/3062
H8/3061
H8/3060
H8/3064
H8/3062
H8/3062F-ZTAT
Masked ROM Masked ROM Masked ROM
F-ZTAT
F-ZTAT
R-Mask Version
Version
Version
Version
B-Mask Version B-Mask Version
1
VCC
VCC
VCC
VCC
VCL
VCC
10
FWE
RESO
RESO
RESO
FWE
FWE
3
VCC
VCC
VCC
VCC
VCL
VCL
12
FWE
RESO
RESO
RESO
FWE
FWE
Pin
Number
H8/3064
Masked ROM
B-Mask
Version
H8/3062
H8/3061
H8/3060
Masked ROM Masked ROM Masked ROM
B-Mask
B-Mask
B-Mask
Version
Version
Version
1
VCL
VCL
VCL
VCL
10
RESO
RESO
RESO
RESO
3
VCL
VCL
VCL
VCL
12
RESO
RESO
RESO
RESO
Rev. 6.00 Mar 18, 2005 page 8 of 970
REJ09B0215-0600
P52 /A 18
P51 /A 17
P50 /A 16
P27 /A 15
P26 /A 14
54
53
52
51
STBY
62
P53 /A 19
RES
63
55
NMI
64
VSS
VSS
65
56
EXTAL
66
P60 /WAIT
XTAL
67
57
VCC
68
P61 /BREQ
P63 /AS
69
58
P64 /RD
70
59
P65 /HWR
71
P67/φ
P66 /LWR
72
P62 /BACK
MD0
73
60
MD1
74
61
MD2
75
Section 1 Overview
AV CC
76
50
A13 /P25
VREF
77
49
A12 /P24
P70 /AN0
78
48
A11 /P23
P71 /AN1
79
47
A10 /P22
P72 /AN2
80
46
A9 /P21
P73 /AN3
81
45
A8 /P20
P74 /AN4
82
44
VSS
P75 /AN5
83
43
A7 /P17
P76 /AN6 /DA 0
P77 /AN7 /DA 1
84
42
A6 /P16
85
41
A5 /P15
AV SS
IRQ0 /P80
86
40
A4 /P14
39
A3 /P13
CS 3 /IRQ1/P81
88
38
A2 /P12
CS2/IRQ2/P82
89
37
A1 /P11
ADTRG/CS1/IRQ3/P83
90
36
A0 /P10
CS0/P84
91
35
VCC
87
Top view
(FP-100B, TFP-100B)
VSS
92
34
TCLKA/TP0/PA0
93
33
D15/P37
D14/P36
18
19
20
21
22
23
24
25
D1 /P41
D2 /P42
D3 /P43
VSS
D4 /P44
D5 /P45
D6 /P46
15
RxD1 /P93
17
14
RxD0 /P92
D0 /P40
13
TxD1 /P91
IRQ5 /SCK1 /P95
12
TxD0 /P90
16
11
VSS
IRQ4 /SCK0 /P94
10
D7 /P47
9
26
TP15/PB7
RESO / FWE*
100
8
D8 /P30
A20/TIOCB2/TP7/PA7
TP14/PB6
D9 /P31
27
7
28
99
TP13/PB5
98
A21/TIOCA2/TP6/PA6
6
A22/TIOCB1/TP5/PA5
TP12/PB4
D11/P33
D10/P32
5
29
CS4 /TMIO 3/TP11/PB3
97
4
A23/TIOCA1/TP4/PA4
CS5 /TMO2/TP10/PB2
30
3
96
CS6 /TMIO 1/TP9/PB1
D12/P34
TCLKD/TIOCB0/TP3/PA3
2
D13/P35
31
1
32
95
VCC
94
CS7/TMO0/TP8/PB0
TCLKB/TP1/PA1
TCLKC/TIOCA0/TP2/PA2
Note: * Functions as RESO in the on-chip masked ROM versions, and as FWE in the on-chip flash memory
versions.
Figure 1.2 Pin Arrangement of H8/3062F-ZTAT R-Mask Version,
H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
and H8/3060 Masked ROM Version
(FP-100B or TFP-100B Package, Top View)
Rev. 6.00 Mar 18, 2005 page 9 of 970
REJ09B0215-0600
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P70/AN0
VREF
AVCC
MD2
MD1
MD0
P66/LWR
P65/HWR
P64/RD
P63/AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
P67/φ
P62/BACK
P61/BREQ
P60/WAIT
VSS
P53/A19
P52/A18
P51/A17
P50/A16
P27/A15
P26/A14
P25/A13
P24/A12
Section 1 Overview
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Top view
(FP-100A)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A11 /P23
A10 /P22
A 9 /P2 1
A 8 /P2 0
V SS
A7 /P17
A6 /P16
A5 /P15
A4 /P14
A3 /P13
A2 /P12
A1 /P11
A0 /P10
V CC
D15 /P3 7
D14 /P3 6
D13 /P3 5
D12 /P3 4
D11 /P3 3
D10 /P32
A21/TIOCA2 /TP6 /PA6
A20/TIOCB2 /TP7 /PA7
V CC
CS7 /TMO0 /TP8 /PB0
CS 6 /TMIO1 /TP9 /PB1
CS 5 /TMO 2 /TP10 /PB2
CS 4 /TMIO 3 /TP11/PB3
TP12 /PB4
TP13 /PB5
TP14 /PB6
TP15 /PB 7
RESO/FWE*
VSS
TxD0 /P90
TxD1 /P91
RxD0 /P9 2
RxD1 /P9 3
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
D0 /P4 0
D1 /P41
D2 /P42
D3 /P43
V SS
D4 /P44
D5 /P4 5
D6 /P4 6
D7 /P4 7
D8 /P3 0
D9 /P3 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P80/IRQ0
P81/IRQ1/CS3
P82/IRQ2/CS2
P83/IRQ3/CS1/ADTRG
P84/CS0
VSS
PA0/TP0/TCLKA
PA1/TP1/TCLKB
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23
PA5/TP5/TIOCB1/A22
Note: * Functions as RESO in the on-chip masked ROM versions, and as FWE in the on-chip flash memory
versions.
Figure 1.3 Pin Arrangement of H8/3062F-ZTAT R-Mask Version,
H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
and H8/3060 Masked ROM Version
(FP-100A Package, Top View)
Rev. 6.00 Mar 18, 2005 page 10 of 970
REJ09B0215-0600
MD2
MD1
MD0
P66 /LWR
P65 /HWR
P64 /RD
P63 /AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
P67/φ
P62 /BACK
P61 /BREQ
P60 /WAIT
VSS
P53 /A 19
P52 /A 18
P51 /A 17
P50 /A 16
P27 /A 15
P26 /A 14
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Section 1 Overview
AV CC
76
50
P25/A13
VREF
77
49
P24/A12
P70 /AN0
78
48
P23/A11
P71 /AN1
79
47
P22/A10
P72 /AN2
80
46
P21/A9
P73 /AN3
81
45
P20/A8
P74 /AN4
82
44
VSS
P75 /AN5
83
43
P17/A7
P76 /AN6 /DA 0
84
42
P16/A6
P77 /AN7 /DA 1
85
41
P15/A5
AV SS
IRQ0 /P80
86
40
P14/A4
39
P13/A3
CS 3 /IRQ1/P81
88
38
P12/A2
CS2/IRQ2/P82
89
37
P11/A1
ADTRG/CS1/IRQ3/P83
90
36
P10/A0
CS0/P84
91
35
VCC
87
Top view
(FP-100B, TFP-100B)
VSS
92
34
TCLKA/TP0/PA0
93
33
D15/P37
D14/P36
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TxD0 /P90
TxD1 /P91
RxD0 /P92
RxD1 /P93
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
D0 /P40
D1 /P41
D2 /P42
D3 /P43
VSS
D4 /P44
D5 /P45
D6 /P46
10
FWE
VSS
D7/P47
9
26
TP15/PB7
100
8
D8/P30
A20/TIOCB2/TP7/PA7
TP14/PB6
D9/P31
27
7
28
99
TP13/PB5
98
A21/TIOCA2/TP6/PA6
6
A22/TIOCB1/TP5/PA5
TP12/PB4
D11/P33
D10/P32
5
29
CS4 /TMIO 3/TP11/PB3
97
4
A23/TIOCA1/TP4/PA4
CS5 /TMO2/TP10/PB2
30
3
96
CS6 /TMIO 1/TP9/PB1
D12/P34
TCLKD/TIOCB0/TP3/PA3
2
D13/P35
31
1
32
95
VCL*
94
CS7/TMO0/TP8/PB0
TCLKB/TP1/PA1
TCLKC/TIOCA0/TP2/PA2
1
0.1 µF
Note: * An external capacitor must be connected to the VCL pin.
Figure 1.4 Pin Arrangement of H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,
H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,
and H8/3060 Masked ROM B-Mask Version
(FP-100B or TFP-100B Package, Top View)
Rev. 6.00 Mar 18, 2005 page 11 of 970
REJ09B0215-0600
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P70/AN0
VREF
AVCC
MD2
MD1
MD0
P66/LWR
P65/HWR
P64/RD
P63/AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
P67/φ
P62/BACK
P61/BREQ
P60/WAIT
VSS
P53/A19
P52/A18
P51/A17
P50/A16
P27/A15
P26/A14
P25/A13
P24/A12
Section 1 Overview
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Top view
(FP-100A)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P23/A11
P22/A10
P21/A9
P20/A8
VSS
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
V CC
D15 /P3 7
D14 /P3 6
D13 /P3 5
D12 /P3 4
D11 /P3 3
D10 /P32
A21/TIOCA2 /TP6 /PA6
A20/TIOCB2 /TP7 /PA7
VCL*
CS7 /TMO0 /TP8 /PB0
CS 6 /TMIO1 /TP9 /PB1
CS 5 /TMO 2 /TP10 /PB2
CS 4 /TMIO 3 /TP11/PB3
TP12 /PB4
TP13 /PB5
TP14 /PB6
TP15 /PB 7
FWE
VSS
TxD0 /P90
TxD1 /P91
RxD0 /P9 2
RxD1 /P9 3
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
D0 /P4 0
D1 /P41
D2 /P42
D3 /P43
V SS
D4 /P44
D5 /P4 5
D6 /P4 6
D7 /P4 7
D8 /P3 0
D9 /P3 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P80/IRQ0
P81/IRQ1/CS3
P82/IRQ2/CS2
P83/IRQ3/CS1/ADTRG
P84/CS0
VSS
PA0/TP0/TCLKA
PA1/TP1/TCLKB
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23
PA5/TP5/TIOCB1/A22
3
0.1 µF
Note: * An external capacitor must be connected to the VCL pin.
Figure 1.5 Pin Arrangement of H8/3064F-ZTAT B-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,
H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,
and H8/3060 Masked ROM B-Mask Version
(FP-100A Package, Top View)
Rev. 6.00 Mar 18, 2005 page 12 of 970
REJ09B0215-0600
Section 1 Overview
1.3.2
Pin Functions
Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT
B-mask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask version,
H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version have a VCL
pin, and require the connection of an external capacitor.
Table 1.3
Pin Functions
Pin No.
Type
Power
Symbol
Name and Function
VCC
1*1, 35,
68
3*1, 37,
70
Input
Power: For connection to the power supply.
Connect all VCC pins to the system power
supply.
VSS
11, 22,
44, 57,
65, 92
1 *2
13, 24,
46, 59,
67, 94
3*2
Input
Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
Internal
VCL
step-down
pin
Clock
FP-100B
TFP-100B FP-100A I/O
Output Connect an external capacitor between this
pin and GND (0 V). Do not connect to VCC.
VCL
0.1 µF
XTAL
67
69
Input
For connection to a crystal resonator.
For examples of crystal resonator and
external
clock input, see section 20, Clock Pulse
Generator.
EXTAL
66
68
Input
For connection to a crystal resonator or input
of an external clock signal. For examples of
crystal resonator and external clock input, see
section 20, Clock Pulse Generator.
φ
61
63
Output System clock: Supplies the system clock to
external devices.
Rev. 6.00 Mar 18, 2005 page 13 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
Type
Symbol
Operating MD2 to
MD0
mode
control
System
control
75 to 73
77 to 75 Input
Name and Function
Modes 2 to 0: For setting the operating
mode, as follows. Inputs at these pins must
not be changed during operation.
MD2
MD1
MD0
Operating Mode
0
0
0
Setting prohibited
0
0
1
Mode 1
0
1
0
Mode 2
0
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
1
1
0
Mode 6
1
1
1
Mode 7
RES
63
65
Input
RESO
10
12
Output Reset output (On-chip masked ROM
versions): Outputs the reset signal generated
by the watchdog timer to external devices.
FWE
10
12
Input
Write enable signal (On-chip flash memory
versions): Flash memory programming
control signal
STBY
62
64
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode.
BREQ
59
61
Input
Bus request: Used by an external bus
master to request the bus right.
BACK
60
62
Output Bus request acknowledge: Indicates that
the bus has been granted to an external bus
master.
64
66
Input
17, 16,
90 to 87
19, 18, Input
92 to 89
Interrupts NMI
IRQ5
IRQ0
Address
bus
FP-100B
TFP-100B FP-100A I/O
to
Reset input: When driven low, this pin resets
the chip. This pin must be driven low at
power-up.
Nonmaskable interrupt: Requests a
nonmaskable interrupt.
Interrupt request 5 to 0: Maskable interrupt
request pins
A23 to A0 97 to 100, 99, 100, Output Address bus: Output address signals.
56 to 45, 1, 2,
43 to 36
58 to 47,
45 to 38
Rev. 6.00 Mar 18, 2005 page 14 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
FP-100B
TFP-100B FP-100A I/O
Type
Symbol
Data bus
D15 to D0 34 to 23,
21 to 18
Bus
control
CS7
36 to 25, Input/ Data bus: Bidirectional data bus
23 to 20 output
CS0
2 to 5,
88 to 91
4 to 7,
Output Chip select: Select signals for areas 7 to 0.
90 to 93
AS
69
71
Output Address strobe: Goes low to indicate valid
address output on the address bus.
RD
70
72
Output Read: Goes low to indicate reading from the
external address space.
HWR
71
73
Output High write: Goes low to indicate writing to the
external address space; indicates valid data
on the upper data bus (D15 to D8).
LWR
72
74
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data
on the lower data bus (D7 to D0).
WAIT
58
60
Input
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space.
TCLKD
to
TCLKA
96 to 93
98 to95
Input
Clock input D to A: External clock inputs
TIOCA2
to
TIOCA0
99, 97,
95
1, 99,
97
Input/ Input capture/output compare A2 to A0:
output GRA2 to GRA0 output compare or input
capture, or PWM output
TIOCB2
to
TIOCB0
100, 98, 96 2, 100,
98
Input/ Input capture/output compare B2 to B0:
output GRB2 to GRB0 output compare or input
capture
8-bit timer TMO0,
TMO2
2, 4
4, 6
Output Compare match output: Compare match
output pins
TMIO1,
TMIO3
3, 5
5, 7
Input/ Input capture input/compare match output:
output Input capture input or compare match output
pins
TCLKD
to
TCLKA
96 to 93
98 to 95 Input
16-bit
timer
to
Name and Function
Counter external clock input: These pins
input an external clock to the counters.
Rev. 6.00 Mar 18, 2005 page 15 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B FP-100A I/O
Programmable
timing
pattern
controller
(TPC)
TP15 to
TP0
9 to 2,
100 to 93
11 to 4,
2, 1,
100 to
95
Output TPC output 15 to 0: Pulse output
Serial
communication
interface
(SCI)
TxD1,
TxD0
13, 12
15, 14
Output Transmit data (channels 0, 1): SCI data
output
RxD1,
RxD0
15, 14
17, 16
Input
SCK1,
SCK0
17, 16
19, 18
Input/ Serial clock (channels 0, 1): SCI clock
output input/output
AN7 to
AN0
85 to 78
87 to 80 Input
Analog 7 to 0: Analog input pins
ADTRG
90
92
Input
A/D conversion external trigger input:
External trigger input for starting A/D
conversion
A/D
converter
Name and Function
Receive data (channels 0, 1): SCI data input
D/A
converter
DA1, DA0 85, 84
87, 86
Output Analog output: Analog output from the
D/A converter
Analog
power
supply
AVCC
76
78
Input
Power supply pin for the A/D and D/A
converters. Connect to the system power
supply when not using the A/D and D/A
converters.
AVSS
86
88
Input
Ground pin for the A/D and D/A converters.
Connect to system ground (0 V).
VREF
77
79
Input
Reference voltage input pin for the A/D and
D/A converters. Connect to the system power
supply when not using the A/D and
D/A converters.
Rev. 6.00 Mar 18, 2005 page 16 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
FP-100B
TFP-100B FP-100A I/O
Type
Symbol
I/O ports
P17 to
P10
43 to 36
45 to 38 Input/ Port 1: Eight input/output pins. The direction
output of each pin can be selected in the port 1 data
direction register (P1DDR).
P27 to
P20
52 to 45
54 to 47 Input/ Port 2: Eight input/output pins. The direction
output of each pin can be selected in the port 2 data
direction register (P2DDR).
P37 to
P30
34 to 27
36 to 29 Input/ Port 3: Eight input/output pins. The direction
output of each pin can be selected in the port 3 data
direction register (P3DDR).
P47 to
P40
26 to 23,
21 to 18
28 to 25, Input/ Port 4: Eight input/output pins. The direction
23 to 20 output of each pin can be selected in the port 4 data
direction register (P4DDR).
P53 to
P50
56 to 53
58 to 55 Input/ Port 5: Four input/output pins. The direction
output of each pin can be selected in the port 5 data
direction register (P5DDR).
P67 to
P60
61,
72 to 69,
60 to 58
63,
Input/ Port 6: Eight input/output pins. The direction
74 to 71, output of each pin can be selected in the port 6 data
62 to 60
direction register (P6DDR).
P77 to
P70
85 to 78
87 to 80 Input
P84 to
P80
91 to 87
93 to 89 Input/ Port 8: Five input/output pins. The direction of
output each pin can be selected in the port 8 data
direction register (P8DDR).
P95 to
P90
17 to 12
19 to 14 Input/ Port 9: Six input/output pins. The direction of
output each pin can be selected in the port 9 data
direction register (P9DDR).
PA7 to
PA0
100 to 93 2, 1,
100 to
95
Input/ Port A: Eight input/output pins. The direction
output of each pin can be selected in the port A data
direction register (PADDR).
PB7 to
PB0
9 to 2
Input/ Port B: Eight input/output pins. The direction
output of each pin can be selected in the port B data
direction register (PBDDR).
11 to 4
Name and Function
Port 7: Eight input pins
Notes: 1. In the H8/3062F-ZTAT R-mask version, H8/3062 masked ROM version, H8/3061
masked ROM version, and H8/3060 masked ROM version
2. In the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064
masked ROM B-mask version, H8/3062 masked ROM B-mask version, H8/3061
masked ROM B-mask version, and H8/3060 masked ROM B-mask version.
Rev. 6.00 Mar 18, 2005 page 17 of 970
REJ09B0215-0600
Section 1 Overview
1.3.3
Pin Assignments in Each Mode
Table 1.4 lists the pin assignments in each mode.
Table 1.4
Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)
Pin No.
FP-100B
TFP-100B
Pin Name
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
1
3
4
vCC (vCL)*
4
vCC (vCL)*
4
vCC (vCL)*
4
vCC (vCL)*
4
vCC (vCL)*
4
vCC (vCL)*
vCC (vCL)*
2
4
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0/CS7
PB0/TP8/
TMO0
PB0/TP8/
TMO0
3
5
PB1/TP9/
PB1/TP9/
PB1/TP9/
PB1/TP9/
PB1/TP9/
PB1/TP9/
TMIO1/CS6 TMIO1/CS6 TMIO1/CS6 TMIO1/CS6 TMIO1/CS6 TMIO1
PB1/TP9/
TMIO1
4
6
PB2/TP10/
TMO2/CS5
PB2/TP10/
TMO2
PB2/TP10/
TMO2
5
7
PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/
TMIO3/CS4 TMIO3/CS4 TMIO3/CS4 TMIO3/CS4 TMIO3/CS4 TMIO3
PB3/TP11/
TMIO3
6
8
PB4/TP12
PB4/TP12
PB4/TP12
PB4/TP12
PB4/TP12
PB4/TP12
PB4/TP12
7
9
PB5/TP13
PB5/TP13
PB5/TP13
PB5/TP13
PB5/TP13
PB5/TP13
PB5/TP13
8
10
PB6/TP14
PB6/TP14
PB6/TP14
PB6/TP14
PB6/TP14
PB6/TP14
PB6/TP14
9
11
PB7/TP15
PB7/TP15
PB7/TP15
PB7/TP15
PB7/TP15
PB7/TP15
PB7/TP15
10
12
RESO/
RESO/
RESO/
RESO/
RESO/
RESO/
RESO/
FWE*3
PB2/TP10/
TMO2/CS5
FWE*3
PB2/TP10/
TMO2/CS5
FWE*3
PB2/TP10/
TMO2/CS5
FWE*3
PB2/TP10/
TMO2/CS5
FWE*3
FWE*3
4
FWE*3
11
13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12
14
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
13
15
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
14
16
P92/RxD0
P92/RxD0
P92/RxD0
P92/RxD0
P92/RxD0
P92/RxD0
P92/RxD0
15
17
P93/RxD1
P93/RxD1
P93/RxD1
P93/RxD1
P93/RxD1
P93/RxD1
P93/RxD1
16
18
17
19
P94 /SCK0/ P94 /SCK0/ P94 /SCK0/ P94 /SCK0/ P94 /SCK0/ P94 /SCK0/ P94 /SCK0/
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
P95 /SCK1/ P95 /SCK1/ P95 /SCK1/ P95 /SCK1/ P95 /SCK1/ P95 /SCK1/ P95 /SCK1/
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
20
P40/D0 *1
P40/D0 *2
P40/D0 *1
P40/D0 *2
P40/D0 *1
P40
P40
19
21
1
P41/D1 *
2
P41/D1 *
1
P41/D1 *
2
P41/D1 *
1
P41/D1 *
P41
P41
20
22
P42/D2 *1
P42/D2 *2
P42/D2 *1
P42/D2 *2
P42/D2 *1
P42
P42
21
23
P43/D3 *1
P43/D3 *2
P43/D3 *1
P43/D3 *2
P43/D3 *1
P43
P43
22
24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
25
P44/D4 *1
P44/D4 *2
P44/D4 *1
P44/D4 *2
P44/D4 *1
P44
P44
18
23
Rev. 6.00 Mar 18, 2005 page 18 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
FP-100B
TFP-100B
Pin Name
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
24
26
1
P45/D5 *
2
P45/D5 *
1
P45/D5 *
2
P45/D5 *
1
P45/D5 *
P45
P45
25
27
P46/D6 *
P46/D6 *
P46/D6 *
P46/D6 *
P46/D6 *
1
P46
P46
26
28
1
P47/D7 *
2
P47/D7 *
1
P47/D7 *
2
P47/D7 *
1
P47/D7 *
P47
P47
27
29
D8
D8
D8
D8
D8
P30
P30
28
30
D9
D9
D9
D9
D9
P31
P31
29
31
D10
D10
D10
D10
D10
P32
P32
30
32
D11
D11
D11
D11
D11
P33
P33
31
33
D12
D12
D12
D12
D12
P34
P34
32
34
D13
D13
D13
D13
D13
P35
P35
33
35
D14
D14
D14
D14
D14
P36
P36
34
36
D15
D15
D15
D15
D15
P37
P37
35
37
VCC
VCC
VCC
VCC
VCC
VCC
VCC
36
38
A0
A0
A0
A0
P10/A0
P10
P10
37
39
A1
A1
A1
A1
P11/A1
P11
P11
38
40
A2
A2
A2
A2
P12/A2
P12
P12
39
41
A3
A3
A3
A3
P13/A3
P13
P13
40
42
A4
A4
A4
A4
P14/A4
P14
P14
41
43
A5
A5
A5
A5
P15/A5
P15
P15
42
44
A6
A6
A6
A6
P16/A6
P16
P16
43
45
A7
A7
A7
A7
P17/A7
P17
P17
44
46
VSS
VSS
VSS
VSS
VSS
VSS
VSS
45
47
A8
A8
A8
A8
P20/A8
P20
P20
46
48
A9
A9
A9
A9
P21/A9
P21
P21
47
49
A10
A10
A10
A10
P22/A10
P22
P22
48
50
A11
A11
A11
A11
P23/A11
P23
P23
49
51
A12
A12
A12
A12
P24/A12
P24
P24
50
52
A13
A13
A13
A13
P25/A13
P25
P25
51
53
A14
A14
A14
A14
P26/A14
P26
P26
52
54
A15
A15
A15
A15
P27/A15
P27
P27
53
55
A16
A16
A16
A16
P50/A16
P50
P50
54
56
A17
A17
A17
A17
P51/A17
P51
P51
55
57
A18
A18
A18
A18
P52/A18
P52
P52
56
58
A19
A19
A19
A19
P53/A19
P53
P53
1
2
1
2
Rev. 6.00 Mar 18, 2005 page 19 of 970
REJ09B0215-0600
Section 1 Overview
Pin No.
Pin Name
FP-100B
TFP-100B
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
57
59
VSS
VSS
VSS
VSS
VSS
VSS
VSS
58
60
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
P60
P60
59
61
P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61
P61
60
62
P62/BACK
P62/BACK
P62/BACK
P62/BACK
P62/BACK
P62
P62
61
63
φ
φ
φ
φ
P67/φ
P67/φ
P67/φ
62
64
63
65
STBY
RES
STBY
RES
STBY
RES
STBY
RES
STBY
RES
STBY
RES
STBY
RES
64
66
NMI
NMI
NMI
NMI
NMI
NMI
NMI
65
67
VSS
VSS
VSS
VSS
VSS
VSS
VSS
66
68
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
67
69
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
68
70
VCC
VCC
69
71
P63
P63
70
72
P64
P64
71
73
P65
P65
72
P66
P66
VCC
VCC
VCC
VCC
VCC
74
AS
RD
HWR
LWR
AS
RD
HWR
LWR
AS
RD
HWR
LWR
AS
RD
HWR
LWR
AS
RD
HWR
LWR
73
75
MD0
MD0
MD0
MD0
MD0
MD0
MD0
74
76
MD1
MD1
MD1
MD1
MD1
MD1
MD1
75
77
MD2
MD2
MD2
MD2
MD2
MD2
MD2
76
78
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
77
79
VREF
VREF
VREF
VREF
VREF
VREF
VREF
78
80
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
79
81
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
80
82
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
81
83
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
82
84
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
83
85
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
84
86
P76/AN6/DA P76/AN6/DA P76/AN6/DA P76/AN6/DA P76/AN6/DA P76/AN6/DA P76/AN6/DA
0
0
0
0
0
0
0
85
87
P77/AN7/DA P77/AN7/DA P77/AN7/DA P77/AN7/DA P77/AN7/DA P77/AN7/DA P77/AN7/DA
1
1
1
1
1
1
1
86
88
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
87
89
P80/IRQ0
P80/IRQ0
P80/IRQ0
P80/IRQ0
P80/IRQ0
P80/IRQ0
P80/IRQ0
88
90
CS3
CS3
CS3
CS3
CS3
P81/IRQ1/
P81/IRQ1/
Rev. 6.00 Mar 18, 2005 page 20 of 970
REJ09B0215-0600
P81/IRQ1/
P81/IRQ1/
P81/IRQ1/
P81/IRQ1
P81/IRQ1
Section 1 Overview
Pin No.
FP-100B
TFP-100B
FP-100A
89
91
90
92
Pin Name
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
P82/IRQ2/
P82/IRQ2/
P82/IRQ2/
P82/IRQ2/
P82/IRQ2/
P82/IRQ2
P82/IRQ2
CS2
CS2
CS2
CS2
CS2
91
93
P83/IRQ3/ P83/IRQ3/ P83/IRQ3/ P83/IRQ3/ P83/IRQ3/ P83/IRQ3/ P83/IRQ3/
CS1/
CS1/
CS1/
CS1/
CS1/
ADTRG ADTRG
ADTRG ADTRG ADTRG ADTRG ADTRG
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84
P84
92
94
VSS
VSS
VSS
VSS
VSS
VSS
VSS
93
95
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
PA0/TP0/
TCLKA
94
96
PA1/TP1/
TCLKB
PA1/TP1/
TCLKB
PA1/TP1
/TCLKB
PA1/TP1/
TCLKB
PA1/TP1/
TCLKB
PA1/TP1/
TCLKB
PA1/TP1/
TCLKB
95
97
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
96
98
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
97
99
PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1
PA4/TP4/
PA4/TP4/
PA4/TP4/
PA4/TP4/
TIOCA1/A23 TIOCA1/A23 TIOCA1/A23 TIOCA1
PA4/TP4/
TIOCA1
98
100
PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1
PA5/TP5/
PA5/TP5/
PA5/TP5/
PA5/TP5/
TIOCB1/A22 TIOCB1/A22 TIOCB1/A22 TIOCB1
PA5/TP5/
TIOCB1
99
1
PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2
PA6/TP6/
PA6/TP6/
PA6/TP6/
PA6/TP6/
TIOCA2/A21 TIOCA2/A21 TIOCA2/A21 TIOCA2
PA6/TP6/
TIOCA2
100
2
PA7/TP7/
TIOCB2
PA7/TP7/
TIOCB2
A20
PA7/TP7/
TIOCB2
A20
PA7/TP7/
PA7/TP7/
TIOCB2/A20 TIOCB2
Notes: 1. In modes 1, 3, and 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after
a reset, but they can be changed by software.
2. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
3. Functions as RESO in the on-chip masked ROM versions, and as FWE in the on-chip
flash memory versions. Functions as the programming control signal in modes 5 and 7.
4. Functions as VCC in the H8/3062F-ZTAT R-mask version, H8/3062 masked ROM
version, H8/3061 masked ROM version, and H8/3060 masked ROM version. In the
H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked
ROM B-mask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM
B-mask version, and H8/3060 masked ROM B-mask version, this pin functions as VCL.
Rev. 6.00 Mar 18, 2005 page 21 of 970
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Section 1 Overview
1.4
Notes on H8/3062F-ZTAT R-Mask Version
Points to be noted when using the H8/3062F-ZTAT R-mask version are given below.
1.4.1
Pin Arrangement
The H8/3062F-ZTAT R-mask version has the same pin arrangement as the H8/3062 masked ROM
version, H8/3061 masked ROM version, and H8/3060 masked ROM version. Except for the VCL
pin, it also has the same pin arrangement as the H8/3062F-ZTAT B-mask version, H8/3064FZTAT B-mask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask
version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version.
1.4.2
Differences between H8/3062F-ZTAT R-Mask Version and H8/3064F-ZTAT
B-Mask Version
Table 1.5 shows the differences between the H8/3062F-ZTAT R-mask version and the on-chip
masked ROM versions.
Table 1.5
Differences between H8/3062F-ZTAT R-Mask Version and On-Chip Masked
ROM Versions
On-Chip Flash Memory Versions
Item
HD64F3062R
ROM
Address
output
functions
ADRCR
register
(H'FEE01E)
On-Chip Masked ROM Versions
HD6433062
HD6433061
HD6433060
128 kbytes
masked ROM
96 kbytes
masked ROM
64 kbytes
masked ROM
Choice of address update mode 1 (compatible with previous H8/300H Series) or
address update mode 2
See the section on the bus controller for details.
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ADRCTL
See the section on the bus controller for the bit function.
The address output functions and ADRCR register specification of the H8/3064F-ZTAT B-mask
version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM B-mask version, H8/3062
masked ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked
ROM B-mask version are the same as for the H8/3062F-ZTAT R-mask version.
Rev. 6.00 Mar 18, 2005 page 22 of 970
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Section 1 Overview
1.5
Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT
B-Mask Version, H8/3064 Masked ROM B-Mask Version, H8/3062
Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask
Version, and H8/3060 Masked ROM B-Mask Version
The H8/3062 Group includes one model with 128-kbyte on-chip flash memory, the H8/3062FZTAT B-mask version developed on the basis of the H8/3062F-ZTAT R-mask version, and one
model with 256-kbyte large-capacity on-chip flash memory, the H8/3064F-ZTAT B-mask version.
The H8/3062F-ZTAT B-mask version and H8/3064F-ZTAT B-mask version have the following
features:
1. Low power consumption
2. Functional compatibility with the H8/3062F-ZTAT R-mask version
3. Pin arrangement compatibility (except for the VCL pin)
Points to be noted when using the H8/3062F-ZTAT B-mask version or H8/3064F-ZTAT B-mask
version are given below.
1.5.1
Pin Arrangement
Except for the VCL pin, the H8/3062F-ZTAT R-mask version has the same pin arrangement as the
H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM Bmask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version,
and H8/3060 masked ROM B-mask version.
Rev. 6.00 Mar 18, 2005 page 23 of 970
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Section 1 Overview
1.5.2
Product Type Names and Markings
Table 1.6 shows the product type names and differences in sample markings for the H8/3062FZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version.
Table 1.6
TFP-100
Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask
Version, and H8/3064F-ZTAT B-Mask Version Markings
Product
type name
Sample
markings
H8/3062F-ZTAT
R-Mask Version
H8/3062F-ZTAT
B-Mask Version
H8/3064F-ZTAT
B-Mask Version
HD64F3062RTE
HD64F3062BTE
HD64F3064BTE
H8/3062
R
HD
64F3062TE20
JAPAN
FP-100B
Product
type name
Sample
markings
HD64F3062RF
H8/3062
R
HD
64F3062F20
JAPAN
FP-100A
Product
type name
Sample
markings
H8/3062
B
HD
64F3062TE25
JAPAN
H8/3064
B
HD
64F3064TE25
JAPAN
“B” is printed above
the type name.
“B” is printed above
the type name.
HD64F3062BF
HD64F3064BF
H8/3062
B
HD
64F3062F25
JAPAN
H8/3064
B
HD
64F3064F25
JAPAN
“B” is printed above
the type name.
“B” is printed above
the type name.
HD64F3062RFP
HD64F3062BFP
HD64F3064BFP
H8/3062
R
HD
64F3062FP20
H8/3062
B
HD
64F3062FP25
H8/3064
B
HD
64F3064FP25
JAPAN
JAPAN
“B” is printed above
the type name.
Rev. 6.00 Mar 18, 2005 page 24 of 970
REJ09B0215-0600
JAPAN
“B” is printed above
the type name.
Section 1 Overview
1.5.3
VCL Pin
The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip masked
ROM B-mask versions have a VCL (internal step-down) pin, to which a 0.1 µF internal voltage
stabilization capacitor must be connected.
The method of connecting the external capacitor is shown in figure 1.6.
Do not connect the VCC power supply to the VCL pin (Connect the VCC power supply to other VCC
pins as usual). Note that the VCL output pin occupies the same location as a VCC pin in the
H8/3062F-ZTAT R-mask version and on-chip masked ROM versions.
VCC power
supply
External
capacitor
0.1 µF
VCL
VCC
H8/3062F-ZTAT B-mask version,
H8/3064F-ZTAT B-mask version,
H8/3064 masked ROM B-mask version,
H8/3062 masked ROM B-mask version,
H8/3061 masked ROM B-mask version,
H8/3060 masked ROM B-mask version
(5 V model)
H8/3062F-ZTAT R-mask
version,
H8/3062 masked ROM version,
H8/3061 masked ROM version,
H8/3060 masked ROM version
Do not connect the VCC power supply to the VCL
pin (Connect the VCC power supply to other VCC
pins as usual).
Place the capacitor close to the pin.
These versions have a VCC power supply
pin in the same pin position as a VCC pin in
the H8/3062F-ZTAT B-mask version and
H8/3064F-ZTAT B-mask version.
Figure 1.6 H8/3062F-ZTAT B-Mask Version, H8/3064F-ZTAT B-Mask Version, and
On-Chip Masked ROM B-Mask Versions
Rev. 6.00 Mar 18, 2005 page 25 of 970
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Section 1 Overview
1.5.4
Notes on Changeover to On-Chip Masked ROM Versions and On-Chip Masked
ROM B-Mask Versions
(1) Care is required when changing from the H8/3062F-ZTAT B-mask version with on-chip flash
memory to a model with on-chip masked ROM.
An external capacitor must be connected to the VCL pin of the H8/3062F-ZTAT B-mask
version (5 V model). This VCL pin occupies the same location as a VCC pin in the on-chip
masked ROM versions. Changeover to a masked ROM version must therefore be taken into
account when undertaking pattern design, etc., in the board design stage.
(2) When changing from the H8/3062F-ZTAT B-mask version with on-chip flash memory to the
on-chip masked ROM B-mask version, note (1) above does not need to be considered because
the VCL pin is assigned to the same location in both versions. It does not need to be considered
either when changing from the H8/3064F-ZTAT B-mask version to the on-chip masked ROM
B-mask version.
H8/3062 Group chip
VCC power
supply
VCC pin
VCL pin
← Land pattern for on-chip masked ROM versions
(0 Ω resistance mounted)
← Land pattern for H8/3062F-ZTAT B-mask version
(0.1 µF capacitor mounted)
Figure 1.7 Example of Board Pattern Providing for External Capacitor
Rev. 6.00 Mar 18, 2005 page 26 of 970
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Section 1 Overview
1.6
Setting Oscillation Settling Wait Time
When software standby mode is used, after exiting software standby mode a wait period must be
provided to allow the clock to stabilize. Select the length of time for which the CPU and
peripheral functions are to wait by setting bits STS2 to STS0 in the system control register
(SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the
operating frequency of the chip.
For the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip masked
ROM B-mask versions ensure that the oscillation settling wait time is at least 0.1 ms when
operating on an external clock.
For setting details, see section 21.4.3, Selection of Waiting Time for Exit from Software Standby
Mode.
1.7
Caution on Crystal Resonator Connection
The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip masked
ROM B-mask versions support an operating frequency of up to 25 MHz. If a crystal resonator
with a frequency higher than 20 MHz is connected, attention must be paid to circuit constants such
as external load capacitance values. For details see section 20.2.1, Connecting a Crystal Resonator.
Rev. 6.00 Mar 18, 2005 page 27 of 970
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Section 1 Overview
Rev. 6.00 Mar 18, 2005 page 28 of 970
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Section 2 CPU
Section 2 CPU
2.1
Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1
Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs.
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• 64 basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, or @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8, PC) or @(d:16, PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte linear address space
• High-speed operation
 All frequently-used instructions execute in two to four states
 Maximum clock frequency:
20 MHz (H8/3062F-ZTAT R-mask version, H8/3062 masked ROM version, H8/3061
masked ROM version, H8/3060 masked ROM version)
Rev. 6.00 Mar 18, 2005 page 29 of 970
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Section 2 CPU
25 MHz (H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064
masked ROM B-mask version, H8/3062 masked ROM B-mask version, H8/3061 masked
ROM B-mask version, and H8/3060 masked ROM B-mask version)
 8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 MHz)
 8 × 8-bit register-register multiply:
700 ns@20 MHz (560 ns@25 MHz)
 16 ÷ 8-bit register-register divide:
700 ns@20 MHz (560 ns@25 MHz)
 16 × 16-bit register-register multiply:
1.1 µs@20 MHz (0.88 µs@25 MHz)
 32 ÷ 16-bit register-register divide:
1.1 µs@20 MHz (0.88 µs@25 MHz)
• Two CPU operating modes
 Normal mode
 Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
 Advanced mode supports a maximum 16-Mbyte address space.
 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
 Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
 Signed multiply/divide instructions and other instructions have been added.
Rev. 6.00 Mar 18, 2005 page 30 of 970
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Section 2 CPU
2.2
CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.
Normal mode
Maximum 64 kbytes, program
and data areas combined.
Advanced mode
Maximum 16 Mbytes, program
and data areas combined.
CPU operating modes
Figure 2.1 CPU Operating Modes
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Section 2 CPU
2.3
Address Space
Figure 2.2 shows a simple memory map for the H8/3062 Group. The H8/300H CPU can address a
linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in
advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'0000
H'00000
H'000000
H'FFFF
H'FFFFF
H'FFFFFF
a. 1-Mbyte mode
Normal mode
b. 16-Mbyte mode
Advanced mode
Figure 2.2 Memory Map
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Section 2 CPU
2.4
Register Configuration
2.4.1
Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
R7H
R7L
(SP)
E7
ER7
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP : Stack pointer
PC : Program counter
CCR : Condition code register
I
: Interrupt mask bit
UI : User bit or interrupt mask bit
H
: Half-carry flag
U
: User bit
N
: Negative flag
Z
: Zero flag
V
: Overflow flag
C
: Carry flag
Figure 2.3 CPU Registers
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Section 2 CPU
2.4.2
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers
(extended registers)
E0 to E7
RH registers
R0H to R7H
ER registers
ER0 to ER7
R registers
R0 to R7
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.5 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. When an
instruction is fetched, the least significant PC bit is regarded as 0.
Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including the interrupt mask bit (I)
and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
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Section 2 CPU
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the
sign bit.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and
cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4
Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must
therefore be initialized by an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
Data Type
General
Register
1-bit data
RnH
7 6 5 4 3 2 1 0
1-bit data
RnL
Don’t care
4-bit BCD data
RnH
Upper digit Lower digit
4-bit BCD data
RnL
Don’t care
Byte data
RnH
Data Format
7
0
Don’t care
7
7
4 3
0
Don’t care
7
7
RnL
4 3
0
Upper digit Lower digit
0
Don’t care
MSB
Byte data
0
7 6 5 4 3 2 1 0
LSB
7
0
MSB
LSB
Don’t care
Legend:
RnH : General register RH
RnL : General register RL
Figure 2.6 General Register Data Formats
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Section 2 CPU
Data Type
General
Register
Word data
Rn
Word data
Data Format
15
0
MSB
LSB
15
0
MSB
LSB
En
31
16 15
0
Longword data ERn
MSB
LSB
Legend:
ERn : General register
En : General register E
Rn : General register R
MSB : Most significant bit
LSB : Least significant bit
Figure 2.7 General Register Data Formats
2.5.2
Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
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Section 2 CPU
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
Address 2N
2
1
0
LSB
Address 2M + 1
Longword data
3
LSB
MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
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Section 2 CPU
2.6
Instruction Set
2.6.1
Instruction Set Overview
The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.
Table 2.1
Instruction Classification
Function
Instruction
Types
Data transfer
MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*2
5
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,
EXTU
18
Logic operations
AND, OR, XOR, NOT
4
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
14
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
Bcc*3, JMP, BSR, JSR, RTS
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
9
Block data transfer
EEPMOV
1
Total 64 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3062 Group.
3. Bcc is a generic branching instruction.
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Section 2 CPU
2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2
Instructions and Addressing Modes
@ (d:24, ERn)
@ERn+/@–ERn
@aa:8
@aa:16
@aa:24
BWL
BWL
BWL
BWL
B
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
MOVFPE,
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
WL
BWL
—
—
—
—
—
—
—
—
—
—
—
ADDX, SUBX
B
B
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS
—
L
—
—
—
—
—
—
—
—
—
—
—
INC, DEC
—
BWL
—
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
—
MULXU,
—
BW
—
—
—
—
—
—
—
—
—
—
—
NEG
—
BWL
—
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
@ (d:16, ERn)
BWL
—
MOV
@@aa:8
@ERn
Data
transfer
Instruction
@ (d:16, PC)
Rn
BWL
POP, PUSH
Function
@(d:8, PC)
#xx
Addressing Modes
MOVTPE
Arithmetic
operations
ADD, CMP
SUB
MULXS,
DIVXU,
DIVXS
Logic
operations
AND, OR, XOR
—
BWL
—
—
—
—
—
—
—
—
—
—
—
NOT
—
BWL
—
—
—
—
—
—
—
—
—
—
—
Shift instructions
—
BWL
—
—
—
—
—
—
—
—
—
—
—
Bit manipulation
—
B
B
—
—
—
B
—
—
—
—
—
—
Branch
Bcc, BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
JMP, JSR
—
—
—
—
—
—
—
—
—
—
RTS
—
—
—
—
—
—
—
—
—
—
TRAPA
—
—
—
—
—
—
—
—
—
—
—
—
RTE
—
—
—
—
—
—
—
—
—
—
—
—
SLEEP
—
—
—
—
—
—
—
—
—
—
—
—
LDC
B
B
W
W
W
W
—
W
W
—
—
—
STC
—
B
W
W
W
W
—
W
W
—
—
—
—
ANDC, ORC,
XORC
B
—
—
—
—
—
—
—
—
—
—
—
—
NOP
—
—
—
—
—
—
—
—
—
—
—
—
Block data transfer
—
—
—
—
—
—
—
—
—
—
—
—
System
control
—
BW
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Section 2 CPU
2.6.3
Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)*
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Rd
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in the H8/3062 Group.
MOVTPE
B
Rs → (EAs)
Cannot be used in the H8/3062 Group.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn,
@–SP.
Note: * Size refers to the operand size.
B : Byte
W : Word
L : Longword
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Section 2 CPU
Table 2.4
Arithmetic Operation Instructions
Instruction
Size*
Function
ADD,SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from data in a general register. Use the SUBX or
ADD instruction.)
ADDX,
SUBX
B
INC,
DEC
B/W/L
ADDS,
SUBS
L
DAA,
DAS
B
MULXU
B/W
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two
general registers, or on immediate data and data in a general register.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
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Section 2 CPU
Instruction
Size*
Function
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
EXTS
W/L
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword
data, by extending the sign bit.
EXTU
W/L
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword
data, by padding with zeros.
Note: * Size refers to the operand size.
B : Byte
W : Word
L : Longword
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Section 2 CPU
Table 2.5
Logic Operation Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ Rd → Rd
Takes the one’s complement (logical complement) of general register
contents.
Note: * Size refers to the operand size.
B : Byte
W : Word
L : Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL,
SHAR
B/W/L
Rd (shift) → Rd
SHLL,
SHLR
B/W/L
ROTL,
ROTR
B/W/L
ROTXL,
ROTXR
B/W/L
Performs an arithmetic shift on general register contents.
Rd (shift) → Rd
Performs a logical shift on general register contents.
Rd (rotate) → Rd
Rotates general register contents.
Rd (rotate) → Rd
Rotates general register contents, including the carry bit.
Note: * Size refers to the operand size.
B : Byte
W : Word
L : Longword
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower 3 bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIAND
B
C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Instruction
Size*
Function
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIOR
B
C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIXOR
B
C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
The bit number is specified by 3-bit immediate data.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
The bit number is specified by 3-bit immediate data.
BIST
B
C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B : Byte
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Section 2 CPU
Table 2.8
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to a specified address if address specified condition is met.
The branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
Bcc (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine.
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to the power-down state.
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data
is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC
B
NOP
—
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B : Byte
W : Word
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Section 2 CPU
Table 2.10 Block Transfer Instruction
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Block transfer instruction. This instruction transfers the number of data
bytes specified by R4L or R4, starting from the address indicated by ER5,
to the location starting at the address indicated by ER6. At the end of the
transfer, the next instruction is executed.
2.6.4
Basic Instruction Formats
The H8/300H instructions consist of 2-byte (word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: 8, 16, or 32 bits specifying immediate data, an absolute address, or
a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits
are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
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Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA (disp)
Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:8
Figure 2.9 Instruction Formats
2.6.5
Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
Step
Description
1
Read
Read one data byte at the specified address
2
Modify
Modify one bit in the data byte
3
Write
Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47, P46: Input pins
P45 – P40: Output pins
The intended purpose of this BCLR instruction is to switch P40 from output to input.
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Before Execution of BCLR Instruction
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
DDR
0
0
1
1
1
1
1
1
Execution of BCLR Instruction
BCLR #0, P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
DDR
1
1
1
1
1
1
1
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
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2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8, PC)/@(d:16, PC)
8
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2. Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
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4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5. Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible
address ranges.
Table 2.12 Absolute Address Access Ranges
Absolute
Address
1-Mbyte Modes
16-Mbyte Modes
8 bits (@aa:8)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
16 bits (@aa:16)
H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)
24 bits (@aa:24)
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
6. Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
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7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2
Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
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4
3
2
r
r
r
op
r
Register indirect with pre-decrement
@–ERn
op
Register indirect with post-increment
@ERn+
Register indirect with post-increment
or pre-decrement
op
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
op
Register indirect (@ERn)
rm rn
Register direct (Rn)
1
op
Addressing Mode and
Instruction Format
No.
31
31
1 for a byte operand,
2 for a word operand,
4 for a longword operand
1, 2, or 4
General register contents
1, 2, or 4
General register contents
disp
General register contents
General register contents
Sign extension
31
31
Effective Address Calculation
0
0
0
0
23
23
23
23
Operand is general
register contents
Effective Address
0
0
0
0
Section 2 CPU
Table 2.13 Effective Address Calculation
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7
6
5
No.
abs
abs
abs
IMM
op
disp
Program-counter relative
@(d:8, PC) or @(d:16, PC)
op
Immediate
#xx:8, #xx:16, or #xx:32
op
@aa:24
op
@aa:16
op
Absolute address
@aa:8
Addressing Mode and
Instruction Format
disp
PC contents
Sign
extension
23
Effective Address Calculation
0
16 15
H'FFFF
8 7
23
Operand is immediate data
23
Sign
extension
23
23
Effective Address
0
0
0
0
Section 2 CPU
Memory indirect @@aa:8
8
abs
abs
Legend:
r, rm, rn : Register field
op
: Operation field
disp
: Displacement
IMM
: Immediate data
abs
: Absolute address
op
Advanced mode
op
Normal mode
Addressing Mode and
Instruction Format
No.
31
8 7
abs
0
H'0000
8 7
abs
0
0
15
0
Memory contents
H'0000
Memory contents
23
23
Effective Address Calculation
23
23 16 15
H'00
Effective Address
0
0
Section 2 CPU
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Section 2 CPU
2.8
Processing States
2.8.1
Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing
states. Figure 2.13 indicates the state transitions.
Processing states
Program execution state
The CPU executes program instructions in sequence.
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception.
Bus-released state
The external bus has been released in response to a bus request
signal from a bus master other than the CPU.
Reset state
The CPU and all on-chip supporting modules are initialized and halted.
Sleep mode
Power-down state
The CPU is halted to conserve power.
Software standby mode
Hardware standby mode
Figure 2.11 Processing States
2.8.2
Program Execution State
In this state the CPU executes program instructions in normal sequence.
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2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU refers to the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority
Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately when RES changes
from low to high
Interrupt
End of instruction execution
or end of exception
handling*
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Trap instruction
When TRAPA instruction is
executed
Exception handling starts when a
trap (TRAPA) instruction is
executed
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
Reset
External interrupts
Exception
sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2.12 Classification of Exception Sources
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Bus request
End of bus release
Program execution state
End of bus
release
Bus
request
Exception
handling source
Bus-released state
End of
exception
handling
Interrupt source
Exception-handling state
NMI, IRQ 0 , IRQ 1,
or IRQ 2 interrupt
SLEEP
instruction
with SSBY = 0
Sleep mode
SLEEP instruction
with SSBY = 1
Software standby mode
RES = "High"
Reset state
*1
STBY="High", RES ="Low"
Hardware standby mode
*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
2.8.4
Exception Handling Operation
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
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Section 2 CPU
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
SP–4
SP (ER7)
SP–3
SP+1
SP–2
SP+2
SP–1
SP+3
SP (ER7)
Stack area
Before exception
handling starts
CCR
PC
SP+4
Even
address
Pushed on stack
After exception
handling ends
Legend:
CCR: Condition code register
SP:
Stack pointer
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
2.8.5
Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU is an external bus master. While the bus is released, the CPU
halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6,
Bus Arbiter.
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2.8.6
Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 11,
Watchdog Timer.
2.8.7
Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 21, Power-Down State.
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2.9
Basic Operational Timing
2.9.1
Overview
The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2
On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states.
Bus cycle
T1 state
T2 state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.15 On-Chip Memory Access Cycle
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T1
T2
φ
Address bus
AS , RD, HWR , LWR
Address
High
High impedance
D15 to D0
Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
Bus cycle
T1 state
T2 state
T3 state
φ
Address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
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T1
T2
T3
φ
Address bus
AS , RD, HWR , LWR
Address
High
High impedance
D15 to D0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4
Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed
in two or three states. For details see section 6, Bus Controller.
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8/3062 Group has seven operating modes (modes 1 to 7) that are selected by the mode pins
(MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address
space and the initial bus mode.
Table 3.1
Operating Mode Selection
Description
Operating
Mode
MD2
Mode Pins
MD1
MD0
Address Space
Initial Bus On-Chip
Mode*1
ROM
On-Chip
RAM
—
0
0
0
Setting prohibited
Mode 1
0
0
1
Expanded mode
Setting
Setting
Setting
prohibited prohibited prohibited
8 bits
Disabled Enabled*2
Mode 2
0
1
0
Expanded mode
16 bits
Disabled
Mode 3
0
1
1
Expanded mode
8 bits
Disabled
Mode 4
1
0
0
Expanded mode
16 bits
Disabled
Mode 5
1
0
1
Expanded mode
8 bits
Enabled
Enabled*2
Enabled*2
Mode 6
1
1
0
Single-chip normal mode
—
Enabled
Enabled
Mode 7
1
1
1
Single-chip advanced
mode
—
Enabled
Enabled
Enabled*2
Enabled*2
Notes: 1. In modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see
section 6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbyte. The external
data bus is either 8 or 16 bits wide depending on ABWCR settings. 8-bit bus mode is used only if
8-bit access is selected for all areas. For details see section 6, Bus Controller.
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space
of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.
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Section 3 MCU Operating Modes
Mode 5 is an externally expanded mode that enables access to external memory and peripheral
devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space
of 16 Mbytes.
Modes 6 and 7 are single-chip modes in which the chip operates using only the on-chip ROM,
RAM, and I/O registers. All ports are available in these modes. Mode 6 supports a maximum
address space of 64 kbytes. Mode 7 supports a maximum address space of 1 Mbyte.
The H8/3062 Group can be used only in modes 1 to 7. The inputs at the mode pins must select one
of these seven modes. The inputs at the mode pins must not be changed during operation. Set the
reset state before changing the inputs at these pins.
3.1.2
Register Configuration
The H8/3062 Group has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.
Table 3.2
Registers
Address*
Name
H'EE011
H'EE012
Abbreviation
R/W
Initial Value
Mode control register
MDCR
R
Undetermined
System control register
SYSCR
R/W
H'09
Note: * Lower 20 bits of the address in advanced mode.
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Section 3 MCU Operating Modes
3.2
Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the
H8/3062 Group.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS2
MDS1
MDS0
Initial value
1
1
0
0
0
—*
—*
—*
Read/Write
—
—
—
—
—
R
R
R
Reserved bits
Mode select 2 to 0
Bits indicating the current
operating mode
Note: * Determined by pins MD2 to MD0.
Bits 7 and 6—Reserved: These bits can not be modified and are always read as 1.
Bits 5 to 3—Reserved: These bits can not be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when
MDCR is read.
Note: The versions with on-chip flash memory have a boot mode in which flash memory can be
programmed. In boot mode, the MDS2 bit value is the inverse of the level at the MD2 pin.
Rev. 6.00 Mar 18, 2005 page 71 of 970
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Section 3 MCU Operating Modes
3.3
System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3062 Group.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Enables or
disables
on-chip RAM
Software standby
output port enable
Selects the output state
of the address bus and
bus control signals in
software standby mode
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
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Section 3 MCU Operating Modes
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 21, Power-Down State.)
When software standby mode is exited by an external interrupt, and a transition is made to normal
operation, this bit remains set to 1. To clear this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time
the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when
software standby mode is exited by an external interrupt.
When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the
system clock rate. When operating on an external clock, care is required in the case of the
H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM
B-mask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version,
and H8/3060 masked ROM B-mask version.
For further information about waiting time selection, see section 21.4.3, Selection of Waiting
Time for Exit from Software Standby Mode.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Waiting time = 8,192 states
0
0
1
Waiting time = 16,384 states
0
1
0
Waiting time = 32,768 states
0
1
1
Waiting time = 65,536 states
1
0
0
Waiting time = 131,072 states
1
0
1
Waiting time = 262,144 states
1
1
0
Waiting time = 1,024 states
1
1
1
Illegal setting
(Initial value)
Rev. 6.00 Mar 18, 2005 page 73 of 970
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Section 3 MCU Operating Modes
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as an interrupt mask bit
1
UI bit in CCR is used as a user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
(Initial value)
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed
in the high-impedance state in software standby mode.
Bit 1
SSOE
Description
0
In software standby mode, the address bus and bus control signals are all highimpedance
(Initial value)
1
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Rev. 6.00 Mar 18, 2005 page 74 of 970
REJ09B0215-0600
(Initial value)
Section 3 MCU Operating Modes
3.4
Operating Mode Descriptions
3.4.1
Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Mode 2
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3
Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR) (In this mode A20 is always used for address output).
3.4.4
Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR (In this mode A20 is always
used for address output).
3.4.5
Mode 5
Ports 1, 2, and 5 and part of port A can function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1, setting ports 1, 2, and 5 to output mode. For A23 to A20 output, write
0 in bits 7 to 4 of BRCR. The versions with on-chip flash memory support an on-board
programming mode in which the flash memory can be programmed. The initial bus mode after a
Rev. 6.00 Mar 18, 2005 page 75 of 970
REJ09B0215-0600
Section 3 MCU Operating Modes
reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in
ABWCR, the bus mode switches to 16 bits.
3.4.6
Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 6 supports a maximum address space of 64 kbytes.
3.4.7
Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.
The versions with on-chip flash memory support an on-board programming mode in which the
flash memory can be programmed.
3.5
Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3
Port
Port 1
Pin Functions in Each Mode
Mode 1
A7 to A0
Mode 2
A7 to A0
Mode 3
A7 to A0
Mode 4
Mode 5
Mode 6
Mode 7
A7 to A0
2
P17 to P10 *
P17 to P10
P17 to P10
Port 2
A15 to A8
A15 to A8
A15 to A8
A15 to A8
P27 to P20 *2
P27 to P20
P27 to P20
Port 3
D15 to D8
D15 to D8
D15 to D8
D15 to D8
D15 to D8
P37 to P30
P37 to P30
Port 4
1
P47 to P40 *
1
D7 to D0 *
1
P47 to P40 *
1
D7 to D0 *
1
P47 to P40 *
P47 to P40
P47 to P40
Port 5
A19 to A16
A19 to A16
A19 to A16
A19 to A16
P53 to P50 *2
P53 to P50
P53 to P50
PA6 to PA4,
A20*3
4
PA7 to PA4* PA7 to PA4
Port A
PA7 to PA4
PA7 to PA4
PA6 to PA4,
A20*3
PA7 to PA4
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of BRCR.
4. Initial state. PA7 to PA4 are switched over to A23 to A20 output by writing 0 in bits 7 to 4
of BRCR.
Rev. 6.00 Mar 18, 2005 page 76 of 970
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Section 3 MCU Operating Modes
3.6
Memory Map in Each Operating Mode
Figures 3.1 to 3.4 show memory maps of the H8/3062 Group. In the expanded modes, the address
space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode
(mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5).
The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8
and @aa:16) also differs.
3.6.1
Comparison of H8/3062 Group Memory Maps
In the H8/3062 Group, the address maps vary according to the size of the on-chip ROM and RAM.
The internal I/O register space is the same in all models, and the H8/3062F-ZTAT B-mask version
and H8/3062 have the same address map. The H8/3064F-ZTAT B-mask version and H8/3064
masked ROM B-mask version have the same address map. Table 3.4 shows the various address
maps in mode 5.
Table 3.4
Address Maps in Mode 5
H8/3062 Masked
ROM Version,
H8/3062 Masked
ROM B-Mask
Version,
H8/3062F-ZTAT
R-Mask Version,
H8/3062F-ZTAT
B-Mask Version
H8/3061 Masked
ROM Version,
H8/3061 Masked
ROM B-Mask
Version
H8/3060 Masked
ROM Version,
H8/3060 Masked
ROM B-Mask
Version
H8/3064 Masked
ROM B-Mask
Version,
H8/3064F-ZTAT
B-Mask Version
On-chip
ROM
Size
128 kbytes
96 kbytes
64 kbytes
256 kbytes
Address
area
H'000000 to
H'01FFFF
H'000000 to
H'017FFF
H'000000 to
H'00FFFF
H'000000 to
H'03FFFF
On-chip
RAM
Size
4 kbytes
4 kbytes
2 kbytes
8 kbytes
Address
area
H'FFEF20 to
H'FFFF1F
H'FFEF20 to
H'FFFF1F
H'FFF720 to
H'FFFF1F
H'FFDF20 to
H'FFFF1F
Rev. 6.00 Mar 18, 2005 page 77 of 970
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Section 3 MCU Operating Modes
3.6.2
Reserved Areas
The H8/3062 Group memory map includes reserved areas to which access (reading or writing) is
prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed.
Reserved Area in Internal I/O Register Space: The H8/3062 Group internal I/O register space
includes a reserved area to which access is prohibited. For details see appendix B, Internal I/O
Registers.
Other Reserved Areas: In mode 5 in the H8/3061 masked ROM version, H8/3061 masked ROM
B-mask version, H8/3060 masked ROM version, and H8/3060 masked ROM B-mask version
there is a reserved area in area 0, as shown in figures 3.2 and 3.3.
In modes 1 to 5 in the H8/3060 masked ROM version and H8/3060 masked ROM B-mask version
there is a reserved area in area 7, as shown in figure 3.3.
Rev. 6.00 Mar 18, 2005 page 78 of 970
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Section 3 MCU Operating Modes
H'EE0FF
H'F8000
H'FEF1F
H'FEF20
H'FFFE9
H'FFFEA
H'FFFFF
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (2)
External
address
space
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
External address
space
On-chip RAM*
16-bit absolute
addresses
Area 0
Area 0
Internal I/O
registers (1)
H'FFF00
H'FFF1F
H'FFF20
H'007FFF
Area 5
16-bit absolute addresses
H'EE000
H'0000FF
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
H'FF8000
H'FFEF1F
H'FFEF20
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
Memory-indirect
branch addresses
H'07FFF
H'000000
8-bit absolute addresses
H'000FF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
16-bit absolute
addresses
Vector area
8-bit absolute addresses
H'00000
Memory-indirect
branch addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 Memory Map of H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM Version,
and H8/3062 Masked ROM B-Mask Version in Each Operating Mode
Rev. 6.00 Mar 18, 2005 page 79 of 970
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Section 3 MCU Operating Modes
H'DFFF
H'E000
Area 0
On-chip RAM
Area 5
H'FF00
Area 6
H'FF1F
H'FF20
Area 7
H'FFFF
H'FFFFFF
Internal I/O
registers (2)
External address
space
External
address
space
H'EE000
16-bit absolute
addresses
Internal I/O
registers (1)
H'EE0FF
H'F8000
H'FEF20
On-chip RAM
H'FFF00
16-bit absolute addresses
H'FFFFE9
H'FFFFEA
H'1FFFF
H'EF20
Area 4
Internal I/O
registers (1)
Internal I/O
registers (2)
H'07FFF
Area 3
8-bit absolute addresses
H'FFFF1F
H'FFFF20
On-chip ROM
H'E0FF
Area 2
H'FFE9
H'FFEF1F
H'FFEF20 On-chip RAM*
H'FFFF00
H'000FF
Internal I/O
registers (1)
Area 1
H'FEE0FF
H'FF8000
Vector area
H'FFF1F
H'FFF20
H'FFFE9
H'FFFFF
Internal I/O
registers (2)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 Memory Map of H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM Version,
and H8/3062 Masked ROM B-Mask Version in Each Operating Mode (cont)
Rev. 6.00 Mar 18, 2005 page 80 of 970
REJ09B0215-0600
16-bit absolute addresses
H'FEE000
On-chip ROM
H'00000
Memory-indirect
branch addresses
H'007FFF
H'01FFFF
H'020000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000 External address
space
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'00FF
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
On-chip ROM
Vector area
Memory-indirect
branch addresses
H'0000FF
H'0000
8-bit absolute addresses
Vector area
Mode 6
(single-chip normal mode)
16-bit absolute
addresses
H'000000
Memory-indirect
branch addresses
Mode 5
(16-Mbyte expanded mode with
on-chip ROM enabled)
Section 3 MCU Operating Modes
H'EE0FF
H'F8000
H'FEF1F
H'FEF20
H'FFFE9
H'FFFEA
H'FFFFF
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (2)
External
address
space
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
External address
space
On-chip RAM*
16-bit absolute
addresses
Area 0
Area 0
Internal I/O
registers (1)
H'FFF00
H'FFF1F
H'FFF20
H'007FFF
Area 5
16-bit absolute addresses
H'EE000
H'0000FF
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
H'FF8000
H'FFEF1F
H'FFEF20
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
8-bit absolute addresses
H'07FFF
H'000000
16-bit absolute
addresses
H'000FF
Memory-indirect
branch addresses
Vector area
8-bit absolute addresses
H'00000
Memory-indirect
branch addresses
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 Memory Map of H8/3061 Masked ROM Version
and H8/3061 Masked ROM B-Mask Version in Each Operating Mode
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Section 3 MCU Operating Modes
H'07FFF
Area 2
H'EF20
Area 3
On-chip RAM
Area 4
Area 6
H'FF00
H'FF1F
H'FF20
Area 7
H'FFE9
Area 5
H'FFFF
Internal I/O
registers (2)
H'EE000
Internal I/O
registers (1)
H'EE0FF
H'F8000
H'FEF20
On-chip RAM
H'FFF00
16-bit absolute addresses
External
address
space
H'FFF1F
H'FFF20
8-bit absolute addresses
Internal I/O
registers (2)
16-bit absolute
addresses
H'E0FF
Area 1
Internal I/O
registers (1)
H'FFEF1F
H'FFEF20 On-chip RAM*2
H'FFFF00
H'FFFFFF
On-chip ROM
(mask ROM)
H'1FFFF
External address
space
H'FF8000
H'FFFFE9
H'FFFFEA
H'000FF
Internal I/O
registers (1)
Area 0
H'FEE0FF
H'FFFF1F
H'FFFF20
Vector area
H'FFFE9
H'FFFFF
Internal I/O
registers(2)
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 Memory Map of H8/3061 Masked ROM Version
and H8/3061 Masked ROM B-Mask Version in Each Operating Mode (cont)
Rev. 6.00 Mar 18, 2005 page 82 of 970
REJ09B0215-0600
16-bit absolute addresses
H'FEE000
H'DFFF
H'E000
Reserved*1
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000 External address
space
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
On-chip ROM
(mask ROM)
H'00000
Memory-indirect
branch addresses
H'007FFF
H'017FFF
H'018000
H'01FFFF
H'020000
H'00FF
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
On-chip ROM
(mask ROM)
Vector area
Memory-indirect
branch addresses
H'0000FF
H'0000
8-bit absolute addresses
Vector area
Mode 6
(single-chip normal mode)
16-bit absolute
addresses
H'000000
Memory-indirect
branch addresses
Mode 5
(16-Mbyte expanded mode with
on-chip ROM enabled)
Section 3 MCU Operating Modes
H'EE0FF
H'F8000
H'FEF1F
H'FEF20
H'FF71F
H'FF720
H'FFF00
H'FFF1F
H'FFF20
H'FFFE9
H'FFFEA
H'FFFFF
H'007FFF
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (1)
External
address
space
Area 3
Area 4
Area 5
Reserved*1
Internal I/O
registers (2)
External
address
space
H'9FFFFF
H'A00000
External address
space
On-chip RAM*2
16-bit absolute
addresses
Area 0
Area 0
16-bit absolute addresses
H'EE000
H'0000FF
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
H'FF8000
H'FFEF1F
H'FFEF20
H'FFF71F
H'FFF720
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
External address
space
Reserved*1
On-chip RAM*2
Internal I/O
registers (2)
External
address
space
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
8-bit absolute addresses
H'07FFF
H'000000
16-bit absolute
addresses
H'000FF
Memory-indirect
branch addresses
Vector area
8-bit absolute addresses
H'00000
Memory-indirect
branch addresses
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'FFFFFF
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.3 Memory Map of H8/3060 Masked ROM Version
and H8/3060 Masked ROM B-Mask Version in Each Operating Mode
Rev. 6.00 Mar 18, 2005 page 83 of 970
REJ09B0215-0600
Section 3 MCU Operating Modes
H'FF8000
H'FFEF1F
H'FFEF20
H'FFF71F
H'FFF720
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
H'DFFF
H'E000
H'07FFF
16-bit absolute
addresses
Memory-indirect
branch addresses
On-chip ROM
(mask ROM)
H'E0FF
Area 1
Area 2
H'EF20
Area 3
On-chip RAM
Area 4
H'FF00
Area 5
Area 6
H'FF1F
H'FF20
Area 7
H'FFE9
H'FFFF
Internal I/O
registers (2)
H'EE000
Internal I/O
registers (1)
H'EE0FF
H'F8000
H'FEF20
On-chip RAM
H'FFF00
H'FFF1F
H'FFF20
Reserved*1
External
address
space
H'000FF
H'1FFFF
External address
space
Internal I/O
registers (2)
Vector area
Internal I/O
registers (1)
Area 0
Internal I/O
registers (1)
On-chip RAM*2
H'00000
H'FFFE9
H'FFFFF
Internal I/O
registers(2)
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.3 Memory Map of H8/3060 Masked ROM Version
and H8/3060 Masked ROM B-Mask Version in Each Operating Mode (cont)
Rev. 6.00 Mar 18, 2005 page 84 of 970
REJ09B0215-0600
16-bit absolute addresses
H'FEE0FF
On-chip ROM
(mask ROM)
16-bit absolute addresses
H'FEE000
H'00FF
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
H'007FFF
H'00FFFF
H'010000
Reserved*1
H'01FFFF
H'020000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000 External address
space
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Vector area
Memory-indirect
branch addresses
On-chip ROM
(mask ROM)
H'0000
8-bit absolute addresses
H'0000FF
Mode 6
(single-chip normal mode)
16-bit absolute
addresses
Vector area
8-bit absolute addresses
H'000000
Memory-indirect
branch addresses
Mode 5
(16-Mbyte expanded mode with
on-chip ROM enabled)
Section 3 MCU Operating Modes
H'EE0FF
H'F8000
H'FDF1F
H'FDF20
H'FFFE9
H'FFFEA
H'FFFFF
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (2)
External
address
space
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
External address
space
On-chip RAM*
16-bit absolute
addresses
Area 0
Area 0
Internal I/O
registers (1)
H'FFF00
H'FFF1F
H'FFF20
H'007FFF
Area 5
16-bit absolute addresses
H'EE000
H'0000FF
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
H'FF8000
H'FFDF1F
H'FFDF20
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
8-bit absolute addresses
H'07FFF
H'000000
16-bit absolute
addresses
H'000FF
Memory-indirect
branch addresses
Vector area
8-bit absolute addresses
H'00000
Memory-indirect
branch addresses
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.4 H8/3064F-ZTAT B-Mask Version and H8/3064 Masked ROM B-Mask Version
Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
H'DFFF
H'E000
Area 0
On-chip RAM
Area 5
H'FF00
Area 6
H'FF1F
H'FF20
Area 7
H'FFFF
H'FFFFFF
Internal I/O
registers (2)
External address
space
External
address
space
H'EE000
16-bit absolute
addresses
Internal I/O
registers (1)
H'EE0FF
H'F8000
H'FDF20
On-chip RAM
H'FFF00
16-bit absolute addresses
H'FFFFE9
H'FFFFEA
H'3FFFF
H'E720
Area 4
Internal I/O
registers (1)
Internal I/O
registers (2)
H'07FFF
Area 3
8-bit absolute addresses
H'FFFF1F
H'FFFF20
On-chip ROM
(flash memory)
H'E0FF
Area 2
H'FFE9
H'FFDF1F
H'FFDF20 On-chip RAM*
H'FFFF00
H'000FF
Internal I/O
registers (1)
Area 1
H'FEE0FF
H'FF8000
Vector area
H'FFF1F
H'FFF20
H'FFFE9
H'FFFFF
Internal I/O
registers(2)
16-bit absolute addresses
H'FEE000
On-chip ROM
(flash memory)
H'00000
Memory-indirect
branch addresses
H'007FFF
H'03FFFF
H'040000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000 External address
space
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'00FF
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
On-chip ROM
(flash memory)
Vector area
Memory-indirect
branch addresses
H'0000FF
H'0000
8-bit absolute addresses
Vector area
Mode 6
(single-chip normal mode)
16-bit absolute
addresses
H'000000
Memory-indirect
branch addresses
Mode 5
(16-Mbyte expanded mode with
on-chip ROM enabled)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.4 H8/3064F-ZTAT B-Mask Version and H8/3064 Masked ROM B-Mask Version
Memory Map in Each Operating Mode (cont)
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the
RES pin
Interrupt
Interrupt requests are handled when execution of the
current instruction or handling of the current exception
is completed
Low
Trap instruction (TRAPA)
Started by execution of a trap instruction (TRAPA)
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
Note: For a reset exception, steps 2 and 3 above are carried out.
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Section 4 Exception Handling
4.1.3
Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.
• Reset
External interrupts: NMI, IRQ 0 to IRQ5
Exception
sources
• Interrupts
• Trap instruction
Internal interrupts: 27 interrupts from on-chip
supporting modules
Figure 4.1 Exception Sources
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Section 4 Exception Handling
Table 4.2
Exception Vector Table
Vector Address*1
Exception Source
Vector Number
Advanced Mode
Normal Mode
Reset
0
H'0000 to H'0003
H'0000 to H'0001
Reserved for system use
1
H'0004 to H'0007
H'0002 to H'0003
2
H'0008 to H'000B
H'0004 to H'0005
3
H'000C to H'000F
H'0006 to H'0007
4
H'0010 to H'0013
H'0008 to H'0009
5
H'0014 to H'0017
H'000A to H'000B
6
H'0018 to H'001B
H'000C to H'000D
7
H'001C to H'001F
H'000E to H'000F
External interrupt (NMI)
Trap instruction (4 sources)
8
H'0020 to H'0023
H'0010 to H'0011
9
H'0024 to H'0027
H'0012 to H'0013
10
H'0028 to H'002B
H'0014 to H'0015
11
H'002C to H'002F
H'0016 to H'0017
External interrupt IRQ0
12
H'0030 to H'0033
H'0018 to H'0019
External interrupt IRQ1
13
H'0034 to H'0037
H'001A to H'001B
External interrupt IRQ2
14
H'0038 to H'003B
H'001C to H'001D
External interrupt IRQ3
15
H'003C to H'003F
H'001E to H'001F
External interrupt IRQ4
16
H'0040 to H'0043
H'0020 to H'0021
External interrupt IRQ5
17
H'0044 to H'0047
H'0022 to H'0023
Reserved for system use
18
H'0048 to H'004B
H'0024 to H'0025
19
H'004C to H'004F
H'0026 to H'0027
20
to
63
H'0050 to H'0053
to
H'00FC to H'00FF
H'0028 to H'0029
to
H'007E to H'007F
2
Internal interrupts*
Notes: 1. Lower 16 bits of the address
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector
Table.
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Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 11,
Watchdog Timer.
4.2.2
Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (φ) cycles. In the versions
with on-chip flash memory, the RES pin must be held low for at least 20 system clock cycles. See
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to
H'0001 in normal mode) are read, and program execution starts from the address indicated in
the vector address.
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4. Figure 4.4 shows the reset sequence in mode 6.
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:
:
:
:
(2)
(4)
(3)
(6)
(5)
(8)
(7)
Internal
processing
(10)
(9)
Prefetch of
first program
instruction
Address of reset exception handling vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
High
(1)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
(1), (3), (5), (7)
(2), (4), (6), (8)
(9)
(10)
D15 to D8
HWR , LWR
RD
Address
bus
RES
φ
Vector fetch
Section 4 Exception Handling
Figure 4.2 Reset Sequence (Modes 1 and 3)
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Section 4 Exception Handling
Internal
processing
Vector fetch
Prefetch of first
program instruction
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR , LWR
D15 to D0
(1), (3)
(2), (4)
(5)
(6)
:
:
:
:
High
(2)
(4)
(6)
Address of reset exception handling vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
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Section 4 Exception Handling
Vector fetch
Internal
processing
Prefetch of
first program
instruction
φ
RES
Internal
address bus
(1)
(2)
Internal
read signal
Internal
write signal
High
Internal
data bus
(16 bits wide)
(2)
(3)
(1) : Address of reset exception handling vector (H'0000)
(2) : Start address (contents of reset exception handling vector address)
(3) : First instruction of program
Figure 4.4 Reset Sequence (Mode 6)
4.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset exception handling. The first instruction of
the program is always executed immediately after the reset state ends. This instruction should
initialize the stack pointer (example: MOV.L #xx:32, SP).
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Section 4 Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and
27 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source
has a separate vector address.
NMI is the highest-priority interrupt and is always accepted*. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details
see section 17.6.4, NMI Input Disabling Conditions.
External interrupts
NMI (1)
IRQ 0 to IRQ 5 (6)
Internal interrupts
WDT* (1)
16-bit timer (9)
8-bit timer (8)
SCI (8)
A/D converter (1)
Interrupts
Notes: Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
Figure 4.5 Interrupt Sources and Number of Interrupts
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1 in CCR. The TRAPA instruction
fetches a start address from a vector table entry corresponding to a vector number from 0 to 3,
which is specified in the instruction code.
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Section 4 Exception Handling
4.5
Stack Status after Exception Handling
Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
Stack area
Before exception handling
CCR
CCR *
PC H
PC L
Even address
After exception handling
Pushed on stack
a. Normal mode
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
Stack area
Before exception handling
CCR
PC E
PC H
PC L
Even address
After exception handling
Pushed on stack
b. Advanced mode
Legend:
PCE : Bits 23 to 16 of program counter (PC)
PCH : Bits 15 to 8 of program counter (PC)
PCL : Bits 7 to 0 of program counter (PC)
CCR : Condition code register
SP : Stack pointer
Notes: * Ignored at return.
1. PC indicates the address of the first instruction that will be executed after return.
2. Registers must be saved in word or longword size at even addresses.
Figure 4.6 Stack after Completion of Exception Handling
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Section 4 Exception Handling
4.6
Notes on Stack Usage
When accessing word data or longword data, the H8/3062 Group regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP:ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn
PUSH.L ERn
(or MOV.W Rn, @–SP)
(or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn
POP.L ERn
(or MOV.W @SP+, Rn)
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what
happens when the SP value is odd.
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Section 4 Exception Handling
SP
CCR
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
SP
TRAPA instruction executed
SP set to H'FFFEFF
MOV. B R1L, @-ER7
Data saved above SP
CCR contents lost
Legend:
CCR : Condition code register
PC : Program counter
R1L : General register R1L
SP : Stack pointer
Note: The diagram illustrates modes 3 to 5.
Figure 4.7 Operation when SP Value is Odd
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Section 4 Exception Handling
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enabling/disabling by the I and UI bits in the CPU’s condition code register (CCR)
and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted*; either the rising or falling edge can be
selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected
independently.
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details
see section 17.6.4, NMI Input Disabling Conditions.
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Section 5 Interrupt Controller
5.1.2
Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
CPU
ISCR
IER
IPRA, IPRB
NMI
input
IRQ input
section ISR
IRQ input
OVF
TME
.
.
.
.
.
.
.
TEI
TEIE
Priority
decision logic
Interrupt
request
Vector
number
.
.
.
I
UI
Interrupt controller
UE
Legend:
ISCR :
IER
:
ISR
:
IPRA :
IPRB :
SYSCR :
SYSCR
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
System control register
Figure 5.1 Interrupt Controller Block Diagram
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CCR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 lists the interrupt pins.
Table 5.1
Interrupt Pins
Name
Abbreviation I/O
Nonmaskable interrupt
NMI
External interrupt request 5 to 0
IRQ5
Function
Input Nonmaskable interrupt*, rising edge or
falling edge selectable
to IRQ0
Input Maskable interrupts, falling edge or level
sensing selectable
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details see
17.6.4, NMI Input Disable Conditions.
5.1.4
Register Configuration
Table 5.2 lists the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'EE012
System control register
SYSCR
R/W
H'09
H'EE014
IRQ sense control register
ISCR
R/W
H'00
H'EE015
IRQ enable register
IER
R/W
H'00
H'EE016
IRQ status register
ISR
R/(W)*2
H'00
H'EE018
Interrupt priority register A
IPRA
R/W
H'00
H'EE019
Interrupt priority register B
IPRB
R/W
H'00
Notes: 1. Lower 20 bits of the address in advanced mode
2. Only 0 can be written, to clear flags.
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
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Section 5 Interrupt Controller
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Software standby
output port enable
NMI edge select
Selects the NMI input edge
Standby timer
select 2 to 0
Software standby
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as interrupt mask bit
1
UI bit in CCR is used as user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG
Description
0
Interrupt is requested at falling edge of NMI input
1
Interrupt is requested at rising edge of NMI input
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
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(Initial value)
Section 5 Interrupt Controller
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority
level A0
Selects the
priority level
of 16-bit timer
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of 16-bit timer channel 1
interrupt requests
Priority level A2
Selects the priority level of
16-bit timer channel 0 interrupt
requests
Priority level A3
Selects the priority level of WDT,
and A/D converter interrupt requests
Priority level A4
Selects the priority level of IRQ 4 and IRQ 5
interrupt requests
Priority level A5
Selects the priority level of IRQ 2 and IRQ 3 interrupt requests
Priority level A6
Selects the priority level of IRQ 1 interrupt requests
Priority level A7
Selects the priority level of IRQ 0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7
IPRA7
Description
0
IRQ0 interrupt requests have priority level 0 (low priority)
1
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6
IPRA6
Description
0
IRQ1 interrupt requests have priority level 0 (low priority)
1
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.
Bit 5
IPRA5
Description
0
IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority)
1
IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit 4
IPRA4
Description
0
IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority)
1
IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, and A/D converter
interrupt requests.
Bit 3
IPRA3
Description
0
WDT, and A/D converter interrupt requests have priority level 0 (low priority)
(Initial value)
1
WDT, and A/D converter interrupt requests have priority level 1 (high priority)
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Section 5 Interrupt Controller
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt
requests.
Bit 2
IPRA2
Description
0
16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 0 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt
requests.
Bit 1
IPRA1
Description
0
16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt
requests.
Bit 0
IPRA0
Description
0
16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 2 interrupt requests have priority level 1 (high priority)
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Section 5 Interrupt Controller
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRB7
IPRB6
—
—
IPRB3
IPRB2
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Priority level B2
Selects the priority level of
SCI channel 1 interrupt requests
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Reserved bit
Priority level B6
Selects the priority level of 8-bit timer channel 2, 3 interrupt requests
Priority level B7
Selects the priority level of 8-bit timer channel 0, 1 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt
requests.
Bit 7
IPRB7
Description
0
8-bit timer channel 0 and 1 interrupt requests have priority level 0 (low priority)
(Initial value)
1
8-bit timer channel 0 and 1 interrupt requests have priority level 1 (high priority)
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Section 5 Interrupt Controller
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt
requests.
Bit 6
IPRB6
Description
0
8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority)
(Initial value)
1
8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority)
Bits 5 and 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3
IPRB3
Description
0
SCI0 channel 0 interrupt requests have priority level 0 (low priority)
1
SCI0 channel 0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
Description
0
SCI1 channel 1 interrupt requests have priority level 0 (low priority)
1
SCI1 channel 1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bits 1 and 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
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Section 5 Interrupt Controller
5.2.3
IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt
requests.
Bit
7
6
5
4
3
2
1
0
—
—
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Reserved bits
IRQ 5 to IRQ0 flags
These bits indicate IRQ 5 to IRQ 0 flag
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can not be modified and are always read as 0.
Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to
IRQ0 interrupt requests.
Bits 5 to 0
IRQ5F to IRQ0F Description
0
1
[Clearing conditions]
(Initial value)
•
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
•
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried
out.
•
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
•
IRQnSC = 0 and IRQn input is low.
•
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
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Section 5 Interrupt Controller
5.2.4
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ5 to IRQ0 interrupt requests.
Bit
7
6
5
4
3
2
1
0
—
—
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ 5 to IRQ0 enable
These bits enable or disable IRQ 5 to IRQ 0 interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable
IRQ5 to IRQ0 interrupts.
Bits 5 to 0
IRQ5E to IRQ0E
Description
0
IRQ5 to IRQ0 interrupts are disabled
1
IRQ5 to IRQ0 interrupts are enabled
(Initial value)
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Section 5 Interrupt Controller
5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ5 to IRQ0.
Bit
7
6
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
4
3
2
1
0
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Reserved bits
IRQ 5 to IRQ0 sense control
These bits select level sensing or falling-edge
sensing for IRQ 5 to IRQ 0 interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge
sensing.
Bits 5 to 0
IRQ5SC to IRQ0SC
Description
0
Interrupts are requested when IRQ5 to IRQ0 inputs are low
1
Interrupts are requested by falling-edge input at IRQ5 to IRQ0
Rev. 6.00 Mar 18, 2005 page 110 of 970
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(Initial value)
Section 5 Interrupt Controller
5.3
Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 27 internal interrupts.
5.3.1
External Interrupts
There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and
IRQ2 can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details
see section 17.6.4, NMI Input Disable Conditions.
IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5.
The IRQ0 to IRQ5 interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ0 to IRQ5, or by the falling edge.
• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared
to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.
IRQnSC
IRQnE
IRQnF
Edge/level
sense circuit
IRQn input
S
Q
IRQn interrupt
request
R
Clear signal
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
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Section 5 Interrupt Controller
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
input pin
IRQnF
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, SCI input/output, or A/D
external trigger input.
5.3.2
Internal Interrupts
27 internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3
Interrupt Exception Handling Vector Table
Table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default
priority order. In the default priority order, smaller vector numbers have higher priority. The
priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a
reset is the default order shown in table 5.3.
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Section 5 Interrupt Controller
Table 5.3
Interrupt Sources, Vector Addresses, and Priority
Interrupt Source
Origin
NMI
External
pins
Vector Address*
Vector
Number Advanced Mode Normal Mode
IPR
7
H'001C to H'001F H'000E to H'000F —
12
H'0030 to H'0033 H'0018 to H'0019 IPRA7
IRQ1
13
H'0034 to H0037
IRQ2
14
H'0038 to H'003B H'001C to H'001D IPRA5
IRQ3
15
H'003C to H'003F H'001E to H'001F
IRQ4
16
H'0040 to H'0043 H'0020 to H'0021 IPRA4
IRQ5
17
H'0044 to H'0047 H'0022 to H'0023
18
H'0048 to H'004B H'0024 to H'0025
19
H'004C to H'004F H'0026 to H'0027
IRQ0
Reserved
—
Watchdog
timer
20
H'0050 to H'0053 H'0028 to H'0029 IPRA3
Reserved
—
21
H'0054 to H'0057 H'002A to H'002B
22
H'0058 to H'005B H'002C to H'002D
ADI (A/D end)
A/D
23
H'005C to H'005F H'002E to H'002F
25
IMIB0
(compare match/
input capture B0)
OVI0 (overflow 0)
High
H'001A to H'001B IPRA6
WOVI
(interval timer)
IMIA0
16-bit timer 24
channel 0
(compare match
input capture A0)/
Priority
H'0060 to H'0063 H'0030 to H'0031 IPRA2
H'0064 to H'0067 H'0032 to H'0033
26
H'0068 to H'006B H'0034 to H'0035
27
H'006C to H'006F H'0036 to H'0037
Reserved
—
IMIA1
(compare match/
input capture A1)
16-bit timer 28
channel 1
IMIB1
(compare match/
input capture B1)
29
H'0074 to H'0077 H'003A to H'003B
OVI1 (overflow 1)
30
H'0078 to H'007B H'003C to H'003D
Reserved
31
H'007C to H'007F H'003E to H'003F
H'0070 to H'0073 H'0038 to H'0039 IPRA1
Low
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Section 5 Interrupt Controller
Vector Address*
Vector
Number Advanced Mode Normal Mode
Interrupt Source
Origin
IMIA2
(compare match/
input capture A2)
16-bit timer 32
channel 2
IMIB2
(compare match/
input capture B2)
33
H'0084 to H'0087 H'0042 to H'0043
OVI2 (overflow 2)
34
H'0088 to H'008B H'0044 to H'0045
35
H'008C to H'008F H'0046 to H'0047
—
CMIA0
(compare match
A0)
8-bit timer 36
channel 0/1
CMIB0
(compare match
B0)
37
H'0094 to H'0097 H'004A to H'004B
CMIA1/CMIB1
(compare match
A1/B1)
38
H'0098 to H'009B H'004C to H'004D
TOVI0/TOVI1
(overflow 0/1)
39
H'009C to H'009F H'004E to H'004F
H'0090 to H'0093 H'0048 to H'0049 IPRB7
CMIA2
(compare match
A2)
8-bit timer 40
channel 2/3
CMIB2
(compare match
B2)
41
H'00A4 to H'00A7 H'0052 to H'0053
CMIA3/CMIB3
(compare match
A3/B3)
42
H'00A8 to H'00AB H'0054 to H'0055
TOVI2/TOVI3
(overflow 2/3)
43
H'00AC to H'00AF H'0056 to H'0057
44
45
46
47
48
49
50
51
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
—
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Priority
H'0080 to H'0083 H'0040 to H'0041 IPRA0 High
Reserved
Reserved
IPR
H'00A0 to H'00A3 H'0050 to H'0051 IPRB6
H'0058 to H'0059 —
H'005A to H'005B
H'005C to H'005D
H'005E to H'005F
H'0060 to H'0061
H'0062 to H'0063
H'0064 to H'0065
H'0066 to H'0067
Low
Section 5 Interrupt Controller
Interrupt Source
Origin
ERI0
(receive error 0)
SCI
channel 0
Vector Address*
Vector
Number Advanced Mode Normal Mode
IPR
Priority
52
H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High
RXI0 (receive
data full 0)
53
H'00D4 to H'00D7 H'006A to H'006B
TXI0 (transmit
data empty 0)
54
H'00D8 to H'00DB H'006C to H'006D
TEI0
(transmit end 0)
55
H'00DC to H'00DF H'006E to H'006F
56
H'00E0 to H'00E3 H'0070 to H'0071 IPRB2
RXI1 (receive
data full 1)
57
H'00E4 to H'00E7 H'0072 to H'0073
TXI1 (transmit
data empty 1)
58
H'00E8 to H'00EB H'0074 to H'0075
TEI1 (transmit
end 1)
59
H'00EC to H'00EF H'0076 to H'0077
60
H'00F0 to H'00F3 H'0078 to H'0079 —
61
H'00F4 to H'00F7 H'007A to H'007B
62
H'00F8 to H'00FB H'007C to H'007D
63
H'00FC to H'00FF H'007E to H'007F
ERI1
(receive error 1)
Reserved
SCI
channel 1
—
Low
Note: * Lower 16 bits of the address
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Section 5 Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Handling Process
The H8/3062 Group handles interrupts differently depending on the setting of the UE bit. When
UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and
UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,
and UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states*. IRQ
interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt
requests are ignored when the enable bits are cleared to 0.
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details
see section 17.6.4, NMI Input Disable Conditions.
Table 5.4
UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
CCR
UE
I
UI
Description
1
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
—
No interrupts are accepted except NMI.
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
NMI and interrupts with priority level 1 are accepted.
1
No interrupts are accepted except NMI.
0
UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
Yes
IRQ 1
IRQ 0
No
Yes
No
IRQ 1
Yes
No
Yes
TEI1
TEI1
Yes
Yes
No
I=0
Yes
Save PC and CCR
I ←1
Read vector address
Branch to interrupt
service routine
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
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Section 5 Interrupt Controller
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of
IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules.
• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and
are unmasked when either the I bit or the UI bit is cleared to 0.
For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
Figure 5.5 shows the transitions among the above states.
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Section 5 Interrupt Controller
I←0
a. All interrupts are
unmasked
I←0
b. Only NMI, IRQ 2 , and
IRQ 3 are unmasked
I ← 1, UI ← 0
Exception handling,
or I ← 1, UI ← 1
UI ← 0
Exception handling,
or UI ← 1
c. All interrupts are
masked except NMI
Figure 5.5 Interrupt Masking State Transitions (Example)
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only interrupts with priority level 1 are accepted; interrupt requests
with priority level 0 are held pending. If the I bit and UI bit are both set to 1, all other interrupt
requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
IRQ 0
Yes
IRQ 1
No
Yes
No
IRQ 1
Yes
No
Yes
TEI1
TEI1
Yes
Yes
No
I=0
No
I=0
Yes
Yes
No
UI = 0
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt
service routine
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
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(2)
(1)
(4)
High
(3)
Instruction Internal
prefetch
processing
(8)
(7)
(10)
(9)
(12)
(11)
Vector fetch
(14)
(13)
(6), (8)
: PC and CCR saved to stack
(9), (11) : Vector address
(10), (12) : Starting address of interrupt service routine (contents of
vector address)
(13)
: Starting address of interrupt service routine; (13) = (10), (12)
(14)
: First instruction of interrupt service routine
(6)
(5)
Stack
Prefetch of
interrupt
Internal
service routine
processing instruction
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
(1)
: Instruction prefetch address (not executed;
return address, same as PC contents)
(2), (4) : Instruction code (not executed)
(3)
: Instruction prefetch address (not executed)
(5)
: SP – 2
(7)
: SP – 4
D15 to D8
HWR , LWR
RD
Address
bus
Interrupt
request
signal
φ
Interrupt level
decision and wait
for end of instruction
5.4.2
Interrupt accepted
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and
stack are in an external memory area accessed in two states via a 16-bit bus.
Figure 5.7 Interrupt Exception Handling Sequence
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Section 5 Interrupt Controller
5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5
Interrupt Response Time
External Memory
No.
On-Chip
Memory
Item
*1
8-Bit Bus
2 States
3 States
2 States
3 States
2*1
2
2
Maximum number
of states until end of
current instruction
1 to 23
1 to 27
1 to 31*4
1 to 23
1 to 25*4
3
Saving PC and CCR
to stack
4
8
12*4
4
6*4
4
Vector fetch
4
8
4
4
8
12*4
12*4
4
6*4
6*4
4
4
4
4
4
19 to 41
31 to 57
43 to 73
19 to 41
25 to 49
Instruction fetch
6
Internal processing*3
Total
2
*1
Interrupt priority
decision
5
2
*1
1
*2
2
*1
16-Bit Bus
Notes: 1. 1 state for internal interrupts
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch
4. The number of states increases if wait states are inserted in external memory access.
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Section 5 Interrupt Controller
5.5
Usage Notes
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag to 0.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer’s TISRA
register.
TISRA write cycle by CPU
IMIA exception handling
φ
Internal
address bus
TISRA address
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
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Section 5 Interrupt Controller
5.5.2
Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3
Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE
L1
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Section 6 Bus Controller
Section 6 Bus Controller
6.1
Overview
The H8/3062 Group has an on-chip bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters—the CPU can release the bus to an external device.
6.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
 Manages the external space as eight areas (0 to 7) of 128 kbytes in 1-Mbyte modes, or 2
Mbytes in 16-Mbyte modes
 Bus specifications can be set independently for each area
• Basic bus interface
 Chip select (CS0 to CS7) can be output for areas 0 to 7
 8-bit access or 16-bit access can be selected for each area
 Two-state access or three-state access can be selected for each area
 Program wait states can be inserted for each area
 Pin wait insertion capability is provided
• Idle cycle insertion
 An idle cycle can be inserted in case of an external read cycle between different areas
 An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
 A built-in bus arbiter grants the bus right to the CPU, or an external bus master
• Other features
 Choice of two address update modes
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Section 6 Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7
ABWCR
ASTCR
BCR
Area
decoder
Chip select
control signals
CSCR
Internal signals
ADRCR
Bus mode control signal
Bus size control signal
Bus control
circuit
Access state control signal
Internal data bus
Internal address bus
Wait state
controller
WAIT
WCRH
WCRL
Internal signals
CPU bus request signal
CPU bus acknowledge signal
BRCR
Bus arbiter
BACK
BREQ
Legend:
ABWCR
ASTCR
WCRH
WCRL
BRCR
CSCR
ADRCR
BCR
:
:
:
:
:
:
:
:
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus release control register
Chip select control register
Address control register
Bus control register
Figure 6.1 Block Diagram of Bus Controller
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Wait request signal
Section 6 Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller.
Table 6.1
Bus Controller Pins
Name
Abbreviation
I/O
Function
Output
Strobe signals selecting areas 0 to 7
Output
Strobe signal indicating valid address output
on the address bus
Address strobe
CS0 to CS7
AS
Read
RD
Output
Strobe signal indicating reading from the
external address space
High write
HWR
Output
Strobe signal indicating writing to the external
address space, with valid data on the upper
data bus (D15 to D8)
Low write
LWR
Output
Strobe signal indicating writing to the external
address space, with valid data on the lower
data bus (D7 to D0)
Wait
WAIT
Input
Wait request signal for access to external
three-state access areas
Bus request
BREQ
Input
Request signal for releasing the bus to an
external device
Bus acknowledge
BACK
Output
Acknowledge signal indicating release of the
bus to an external device
Chip select 0 to 7
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Section 6 Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the bus controller’s registers.
Table 6.2
Bus Controller Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'EE020
Bus width control register
ABWCR
R/W
H'FF*2
H'EE021
Access state control register
ASTCR
R/W
H'FF
H'EE022
Wait control register H
WCRH
R/W
H'FF
H'EE023
Wait control register L
WCRL
R/W
H'FF
H'EE013
Bus release control register
BRCR
R/W
H'FE*3
H'EE01F
Chip select control register
CSCR
R/W
H'0F
H'EE01E
Address control register
ADRCR
R/W
H'FF
H'EE024
Bus control register
BCR
R/W
H'C6
Notes: 1. Lower 20 bits of the address in advanced mode
2. In modes 2 and 4, the initial value is H'00.
3. In modes 3 and 4, the initial value is H'EE.
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Section 6 Bus Controller
6.2
Register Descriptions
6.2.1
Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
7
Bit
ABW7
Modes
Initial value 1
1, 3, 5, 6,
and 7
Read/Write R/W
Modes
2 and 4
Initial value
6
5
4
3
2
1
0
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
Read/Write R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to
D0). In modes 1, 3, 5, 6, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby
mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.
It is not initialized in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0
Description
0
Areas 7 to 0 are 16-bit access areas
1
Areas 7 to 0 are 8-bit access areas
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings. These settings are
therefore invalid in the single-chip modes (modes 6 and 7).
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Section 6 Bus Controller
6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
Description
0
Areas 7 to 0 are accessed in two states
1
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings. These
settings are therefore meaningless in the single-chip modes (modes 6 and 7).
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Section 6 Bus Controller
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
On-chip memory and registers are accessed in a fixed number of states that does not depend on
WCRH/WCRL settings.
WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
WCRH
7
6
5
4
3
2
1
0
W71
W70
W61
W60
W51
W50
W41
W40
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
R/W
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
W71
Bit 6
W70
Description
0
0
Program wait not inserted when external space area 7 is accessed
1
1 program wait state inserted when external space area 7 is accessed
0
2 program wait states inserted when external space area 7 is accessed
1
3 program wait states inserted when external space area 7 is accessed
(Initial value)
1
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Section 6 Bus Controller
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5
W61
Bit 4
W60
Description
0
0
Program wait not inserted when external space area 6 is accessed
1
1 program wait state inserted when external space area 6 is accessed
0
2 program wait states inserted when external space area 6 is accessed
1
3 program wait states inserted when external space area 6 is accessed
(Initial value)
1
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3
W51
Bit 2
W50
Description
0
0
Program wait not inserted when external space area 5 is accessed
1
1 program wait state inserted when external space area 5 is accessed
0
2 program wait states inserted when external space area 5 is accessed
1
3 program wait states inserted when external space area 5 is accessed
(Initial value)
1
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1
W41
Bit 0
W40
Description
0
0
Program wait not inserted when external space area 4 is accessed
1
1 program wait state inserted when external space area 4 is accessed
0
2 program wait states inserted when external space area 4 is accessed
1
3 program wait states inserted when external space area 4 is accessed
(Initial value)
1
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Section 6 Bus Controller
WCRL
7
6
5
4
3
2
1
0
W31
W30
W21
W20
W11
W10
W01
W00
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
R/W
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7
W31
0
1
Bit 6
W30
Description
0
Program wait not inserted when external space area 3 is accessed
1
1 program wait state inserted when external space area 3 is accessed
0
2 program wait states inserted when external space area 3 is accessed
1
3 program wait states inserted when external space area 3 is accessed
(Initial value)
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5
W21
Bit 4
W20
Description
0
0
Program wait not inserted when external space area 2 is accessed
1
1 program wait state inserted when external space area 2 is accessed
0
2 program wait states inserted when external space area 2 is accessed
1
3 program wait states inserted when external space area 2 is accessed
(Initial value)
1
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Section 6 Bus Controller
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
W11
Bit 2
W10
Description
0
0
Program wait not inserted when external space area 1 is accessed
1
1 program wait state inserted when external space area 1 is accessed
0
2 program wait states inserted when external space area 1 is accessed
1
3 program wait states inserted when external space area 1 is accessed
(Initial value)
1
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
Bit 0
W00
Description
0
0
Program wait not inserted when external space area 0 is accessed
1
1 program wait state inserted when external space area 0 is accessed
0
2 program wait states inserted when external space area 0 is accessed
1
3 program wait states inserted when external space area 0 is accessed
(Initial value)
1
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Section 6 Bus Controller
6.2.4
Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and
enables or disables release of the bus to an external device.
Bit
Modes
1, 2, 6,
and 7
7
6
5
4
3
2
1
0
A23E
A22E
A21E
A20E
—
—
—
BRLE
1
1
1
1
1
1
1
0
Read/Write —
—
—
—
—
—
—
R/W
1
1
0
1
1
1
0
R/W
R/W
—
—
—
—
R/W
Initial value
Modes Initial value 1
3 and 4 Read/Write R/W
Mode 5
Initial value
1
Read/Write R/W
1
1
1
1
1
1
0
R/W
R/W
R/W
—
—
—
R/W
Reserved bits
Address 23 to 20 enable
These bits enable PA7 to PA4 to be
used for A23 to A20 address output
Bus release enable
Enables or disables release
of the bus to an external device
BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset
and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin.
Writing 0 in this bit enables A23 output from PA4. In modes other than 3, 4, and 5, this bit cannot
be modified and PA4 has its ordinary port functions.
Bit 7
A23E
Description
0
PA4 is the A23 address output pin
1
PA4 is an input/output pin
(Initial value)
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Section 6 Bus Controller
Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin.
Writing 0 in this bit enables A22 output from PA5. In modes other than 3, 4, and 5, this bit cannot
be modified and PA5 has its ordinary port functions.
Bit 6
A22E
Description
0
PA5 is the A22 address output pin
1
PA5 is an input/output pin
(Initial value)
Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin.
Writing 0 in this bit enables A21 output from PA6. In modes other than 3, 4, and 5, this bit cannot
be modified and PA6 has its ordinary port functions.
Bit 5
A21E
Description
0
PA6 is the A21 address output pin
1
PA6 is an input/output pin
(Initial value)
Bit 4—Address 20 Enable (A20E): Enables PA7 to be used as the A20 address output pin.
Writing 0 in this bit enables A20 output from PA7. This bit can only be modified in mode 5.
Bit 4
A20E
Description
0
PA7 is the A20 address output pin (Initial value when in mode 3 or 4)
1
PA7 is an input/output pin (Initial value when in mode 1, 2, 5, 6 or 7)
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
Description
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
The bus can be released to an external device
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(Initial value)
Section 6 Bus Controller
6.2.5
Bus Control Register (BCR)
7
6
5
4
3
2
1
0
ICIS1
ICIS0
—
—
—
—
RDEA
WAITE
Initial value
1
1
0*
0*
0*
1
1
0
Read/Write
R/W
R/W
—
—
—
—
R/W
Bit
R/W
Note: * 1 must not be written in bits 5 to 3.
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
Description
0
No idle cycle inserted in case of consecutive external read cycles for different
areas
1
Idle cycle inserted in case of consecutive external read cycles for different
areas
(Initial value)
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
Description
0
No idle cycle inserted in case of consecutive external read and write cycles
1
Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
Bits 5 to 3—Reserved (must not be set to 1): These bits can be read and written, but must not be
set to 1. Normal operation cannot be guaranteed if 1 is written in these bits.
Bit 2—Reserved: Read-only bit, always read as 1.
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Section 6 Bus Controller
Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit
is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7.
Bit 1
RDEA
Description
0
Area divisions are as follows:
1
Area 0: 2 Mbytes
Area 4: 1.93 Mbytes
Area 1: 2 Mbytes
Area 5: 4 kbytes
Area 2: 8 Mbytes
Area 6: 23.75 kbytes
(19.75 kbytes)*
Area 3: 2 Mbytes
Area 7: 22 bytes
Areas 0 to 7 are the same size (2 Mbytes)
(Initial value)
Note: * Division in the H8/3064F-ZTAT B-mask version.
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE
Description
0
WAIT pin wait input is disabled, and the WAIT pin can be used as an
input/output port
1
WAIT pin wait input is enabled
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(Initial value)
Section 6 Bus Controller
6.2.6
Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS7 to CS4).
If output of a chip select signal CS7 to CS4 is enabled by a setting in this register, the
corresponding pin functions a chip select signal (CS7 to CS4) output regardless of any other
settings. CSCR cannot be modified in single-chip mode.
Bit
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
—
—
—
—
R/W
Reserved bits
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE
Description
0
Output of chip select signal
1
CSn is disabled
Output of chip select signal CSn is enabled
(Initial value)
Note: n = 7 to 4
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
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Section 6 Bus Controller
6.2.7
Address Control Register (ADRCR)
ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address
update mode 2 as the address output method.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ADRCTL
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
Reserved bits
R/W
Address control
Selects address
update mode 1 or
address update
mode 2
ADRCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Address Control (ADRCTL): Selects the address output method.
Bit 0
ADRCTL
Description
0
Address update mode 2 is selected
1
Address update mode 1 is selected
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(Initial value)
Section 6 Bus Controller
6.3
Operation
6.3.1
Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the
memory map.
H'00000
H'000000
Area 0 (128 kbytes)
H'1FFFF
Area 0 (2 Mbytes)
H'1FFFFF
H'20000
H'200000
Area 1 (128 kbytes)
H'3FFFF
Area 1 (2 Mbytes)
H'3FFFFF
H'40000
H'400000
Area 2 (128 kbytes)
H'5FFFF
Area 2 (2 Mbytes)
H'5FFFFF
H'60000
H'600000
Area 3 (128 kbytes)
H'7FFFF
Area 3 (2 Mbytes)
H'7FFFFF
H'80000
H'800000
Area 4 (128 kbytes)
H'9FFFF
Area 4 (2 Mbytes)
H'9FFFFF
H'A0000
H'A00000
Area 5 (128 kbytes)
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 5 (2 Mbytes)
H'BFFFFF
H'C00000
Area 6 (128 kbytes)
Area 7 (128 Mbytes)
H'DFFFFF
H'E00000
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
H'FFFFF
H'FFFFFF
(a) 1-Mbyte modes (modes 1 and 2)
(b) 16-Mbyte modes (modes 3 to 5)
Figure 6.2 Access Area Map for Each Operating Mode
Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each
area are selected in ABWCR, ASTCR, WCRH, and WCRL.
In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR.
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Section 6 Bus Controller
Area 0
2 Mbytes
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 1
2 Mbytes
2 Mbytes
H'000000
2 Mbytes
H'1FFFFF
H'200000
H'3FFFFF
Area 2
8 Mbytes
2 Mbytes
Area 2
2 Mbytes
H'5FFFFF
H'600000
2 Mbytes
H'400000
Area 3
2 Mbytes
H'7FFFFF
2 Mbytes
H'800000
Area 4
2 Mbytes
2 Mbytes
H'9FFFFF
H'A00000
Area 5
2 Mbytes
H'BFFFFF
H'DFFFFF
H'E00000
Area 6
2 Mbytes
Area 3
2 Mbytes
Area 7
1.93 Mbytes
Area 4
1.93 Mbytes
Internal I/O registers (1)
Internal I/O registers (1)
2 Mbytes
H'C00000
H'FEE000
H'FEE0FF
H'FEE100
Reserved 39.75 kbytes
H'FF7FFF
H'FF8000
Area 5
4 kbytes
H'FF8FFF
Area 6
23.75 kbytes
On-chip RAM
4 kbytes
On-chip RAM
4 kbytes*
Internal I/O registers (2)
Internal I/O registers (2)
Area 7
22 bytes
Area 7
22 bytes
(A) Memory map when RDEA = 1
(b) Memory map when RDEA = 0
H'FFEF1F
H'FFEF20
2 Mbytes
Area 7
67.5 kbytes
Absolute
address 16 bits
H'FF9000
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Absolute
address 8 bits
H'FFFEFF
H'FFFF00
Note: * Area 6 when the RAME bit is cleared.
Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT R-Mask Version, H8/3062FZTAT B-Mask Version, H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,
H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version) (1)
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Section 6 Bus Controller
Area 0
2 Mbytes
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 1
2 Mbytes
2 Mbytes
H'000000
2 Mbytes
H'1FFFFF
H'200000
H'3FFFFF
Area 2
2 Mbytes
H'5FFFFF
2 Mbytes
H'400000
Area 2
8 Mbytes
2 Mbytes
H'600000
Area 3
2 Mbytes
H'7FFFFF
2 Mbytes
H'800000
Area 4
2 Mbytes
2 Mbytes
H'9FFFFF
H'A00000
Area 5
2 Mbytes
Area 6
2 Mbytes
Area 3
2 Mbytes
Area 7
1.93 Mbytes
Area 4
1.93 Mbytes
Internal I/O registers (1)
Internal I/O registers (1)
2 Mbytes
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FEE000
H'FEE0FF
H'FEE100
Reserved 39.75 kbytes
H'FF7FFF
H'FF8000
Area 5
4 kbytes
H'FF8FFF
Area 6
23.75 kbytes
On-chip RAM
2 kbytes
On-chip RAM
2 kbytes*
Internal I/O registers (2)
Internal I/O registers (2)
Area 7
22 bytes
Area 7
22 bytes
(A) Memory map when RDEA = 1
(b) Memory map when RDEA = 0
H'FFEF1F
H'FFF720
2 Mbytes
Area 7
67.5 kbytes
Absolute
address 16 bits
H'FF9000
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Absolute
address 8 bits
H'FFFEFF
H'FFFF00
Note: * Area 6 when the RAME bit is cleared.
Figure 6.3 Memory Map in 16-Mbyte Mode
(H8/3060 Masked ROM Version, H8/3060 Masked ROM B-Mask Version) (2)
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Section 6 Bus Controller
Area 0
2 Mbytes
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 1
2 Mbytes
2 Mbytes
H'000000
H'1FFFFF
2 Mbytes
H'200000
H'3FFFFF
Area 2
2 Mbytes
H'5FFFFF
2 Mbytes
H'400000
Area 2
8 Mbytes
2 Mbytes
H'600000
Area 3
2 Mbytes
H'7FFFFF
2 Mbytes
H'800000
Area 4
2 Mbytes
H'9FFFFF
2 Mbytes
H'A00000
Area 5
2 Mbytes
H'BFFFFF
Area 6
2 Mbytes
Area 3
2 Mbytes
Area 7
1.93 Mbytes
Area 4
1.93 Mbytes
Internal I/O registers (1)
Internal I/O registers (1)
2 Mbytes
H'C00000
H'DFFFFF
H'E00000
H'FEE000
H'FEE0FF
H'FEE100
Reserved 39.75 kbytes
H'FF7FFF
H'FF8000
Area 6
19.75 kbytes
On-chip RAM
8 kbytes
On-chip RAM
8 kbytes*
Internal I/O registers (2)
Internal I/O registers (2)
Area 7
22 bytes
Area 7
22 bytes
(A) Memory map when RDEA = 1
(b) Memory map when RDEA = 0
H'FFDF1F
H'FFDF20
2 Mbytes
Area 7
63.5 kbytes
Absolute
address 16 bits
Area 5
4 kbytes
H'FF8FFF
H'FF9000
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Absolute
address 8 bits
H'FFFEFF
H'FFFF00
Note: * Area 6 when the RAME bit is cleared.
Figure 6.3 Memory Map in 16-Mbyte Mode
(H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version) (3)
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Section 6 Bus Controller
6.3.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states.
The bus width and number of access states for on-chip memory and registers are fixed, and are not
affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16bit access, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which two-state access is selected functions as a two-state access space, and an area for which
three-state access is selected functions as a three-state access space.
When two-state access space is designated, wait insertion is disabled.
Number of Program Wait States: When three-state access space is designated in ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
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Section 6 Bus Controller
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
WCRH/WCRL
ABWn
ASTn
Wn1
Wn0
Bus Width
Access States
Program Wait States
0
0
—
—
16
2
0
1
0
0
3
0
1
1
1
1
0
2
1
3
0
—
—
1
0
0
1
Bus Specifications (Basic Bus Interface)
8
2
0
3
0
1
1
0
2
1
3
Note: n = 0 to 7
6.3.3
Memory Interfaces
As its memory interface, the H8/3062 Group has only a basic bus interface that allows direct
connection of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows
direct connection of DRAM, or a burst ROM interface that allows direct connection of burst
ROM.
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Section 6 Bus Controller
6.3.4
Chip Select Signals
For each of areas 0 to 7, the H8/3062 Group can output a chip select signal (CS0 to CS7) that goes
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a CSn signal.
Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and
pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS0 to CS3 in the input state. To output chip select signals CS0 to CS3, the corresponding DDR
bits must be set to 1. For details, see section 7, I/O Ports.
Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals
CS4 to CS7, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
φ
Address bus
External address in area n
CSn
Figure 6.4
CSn Signal Output Timing (n = 0 to 7)
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS0 to CS7 remain
high. The CSn signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
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Section 6 Bus Controller
6.3.5
Address Output Method
The H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT B-mask version, H8/3062 masked ROM
version, H8/3061 masked ROM version, H8/3060 masked ROM version, and H8/3064F-ZTAT Bmask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask version,
H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version provide a
choice of two address update methods: either the same method as in the previous H8/300H Series
(address update mode 1), or a method in which address updating is restricted to external space
accesses (address update mode 2).
Figure 6.5 shows examples of address output in these two update modes.
On-chip
memory cycle
External
read cycle
On-chip
memory cycle
External
read cycle
On-chip
memory cycle
Address bus
(Address update
mode 1)
Address bus
(Address update
mode 2)
RD
Figure 6.5 Sample Address Output in Each Address Update Mode
(Basic Bus Interface, 3-State Space)
Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H
Series. Addresses are always updated between bus cycles.
Address Update Mode 2: In address update mode 2, address updating is performed only in
external space accesses. In this mode, the address can be retained between an external space read
cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory.
Address update mode 2 is therefore useful when connecting a device that requires address hold
time with respect to the rise of the RD strobe.
Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in
ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing
compatibility with the previous H8/300H Series.
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Section 6 Bus Controller
• When address update mode 2 is selected, the address in an internal space (on-chip memory or
internal I/O) access cycle is not output externally.
• In order to secure address holding with respect to the rise of RD, when address update mode 2
is used an external space read access must be completed within a single access cycle. For
example, in a word access to 8-bit access space, the bus cycle is split into two as shown in
figure 6.6., and so there is not a single access cycle. In this case, address holding is not
guaranteed at the rise of RD between the first (even address) and second (odd address) access
cycles (area inside the ellipse in the figure).
On-chip
memory cycle
Address update
mode 2
External read cycle
(8-bit space word access)
Even address
On-chip
memory cycle
Odd address
RD
Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2
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Section 6 Bus Controller
6.4
Basic Bus Interface
6.4.1
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.3).
6.4.2
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data
that can be accessed at one time is one byte: a word access is performed as two byte accesses, and
a longword access, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area)
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Section 6 Bus Controller
16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
• Even address
Byte size
• Odd address
Word size
Longword size
1st bus cycle
2nd bus cycle
Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)
6.4.3
Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
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Section 6 Bus Controller
Table 6.4
Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
8-bit access
area
Byte
Read
—
Write
—
16-bit access
area
Byte
Area
Read
Even
Valid
Strobe
RD
HWR
RD
Odd
Write
Even
Odd
Word
Read
—
Write
—
HWR
LWR
RD
HWR,
LWR
Upper Data Bus
(D15 to D8)
Lower Data Bus
(D7 to D0)
Valid
Invalid
Undetermined data
Valid
Invalid
Invalid
Valid
Valid
Undetermined data
Undetermined data Valid
Valid
Valid
Valid
Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4
Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width
is selected according to the operating mode.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS0 signal can be output.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 to 5.
Areas 1 to 6: In external expansion mode, areas 1 to 6 are entirely external space.
When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals respectively can be output.
The size of areas 1 to 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 to 5.
Area 7: Area 7 includes the on-chip RAM and registers. In external expansion mode, the space
excluding the on-chip RAM and registers is external space. The on-chip RAM is enabled when
the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to
0, the on-chip RAM is disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS7 signal can be output.
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 to 5.
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Section 6 Bus Controller
6.4.5
Basic Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The
LWR pin is always high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
D7 to D0
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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Section 6 Bus Controller
8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
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Section 6 Bus Controller
16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals
for a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in
accesses to even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait
states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
Even external address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
Odd external address in area n
CSn
AS
RD
Read access
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write access
D15 to D8
Undetermined data
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write access
D15 to D8
Valid
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
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Section 6 Bus Controller
16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to
even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot
be inserted.
Bus cycle
T1
T2
φ
Address bus
Even external address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
φ
Address bus
Odd external address in area n
CSn
AS
RD
Read access
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write access
D15 to D8
Undetermined data
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write access
D15 to D8
Valid
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access)
6.4.6
Wait Control
When accessing external space, the H8/3062 Group can extend the bus cycle by inserting wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in three-state access space, according to the settings
of WCRH and WCRL.
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Section 6 Bus Controller
Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the
WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the
WAIT pin is low at the falling edge of φ in the last T2 or TW state, another TW state is inserted. If
the WAIT pin is held low, TW states are inserted until it goes high.
This is useful when inserting four or more TW states, or when changing the number of TW states
for different external devices.
The WAITE bit setting applies to all areas.
Figure 6.17 shows an example of the timing for insertion of one program wait state in 3-state
space.
T1
Inserted
by program wait Inserted by WAIT pin
T2
Tw
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read access
Data bus
Read data
HWR, LWR
Write access
Data bus
Note:
Write data
indicates the timing of WAIT pin sampling.
Figure 6.17 Example of Wait State Insertion Timing
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Section 6 Bus Controller
6.5
Idle Cycle
6.5.1
Operation
When the H8/3062 Group chip accesses external space, it can insert a 1-state idle cycle (Ti)
between bus cycles in the following cases: when read accesses between different areas occur
consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle
cycle it is possible, for example, to avoid data collisions between ROM, which has a long output
floating time, and high-speed memory, I/O interfaces, and so on.
The initial value of the ICIS1 and ICIS0 bits in BCR is 1, so that idle cycle insertion is performed
in the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is
inserted, and a data collision is prevented.
Bus cycle A Bus cycle B
φ
T1
T2
T3
T1
Bus cycle A Bus cycle B
T2
φ
Address bus
Address bus
RD
RD
Data bus
Data bus
Data collision
Long buffer-off time
(a) Idle cycle not inserted
T1
T2
T3
Ti T1
(b) Idle cycle inserted
Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1)
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T2
Section 6 Bus Controller
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.19 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
Bus cycle A Bus cycle B
φ
T1
T2
T3
T1
Bus cycle A Bus cycle B
T2
φ
Address bus
Address bus
RD
RD
HWR
HWR
Data bus
Data bus
Long buffer-off time
(a) Idle cycle not inserted
T1
T2
T3
Ti T1
T2
Data collision
(b) Idle cycle inserted
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion) of CSn may occur simultaneously. Figure 6.20 shows an example of the operation in
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of RD in the first read cycle and assertion of CSn in the following bus cycle
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CSn low output in the following
bus cycle will overlap.
As long as RD and CSn do not change simultaneously, or if there is no problem even if they do,
non-insertion of an idle cycle can be specified.
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Section 6 Bus Controller
Bus cycle A Bus cycle B
φ
T1
T2
T3
T1
Bus cycle A Bus cycle B
T2
φ
Address bus
Address bus
RD
RD
CSn
CSn
T1
T2
T3
Ti T1
Simultaneous change of RD and
CSn: possibility of mutual overlap
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.20 Example of Idle Cycle Operation
6.5.2
Pin States in Idle Cycle
Table 6.5 shows the pin states in an idle cycle.
Table 6.5
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Next cycle address value
D15 to D0
High impedance
CSn
AS
RD
HWR
LWR
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High
High
High
High
High
T2
Section 6 Bus Controller
6.6
Bus Arbiter
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus
master can be either the CPU or an external bus master. When a bus master has the bus right it can
carry out read and write operations. Each bus master uses a bus request signal to request the bus
right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to
grant the bus to a bus master, which can the operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master. When two or more bus masters request the bus,
the highest-priority bus master receives an acknowledge signal. The bus master that receives an
acknowledge signal can continue to use the bus until the acknowledge signal is deactivated.
The bus master priority order is:
(High)
External bus master > CPU
(Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
6.6.1
Operation
CPU: The CPU is the lowest-priority bus master. If an external bus master requests the bus while
the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it.
The bus right is transferred at the following times:
• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
• If another bus master requests the bus while the CPU is performing internal operations, such as
executing a multiply or divide instruction, the bus right is transferred immediately. The CPU
continues its internal operations.
• If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
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Section 6 Bus Controller
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it
keeps the bus until the BREQ signal goes high. While the bus is released to an external bus
master, the H8/3062 Group chip holds the address bus, data bus, bus control signals (AS, RD,
HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds
the BACK pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the
bus-release cycle.
Figure 6.21 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
BREQ signal goes low until the bus is released.
CPU cycles
T0
φ
T1
External bus released
High-impedance
Address
Address bus
CPU cycles
T2
High-impedance
Data bus
High-impedance
AS
RD
High-impedance
High
High-impedance
HWR, LWR
BREQ
BACK
Minimum 3 cycles
(1)
(2)
(3)
(4)
(5)
(6)
Figure 6.21 Example of External Bus Master Operation
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Section 6 Bus Controller
When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
6.7
Register and Pin Input Timing
6.7.1
Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address bus
ASTCR address
3-state access to area 0
2-state access to area 0
Figure 6.22 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of
the DDR write cycle. Figure 6.23 shows the timing when the CS1 pin is changed from generic
input to CS1 output.
T1
T2
T3
φ
Address bus
P8DDR address
CS1
High-impedance
Figure 6.23 DDR Write Timing
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Section 6 Bus Controller
BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and
generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure
6.24 shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output.
T1
T2
T3
φ
Address bus
BRCR address
PA7 to PA4
(A23 to A20)
High-impedance
Figure 6.24 BRCR Write Timing
6.7.2
BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
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If
Section 7 I/O Ports
Section 7 I/O Ports
7.1
Overview
The H8/3062 Group has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one inputonly port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed
as shown in table 7.1.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for storing output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up
control register (PCR) for switching input pull-up transistors on and off.
Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can
drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington
pair. Ports 1, 2, and 5 can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0 have
Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
Table 7.1
Port Functions
Single-Chip
Modes
Expanded Modes
Port
Description
Port 1 • 8-bit I/O
port
Pins
P17 to P10/
A7 to A0
Mode 1 Mode 2 Mode 3 Mode 4
Address output pins (A7 to A0)
• Can drive
LEDs
Mode 5
Mode 6 Mode 7
Address output Generic input/
(A7 to A0) and output
generic input
DDR = 0:
generic input
DDR = 1:
address output
Port 2 • 8-bit I/O
port
P27 to P20/
A15 to A8
Address output pins (A15 to A8)
• Built-in
input
pull-up
transistors
DDR = 0:
generic input
DDR = 1:
address output
• Can drive
LEDs
Port 3 • 8-bit I/O
port
Address output Generic input/
(A15 to A8) and output
generic input
P37 to P30/
D15 to D8
Data input/output (D15 to D8)
Generic input/
output
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Section 7 I/O Ports
Single-Chip
Modes
Expanded Modes
Port
Description
Port 4 • 8-bit I/O
port
Pins
P47 to P40/
D7 to D0
• Built-in
input
pull-up
transistors
Port 5 • 4-bit I/O
port
Mode 1 Mode 2 Mode 3 Mode 4
Mode 6 Mode 7
Generic input/
output
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
P53 to P50/
A19 to A16
Address output (A19 to A16)
• Built-in
input
pull-up
transistors
Address output Generic input/
(A19 to A16) and output
4-bit generic
input
DDR = 0:
generic input
• Can drive
LEDs
Port 6 • 8-bit I/O
port
Mode 5
Data input/output (D7 to D0) and 8-bit generic
input/output
DDR = 1:
address output
P67/φ
Clock output (φ) and generic input
P66/LWR
Bus control signal output (LWR, HWR, RD, AS)
Generic input/
output
Bus control signal input/output (BACK, BREQ, WAIT)
and 3-bit generic input/output
Generic input/
output
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
Port 7 • 8-bit I/O
port
P77/AN7/
DA1
Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from
D/A converter, and generic input
P76/AN6/
DA0
Port 8 • 5-bit I/O
port
• P82 to P80
have
Schmitt
inputs
P75 to P70/
AN5 to AN0
Analog input (AN5 to AN0) to A/D converter, and generic input
P84/CS0
DDR = 0: generic input
DDR = 1 (after reset): CS0 output
DDR = 0 (after
reset): generic
input
Generic input/
output
DDR = 1: CS0
output
IRQ3 input, CS1 output, external trigger input (ADTRG)
P83/IRQ3/
CS1/ADTRG to A/D converter, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS1 output
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IRQ3 input,
external trigger
input (ADTRG) to
A/D converter,
and generic
input/output
Section 7 I/O Ports
Single-Chip
Modes
Expanded Modes
Port
Description
Port 8 • 5-bit I/O
port
• P82 to P80
have
Schmitt
inputs
Port 9 • 6-bit I/O
port
Pins
P82/IRQ2/
Mode 1 Mode 2 Mode 3 Mode 4
Mode 5
Mode 6 Mode 7
IRQ2 and IRQ1 input, CS2 and CS3 output, and generic IRQ2 and IRQ1
CS2
input
P81/IRQ1/
DDR = 0 (after reset): generic input
input and generic
input/output
CS3
DDR = 1: CS2 and CS3 output
P80/IRQ0
IRQ0 input, and generic input/output
P95/IRQ5 /
SCK1
Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial
communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-bit
generic input/output
P94/IRQ4 /
SCK0
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Port A • 8-bit I/O
port
PA7/TP7/
TIOCB2/A20
Output (TP7) from Address output
(A20)
pro-grammable
timing pattern
controller (TPC),
input or output
(TIOCB2) for 16-bit
timer and generic
input/
output
PA6/TP6/
TIOCA2/A21
PA4/TP4/
TIOCA1/A23
TPC output (TP6
to TP4), 16-bit
timer input and
output (TIOCA2,
TIOCB1, TIOCA1),
and generic
input/output
PA3/TP3/
TIOCB0/
TCLKD
TPC output (TP3 to TP0), 16-bit timer input and output (TIOCB0, TIOCA0,
TCLKD, TCLKC, TCLKB, TCLKA), 8-bit timer input (TCLKD, TCLKC,
TCLKB, TCLKA), and generic input/output
• Schmitt
inputs
PA5/TP5/
TIOCB1/A22
Address output
(A20), TPC
output (TP7),
input or output
(TIOCB2) for
16-bit timer,
and generic
input/output
TPC output (TP6 to TP4),16-bit
timer input and output (TIOCA2,
TIOCB1, TIOCA1), address output
(A23 to A21), and generic input/
output
TPC output (TP7),
16-bit timer input
or output
(TIOCB2), and
generic
input/output
TPC output (TP6
to TP4), 16-bit
timer input and
output (TIOCA2,
TIOCB1, TIOCA1)
and generic
input/output
PA2/TP2/
TIOCA0/
TCLKC
PA1/TP1/
TCLKB
PA0/TP0/
TCLKA
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Section 7 I/O Ports
Single-Chip
Modes
Expanded Modes
Port
Description
Port B • 8-bit I/O
port
Pins
PB7/TP15
Mode 1 Mode 2 Mode 3 Mode 4
Mode 5
Mode 6 Mode 7
TPC output (TP15 to TP12) and generic input/output
PB6/TP14
PB5/TP13
PB4/TP12
PB3/TP11/
TMIO3/CS4
PB2/TP10/
TMO2/CS5
TPC output (TP11 to TP8), 8-bit timer input and output
(TMIO3, TMO2, TMIO1, TMO0), CS7 to CS4 output, and
generic input/output
PB1/TP9/
TMIO1/CS6
PB0/TP8/
TMO0/CS7
Legend:
SCI0 :
16TIM :
SCI1 :
8TIM :
TPC :
Serial communication interface channel 0
16-bit timer
Serial communication interface channel 1
8-bit timer
Programmable timing pattern controller
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TPC output (TP11
to TP8), 8-bit timer
input and output
(TMIO3, TMO2,
TMIO1, TMO0),
and generic
input/output
Section 7 I/O Ports
7.2
Port 1
7.2.1
Overview
Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown
in figure 7.1. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded
modes with on-chip ROM disabled), they are address bus output pins (A7 to A0).
In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction
register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input. In modes 6
and 7 (single-chip mode), port 1 is a generic input/output port.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 1 pins
Port 1
Modes 1 to 4
Mode 5
Modes 6 and 7
P17 /A 7
A 7 (output)
P17 (input)/A 7 (output)
P17 (input/output)
P16 /A 6
A 6 (output)
P16 (input)/A 6 (output)
P16 (input/output)
P15 /A 5
A 5 (output)
P15 (input)/A 5 (output)
P15 (input/output)
P14 /A 4
A 4 (output)
P14 (input)/A 4 (output)
P14 (input/output)
P13 /A 3
A 3 (output)
P13 (input)/A 3 (output)
P13 (input/output)
P12 /A 2
A 2 (output)
P12 (input)/A 2 (output)
P12 (input/output)
P11 /A 1
A 1 (output)
P11 (input)/A 1 (output)
P11 (input/output)
P10 /A 0
A 0 (output)
P10 (input)/A 0 (output)
P10 (input/output)
Figure 7.1 Port 1 Pin Configuration
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Section 7 I/O Ports
7.2.2
Register Descriptions
Table 7.2 summarizes the registers of port 1.
Table 7.2
Port 1 Registers
Initial Value
Address*
Name
Abbreviation R/W
Modes 1 to 4
Modes 5 to 7
H'EE000
Port 1 data direction register P1DDR
W
H'FF
H'00
H'FFFD0
Port 1 data register
R/W
H'00
H'00
P1DR
Note: * Lower 20 bits of the address in advanced mode
Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select
input or output for each pin in port 1.
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 1 data direction 7 to 0
These bits select input or
output for port 1 pins
• Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled)
P1DDR values are fixed at 1. Port 1 functions as an address bus.
• Mode 5 (Expanded Modes with On-Chip ROM Enabled)
After a reset, port 1 functions as an input port. A pin in port 1 becomes an address output pin if
the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0.
• Modes 6 and 7 (Single-Chip Mode)
Port 1 functions as an input/output port. A pin in port 1 becomes an output port if the
corresponding P1DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P1DDR bits are always read as 1, and cannot be modified.
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Section 7 I/O Ports
In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P1DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in
hardware standby mode. In sofware standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 1 is functioning as an input/output port and
a P1DDR bit is set to 1, the corresponding pin maintains its output state.
Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores port 1
output data. When port 1 functions as an output port, the value of this register is output. When
this register is read, the pin logic level is read for bits for which the P1DDR setting is 0, and the
P1DR value is read for bits for which the P1DDR setting is 1.
Bit
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 data 7 to 0
These bits store data for port 1 pins
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
7.3
Port 2
7.3.1
Overview
Port 2 is an 8-bit input/output port which also has an address output function. It’s pin
configuration is shown in figure 7.2. The pin functions differ according to the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus
output pins (A15 to A8). In mode 5 (expanded modes with on-chip ROM enabled), settings in the
port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or
generic input. In modes 6 and 7 (single-chip mode), port 2 is a generic input/output port.
Port 2 has software-programmable built-in pull-up transistors.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 2
Port 2 pins
Modes 1 to 4
Mode 5
Modes 6 and 7
P27 /A 15
A15 (output)
P27 (input)/A15 (output)
P27 (input/output)
P26 /A 14
A14 (output)
P26 (input)/A14 (output)
P26 (input/output)
P25 /A 13
A13 (output)
P25 (input)/A13 (output)
P25 (input/output)
P24 /A 12
A12 (output)
P24 (input)/A12 (output)
P24 (input/output)
P23 /A 11
A11 (output)
P23 (input)/A11 (output)
P23 (input/output)
P22 /A 10
A10 (output)
P22 (input)/A10 (output)
P22 (input/output)
P21 /A 9
A9 (output)
P21 (input)/A9 (output)
P21 (input/output)
P20 /A 8
A8 (output)
P20 (input)/A8 (output)
P20 (input/output)
Figure 7.2 Port 2 Pin Configuration
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Section 7 I/O Ports
7.3.2
Register Descriptions
Table 7.3 summarizes the registers of port 2.
Table 7.3
Port 2 Registers
Initial Value
Address* Name
Abbreviation R/W
Modes 1 to 4 Modes 5 to 7
H'EE001
Port 2 data direction register
P2DDR
W
H'FF
H'00
H'FFFD1
Port 2 data register
P2DR
R/W
H'00
H'00
H'EE03C
Port 2 input pull-up MOS control
register
P2PCR
R/W
H'00
H'00
Note: * Lower 20 bits of the address in advanced mode
Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select
input or output for each pin in port 2.
Bit
7
6
5
4
3
2
1
0
P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
• Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled)
P2DDR values are fixed at 1. Port 2 functions as an address bus.
• Mode 5 (Expanded Modes with On-Chip ROM Enabled)
Following a reset, port 2 is an input port. A pin in port 2 becomes an address output pin if the
corresponding P2DDR bit is set to 1, and a generic input port if this bit is cleared to 0.
• Modes 6 and 7 (Single-Chip Mode)
Port 2 functions as an input/output port. A pin in port 2 becomes an output port if the
corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0.
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Section 7 I/O Ports
In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified.
In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 2 is functioning as an input/output port and
a P2DDR bit is set to 1, the corresponding pin maintains its output state.
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data
for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit
in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a
bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read.
Bit
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 2.
Bit
7
6
5
4
3
2
1
0
P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 input pull-up MOS control 7 to 0
These bits control input pull-up
transistors built into port 2
In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P2PCR is set to 1, the input pull-up transistor is turned on.
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Section 7 I/O Ports
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 7.4 summarizes the states of the input pull-ups in each mode.
Table 7.4
Input Pull-Up Transistor States (Port 2)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
Other Modes
1
2
3
4
Off
Off
Off
Off
5
6
7
Off
Off
On/off
On/off
Legend:
Off
: The input pull-up transistor is always off.
On/off : The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.
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Section 7 I/O Ports
7.4
Port 3
7.4.1
Overview
Port 3 is an 8-bit input/output port which also functions as a data bus. It’s pin configuration is
shown in figure 7.3. Port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic
input/output port in modes 6 and 7 (single-chip mode).
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 3
Port 3 pins
Modes 1 to 5
Modes 6 and 7
P37 /D15
D15 (input/output)
P37 (input/output)
P36 /D14
D14 (input/output)
P36 (input/output)
P35 /D13
D13 (input/output)
P35 (input/output)
P34 /D12
D12 (input/output)
P34 (input/output)
P33 /D11
D11 (input/output)
P33 (input/output)
P32 /D10
D10 (input/output)
P32 (input/output)
P31 /D9
D9 (input/output)
P31 (input/output)
P30 /D8
D8 (input/output)
P30 (input/output)
Figure 7.3 Port 3 Pin Configuration
7.4.2
Register Descriptions
Table 7.5 summarizes the registers of port 3.
Table 7.5
Port 3 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE002
Port 3 data direction register
P3DDR
W
H'00
H'FFFD2
Port 3 data register
P3DR
R/W
H'00
Note: * Lower 20 bits of the address in advanced mode
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Section 7 I/O Ports
Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select
input or output for each pin in port 3.
Bit
7
6
5
4
3
2
1
0
P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 data direction 7 to 0
These bits select input or output for port 3 pins
• Modes 1 to 5 (Expanded Modes)
Port 3 functions as a data bus, regardless of the P3DDR settings.
• Modes 6 and 7 (Single-Chip Mode)
Port 3 functions as an input/output port. A pin in port 3 becomes an output port if the
corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0.
P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port 3 is functioning as an input/output port and a P3DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 3 Data Register (P3DR): P3DR is an 8-bit readable/writable register that stores output data
for port 3. When port 3 functions as an output port, the value of this register is output. When a bit
in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned. When a
bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin logic level is read.
Bit
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 data 7 to 0
These bits store data for port 3 pins
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
7.5
Port 4
7.5.1
Overview
Port 4 is an 8-bit input/output port which also functions as a data bus. It’s pin configuration is
shown in figure 7.4. The pin functions differ depending on the operating mode.
In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates
areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic
input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip
operates in 16-bit bus mode and port 4 becomes part of the data bus. In modes 6 and 7 (single-chip
mode), port 4 is a generic input/output port.
Port 4 has software-programmable built-in pull-up transistors.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 4
Port 4 pins
Modes 1 to 5
Modes 6 and 7
P47 /D7
P47 (input/output)/D7 (input/output)
P47 (input/output)
P46 /D6
P46 (input/output)/D6 (input/output)
P46 (input/output)
P45 /D5
P45 (input/output)/D5 (input/output)
P45 (input/output)
P44 /D4
P44 (input/output)/D4 (input/output)
P44 (input/output)
P43 /D3
P43 (input/output)/D3 (input/output)
P43 (input/output)
P42 /D2
P42 (input/output)/D2 (input/output)
P42 (input/output)
P41 /D1
P41 (input/output)/D1 (input/output)
P41 (input/output)
P40 /D0
P40 (input/output)/D0 (input/output)
P40 (input/output)
Figure 7.4 Port 4 Pin Configuration
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Section 7 I/O Ports
7.5.2
Register Descriptions
Table 7.6 summarizes the registers of port 4.
Table 7.6
Address*
Port 4 Registers
Name
Abbreviation
R/W
Initial Value
H'EE003
Port 4 data direction register
P4DDR
W
H'00
H'FFFD3
Port 4 data register
P4DR
R/W
H'00
H'EE03E
Port 4 input pull-up MOS control
register
P4PCR
R/W
H'00
Note: * Lower 20 bits of the address in advanced mode
Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select
input or output for each pin in port 4.
Bit
7
6
5
4
3
2
1
0
P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 4 data direction 7 to 0
These bits select input or output for port 4 pins
• Modes 1 to 5 (Expanded Modes)
When all areas are designated as 8-bit-access areas by the bus controller’s bus width control
register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this
case, a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an
input port if this bit is cleared to 0.
When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4
functions as part of the data bus, regardless of the P4DDR settings.
• Modes 6 and 7 (Single-Chip Mode)
Port 4 functions as an input/output port. A pin in port 4 becomes an output port if the
corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0.
P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
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Section 7 I/O Ports
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is
made to software standby mode while port 4 is functioning as an input/output port and a P4DDR
bit is set to 1, the corresponding pin maintains its output state.
Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data
for port 4. When port 4 functions as an output port, the value of this register is output. When a bit
in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a
bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read.
Bit
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 data 7 to 0
These bits store data for port 4 pins
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 4.
Bit
7
6
5
4
3
2
1
0
P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 input pull-up MOS control 7 to 0
These bits control input pull-up transistors built into port 4
In modes 6 and 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 5 (expanded modes),
when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set
to 1, the input pull-up transistor is turned on.
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Section 7 I/O Ports
P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 7.7 summarizes the states of the input pull-up MOS in each operating mode.
Table 7.7
Input Pull-Up Transistor States (Port 4)
Mode
1 to 5
8-bit bus mode
16-bit bus mode
6 and 7
Reset
Hardware
Standby Mode
Off
Off
Software
Standby Mode
Other Modes
On/off
On/off
Off
Off
On/off
On/off
Legend:
Off
: The input pull-up transistor is always off.
On/off : The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
Rev. 6.00 Mar 18, 2005 page 185 of 970
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Section 7 I/O Ports
7.6
Port 5
7.6.1
Overview
Port 5 is a 4-bit input/output port which also has an address output function. It’s pin configuration
is shown in figure 7.5. The pin functions differ depending on the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output
pins (A19 to A16). In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 5
data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic
input. In modes 6 and 7 (single-chip mode), port 5 is a generic input/output port.
Port 5 has software-programmable built-in pull-up transistors.
Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 5
Port 5
pins
Modes 1 to 4
Mode 5
Modes 6 and 7
P53 /A 19
A19 (output)
P5 3 (input)/A19 (output)
P5 3 (input/output)
P52 /A 18
A18 (output)
P5 2 (input)/A18 (output)
P5 2 (input/output)
P51 /A 17
A17 (output)
P5 1 (input)/A17 (output)
P5 1 (input/output)
P50 /A 16
A16 (output)
P5 0 (input)/A16 (output)
P5 0 (input/output)
Figure 7.5 Port 5 Pin Configuration
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Section 7 I/O Ports
7.6.2
Register Descriptions
Table 7.8 summarizes the registers of port 5.
Table 7.8
Port 5 Registers
Initial Value
Address* Name
Abbreviation
R/W Modes 1 to 4 Modes 5 to 7
H'EE004
Port 5 data direction register
P5DDR
W
H'FF
H'F0
H'FFFD4
Port 5 data register
P5DR
R/W H'F0
H'F0
H'EE03F
Port 5 input pull-up MOS control
register
P5PCR
R/W H'F0
H'F0
Note: * Lower 20 bits of the address in advanced mode
Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select
input or output for each pin in port 5.
Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.
Bit
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
7
6
5
4
—
—
—
—
3
2
1
0
P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
1
1
1
1
0
0
0
0
—
—
—
—
W
W
W
W
Reserved bits
Port 5 data direction 3 to 0
These bits select input or
output for port 5 pins
• Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled)
P5DDR values are fixed at 1. Port 5 functions as an address bus output.
• Mode 5 (Expanded Modes with On-Chip ROM Enabled)
Following a reset, port 5 is an input port. A pin in port 5 becomes an address output pin if the
corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.
• Modes 6 and 7 (Single-Chip Mode)
Port 5 functions as an input/output port. A pin in port 5 becomes an output port if the
corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.
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Section 7 I/O Ports
In modes 1 to 4, P5DDR bits are always read as 1, and cannot be modified.
In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 5 is functioning as an input/output port and
a P5DDR bit is set to 1, the corresponding pin maintains its output state.
Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores output data
for port 5. When port 5 functions as an output port, the value of this register is output. When a bit
in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned. When a
bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin logic level is read.
Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P53
P52
P51
P50
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Port 5 data 3 to 0
These bits store data
for port 5 pins
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 6.00 Mar 18, 2005 page 188 of 970
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Section 7 I/O Ports
Port 5 Input Pull-Up MOS Control Register (P5PCR): P5PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 5.
Bits 7 to 4 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
4
—
—
—
—
2
3
1
0
P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Port 5 input pull-up MOS control 3 to 0
These bits control input pull-up
transistors built into port 5
In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P5PCR is set to 1, the input pull-up transistor is turned on.
P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
Table 7.9 summarizes the states of the input pull-ups in each mode.
Table 7.9
Input Pull-Up Transistor States (Port 5)
Mode
Reset
Hardware Standby Mode
Software Standby Mode
Other Modes
1
2
3
4
Off
Off
Off
Off
5
6
7
Off
Off
On/off
On/off
Legend:
Off
: The input pull-up transistor is always off.
On/off : The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.
Rev. 6.00 Mar 18, 2005 page 189 of 970
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Section 7 I/O Ports
7.7
Port 6
7.7.1
Overview
Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals
(LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output.
The port 6 pin configuration is shown in figure 7.6.
See table 7.11 for the selection of the pin functions.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 6 pins
P6 7 / φ
Port 6
Modes 6 and 7
(single-chip mode)
Modes 1 to 5
(expanded modes)
P67 (input)/ φ
(output)
P6 7 (input) / φ(output)
P6 6 / LWR
LWR (output)
P6 6 (input/output)
P6 5 / HWR
HWR (output)
P6 5 (input/output)
P6 4 / RD
RD
(output)
P6 4 (input/output)
P6 3 / AS
AS
(output)
P6 3 (input/output)
P6 2 / BACK
P62 (input/output) BACK (output)
P6 2 (input/output)
P6 1 / BREQ
P61 (input/output)/ BREQ (input)
P6 1 (input/output)
P6 0 / WAIT
P60 (input/output)/ WAIT (input)
P6 0 (input/output)
Figure 7.6 Port 6 Pin Configuration
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Section 7 I/O Ports
7.7.2
Register Descriptions
Table 7.10 summarizes the registers of port 6.
Table 7.10 Port 6 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE005
Port 6 data direction register
P6DDR
W
H'80
H'FFFD5
Port 6 data register
P6DR
R/W
H'80
Note: * Lower 20 bits of the address in advanced mode
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bit 7 is reserved. It is fixed at 1, and cannot be modified.
Bit
7
—
6
5
4
3
2
1
0
P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
W
W
W
W
W
W
W
Reserved bit
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
• Modes 1 to 5 (Expanded Modes)
P67 functions as the clock output pin (φ) or an input port. P67 is the clock output pin (φ) if the
PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1.
P66 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
settings of bits P66DDR to P63DDR.
P62 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or
input/output ports. For the method of selecting the pin functions, see table 7.11.
When P62 to P60 function as input/output ports, the pin becomes an output port if the
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
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Section 7 I/O Ports
• Modes 6 and 7 (Single-Chip Mode)
P67 functions as the clock output pin (φ) or an input port. P66 to P60 function as generic
input/output ports. P67 is the clock output pin (φ) if the PSTOP bit in MSTCRH is cleared to 0
(initial value), and an input port if this bit is set to 1. A pin in port 6 becomes an output port if
the corresponding bit of P66DDR to P60DDR is set to 1, and an input port if this pin is cleared
to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port 6 is functioning as an input/output port and a P6DDR bit is set to 1, the
corresponding pin maintains its output state.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P67 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
Bit
7
6
5
4
3
2
1
0
P67
P6 6
P6 5
P6 4
P6 3
P6 2
P6 1
P6 0
Initial value
1
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 6 data 7 to 0
These bits store data for port 6 pins
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
Table 7.11 Port 6 Pin Functions in Modes 1 to 5
Pin
Pin Functions and Selection Method
P67/φ
Bit PSTOP in MSTCRH selects the pin function.
PSTOP
Pin function
LWR
0
1
φ output
P67 input
Functions as LWR regardless of the setting of bit P66DDR.
P66DDR
0
1
LWR output
Pin function
HWR
Functions as HWR regardless of the setting of bit P65DDR.
P65DDR
0
HWR output
Pin function
RD
1
Functions as RD regardless of the setting of bit P64DDR.
P64DDR
0
1
RD output
Pin function
AS
Functions as AS regardless of the setting of bit P63DDR.
P63DDR
0
1
AS output
Pin function
P62/BACK
Bit BRLE in BRCR and bit P62DDR select the pin function as follows.
BRLE
P62DDR
Pin function
P61/BREQ
0
1
0
1
—
P62 input
P62 output
BACK output
Bit BRLE in BRCR and bit P61DDR select the pin function as follows.
BRLE
P61DDR
Pin function
0
1
0
1
—
P61 input
P61 output
BREQ input
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Section 7 I/O Ports
Pin
Pin Functions and Selection Method
P60/WAIT
Bit WAITE in BCR and bit P60DDR select the pin function as follows.
WAITE
0
1
P60DDR
0
1
0*
Pin function
P60 input
P60 output
WAIT input
Note: * Do not set bit P60DDR to 1.
7.8
Port 7
7.8.1
Overview
Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog
output from the D/A converter. The pin functions are the same in all operating modes. Figure 7.7
shows the pin configuration of port 7.
See section 14, A/D Converter, for details of the A/D converter analog input pins, and section 15,
D/A Converter, for details of the D/A converter analog output pins.
Port 7 pins
P77 (input)/AN 7 (input)/DA 1 (output)
P76 (input)/AN 6 (input)/DA 0 (output)
P75 (input)/AN 5 (input)
Port 7
P74 (input)/AN 4 (input)
P73 (input)/AN 3 (input)
P72 (input)/AN 2 (input)
P71 (input)/AN 1 (input)
P70 (input)/AN 0 (input)
Figure 7.7 Port 7 Pin Configuration
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Section 7 I/O Ports
7.8.2
Register Description
Table 7.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction
register.
Table 7.12 Port 7 Data Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFFD6
Port 7 data register
P7DR
R
Undetermined
Note: * Lower 20 bits of the address in advanced mode
Port 7 Data Register (P7DR)
Bit
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note: * Determined by pins P77 to P70.
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
7.9
Port 8
7.9.1
Overview
Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, IRQ3 to IRQ0 input, and
A/D converter ADTRG input. Figure 7.8 shows the pin configuration of port 8.
In modes 1 to 5 (expanded modes), port 8 can provide CS3 to CS0 output, IRQ3 to IRQ0 input, and
ADTRG input. See table 7.14 for the selection of pin functions in expanded modes.
In modes 6 and 7 (single-chip modes), port 8 can provide IRQ3 to IRQ0 input and ADTRG input.
See table 7.15 for the selection of pin functions in single-chip mode.
See section 14, A/D Converter, for a description of the A/D converter’s ADTRG input pin.
The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for
input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
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Section 7 I/O Ports
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Pins P82 to P80 have Schmitt-trigger inputs.
Port 8
Port 8 pins
Pin functions in modes 1 to 5
(expanded modes)
P84 / CS 0
P84 (input)/ CS 0 (output)
P83 / CS 1 / IRQ 3 / ADTRG
P83 (input)/ CS 1 (output)/ IRQ 3 (input) / ADTRG (input)
P82 / CS 2 / IRQ 2
P82 (input)/ CS 2 (output)/ IRQ 2 (input)
P81 / CS 3 / IRQ 1
P81 (input)/ CS 3 (output)/ IRQ 1 (input)
P80 / IRQ 0
P80 (input/output)/ IRQ 0 (input)
Pin functions in modes 6 and 7
(single-chip mode)
P84 /(input/output)
P83 /(input/output)/ IRQ 3 (input) / ADTRG (input)
P82 /(input/output)/ IRQ 2 (input)
P81 /(input/output)/ IRQ 1 (input)
P80 /(input/output)/ IRQ 0 (input)
Figure 7.8 Port 8 Pin Configuration
7.9.2
Register Descriptions
Table 7.13 summarizes the registers of port 8.
Table 7.13 Port 8 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Mode 1 to 4
Mode 5 to 7
H'EE007
Port 8 data direction
register
P8DDR
W
H'F0
H'E0
H'FFFD7
Port 8 data register
P8DR
R/W
H'E0
H'E0
Note: * Lower 20 bits of the address in advanced mode
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Section 7 I/O Ports
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
—
—
—
4
3
2
1
0
P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR
Modes Initial value
1 to 4 Read/Write
1
1
1
1
0
0
0
0
—
—
—
W
W
W
W
W
Modes Initial value
5 to 7 Read/Write
1
1
1
0
0
0
0
0
—
—
—
W
W
W
W
W
Reserved bits
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
• Modes 1 to 5 (Expanded Modes)
When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in
P8DDR are cleared to 0, the corresponding pins become input ports.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P84 functions
as the CS0 output, while CS1 to CS3 are input ports. In mode 5 (expanded mode with on-chip
ROM enabled), following a reset CS0 to CS3 are all input ports.
• Modes 6 and 7 (Single-Chip Mode)
Port 8 is a generic input/output port. A pin in port 8 becomes an output port if the
corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore,
if a transition is made to software standby mode while port 8 is functioning as an input/output port
and a P8DDR bit is set to 1, the corresponding pin maintains its output state.
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Section 7 I/O Ports
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When port 8 functions as an output port, the value of this register is output. When a bit
in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned. When
a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin logic level is read.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
4
3
2
1
0
—
—
—
P84
P83
P82
P81
P80
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
Table 7.14 Port 8 Pin Functions in Modes 1 to 5
Pin
Pin Functions and Selection Method
P84/CS0
Bit P84DDR selects the pin function as follows.
P84DDR
Pin function
P83/CS1/IRQ3/
ADTRG
0
1
P84 input
CS0 output
Bit P83DDR selects the pin function as follows
P83DDR
Pin function
0
1
P83 input
CS1 output
IRQ3 input
ADTRG input
P82/CS2/IRQ2
Bit P82DDR selects the pin function as follows.
P82DDR
Pin function
0
1
P82 input
CS2 output
IRQ2 input
P81/CS3/IRQ1
Bit P81DDR selects the pin function as follows.
P81DDR
Pin function
0
1
P81 input
CS3 output
IRQ1 input
P80/IRQ0
Bit P80DDR selects the pin function as follows.
P80DDR
Pin function
0
1
P80 input
P80 output
IRQ0 input
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Section 7 I/O Ports
Table 7.15 Port 8 Pin Functions in Modes 6 and 7
Pin
Pin Functions and Selection Method
P84
Bit P84DDR selects the pin function as follows.
P84DDR
Pin function
P83/IRQ3/ADTRG
0
1
P84 input
P84 output
Bit P83DDR selects the pin function as follows.
P83DDR
Pin function
0
1
P83 input
P83 output
IRQ3 input
ADTRG input
P82/IRQ2
Bit P82DDR selects the pin function as follows.
P82DDR
Pin function
0
1
P82 input
P82 output
IRQ2 input
P81/IRQ1
Bit P81DDR selects the pin function as follows.
P81DDR
Pin function
0
1
P81 input
P81 output
IRQ1 input
P80/IRQ0
Bit P80DDR select the pin function as follows.
P80DDR
Pin function
0
1
P80 input
P80 output
IRQ0 input
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Section 7 I/O Ports
7.10
Port 9
7.10.1
Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,
SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5
and IRQ4 input. See table 7.17 for the selection of pin functions.
The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used
for input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
Port 9 has the same set of pin functions in all operating modes. Figure 7.9 shows the pin
configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 9 pins
P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input)
P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input)
Port 9
P93 (input/output)/RxD1 (input)
P92 (input/output)/RxD0 (input)
P91 (input/output)/TxD1 (output)
P90 (input/output)/TxD0 (output)
Figure 7.9 Port 9 Pin Configuration
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Section 7 I/O Ports
7.10.2
Register Descriptions
Table 7.16 summarizes the registers of port 9.
Table 7.16 Port 9 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE008
Port 9 data direction register
P9DDR
W
H'C0
H'FFFD8
Port 9 data register
P9DR
R/W
H'C0
Note: * Lower 20 bits of the address in advanced mode
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
—
—
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
5
4
3
2
1
0
P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR
Reserved bits
Port 9 data direction 5 to 0
These bits select input or
output for port 9 pins
When port 9 functions as an input/output port, a pin in port 9 becomes an output port if the
corresponding P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For the method of
selecting the pin functions, see table 7.17.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port 9 is functioning as an input/output port and a P9DDR bit is set to 1, the corresponding pin
maintains its output state.
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Section 7 I/O Ports
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data
for port 9. When port 9 functions as an output port, the value of this register is output. When a bit
in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a
bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read.
Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified.
Bit
7
6
5
4
3
2
1
0
—
—
P95
P94
P93
P92
P91
P90
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 9 data 5 to 0
These bits store data
for port 9 pins
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
Table 7.17 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P95/SCK1/IRQ5
Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR
select the pin function as follows.
CKE1
0
C/A
0
CKE0
P95DDR
Pin function
1
0
1
—
1
—
—
0
1
—
—
—
P95
input
P95
output
SCK1
output
SCK1
output
SCK1
input
IRQ5 input
P94/SCK0/IRQ4
Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR
select the pin function as follows.
CKE1
0
C/A
0
CKE0
P94DDR
Pin function
1
0
1
—
1
—
—
0
1
—
—
—
P94
input
P94
output
SCK0
output
SCK0
output
SCK0
input
IRQ4 input
P93/RxD1
Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin
function as follows.
SMIF
0
RE
P93DDR
Pin function
Rev. 6.00 Mar 18, 2005 page 204 of 970
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0
1
1
—
0
1
—
—
P93 input
P93 output
RxD1 input
RxD1 input
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
P92/RxD0
Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin
function as follows.
SMIF
0
RE
P92DDR
Pin function
P91/TxD1
0
1
1
—
0
1
—
—
P92 input
P92 output
RxD0 input
RxD0 input
Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin
function as follows.
SMIF
0
TE
P91 DDR
Pin function
0
0
1
P91 input
P91 output
1
1
—
—
—
TxD1 output TxD1 output*
Note: * Functions as the TxD1 output pin, but there are two states: one in
which the pin is driven, and another in which the pin is at highimpedance.
P90/TxD0
Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin
function as follows.
SMIF
0
TE
P90DDR
Pin function
0
0
1
P90 input
P90 output
1
1
—
—
—
TxD0 output TxD0 output*
Note: * Functions as the TxD0 output pin, but there are two states: one in
which the pin is driven, and another in which the pin is at highimpedance.
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Section 7 I/O Ports
7.11
Port A
7.11.1
Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the
programmable timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1,
TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, clock input
(TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, and address output (A23 to A20). A reset
or hardware standby transition leaves port A as an input port, except that in modes 3 and 4, one
pin is always used for A20 output. See table 7.19 to 7.21 for the selection of pin functions.
Usage of pins for TPC, 16-bit timer, and 8-bit timer input and output is described in the sections
on those modules. For output of address bits A23 to A20 in modes 3, 4, and 5, see section 6.2.4,
Bus Release Control Register (BRCR). Pins not assigned to any of these functions are available
for generic input/output. Figure 7.10 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
Rev. 6.00 Mar 18, 2005 page 206 of 970
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Section 7 I/O Ports
Port A pins
PA 7 /TP7 /TIOCB2 /A20
PA 6 /TP6 /TIOCA2 /A21
PA 5 /TP5 /TIOCB1 /A22
PA 4 /TP4 /TIOCA1 /A23
Port A
PA 3 /TP3 /TIOCB0 /TCLKD
PA 2 /TP2 /TIOCA0 /TCLKC
PA 1 /TP1 /TCLKB
PA 0 /TP0 /TCLKA
Pin functions in modes 1, 2, 6 and 7
PA 7 (input/output)/TP 7 (output)/TIOCB 2 (input/output)
PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output)
PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output)
PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output)
PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP 1 (output)/TCLKB (input)
PA 0 (input/output)/TP 0 (output)/TCLKA (input)
Pin functions in modes 3 and 4
A 20 (output)
PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output)/A 21(output)
PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output)/A 22(output)
PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output)/A 23(output)
PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP 1 (output)/TCLKB (input)
PA 0 (input/output)/TP 0 (output)/TCLKA (input)
Pin functions in mode 5
PA 7 (input/output)/TP7 (output)/TIOCB2 (input/output)/A 20 (output)
PA 6 (input/output)/TP6 (output)/TIOCA2 (input/output)/A 21 (output)
PA 5 (input/output)/TP5 (output)/TIOCB1 (input/output)/A 22 (output)
PA 4 (input/output)/TP4 (output)/TIOCA1 (input/output)/A 23 (output)
PA 3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP1 (output)/TCLKB (input)
PA 0 (input/output)/TP0 (output)/TCLKA (input)
Figure 7.10 Port A Pin Configuration
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Section 7 I/O Ports
7.11.2
Register Descriptions
Table 7.18 summarizes the registers of port A.
Table 7.18 Port A Registers
Initial Value
Address*
Name
H'EE009
Port A data direction
register
H'FFFD9
Port A data register
R/W
Modes 1, 2, 5, 6 and 7
Modes 3, 4
PADDR
W
H'00
H'80
PADR
R/W
H'00
H'00
Note: * Lower 20 bits of the address in advanced mode
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR
Modes Initial value 1
3 and 4 Read/Write —
Modes Initial value 0
1, 2, 5,
6 and 7 Read/Write W
0
0
0
0
0
0
0
W
W
W
W
W
W
W
0
0
0
0
0
0
0
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
The pin functions that can be selected for pins PA7 to PA4 differ between modes 1, 2, 6, and 7, and
modes 3 to 5. For the method of selecting the pin functions, see tables 7.19 and 7.20.
The pin functions that can be selected for pins PA3 to PA0 are the same in modes 1 to 7. For the
method of selecting the pin functions, see table 7.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA7DDR is fixed at 1 and PA7 functions as the A20 address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
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Section 7 I/O Ports
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
standby mode it retains its previous setting. Therefore, if a transition is made to software standby
mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 7 I/O Ports
Table 7.19 Port A Pin Functions (Modes 1, 2, 6, and 7)
Pin
Pin Functions and Selection Method
PA7/TP7/
TIOCB2
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit
PA7DDR select the pin function as follows.
16-bit timer
channel 2 settings
(1) in table below
(2) in table below
PA7DDR
—
0
1
1
NDER7
—
—
0
1
TIOCB2 output
PA7
input
PA7
output
TP7
output
Pin function
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
16-bit timer
channel 2 settings
(2)
IOB2
PA6/TP6/
TIOCA2
(1)
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit
PA6DDR select the pin function as follows.
16-bit timer
channel 2 settings
(1) in table below
(2) in table below
PA6DDR
—
0
1
1
NDER6
—
—
0
1
TIOCA2 output
PA6
input
PA6
output
TP6
output
Pin function
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer
channel 2 settings
(2)
(1)
PWM2
(2)
0
IOA2
(1)
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 6.00 Mar 18, 2005 page 210 of 970
REJ09B0215-0600
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PA5/TP5/
TIOCB1
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit
PA5DDR select the pin function as follows.
16-bit timer
channel 1 settings
(1) in table below
(2) in table below
PA5DDR
—
0
1
1
NDER5
—
—
0
1
TIOCB1 output
PA5
input
PA5
output
TP5
output
Pin function
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1 settings
(2)
(1)
IOB2
PA4/TP4/
TIOCA1
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit
PA4DDR select the pin function as follows.
16-bit timer
channel 1 settings
(1) in table below
PA4DDR
(2) in table below
—
NDER4
Pin function
0
1
1
—
—
0
1
TIOCA1 output
PA4
input
PA4
output
TP4
output
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1 settings
(2)
(1)
PWM1
(2)
0
IOA2
(1)
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 6.00 Mar 18, 2005 page 211 of 970
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Section 7 I/O Ports
Table 7.20 Port A Pin Functions (Modes 3 to 5)
Pin
Pin Functions and Selection Method
Modes 3 and 4: Always used as A20 output.
PA7/TP7/
TIOCB2/ A20 Pin function
A20 output
Mode 5: Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit
A20E in BRCR, and bit PA7DDR select the pin function as follows.
A20E
16-bit timer
channel 2 settings
1
(1) in table below
0
(2) in table below
—
PA7DDR
—
0
1
1
—
NDER7
—
—
0
1
—
TIOCB2 output
PA7
input
PA7
output
TP7
output
A20
output
Pin function
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
16-bit timer channel 2 settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 6.00 Mar 18, 2005 page 212 of 970
REJ09B0215-0600
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PA6/TP6/
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in
TIOCA2/A21 BRCR, and bit PA6DDR select the pin function as follows.
A21E
16-bit timer
channel 2 settings
PA6DDR
NDER6
Pin function
1
(1) in table below
0
(2) in table below
—
0
1
—
1
—
—
—
0
1
—
TIOCA2 output
PA6
input
PA6
output
TP6
output
A21
output
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer channel 2 settings
(2)
(1)
PWM2
(2)
(1)
0
IOA2
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
PA5/TP5/
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in
TIOCB1/A22 BRCR, and bit PA5DDR select the pin function as follows.
A22E
16-bit timer
channel 1 settings
1
(1) in table below
0
(2) in table below
—
PA5DDR
—
0
1
1
—
NDER5
—
—
0
1
—
TIOCB1 output
PA5
input
PA5
output
TP5
output
A22
output
Pin function
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1 settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 6.00 Mar 18, 2005 page 213 of 970
REJ09B0215-0600
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PA4/TP4/
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in
TIOCA1/A23 BRCR, and bit PA4DDR select the pin function as follows.
A23E
16-bit timer
channel 1 settings
1
(1) in table below
PA4DDR
Pin function
(2) in table below
—
NDER4
0
0
1
—
1
—
—
—
0
1
—
TIOCA1 output
PA4
input
PA4
output
TP4
output
A23
output
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1 settings
(2)
(1)
PWM1
(2)
0
IOA2
(1)
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 6.00 Mar 18, 2005 page 214 of 970
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Section 7 I/O Ports
Table 7.21 Port A Pin Functions (Modes 1 to 7)
Pin
Pin Functions and Selection Method
PA3/TP3/
TIOCB0/
TCLKD
Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to
16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit
NDER3 in NDERA, and bit PA3DDR select the pin function as follows.
16-bit timer
channel 0 settings
(1) in table below
(2) in table below
PA3DDR
—
0
1
1
NDER3
—
—
0
1
TIOCB0
output
PA3
input
PA3
output
TP3
output
Pin function
TIOCB0 input*1
TCLKD input*2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to
16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table
below.
16-bit timer
channel 0 settings
(2)
(1)
IOB2
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
8-bit timer
channel 2 settings
(4)
CKS2
0
CKS1
—
CKS0
—
(3)
1
0
0
1
1
—
Rev. 6.00 Mar 18, 2005 page 215 of 970
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Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to
16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit
NDER2 in NDERA, and bit PA2DDR select the pin function as follows.
16-bit timer
channel 0 settings
(1) in table below
PA2DDR
(2) in table below
—
NDER2
Pin function
0
1
1
—
—
0
1
TIOCA0 output
PA2
input
PA2
output
TP2
output
TIOCA0 input*1
TCLKC input*2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of
16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in (3)
in the table below.
16-bit timer
channel 0 settings
(2)
(1)
PWM0
(2)
(1)
0
IOA2
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
8-bit timer
channel 0 settings
(4)
CKS2
0
CKS1
—
CKS0
—
Rev. 6.00 Mar 18, 2005 page 216 of 970
REJ09B0215-0600
(3)
1
0
0
1
1
—
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PA1/TP1/
TCLKB
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit
PA1DDR select the pin function as follows.
PA1DDR
0
1
1
NDER1
—
0
1
PA1 input
PA1 output
TP1 output
Pin function
TCLKB input*
Note: * CLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR3 are
as shown in (1) in the table below.
8-bit timer
channel 3 settings
PA0/TP0/
TCLKA
(2)
CKS2
0
CKS1
—
CKS0
—
(1)
1
0
0
1
1
—
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA0DDR select the pin function as follows.
PA0DDR
0
NDER0
—
0
1
PA0 input
PA0 output
TP0 output
Pin function
1
TCLKA input*
Note: * TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1 and TPSC1 = 0, and
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR1 are
as shown in (1) in the table below.
8-bit timer
channel 1 settings
(2)
CKS2
0
CKS1
—
CKS0
—
(1)
1
0
0
1
1
—
Rev. 6.00 Mar 18, 2005 page 217 of 970
REJ09B0215-0600
Section 7 I/O Ports
7.12
Port B
7.12.1
Overview
Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the
programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by
the 8-bit timer, and CS7 to CS4 output. See tables 7.23 and 7.24 for the selection of pin functions.
A reset or hardware standby transition leaves port B as an input/output port. For output of CS7 to
CS4 in modes 1 to 5, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these
functions are available for generic input/output. Figure 7.11 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
Rev. 6.00 Mar 18, 2005 page 218 of 970
REJ09B0215-0600
Section 7 I/O Ports
Port B pins
PB7/TP15
PB6/TP14
PB5/TP13
PB4/TP12
Port B
PB3/TP11 /TMIO3/CS4
PB2/TP10 /TMO2/CS5
PB1/TP9 /TMIO1/CS6
PB0/TP8 /TMO0/CS7
Pin functions in modes 1 to 5
PB7 (input/output)/TP15 (output)
PB6 (input/output)/TP14 (output)
PB5 (input/output)/TP13 (output)
PB4 (input/output)/TP12 (output)
PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /CS4 (output)
PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output)
PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /CS6 (output)
PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output)
Pin functions in modes 6 and 7
PB7 (input/output)/TP15 (output)
PB6 (input/output)/TP14 (output)
PB5 (input/output)/TP13 (output)
PB4 (input/output)/TP12 (output)
PB3 (input/output)/TP11 (output) /TMIO3 (input/output)
PB2 (input/output)/TP10 (output) /TMO2 (output)
PB1 (input/output)/TP9 (output) /TMIO1 (input/output)
PB0 (input/output)/TP8 (output) /TMO0 (output)
Figure 7.11 Port B Pin Configuration
Rev. 6.00 Mar 18, 2005 page 219 of 970
REJ09B0215-0600
Section 7 I/O Ports
7.12.2
Register Descriptions
Table 7.22 summarizes the registers of port B.
Table 7.22 Port B Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE00A
Port B data direction register
PBDDR
W
H'00
H'FFFDA
Port B data register
PBDR
R/W
H'00
Note: * Lower 20 bits of the address in advanced mode.
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7.
For the method of selecting the pin functions, see tables 7.23 and 7.24.
When port B functions as an input/output port, a pin in port B becomes an output port if the
corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin
maintains its output state.
Rev. 6.00 Mar 18, 2005 page 220 of 970
REJ09B0215-0600
Section 7 I/O Ports
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data
for pins port B. When port B functions as an output port, the value of this register is output. When
a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned.
When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Bit
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port B data 7 to 0
These bits store data for port B pins
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 6.00 Mar 18, 2005 page 221 of 970
REJ09B0215-0600
Section 7 I/O Ports
Table 7.23 Port B Pin Functions (Modes 1 to 5)
Pin
Pin Functions and Selection Method
PB7/TP15
Bit NDER15 in NDERB and bit PB7DDR select the pin function as follows.
PB7DDR
0
1
1
NDER15
—
0
1
PB7 input
PB7 output
TP15 output
Pin function
PB6/TP14
Bit NDER14 in NDERB and bit PB6DDR select the pin function as follows.
PB6DDR
0
1
1
NDER14
—
0
1
PB6 input
PB6 output
TP14 output
Pin function
PB5/TP13
Bit NDER13 in NDERB and bit PB5DDR select the pin function as follows.
PB5DDR
0
1
1
NDER13
—
0
1
PB5 input
PB5 output
TP13 output
Pin function
PB4/TP12
Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.
PB4DDR
0
1
1
NDER12
—
0
1
PB4 input
PB4 output
TP12 output
Pin function
PB3/TP11/
Bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1/0 in 8TCR3, bit CS4E in CSCR, bit
TMIO3/CS4 NDER11 in NDERB, and bit PB3DDR select the pin function as follows.
All 0
OIS3/2 and
OS1/0
CS4E
Not all 0
1
—
PB3DDR
0
1
1
—
—
NDER11
—
0
1
—
—
PB3
input
PB3
output
TP11
output
CS4
TMIO3 output
Pin function
0
output
TMIO3 input*
Note: * TMIO3 input when bit ICE = 1 in 8TCSR3.
Rev. 6.00 Mar 18, 2005 page 222 of 970
REJ09B0215-0600
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PB2/TP10/
TMO2/CS5
Bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and
bit PB2DDR select the pin function as follows.
OIS3/2 and
OS1/0
All 0
CS5E
PB2DDR
NDER10
Pin function
Not all 0
0
0
1
1
1
—
—
—
—
0
1
—
—
PB2
input
PB2
output
TP10
output
CS5
TMIO2
output
output
PB1/TP9/
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1/0 in 8TCR1, bit CS6E in CSCR, bit
TMIO1/CS6 NDER9 in NDERB, and bit PB1DDR select the pin function as follows.
All 0
OIS3/2 and
OS1/0
CS6E
PB1DDR
NDER9
Pin function
Not all 0
0
0
1
1
1
—
—
—
—
0
1
—
—
PB1
input
PB1
output
TP9
output
CS6
TMIO1
output
output
TMIO1 input*
Note: * TMIO1 input when bit ICE = 1 in 8TCSR1.
PB0/TP8/
TMO0/CS7
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and bit
PB0DDR select the pin function as follows.
OIS3/2 and
OS1/0
All 0
CS7E
Not all 0
0
1
—
PB0DDR
0
1
1
—
—
NDER8
—
0
1
—
—
PB0
input
PB0
output
TP8
output
CS7
output
TMO0
output
Pin function
Rev. 6.00 Mar 18, 2005 page 223 of 970
REJ09B0215-0600
Section 7 I/O Ports
Table 7.24 Port B Pin Functions (Modes 6 and 7)
Pin
Pin Functions and Selection Method
PB7/TP15
Bit NDER15 in NDERB and bit PB7DDR select the pin function as follows.
PB7DDR
0
1
1
NDER15
—
0
1
PB7 input
PB7 output
TP15 output
Pin function
PB6/TP14
Bit NDER14 in NDERB and bit PB6DDR select the pin function as follows.
PB6DDR
0
1
1
NDER14
—
0
1
PB6 input
PB6 output
TP14 output
Pin function
PB5/TP13
Bit NDER13 in NDERB and bit PB5DDR select the pin function as follows.
PB5DDR
0
1
1
NDER13
—
0
1
PB5 input
PB5 output
TP13 output
Pin function
PB4/TP12
Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.
PB4DDR
0
1
1
NDER12
—
0
1
PB4 input
PB4 output
TP12 output
Pin function
PB3/TP11/
TMIO3
Bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1/0 in 8TCR3, bit NDER11 in NDERB,
and bit PB3DDR select the pin function as follows.
All 0
OIS3/2 and
OS1/0
Not all 0
PB3DDR
0
1
1
—
NDER11
—
0
1
—
PB3 input
PB3 output
Pin function
TP11 output
TMIO3 input*
Note: * TMIO3 input when bit ICE = 1 in 8TCSR3.
Rev. 6.00 Mar 18, 2005 page 224 of 970
REJ09B0215-0600
TMIO3 output
Section 7 I/O Ports
Pin
Pin Functions and Selection Method
PB2/TP10/
TMO2
Bits OIS3/2 and OS1/0 in 8TCSR2, bit NDER10 in NDERB, and bit PB2DDR select
the pin function as follows.
OIS3/2 and
OS1/0
Not all 0
PB2DDR
0
1
1
—
NDER10
—
0
1
—
PB2 input
PB2 output
TP10 output
TMO2 output
Pin function
PB1/TP9/
TMIO1
All 0
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in 8TCR0, bit NDER9 in
NDERB, and bit PB1DDR select the pin function as follows.
OIS3/2 and
OS1/0
All 0
Not all 0
PB1DDR
0
1
1
—
NDER9
—
0
1
—
PB1
input
PB1
output
Pin function
TP9
output
TMIO1 input*
TMIO1
output
Note: * TMIO1 input when bit ICE = 1 in 8TCSR1.
PB2/TP8/
TMO0
Bits OIS3/2 and OS1/0 in 8TCSR0, bit NDER8 in NDERB, and bit PB0DDR select the
pin function as follows.
OIS3/2 and
OS1/0
All 0
Not all 0
PB2DDR
0
1
1
—
NDER8
—
0
1
—
PB0
input
PB0
output
TP8
output
TMO0
output
Pin function
Rev. 6.00 Mar 18, 2005 page 225 of 970
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Section 7 I/O Ports
Rev. 6.00 Mar 18, 2005 page 226 of 970
REJ09B0215-0600
Section 8 16-Bit Timer
Section 8 16-Bit Timer
8.1
Overview
The H8/3062 Group has built-in 16-bit timer module with three 16-bit counter channels.
8.1.1
Features
16-bit timer features are listed below.
• Capability to process up to six pulse outputs or six pulse inputs
• Six general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
• Selection of eight counter clock sources for each channel:
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
 Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
 Input capture function
Rising edge, falling edge, or both edges (selectable)
 Counter clearing function
Counters can be cleared by compare match or input capture
 Synchronization
Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
 PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
three-phase PWM output is possible
• Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
• High-speed access via internal 16-bit bus
The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
• Any initial timer output value can be set
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Section 8 16-Bit Timer
• Nine interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
• Output triggering of programmable timing pattern controller (TPC)
Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers.
Table 8.1 summarizes the 16-bit timer functions.
Table 8.1
16-bit timer Functions
Item
Channel 0
Channel 1
Channel 2
Internal clocks: φ, φ/2, φ/4, φ/8
Clock sources
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable
independently
General registers (output compare/ GRA0, GRB0
input capture registers)
GRA1, GRB1
GRA2, GRB2
Input/output pins
TIOCA0, TIOCB0
TIOCA1, TIOCB1
TIOCA2, TIOCB2
Counter clearing function
GRA0/GRB0 compare
match or input capture
GRA1/GRB1 compare
match or input capture
GRA2/GRB2 compare
match or input capture
Initial output value setting function
Compare match
output
Available
Available
Available
0
Available
Available
Available
1
Available
Available
Available
Toggle
Available
Available
Not available
Input capture function
Available
Available
Available
Synchronization
Available
Available
Available
PWM mode
Available
Available
Available
Phase counting mode
Not available
Not available
Available
Interrupt sources
Three sources
Three sources
Three sources
• Compare match/
input capture A0
• Compare match/
input capture A1
• Compare match/
input capture A2
• Compare match/
input capture B0
• Compare match/
input capture B1
• Compare match/
input capture B2
• Overflow
• Overflow
• Overflow
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Section 8 16-Bit Timer
8.1.2
Block Diagrams
16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer.
TCLKA to TCLKD
IMIA0 to IMIA2
IMIB0 to IMIB2
OVI0 to OVI2
Clock selector
φ, φ/2, φ/4, φ/8
Control logic
TIOCA0 to TIOCA2
TIOCB0 to TIOCB2
TOLR
TISRA
TISRB
Internal data bus
TMDR
Bus interface
TSNR
16-bit timer channel 0
16-bit timer channel 1
16-bit timer channel 2
TSTR
TISRC
Module data bus
Legend:
TSTR :
TSNR :
TMDR :
TOLR :
TISRA :
TISRB :
TISRC :
Timer start register (8 bits)
Timer synchro register (8 bits)
Timer mode register (8 bits)
Timer output level setting register (8 bits)
Timer interrupt status register A (8 bits)
Timer interrupt status register B (8 bits)
Timer interrupt status register C (8 bits)
Figure 8.1 16-bit timer Block Diagram (Overall)
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Section 8 16-Bit Timer
Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.
Both have the structure shown in figure 8.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA0
TIOCB0
Clock selector
Control logic
IMIA0
IMIB0
OVI0
TIOR
16TCR
GRB
GRA
16TCNT
Comparator
Module data bus
Legend:
16TCNT
GRA, GRB
TCR
TIOR
:
:
:
:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits × 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
Figure 8.2 Block Diagram of Channels 0 and 1
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Section 8 16-Bit Timer
Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA2
TIOCB2
Clock selector
Control logic
IMIA2
IMIB2
OVI2
TIOR2
16TCR2
GRB2
GRA2
16TCNT2
Comparator
Module data bus
Legend:
16TCNT2
: Timer counter 2 (16 bits)
GRA2, GRB2 : General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
TCR2
: Timer control register 2 (8 bits)
TIOR2
: Timer I/O control register 2 (8 bits)
Figure 8.3 Block Diagram of Channel 2
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Section 8 16-Bit Timer
8.1.3
Pin Configuration
Table 8.2 summarizes the 16-bit timer pins.
Table 8.2
16-bit timer Pins
Channel Name
Abbreviation
Input/
Output
Common Clock input A
TCLKA
Input
External clock A input pin
(phase-A input pin in phase counting
mode)
Clock input B
TCLKB
Input
External clock B input pin
(phase-B input pin in phase counting
mode)
Clock input C
TCLKC
Input
External clock C input pin
Clock input D
TCLKD
Input
External clock D input pin
Input capture/output
compare A0
TIOCA0
Input/
output
GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B0
TIOCB0
Input/
output
GRB0 output compare or input capture pin
Input capture/output
compare A1
TIOCA1
Input/
output
GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B1
TIOCB1
Input/
output
GRB1 output compare or input capture pin
Input capture/output
compare A2
TIOCA2
Input/
output
GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B2
TIOCB2
Input/
output
GRB2 output compare or input capture pin
0
1
2
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Function
Section 8 16-Bit Timer
8.1.4
Register Configuration
Table 8.3 summarizes the 16-bit timer registers.
Table 8.3
16-bit timer Registers
Channel
Address*1
Name
Abbreviation
R/W
Initial
Value
Common
H'FFF60
Timer start register
TSTR
R/W
H'F8
H'FFF61
Timer synchro register
TSNC
R/W
H'F8
0
1
H'FFF62
Timer mode register
TMDR
R/W
H'98
H'FFF63
Timer output level setting register
TOLR
W
H'C0
H'FFF64
Timer interrupt status register A
TISRA
H'88
H'FFF65
Timer interrupt status register B
TISRB
R/(W)*2
R/(W)*2
TISRC
R/(W)*2
H'88
H'FFF66
Timer interrupt status register C
H'88
H'FFF68
Timer control register 0
16TCR0
R/W
H'80
H'FFF69
Timer I/O control register 0
TIOR0
R/W
H'88
H'FFF6A
Timer counter 0H
16TCNT0H R/W
H'00
H'FFF6B
Timer counter 0L
16TCNT0L R/W
H'00
H'FFF6C
General register A0H
GRA0H
R/W
H'FF
H'FFF6D
General register A0L
GRA0L
R/W
H'FF
H'FFF6E
General register B0H
GRB0H
R/W
H'FF
H'FFF6F
General register B0L
GRB0L
R/W
H'FF
H'FFF70
Timer control register 1
16TCR1
R/W
H'80
H'FFF71
Timer I/O control register 1
TIOR1
R/W
H'88
H'FFF72
Timer counter 1H
16TCNT1H R/W
H'00
H'FFF73
Timer counter 1L
16TCNT1L R/W
H'00
H'FFF74
General register A1H
GRA1H
R/W
H'FF
H'FFF75
General register A1L
GRA1L
R/W
H'FF
H'FFF76
General register B1H
GRB1H
R/W
H'FF
H'FFF77
General register B1L
GRB1L
R/W
H'FF
Rev. 6.00 Mar 18, 2005 page 233 of 970
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Section 8 16-Bit Timer
Channel
2
Address*1
Name
Abbreviation
R/W
Initial
Value
H'FFF78
Timer control register 2
16TCR2
R/W
H'80
H'FFF79
Timer I/O control register 2
TIOR2
R/W
H'88
H'FFF7A
Timer counter 2H
16TCNT2H R/W
H'00
H'FFF7B
Timer counter 2L
16TCNT2L R/W
H'00
H'FFF7C
General register A2H
GRA2H
R/W
H'FF
H'FFF7D
General register A2L
GRA2L
R/W
H'FF
H'FFF7E
General register B2H
GRB2H
R/W
H'FF
H'FFF7F
General register B2L
GRB2L
R/W
H'FF
Notes: 1. The lower 20 bits of the address in advanced mode are indicated.
2. Only 0 can be written in bits 3 to 0, to clear the flags.
8.2
Register Descriptions
8.2.1
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in
channels 0 to 2.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
STR2
STR1
STR0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Reserved bits
Counter start 2 to 0
These bits start and
stop 16TCNT2 to 16TCNT0
TSTR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
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Section 8 16-Bit Timer
Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2).
Bit 2
STR2
Description
0
16TCNT2 is halted
1
16TCNT2 is counting
(Initial value)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1).
Bit 1
STR1
Description
0
16TCNT1 is halted
1
16TCNT1 is counting
(Initial value)
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0).
Bit 0
STR0
Description
0
16TCNT0 is halted
1
16TCNT0 is counting
8.2.2
(Initial value)
Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Reserved bits
Timer sync 2 to 0
These bits synchronize
channels 2 to 0
TSNC is initialized to H'F8 by a reset and in standby mode.
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Section 8 16-Bit Timer
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2
Description
0
Channel 2’s timer counter (16TCNT2) operates independently
16TCNT2 is preset and cleared independently of other channels
1
Channel 2 operates synchronously
16TCNT2 can be synchronously preset and cleared
(Initial value)
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1
Description
0
Channel 1’s timer counter (16TCNT1) operates independently
16TCNT1 is preset and cleared independently of other channels
1
Channel 1 operates synchronously
16TCNT1 can be synchronously preset and cleared
(Initial value)
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0
Description
0
Channel 0’s timer counter (16TCNT0) operates independently
16TCNT0 is preset and cleared independently of other channels
1
Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
Rev. 6.00 Mar 18, 2005 page 236 of 970
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(Initial value)
Section 8 16-Bit Timer
8.2.3
Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
7
6
5
4
3
2
1
0
—
MDF
FDIR
—
—
PWM2
PWM1
PWM0
Initial value
1
0
0
1
1
0
0
0
Read/Write
—
R/W
R/W
—
—
R/W
R/W
R/W
Reserved bit
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
Description
0
Channel 2 operates normally
1
Channel 2 operates in phase counting mode
(Initial value)
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Section 8 16-Bit Timer
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
Down-Counting
TCLKA pin
TCLKB pin
Up-Counting
High
Low
Low
High
Low
High
High
Low
In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2
and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting
mode operations take precedence.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
Description
0
OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
1
OVF is set to 1 in TISRC when 16TCNT2 overflows
(Initial value)
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2
Description
0
Channel 2 operates normally
1
Channel 2 operates in PWM mode
(Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
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Section 8 16-Bit Timer
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1
Description
0
Channel 1 operates normally
1
Channel 1 operates in PWM mode
(Initial value)
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
Description
0
Channel 0 operates normally
1
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
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Section 8 16-Bit Timer
8.2.4
Timer Interrupt Status Register A (TISRA)
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables GRA compare match and input capture interrupt requests.
Bit
7
—
Initial value
Read/Write
1
—
6
5
4
IMIEA2 IMIEA1 IMIEA0
0
R/W
0
R/W
0
R/W
3
2
1
0
—
IMFA2
IMFA1
IMFA0
1
0
0
0
—
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Reserved bit
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables
the interrupt requested by the IMFA2 when IMFA2 flag is set to 1.
Bit 6
IMIEA2
Description
0
IMIA2 interrupt requested by IMFA2 flag is disabled
1
IMIA2 interrupt requested by IMFA2 flag is enabled
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REJ09B0215-0600
(Initial value)
Section 8 16-Bit Timer
Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1
Description
0
IMIA1 interrupt requested by IMFA1 flag is disabled
1
IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0
Description
0
IMIA0 interrupt requested by IMFA0 flag is disabled
1
IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2
Description
0
[Clearing condition]
1
[Setting conditions]
(Initial value)
Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag
•
16TCNT2 = GRA2 when GRA2 functions as an output compare register
•
16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register
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Section 8 16-Bit Timer
Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1
compare match or input capture events.
Bit 1
IMFA1
Description
0
[Clearing condition]
(Initial value)
Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag
1
[Setting conditions]
•
16TCNT1 = GRA1 when GRA1 functions as an output compare register
•
16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register
Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0
compare match or input capture events.
Bit 0
IMFA0
Description
0
[Clearing condition]
(Initial value)
Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag
1
[Setting conditions]
•
16TCNT0 = GRA0 when GRA0 functions as an output compare register
•
16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register
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Section 8 16-Bit Timer
8.2.5
Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
Bit
7
—
Initial value
Read/Write
1
—
6
5
4
IMIEB2 IMIEB1 IMIEB0
0
R/W
0
R/W
0
R/W
3
2
1
0
—
IMFB2
IMFB1
IMFB0
1
0
0
0
—
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Reserved bit
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.
Bit 6
IMIEB2
Description
0
IMIB2 interrupt requested by IMFB2 flag is disabled
1
IMIB2 interrupt requested by IMFB2 flag is enabled
(Initial value)
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Section 8 16-Bit Timer
Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 when IMFB1 flag is set to 1.
Bit 5
IMIEB1
Description
0
IMIB1 interrupt requested by IMFB1 flag is disabled
1
IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 when IMFB0 flag is set to 1.
Bit 4
IMIEB0
Description
0
IMIB0 interrupt requested by IMFB0 flag is disabled
1
IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2
Description
0
[Clearing condition]
(Initial value)
Read IMFB2 flag when IMFB2 =1, then write 0 in IMFB2 flag
1
[Setting conditions]
•
16TCNT2 = GRB2 when GRB2 functions as an output compare register
•
16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register
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Section 8 16-Bit Timer
Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1
compare match or input capture events.
Bit 1
IMFB1
Description
0
[Clearing condition]
(Initial value)
Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag
1
[Setting conditions]
•
16TCNT1 = GRB1 when GRB1 functions as an output compare register
•
16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1
functions as an input capture register
Bit 0—Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0
compare match or input capture events.
Bit 0
IMFB0
Description
0
[Clearing condition]
(Initial value)
Read IMFB0 flag when IMFB0 =1, then write 0 in IMFB0 flag
1
[Setting conditions]
•
16TCNT0 = GRB0 when GRB0 functions as an output compare register
•
16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register
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Section 8 16-Bit Timer
8.2.6
Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Bit
7
6
5
4
3
2
1
0
—
OVIE2
OVIE1
OVIE0
—
OVF2
OVF1
OVF0
0
0
Initial value
1
0
0
0
1
Read/Write
—
R/W
R/W
R/W
—
R/(W)* R/(W)*
0
R/(W)*
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
Reserved bit
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2
Description
0
OVI2 interrupt requested by OVF2 flag is disabled
1
OVI2 interrupt requested by OVF2 flag is enabled
Rev. 6.00 Mar 18, 2005 page 246 of 970
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(Initial value)
Section 8 16-Bit Timer
Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 when OVF1 flag is set to 1.
Bit 5
OVIE1
Description
0
OVI1 interrupt requested by OVF1 flag is disabled
1
OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the
OVF0 when OVF0 flag is set to 1.
Bit 4
OVIE0
Description
0
OVI0 interrupt requested by OVF0 flag is disabled
1
OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.
Bit 2
OVF2
Description
0
[Clearing condition]
(Initial value)
Read OVF2 flag when OVF2 =1, then write 0 in OVF2 flag
1
[Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF
Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow
occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1—Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.
Bit 1
OVF1
Description
0
[Clearing condition]
(Initial value)
Read OVF1 flag when OVF1 =1, then write 0 in OVF1 flag
1
[Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000
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Section 8 16-Bit Timer
Bit 0—Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0
OVF0
Description
0
[Clearing condition]
(Initial value)
Read OVF0 flag when OVF0 =1, then write 0 in OVF0 flag
1
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000
8.2.7
Timer Counters (16TCNT)
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel
Abbreviation
Function
0
16TCNT0
Up-counter
1
16TCNT1
2
16TCNT2
Phase counting mode: up/down-counter
Other modes: up-counter
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.
The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting
mode and an up-counter in other modes.
16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to
GRA or GRB (counter clearing function).
When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of
the corresponding channel.
When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC
of the corresponding channel.
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Section 8 16-Bit Timer
The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each 16TCNT is initialized to H'0000 by a reset and in standby mode.
8.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each
channel.
Channel
Abbreviation
Function
0
GRA0, GRB0
Output compare/input capture register
1
GRA1, GRB1
2
GRA2, GRB2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is
set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, an external input capture signal are
detected and the current 16TCNT value is stored in the general register. The corresponding IMFA
or IMFB flag in TISRA/TISRB is set to 1 at the same time. The edges of the input capture signal
are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are set as output compare registers (with no pin output) and initialized to H'FFFF
by a reset and in standby mode.
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Section 8 16-Bit Timer
8.2.9
Timer Control Registers (16TCR)
16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel.
Channel
Abbreviation
Function
0
16TCR0
1
16TCR1
2
16TCR2
16TCR controls the timer counter. The 16TCRs in all
channels are functionally identical. When phase counting
mode is selected in channel 2, the settings of bits CKEG1
and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Bit
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Timer prescaler 2 to 0
These bits select the timer
counter clock
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Reserved bit
Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source,
selects the edge or edges of external clock sources, and selects how the counter is cleared.
16TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is
cleared.
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Section 8 16-Bit Timer
Bit 6
CCLR1
0
1
Bit 5
CCLR0
Description
0
16TCNT is not cleared
1
16TCNT is cleared by GRA compare match or input capture*1
16TCNT is cleared by GRB compare match or input capture*1
0
1
(Initial value)
Synchronous clear: 16TCNT is cleared in synchronization with other
synchronized timers*2
Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count rising edges
1
Count falling edges
—
Count both edges
1
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Function
0
0
0
Internal clock: φ
1
Internal clock: φ/2
0
Internal clock: φ/4
1
Internal clock: φ/8
0
External clock A: TCLKA input
1
External clock B: TCLKB input
0
External clock C: TCLKC input
1
External clock D: TCLKD input
1
1
0
1
(Initial value)
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Section 8 16-Bit Timer
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.
8.2.10
Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.
Channel Abbreviation Function
0
TIOR0
1
TIOR1
2
TIOR2
Bit
TIOR controls the general registers. Some functions differ in PWM
mode.
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIORA and TIORB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
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Section 8 16-Bit Timer
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
0
0
0
1
1
1
0
GRB is an output
compare register
No output at compare match
(Initial value)
0 output at GRB compare match*1
0
1 output at GRB compare match*1
1
Output toggles at GRB compare match
1 2
(1 output in channel 2)* *
0
1
1
Function
GRB is an input
compare register
0
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1
output is selected automatically.
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
0
0
0
1
1
1
0
GRA is an output
compare register
No output at compare match
(Initial value)
0 output at GRA compare match*1
0
1 output at GRA compare match*1
1
Output toggles at GRA compare match
(1 output in channel 2)*1 *2
0
1
1
Function
0
GRA is an input
compare register
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. When this setting is made, 1
output is selected automatically.
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Section 8 16-Bit Timer
8.2.11
Timer Output Level Setting Register C (TOLR)
TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.
Bit
7
6
5
4
3
2
1
0
—
—
TOB2
TOA2
TOB1
TOA1
TOB0
TOA0
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
Output level setting A2 to A0, B2 to B0
These bits set the levels of the timer outputs
(TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0)
Reserved bits
A TOLR setting can only be made when the corresponding bit in TSTR is 0.
TOLR is a write-only register, and cannot be read. If it is read, all bits will return a value of 1.
TOLR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified.
Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2.
Bit 5
TOB2
Description
0
TIOCB2 is 0
1
TIOCB2 is 1
(Initial value)
Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2.
Bit 4
TOA2
Description
0
TIOCA2 is 0
1
TIOCA2 is 1
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Section 8 16-Bit Timer
Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1.
Bit 3
TOB1
Description
0
TIOCB1 is 0
1
TIOCB1 is 1
(Initial value)
Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1.
Bit 2
TOA1
Description
0
TIOCA1 is 0
1
TIOCA1 is 1
(Initial value)
Bit 1—Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0.
Bit 0
TOB0
Description
0
TIOCB0 is 0
1
TIOCB0 is 1
(Initial value)
Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0.
Bit 0
TOA0
Description
0
TIOCA0 is 0
1
TIOCA0 is 1
(Initial value)
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Section 8 16-Bit Timer
8.3
CPU Interface
8.3.1
16-Bit Accessible Registers
The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,
and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a
word at a time, or a byte at a time.
Figures 8.4 and 8.5 show examples of word read/write access to a timer counter (16TCNT).
Figures 8.6 to 8.9 show examples of byte read/write access to 16TCNTH and 16TCNTL.
Internal data bus
H
CPU
H
L
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 8.4 16TCNT Access Operation [CPU → 16TCNT (Word)]
Internal data bus
H
CPU
L
H
Bus interface
L
16TCNTH
16TCNTL
Figure 8.5 Access to Timer Counter (CPU Reads 16TCNT, Word)
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Module
data bus
Section 8 16-Bit Timer
Internal data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte)
Internal data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte)
Internal data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 8.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte)
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Section 8 16-Bit Timer
Internal data bus
H
CPU
H
L
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte)
8.3.2
8-Bit Accessible Registers
The registers other than the timer counters and general registers are 8-bit registers. These registers
are linked to the CPU by an internal 8-bit data bus.
Figures 8.10 and 8.11 show examples of byte read and write access to a 16TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
Internal data bus
H
CPU
L
H
Bus interface
L
16TCR
Figure 8.10 16TCR Access (CPU Writes to 16TCR)
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Module
data bus
Section 8 16-Bit Timer
Internal data bus
H
CPU
L
H
Bus interface
L
Module
data bus
16TCR
Figure 8.11 16TCR Access (CPU Reads 16TCR)
8.4
Operation
8.4.1
Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter (16TCNT) and general registers. The
16TCNT counts up, and can operate as a free-running counter, periodic counter, or external event
counter. GRA and GRB can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/downcounter.
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Section 8 16-Bit Timer
8.4.2
Basic Functions
Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR),
16TCNT in the corresponding channel starts counting. The counting can be free-running or
periodic.
• Sample setup procedure for counter
Figure 8.12 shows a sample procedure for setting up a counter.
Counter setup
Select counter clock
Count operation
1
No
Yes
Free-running counting
Periodic counting
Select counter clear source
2
Select output compare
register function
3
Set period
4
Start counter
5
Periodic counter
Start counter
5
Free-running counter
Figure 8.12 Counter Setup Procedure (Example)
1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of
the external clock signal.
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Section 8 16-Bit Timer
2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA
compare match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected
in step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
• Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 8.13 illustrates
free-running counting.
16TCNT value
H'FFFF
H'0000
Time
STR0 to
STR2 bit
OVF
Figure 8.13 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to
H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU
interrupt is requested at this time. After the compare match, 16TCNT continues counting up
from H'0000. Figure 8.14 illustrates periodic counting.
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Section 8 16-Bit Timer
16TCNT value
Counter cleared by general
register compare match
GR
Time
H'0000
STR bit
IMF
Figure 8.14 Periodic Counter Operation
• 16TCNT count timing
 Internal clock source
Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock
sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Figure 8.15 shows the timing.
φ
Internal
clock
16TCNT input
clock
16TCNT
N–1
N
N+1
Figure 8.15 Count Timing for Internal Clock Sources
 External clock source
The external clock pin (TCLKA to TCLKD) can be selected by bits TPSC2 to TPSC0 in
16TCR, and the detected edge by bits CKEG1 and CKEG0. The rising edge, falling edge,
or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter
pulses will not be counted correctly.
Figure 8.16 shows the timing when both edges are detected.
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Section 8 16-Bit Timer
φ
External
clock input
16TCNT input
clock
16TCNT
N–1
N
N+1
Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected)
Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can
cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output
can only go to 0 or go to 1.
• Sample setup procedure for waveform output by compare match
Figure 8.17 shows an example of the setup procedure for waveform output by compare match.
Output setup
1. Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
the value set in TOLR until the first compare match
occurs.
Select waveform
output mode
1
Set output timing
2
2. Set a value in GRA or GRB to designate the
compare match timing.
Start counter
3
3. Set the STR bit to 1 in TSTR to start the timer
counter.
Waveform output
Figure 8.17 Setup Procedure for Waveform Output by Compare Match (Example)
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Section 8 16-Bit Timer
• Examples of waveform output
Figure 8.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
16TCNT value
H'FFFF
GRB
GRA
H'0000
Time
TIOCB
No change
No change
TIOCA
No change
No change
1 output
0 output
Figure 8.18 0 and 1 Output (TOA = 1, TOB = 0)
Figure 8.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared
by compare match B. Toggle output is selected for both compare match A and B.
16TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCB
Toggle
output
TIOCA
Toggle
output
Figure 8.19 Toggle Output (TOA = 1, TOB = 0)
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Section 8 16-Bit Timer
• Output compare output timing
The compare match signal is generated in the last state in which 16TCNT and the general
register match (when 16TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the output
compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8.20 shows the output compare timing.
φ
16TCNT input
clock
16TCNT
N
GR
N
N+1
Compare
match signal
TIOCA,
TIOCB
Figure 8.20 Output Compare Output Timing
Input Capture Function: The 16TCNT value can be transferred to a general register when an
input edge is detected at an input capture input/output compare pin (TIOCA or TIOCB). Risingedge, falling-edge, or both-edge detection can be selected. The input capture function can be used
to measure pulse width or period.
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Section 8 16-Bit Timer
• Sample setup procedure for input capture
Figure 8.21 shows a sample procedure for setting up input capture.
Input selection
1. Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
DDR bit to 0 before making these TIOR settings.
Select input-capture input
1
Start counter
2
2. Set the STR bit to 1 in TSTR to start the timer
counter.
Input capture
Figure 8.21 Setup Procedure for Input Capture (Example)
• Examples of input capture
Figure 8.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA
are selected as capture edges. 16TCNT is cleared by input capture into GRB.
16TCNT value
H'0180
H'0160
H'0005
H'0000
TIOCB
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 8.22 Input Capture (Example)
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Section 8 16-Bit Timer
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Input capture signal
16TCNT
N
N
GRA, GRB
Figure 8.23 Input Capture Signal Timing
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Section 8 16-Bit Timer
8.4.3
Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two
or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 2).
Sample Setup Procedure for Synchronization: Figure 8.24 shows a sample procedure for
setting up synchronization.
Setup for synchronization
Select synchronization
1
Synchronous preset
Write to 16TCNT
Synchronous clear
2
Clearing
synchronized to this
channel?
No
Yes
Synchronous preset
Select counter clear source
3
Select counter clear source
4
Start counter
5
Start counter
5
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in 16TCNT in one of the synchronized channels, the same value is
simultaneously written in 16TCNT in the other channels.
3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 8.24 Setup Procedure for Synchronization (Example)
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Section 8 16-Bit Timer
Example of Synchronization: Figure 8.25 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1,
and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode.
Value of 16TCNT0
to 16TCNT2
Cleared by compare match with GRB0
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
H'0000
TIOCA0
TIOCA1
TIOCA2
Figure 8.25 Synchronization (Example)
8.4.4
PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter
clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
PWM mode can be selected in all channels (0 to 2).
Table 8.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
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Section 8 16-Bit Timer
Table 8.4
PWM Output Pins and Registers
Channel
Output Pin
1 Output
0 Output
0
TIOCA0
GRA0
GRB0
1
TIOCA1
GRA1
GRB1
2
TIOCA2
GRA2
GRB2
Sample Setup Procedure for PWM Mode: Figure 8.26 shows a sample procedure for setting up
PWM mode.
PWM mode
Select counter clock
1
Select counter clear source
2
1. Set bits TPSC2 to TPSC0 in 16TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in 16TCR to
select the desired edge(s) of the
external clock signal.
2. Set bits CCLR1 and CCLR0 in 16TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
Set GRA
3
Set GRB
4
Select PWM mode
5
Start counter
6
PWM mode
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM output
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
Figure 8.26 Setup Procedure for PWM Mode (Example)
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Section 8 16-Bit Timer
Examples of PWM Mode: Figure 8.27 shows examples of operation in PWM mode. In PWM
mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0
at compare match with GRB.
In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
16TCNT value
Counter cleared by compare match A
GRA
GRB
Time
H'0000
TIOCA
a. Counter cleared by GRA (TOA = 1)
16TCNT value
Counter cleared by compare match B
GRB
GRA
Time
H'0000
TIOCA
b. Counter cleared by GRB (TOA = 0)
Figure 8.27 PWM Mode (Example 1)
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Section 8 16-Bit Timer
Figure 8.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
16TCNT value
Counter cleared by compare match B
GRB
GRA
Time
H'0000
TIOCA
Write to GRA
Write to GRA
a. 0% duty cycle (TOA=0)
16TCNT value
Counter cleared by compare match A
GRA
GRB
Time
H'0000
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle (TOA=1)
Figure 8.28 PWM Mode (Example 2)
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Section 8 16-Bit Timer
8.4.5
Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and
settings in TIOR2, TISRA, TISRB, TISRC, setting of STR2 bit in TSTR, GRA2, and GRB2 are
valid. The input capture and output compare functions can be used, and interrupts can be
generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 8.29 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
1
1. Set the MDF bit in TMDR to 1 to select
phase counting mode.
2. Select the flag setting condition with
the FDIR bit in TMDR.
Select flag setting condition
2
Start counter
3
3. Set the STR2 bit to 1 in TSTR to start
the timer counter.
Phase counting mode
Figure 8.29 Setup Procedure for Phase Counting Mode (Example)
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Section 8 16-Bit Timer
Example of Phase Counting Mode: Figure 8.30 shows an example of operations in phase
counting mode. Table 8.5 lists the up-counting and down-counting conditions for 16TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pulse width must be at least 2.5 states.
16TCNT2 value
Counting up
Counting down
TCLKB
TCLKA
Figure 8.30 Operation in Phase Counting Mode (Example)
Table 8.5
Up/Down Counting Conditions
Counting Direction
Up-Counting
TCLKB pin
Down-Counting
High
TCLKA pin
Low
Phase
difference
Low
High
Phase
difference
High
Low
Low
Pulse width
High
Pulse width
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: at least 1.5 states
Pulse width:
at least 2.5 states
Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 8 16-Bit Timer
8.4.6
16-Bit Timer Output Timing
The initial value of 16-bit timer output when a timer count operation begins can be specified
arbitrarily by making a setting in TOLR.
Figure 8.32 shows the timing for setting the initial value with TOLR.
Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
T1
T3
T2
φ
Address bus
TOLR
16-bit timer output pin
TOLR address
N
N
Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR
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Section 8 16-Bit Timer
8.5
Interrupts
The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1
Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when 16TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when 16TCNT is updated
from the matching count to the next count). Therefore, when 16TCNT matches a general register,
the compare match signal is not generated until the next 16TCNT clock input. Figure 8.33 shows
the timing of the setting of IMFA and IMFB.
φ
16TCNT input
clock
16TCNT
N
GR
N+1
N
Compare
match signal
IMF
IMI
Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match
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Section 8 16-Bit Timer
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding
general register. Figure 8.34 shows the timing.
φ
Input capture
signal
IMF
16TCNT
GR
N
N
IMI
Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture
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Section 8 16-Bit Timer
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
Figure 8.35 Timing of Setting of OVF
8.5.2
Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.36 shows the timing.
TISR write cycle
T1
T2
T3
φ
Address
TISR address
IMF, OVF
Figure 8.36 Timing of Clearing of Status Flags
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Section 8 16-Bit Timer
8.5.3
Interrupt Sources
Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare
match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources
of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag
are set to 1.
The priority order of the channels can be modified in interrupt priority registers A (IPRA). For
details see section 5, Interrupt Controller.
Table 8.6 lists the interrupt sources.
Table 8.6
16-bit timer Interrupt Sources
Channel
Interrupt Source
Description
Priority*
0
IMIA0
Compare match/input capture A0
High
IMIB0
Compare match/input capture B0
OVI0
Overflow 0
IMIA1
Compare match/input capture A1
IMIB1
Compare match/input capture B1
OVI1
Overflow 1
IMIA2
Compare match/input capture A2
IMIB2
Compare match/input capture B2
OVI2
Overflow 2
1
2
Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA.
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Section 8 16-Bit Timer
8.6
Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 8.37.
16TCNT write cycle
T2
T1
T3
φ
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 8.37 Contention between 16TCNT Write and Clear
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Section 8 16-Bit Timer
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the
T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.
Figure 8.38 shows the timing in this case.
16TCNT word write cycle
T2
T1
T3
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
16TCNT
N
M
16TCNT write data
Figure 8.38 Contention between 16TCNT Word Write and Increment
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Section 8 16-Bit Timer
Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the
T2 or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not
incremented. The byte data for which a write was not performed is not incremented, and retains its
pre-write value. See figure 8.39, which shows an increment pulse occurring in the T2 state of a
byte write to 16TCNTH.
16TCNTH byte write cycle
T1
T2
T3
φ
16TCNTH address
Address bus
Internal write signal
16TCNT input clock
16TCNTH
N
M
16TCNT write data
16TCNTL
X
X+1
X
Figure 8.39 Contention between 16TCNT Byte Write and Increment
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Section 8 16-Bit Timer
Contention between General Register Write and Compare Match: If a compare match occurs
in the T3 state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 8.40.
General register write cycle
T1
T2
T3
φ
GR address
Address bus
Internal write signal
16TCNT
N
GR
N
N+1
M
General register write data
Compare match signal
Inhibited
Figure 8.40 Contention between General Register Write and Compare Match
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Section 8 16-Bit Timer
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the
T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF
is set to 1. The same holds for underflow. See figure 8.41.
16TCNT write cycle
T1
T2
T3
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
Overflow signal
16TCNT
H'FFFF
M
16TCNT write data
OVF
Figure 8.41 Contention between 16TCNT Write and Overflow
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Section 8 16-Bit Timer
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T3 state of a general register read cycle, the value before input capture is read.
See figure 8.42.
General register read cycle
T2
T1
T3
φ
GR address
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
X
M
X
Figure 8.42 Contention between General Register Read and Input Capture
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Section 8 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8.43.
φ
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
GR
N
H'0000
N
Figure 8.43 Contention between Counter Clearing by Input Capture and Counter
Increment
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Section 8 16-Bit Timer
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T3 state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 8.44.
General register write cycle
T1
T2
T3
φ
Address bus
GR address
Internal write signal
Input capture signal
16TCNT
GR
M
M
Figure 8.44 Contention between General Register Write and Input Capture
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Section 8 16-Bit Timer
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the 16TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f=
φ
(N+1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT
value is modified by byte write access, all 16 bits of all synchronized counters assume the same
value as the counter that was addressed.
(Example) When channels 1 and 2 are synchronized
• Byte write to channel 1 or byte write to channel 2
16TCNT1
W
X
16TCNT2
Y
Z
Upper byte Lower byte
Write A to upper byte
of channel 1
16TCNT1
A
X
16TCNT2
A
X
Upper byte Lower byte
Write A to lower byte
of channel 2
16TCNT1
Y
A
16TCNT2
Y
A
Upper byte Lower byte
• Word write to channel 1 or word write to channel 2
16TCNT1
W
X
16TCNT2
Y
Z
Upper byte Lower byte
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Write AB word to
channel 1 or 2
16TCNT1
A
B
16TCNT2
A
B
Upper byte Lower byte
Section 8 16-Bit Timer
16-bit Timer Operating Modes
Table 8.7 (a) 16-bit Timer Operating Modes (Channel 0)
Register Settings
TSNC
TMDR
TIOR0
16TCR0
Operating Mode
Synchronization
Synchronous preset
SYNC0 = 1 —
—
PWM mode
—
—
PWM0 = 1
—
Output compare A
—
—
PWM0 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
—
—
Input capture A
—
—
PWM0 = 0
Input capture B
—
—
PWM0 = 0
Counter By compare
clearing match/input
capture A
—
—
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
—
—
CCLR1 = 1
CCLR0 = 0
SYNC0 = 1 —
—
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
Legend:
MDF
FDIR PWM
IOA
IOB
Clear
Select
Clock
Select
*
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
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Section 8 16-Bit Timer
Table 8.7 (b) 16-bit Timer Operating Modes (Channel 1)
Register Settings
TSNC
TMDR
TIOR1
16TCR1
Operating Mode
Synchronization
Synchronous preset
SYNC1 = 1 —
—
PWM mode
—
—
PWM1 = 1
—
Output compare A
—
—
PWM1 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
—
—
Input capture A
—
—
PWM1 = 0
Input capture B
—
—
PWM1 = 0
Counter By compare
clearing match/input
capture A
—
—
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
—
—
CCLR1 = 1
CCLR0 = 0
SYNC1 = 1 —
—
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
MDF
FDIR PWM
IOA
IOB
Clear
Select
Clock
Select
*
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
Legend:
Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B
occur simultaneously, the compare match signal is inhibited.
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Section 8 16-Bit Timer
Table 8.7 (c) 16-bit Timer Operating Modes (Channel 2)
Register Settings
TSNC
Operating Mode
Synchronization
Synchronous preset
SYNC2 = 1
TMDR
MDF
FDIR PWM
TIOR2
IOA
IOB
16TCR2
Clear
Select
—
*
PWM mode
—
PWM2 = 1
—
Output compare A
—
PWM2 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
—
Input capture A
—
PWM2 = 0
Input capture B
—
PWM2 = 0
Counter By compare
clearing match/input
capture A
—
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
—
CCLR1 = 1
CCLR0 = 0
—
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
Phase counting
mode
Clock
Select
SYNC2 = 1
MDF = 1
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
—
Legend:
Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
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Section 8 16-Bit Timer
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Section 9 8-Bit Timers
Section 9 8-Bit Timers
9.1
Overview
The H8/3062 Group has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2,
and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two
8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT
value to detect compare match events. The timers can be used as multifunctional timers in a
variety of applications, including the generation of a rectangular-wave output with an arbitrary
duty cycle.
9.1.1
Features
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or input capture B.
• Timer output controlled by two compare match signals
The timer output signal in each channel is controlled by two independent compare match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM
output.
• A/D converter can be activated by a compare match
• Two channels can be cascaded
 Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
 Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
 Channel 1 can count channel 0 compare match events (compare match count mode).
 Channel 3 can count channel 2 compare match events (compare match count mode).
• Input capture function can be set
8-bit or 16-bit input capture operation is available.
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Section 9 8-Bit Timers
• Twelve interrupt sources
There are twelve interrupt sources: four compare match sources, four compare match/input
capture sources, four overflow sources.
Two of the compare match sources and two of the combined compare match/input capture
sources each have an independent interrupt vector. The remaining compare match interrupts,
combined compare match/input capture interrupts, and overflow interrupts have one interrupt
vector for two sources.
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Section 9 8-Bit Timers
9.1.2
Block Diagram
The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0
and 1, and group 1 comprising channels 2 and 3. Figure 9.1 shows a block diagram of 8-bit timer
group 0.
External clock
sources
TCLKA
TCLKC
Internal clock
sources
φ/8
φ/64
φ/8192
Clock 1
Clock 0
Clock select
TCORA0
TCORA1
Compare match A1
Compare match A0 Comparator A0
Comparator A1
Overflow 1
TMO0
TMIO1
8TCNT0
8TCNT1
Internal bus
Overflow 0
Compare match B1
Control logic
Compare match B0 Comparator B0
Input capture B1
Legend:
TCORA :
TCORB :
8TCNT :
8TCSR :
8TCR :
Comparator B1
TCORB0
TCORB1
8TCSR0
8TCSR1
8TCR0
8TCR1
CMIA0
CMIB0
CMIA1/CMIB1
OVI0/OVI1
Interrupt signals
Time constant register A
Time constant register B
Timer counter
Timer control/status register
Timer control register
Figure 9.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)
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Section 9 8-Bit Timers
9.1.3
Pin Configuration
Table 9.1 summarizes the input/output pins of the 8-bit timer module.
Table 9.1
8-Bit Timer Pins
Group
Channel
Name
Abbreviation I/O
0
0
Timer output
TMO0
Output
Compare match output
Timer clock input
TCLKC
Input
Counter external clock input
Timer input/output
TMIO1
I/O
Compare match output/input
capture input
Timer clock input
TCLKA
Input
Counter external clock input
Timer output
TMO2
Output
Compare match output
Timer clock input
TCLKD
Input
Counter external clock input
Timer input/output
TMIO3
I/O
Compare match output/input
capture input
Timer clock input
TCLKB
Input
Counter external clock input
1
1
2
3
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Function
Section 9 8-Bit Timers
9.1.4
Register Configuration
Table 9.2 summarizes the registers of the 8-bit timer module.
Table 9.2
8-Bit Timer Registers
Channel Address*1
Name
Abbreviation R/W
0
H'FFF80
Timer control register 0
8TCR0
H'FFF82
Timer control/status register 0
8TCSR0
H'00
2
*
R/(W)
H'00
H'FFF84
Time constant register A0
TCORA0
R/W
H'FFF86
Time constant register B0
TCORB0
R/W
H'FF
H'FFF88
Timer counter 0
8TCNT0
R/W
H'00
H'FFF81
Timer control register 1
8TCR1
R/W
1
2
3
Initial value
R/W
H'FF
H'00
*2
H'FFF83
Timer control/status register 1
8TCSR1
R/(W)
H'00
H'FFF85
Time constant register A1
TCORA1
R/W
H'FF
H'FFF87
Time constant register B1
TCORB1
R/W
H'FF
H'FFF89
Timer counter 1
8TCNT1
R/W
H'00
H'FFF90
Timer control register 2
8TCR2
R/W
H'00
*2
H'FFF92
Timer control/status register 2
8TCSR2
R/(W)
H'10
H'FFF94
Time constant register A2
TCORA2
R/W
H'FF
H'FFF96
Time constant register B2
TCORB2
R/W
H'FF
H'FFF98
Timer counter 2
8TCNT2
R/W
H'00
H'FFF91
Timer control register 3
8TCR3
R/W
H'00
*2
H'FFF93
Timer control/status register 3
8TCSR3
R/(W)
H'00
H'FFF95
Time constant register A3
TCORA3
R/W
H'FF
H'FFF97
Time constant register B3
TCORB3
R/W
H'FF
H'FFF99
Timer counter 3
8TCNT3
R/W
H'00
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0
register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed
together by word access.
Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the
channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be
accessed together by word access.
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Section 9 8-Bit Timers
9.2
Register Descriptions
9.2.1
Timer Counters (8TCNT)
8TCNT0
8TCNT1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT2
8TCNT3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses
generated from an internal or external clock source. The clock source is selected by clock select
bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or
write to the timer counters.
The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a
16-bit register by word access.
8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1
and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing.
When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status
register (8TCSR) is set to 1.
Each 8TCNT is initialized to H'00 by a reset and in standby mode.
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Section 9 8-Bit Timers
9.2.2
Time Constant Registers A (TCORA)
TCORA0 to TCORA3 are 8-bit readable/writable registers.
TCORA0
TCORA1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA2
TCORA3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a
16-bit register by word access.
The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag A (CMFA) is set to 1 in 8TCSR.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits 1 and 0 (OS1, OS0) in 8TCSR.
Each TCORA register is initialized to H'FF by a reset and in standby mode.
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Section 9 8-Bit Timers
9.2.3
Time Constant Registers B (TCORB)
TCORB0
TCORB1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB2
TCORB3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and
the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access.
The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*.
The timer output can be freely controlled by these compare match signals and the settings of
output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR.
When TCORB is used for input capture, it stores the 8TCNT value on detection of an external
input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register.
The detected edge of the input capture signal is set in 8TCSR.
Each TCORB register is initialized to H'FF by a reset and in standby mode.
Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB flag is
not set by a channel 0 or channel 2 compare match B.
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Section 9 8-Bit Timers
9.2.4
Timer Control Register (8TCR)
Bit
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT
clearing specification, and enables interrupt requests.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 9.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB
Description
0
CMIB interrupt requested by CMFB is disabled
1
CMIB interrupt requested by CMFB is enabled
(Initial value)
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA
Description
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
(Initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt
request when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE
Description
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
(Initial value)
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Section 9 8-Bit Timers
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT
clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.
Bit 4
CCLR1
0
1
Bit 3
CCLR0
Description
0
Clearing is disabled
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
1
Cleared by input capture B
(Initial value)
Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0
and 8TCNT2 are not cleared by compare match B.
Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to
8TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The rising edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.
The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and
8TCR3 are set.
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Section 9 8-Bit Timers
Bit 2
CSK2
Bit 1
CSK1
0
0
1
1
0
Bit 0
CSK0
Description
0
Clock input disabled
1
Internal clock, counted on falling edge of φ/8
(Initial value)
0
Internal clock, counted on falling edge of φ/64
1
Internal clock, counted on falling edge of φ/8192
0
Channel 0 (16-bit count mode): Count on 8TCNT1 overflow
signal*1
Channel 1 (compare match count mode): Count on 8TCNT0
compare match A*1
Channel 2 (16-bit count mode): Count on 8TCNT3 overflow
signal*2
Channel 3 (compare match count mode): Count on 8TCNT2
compare match A*2
1
1
External clock, counted on rising edge
0
External clock, counted on falling edge
1
External clock, counted on both rising and falling edges
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
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Section 9 8-Bit Timers
9.2.5
Timer Control/Status Registers (8TCSR)
8TCSR0
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OIS3
OIS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OIS3
OIS2
OS1
OS0
8TCSR2
Bit
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
—
R/W
R/W
R/W
R/W
6
5
4
3
2
1
0
8TCSR1, 8TCSR3
7
Bit
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input
capture and overflow statuses, and control compare match output/input capture edge selection.
8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in
standby mode.
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Section 9 8-Bit Timers
Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the
occurrence of a TCORB compare match or input capture.
Bit 7
CMFB
Description
0
[Clearing condition]
(Initial value)
Read CMFB when CMFB = 1, then write 0 in CMFB
1
[Setting conditions]
• 8TCNT = TCORB*
•
The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register
Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when 8TCNT0 =
TCORB0 or 8TCNT2 = TCORB2.
Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA
compare match.
Bit 6
CMFA
Description
0
[Clearing condition]
(Initial value)
Read CMFA when CMFA = 1, then write 0 in CMFA
1
[Setting condition]
8TCNT = TCORA
Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed
from H'FF to H'00.
Bit 5
OVF
0
Description
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
8TCNT overflows from H'FF to H'00
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Section 9 8-Bit Timers
Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D
control register (ADCR), enables or disables A/D converter start requests by compare match A or
an external trigger.
TRGE*
Bit 4
ADTE
0
0
A/D converter start requests by compare match A or external trigger pin
(ADTRG) input are disabled
(Initial value)
1
A/D converter start requests by compare match A or external trigger pin
(ADTRG) input are disabled
1
0
1
Description
A/D converter start requests by external trigger pin (ADTRG) input are
enabled, and A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and A/D
converter start requests by external trigger pin (ADTRG) input are disabled
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Bit 4—Reserved (In 8TCSR2): This bit is a reserved bit, but can be read and written.
Bit 4—Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of
TCORB1 and TCORB3.
Bit 4
ICE
Description
0
TCORB1 and TCORB3 are compare match registers
1
TCORB1 and TCORB3 are input capture registers
(Initial value)
When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB
registers in channels 0 to 3 is as shown in the tables below.
Rev. 6.00 Mar 18, 2005 page 306 of 970
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Section 9 8-Bit Timers
Table 9.3
Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register
Register Function
Status Flag Change
Timer Output
Capture Input
Interrupt Request
TCORA0 Compare match CMFA changed from 0 TMO0 output
controllable
operation
to 1 in 8TCSR0 by
compare match
CMIA0 interrupt request
generated by compare
match
TCORB0 Compare match CMFB not changed
No output from
operation
from 0 to 1 in 8TCSR0 TMO0
by compare match
CMIB0 interrupt request
not generated by
compare match
TCORA1 Compare match CMFA changed from 0 TMIO1 is dedicated CMIA1 interrupt request
operation
to 1 in 8TCSR1 by
input capture pin
generated by compare
compare match
match
TCORB1 Input capture
operation
Table 9.4
CMFB changed from 0 TMIO1 is dedicated CMIB1 interrupt request
to 1 in 8TCSR1 by input input capture pin
generated by input
capture
capture
Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register
Register Function
Status Flag Change
Timer Output
Capture Input
Interrupt Request
TCORA2 Compare match CMFA changed from 0 TMO2 output
operation
to 1 in 8TCSR2 by
controllable
compare match
CMIA2 interrupt request
generated by compare
match
TCORB2 Compare match CMFB not changed
No output from
operation
from 0 to 1 in 8TCSR2 TMO2
by compare match
CMIB2 interrupt request
not generated by
compare match
TCORA3 Compare match CMFA changed from 0 TMIO3 is dedicated CMIA3 interrupt request
operation
input capture pin
to 1 in 8TCSR3 by
generated by compare
compare match
match
TCORB3 Input capture
operation
CMFB changed from 0 TMIO3 is dedicated CMIB3 interrupt request
to 1 in 8TCSR3 by input input capture pin
generated by input
capture
capture
Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
Rev. 6.00 Mar 18, 2005 page 307 of 970
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Section 9 8-Bit Timers
ICE Bit in
8TCSR1
(8TCSR3)
Bit 3
OIS3
Bit 2
OIS2
Description
0
0
0
No change when compare match B occurs
1
0 is output when compare match B occurs
0
1 is output when compare match B occurs
1
Output is inverted when compare match B occurs (toggle output)
0
TCORB input capture on rising edge
1
TCORB input capture on falling edge
0
TCORB input capture on both rising and falling edges
1
1
0
1
(Initial value)
1
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
Bit 0
OS0
Description
0
0
No change when compare match A occurs
1
0 is output when compare match A occurs
0
1 is output when compare match A occurs
1
Output is inverted when compare match A occurs (toggle output)
1
(Initial value)
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Rev. 6.00 Mar 18, 2005 page 308 of 970
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Section 9 8-Bit Timers
9.3
CPU Interface
9.3.1
8-Bit Registers
8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected
to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at
a time.
Figures 9.2 and 9.3 show the operation in word read and write accesses to 8TCNT.
Figures 9.4 to 9.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1.
Internal data bus
H
C
P
U
H
Bus
interface
L
L
Module data bus
8TCNT0 8TCNT1
Figure 9.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 9.3 8TCNT Access Operation (CPU Reads 8TCNT, Word)
Rev. 6.00 Mar 18, 2005 page 309 of 970
REJ09B0215-0600
Section 9 8-Bit Timers
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNTH0 8TCNTL1
Figure 9.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNTH0 8TCNTL1
Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 9.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)
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Section 9 8-Bit Timers
9.4
Operation
9.4.1
8TCNT Count Timing
8TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the
system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 9.8 shows the
count timing.
φ
Internal clock
8TCNT input clock
8TCNT
N–1
N
N+1
Note: Even if the same internal clock is selected for the 16-bit timer and the 8-bit timer, the same operation
will not be performed since the incrementing edge is different in each case.
Figure 9.8 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
8TCR: on the rising edge, the falling edge, and both rising and falling edges.
The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge
is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be
counted correctly.
Figure 9.9 shows the timing for incrementation on both edges of the external clock signal.
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Section 9 8-Bit Timers
φ
External clock input
8TCNT input clock
8TCNT
N–1
N
N+1
Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection)
9.4.2
Compare Match Timing
Timer Output Timing: When compare match A or B occurs, the timer output is as specified by
the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Figure 9.10 shows the timing when the output is set to toggle on compare match A.
φ
Compare match A
signal
Timer output
Figure 9.10 Timing of Timer Output
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Section 9 8-Bit Timers
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this
operation.
φ
Compare match signal
8TCNT
N
H'00
Figure 9.11 Timing of Clear by Compare Match
Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when input capture B occurs. Figure 9.12 shows the timing of this
operation.
φ
Input capture input
Input capture signal
8TCNT
N
H '00
Figure 9.12 Timing of Clear by Input Capture
9.4.3
Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR.
Figure 9.13 shows the timing when the rising edge is selected.
The pulse width of the input capture input signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected.
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Section 9 8-Bit Timers
φ
Input capture input
Input capture signal
8TCNT
N
TCORB
N
Figure 9.13 Timing of Input Capture Input Signal
9.4.4
Timing of Status Flag Setting
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB
flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and
8TCNT values match. The compare match signal is generated in the last state of the match (when
the matched 8TCNT count value is updated). Therefore, after the 8TCNT and TCORA or
TCORB values match, the compare match signal is not generated until an incrementing clock
pulse signal is generated. Figure 9.14 shows the timing in this case.
φ
8TCNT
N
TCOR
N
N+1
Compare match signal
CMF
Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs
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Section 9 8-Bit Timers
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 9.15 shows the timing in this case.
φ
8TCNT
N
TCORB
N
Input capture signal
CMFB
Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs
Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 9.16 shows the timing in
this case.
φ
8TCNT
H'FF
H'00
Overflow signal
OVF
Figure 9.16 Timing of OVF Setting
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Section 9 8-Bit Timers
9.4.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit timer mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). Similarly, if bits CKS2 to CKS0 are set to (100) in either 8TCR2 or
8TCR3, the 8-bit timers of channels 2 and 3 are cascaded. With this configuration, the two timers
can be used as a single 16-bit timer (16-bit timer mode),or channel 2 8-bit timer compare matches
can be counted in channel 3 (compare match count mode). In this case, the timer operates as
below.
16-Bit Count Mode
• Channels 0 and 1
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match
occurs.
• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
accordance with the 16-bit compare match conditions.
• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
accordance with the lower 8-bit compare match conditions.
 Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1
and input capture occurs.
• TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR0.
 Counter Clear Specification
• If counter clear on compare match or input capture has been selected by the CCLR1
and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
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Section 9 8-Bit Timers
 OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
H'FF to H'00).
• Channels 2 and 3
When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit
timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match
occurs.
• TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in
accordance with the 16-bit compare match conditions.
• TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in
accordance with the lower 8-bit compare match conditions.
 Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3
and input capture occurs.
• TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR2.
 Counter Clear Specification
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
 OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
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Section 9 8-Bit Timers
Compare Match Count Mode
• Channels 0 and 1
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in
channel 0 cannot be used.
• Channels 2 and 3
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in
channel 2 cannot be used.
Caution
Do not set 16-bit counter mode and compare match count mode simultaneously within the same
group, as the 8TCNT input clock will not be generated and the counters will not operate.
9.4.6
Input Capture Setting
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection
can be selected. In 16-bit count mode, 16-bit input capture can be used.
Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)
• Channel 1
 Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.
 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1.
 Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
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Section 9 8-Bit Timers
• Channel 3
 Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.
 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3.
 Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be
used as a compare match register.
Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2
cannot be used as a compare match register.
Setting Input Capture Operation in 16-Bit Count Mode
• Channels 0 and 1
 In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR1.
 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR1 are ignored.)
 Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channels 2 and 3
 In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR3.
 Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR3 are ignored.)
 Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
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Section 9 8-Bit Timers
9.5
Interrupt
9.5.1
Interrupt Sources
The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and
CMIB) and overflow (TOVI). Table 9.5 shows the interrupt sources and their priority order. Each
interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A
separate interrupt request signal is sent to the interrupt controller by each interrupt source.
Table 9.5
Types of 8-Bit Timer Interrupt Sources and Priority Order
Interrupt Source
Description
Priority
CMIA
Interrupt by CMFA
High
CMIB
Interrupt by CMFB
TOVI
Interrupt by OVF
Low
For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts
(TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts.
Table 9.6 lists the interrupt sources.
Table 9.6
8-Bit Timer Interrupt Sources
Channel
Interrupt Source
Description
0
CMIA0
TCORA0 compare match
CMIB0
TCORB0 compare match/input capture
1
CMIA1/CMIB1
TCORA1 compare match, or TCORB1 compare match/input
capture
0, 1
TOVI0/TOVI1
Counter 0 or counter 1 overflow
2
CMIA2
TCORA2 compare match
CMIB2
TCORB2 compare match/input capture
3
CMIA3/CMIB3
TCORA3 compare match, or TCORB3 compare match/input
capture
2, 3
TOVI2/TOVI3
Counter 2 or counter 3 overflow
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Section 9 8-Bit Timers
9.5.2
A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A.
If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0
compare match A, an A/D conversion start request will be issued to the A/D converter. If the
TRGE bit in ADCR is 1 at this time, the A/D converter will be started. If the ADTE bit in
8TCSR0 is 1, A/D converter external trigger pin (ADTRG) input is disabled.
9.6
8-Bit Timer Application Example
Figure 9.17 shows how the 8-bit timer module can be used to output pulses with any desired duty
cycle. The settings for this example are as follows:
• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a
TCORA compare match.
• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA
compare match and 0 is output on a TCORB compare match.
The above settings enable a waveform with the cycle determined by TCORA and the pulse width
detected by TCORB to be output without software intervention.
8TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 9.17 Example of Pulse Output
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Section 9 8-Bit Timers
9.7
Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
9.7.1
Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the
counter takes priority and the write is not performed. Figure 9.18 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8TCNT address
Internal write signal
Counter clear signal
8TCNT
N
H'00
Figure 9.18 Contention between 8TCNT Write and Clear
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Section 9 8-Bit Timers
9.7.2
Contention between 8TCNT Write and Increment
If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and
8TCNT is not incremented. Figure 9.19 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8 TCNT address
Internal write signal
8TCNT input clock
8TCNT
N
M
8TCNT write data
Figure 9.19 Contention between 8TCNT Write and Increment
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Section 9 8-Bit Timers
9.7.3
Contention between TCOR Write and Compare Match
If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 9.20 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
TCOR address
Address bus
Internal write signal
8TCNT
N
TCOR
N
N+1
M
TCOR write data
Compare match signal
Figure 9.20 Contention between TCOR Write and Compare Match
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Inhibited
Section 9 8-Bit Timers
9.7.4
Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input
capture is read. Figure 9.21 shows the timing in this case.
TCORB read cycle
T1
T2
T3
φ
Address bus
TCORB address
Internal read signal
Input capture signal
TCORB
Internal data bus
N
M
N
Figure 9.21 Contention between TCOR Read and Input Capture
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Section 9 8-Bit Timers
9.7.5
Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 9.22 shows the timing in this case.
T1
T2
T3
φ
Input capture signal
Counter clear signal
8TCNT internal clock
8TCNT
N
TCORB
X
H'00
N
Figure 9.22 Contention between Counter Clearing by Input Capture and Counter
Increment
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Section 9 8-Bit Timers
9.7.6
Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 9.23 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
Input capture signal
M
8TCNT
TCOR
X
M
Figure 9.23 Contention between TCOR Write and Input Capture
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Section 9 8-Bit Timers
9.7.7
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T3 state of an 8TCNT byte write cycle in 16-bit count mode,
the counter write takes priority and the byte data for which the write was performed is not
incremented. The byte data for which a write was not performed is incremented. Figure 9.24
shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT (upper
byte). If an increment pulse occurs in the T2 state, on the other hand, the increment takes priority.
8TCNT (upper byte) byte write cycle
T1
T2
T3
φ
8TCNTH address
Address bus
Internal write signal
8TCNT input clock
8TCNT (upper byte)
N
8TCNT (lower byte)
X
N+1
8TCNT write data
X+1
Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
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Section 9 8-Bit Timers
9.7.8
Contention between Compare Matches A and B
If compare matches A and B occur at the same time, the 8-bit timer operates according to the
relative priority of the output states set for compare match A and compare match B, as shown in
table 9.7.
Table 9.7
Timer Output Priority Order
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
9.7.9
Low
8TCNT Operation and Internal Clock Source Switchover
Switching internal clock sources may cause 8TCNT to increment, depending on the switchover
timing. Table 9.8 shows the relation between the time of the switchover (by writing to bits CKS1
and CKS0) and the operation of 8TCNT.
The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of
the internal clock. If a switchover is made from a low clock source to a high clock source, as in
case No. 3 in table 9.8, the switchover will be regarded as a falling edge, a 8TCNT clock pulse
will be generated, and 8TCNT will be incremented.
8TCNT may also be incremented when switching between internal and external clocks.
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Section 9 8-Bit Timers
Table 9.8
Internal Clock Switchover and 8TCNT Operation
No.
CKS1 and CKS0 Write
Timing
1
High → high switchover*1
8TCNT Operation
Old clock
source
New clock
source
8TCNT clock
8TCNT
N
N+1
CKS bits rewritten
2
High → low switchover
*2
Old clock
source
New clock
source
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
3
Low → high switchover*3
Old clock
source
New clock
source
*4
8TCNT clock
8TCNT
N
N+1
CKS bits rewritten
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N+2
Section 9 8-Bit Timers
No.
CKS1 and CKS0 Write
Timing
4
4
Low → low switchover*
8TCNT Operation
Old clock
source
New clock
source
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
Notes: 1. Including switchovers from the high level to the halted state, and from the halted state
to the high level.
2. Including switchover from the halted state to the low level.
3. Including switchover from the low level to the halted state.
4. The switchover is regarded as a rising edge, causing 8TCNT to increment.
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Section 9 8-Bit Timers
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Section 10 Programmable Timing Pattern Controller (TPC)
Section 10 Programmable Timing Pattern Controller (TPC)
10.1
Overview
The H8/3062 Group has a built-in programmable timing pattern controller (TPC) that provides
pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4bit groups (group 3 to group 0) that can operate simultaneously and independently.
10.1.1
Features
TPC features are listed below.
• 16-bit output data
Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
• Four output groups
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
• Selectable output trigger signals
• Output trigger signals can be selected for each group from the compare match signals of three
16-bit timer channels.
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
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Section 10 Programmable Timing Pattern Controller (TPC)
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of the TPC.
16-bit timer compare match signals
Control logic
TP15
TP14
TP13
TP12
TP11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Legend:
TPMR :
TPCR :
NDERB :
NDERA :
PBDDR :
PADDR :
NDRB :
NDRA :
PBDR :
PADR :
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
Internal
data bus
Pulse output
pins, group 3
PBDR
NDRB
PADR
NDRA
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
Figure 10.1 TPC Block Diagram
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Section 10 Programmable Timing Pattern Controller (TPC)
10.1.3
Pin Configuration
Table 10.1 summarizes the TPC output pins.
Table 10.1 TPC Pins
Name
Symbol
I/O
Function
TPC output 0
TP0
Output
Group 0 pulse output
TPC output 1
TP1
Output
TPC output 2
TP2
Output
TPC output 3
TP3
Output
TPC output 4
TP4
Output
TPC output 5
TP5
Output
TPC output 6
TP6
Output
TPC output 7
TP7
Output
TPC output 8
TP8
Output
TPC output 9
TP9
Output
TPC output 10
TP10
Output
TPC output 11
TP11
Output
TPC output 12
TP12
Output
TPC output 13
TP13
Output
TPC output 14
TP14
Output
TPC output 15
TP15
Output
Group 1 pulse output
Group 2 pulse output
Group 3 pulse output
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Section 10 Programmable Timing Pattern Controller (TPC)
10.1.4
Register Configuration
Table 10.2 summarizes the TPC registers.
Table 10.2 TPC Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'EE009
Port A data direction register
PADDR
W
H'00
H'00
H'FFFD9
Port A data register
PADR
R/(W)*2
H'EE00A
Port B data direction register
PBDDR
W
H'00
H'00
H'FFFDA
Port B data register
PBDR
R/(W)*2
H'FFFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFFA1
TPC output control register
TPCR
R/W
H'FF
H'FFFA2
Next data enable register B
NDERB
R/W
H'00
H'FFFA3
Next data enable register A
NDERA
R/W
H'00
H'FFFA5/
H'FFFA7*3
Next data register A
NDRA
R/W
H'00
H'FFFA4/
H'FFFA6*3
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC
output groups 0 and 1 by settings in TPCR. When the output triggers are different, the
NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address
of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2
and 3 by settings in TPCR. When the output triggers are different, the NDRB address is
H'FFFA6 for group 2 and H'FFFA4 for group 3.
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Section 10 Programmable Timing Pattern Controller (TPC)
10.2
Register Descriptions
10.2.1
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 7.11, Port A.
10.2.2
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 7.11, Port A.
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Section 10 Programmable Timing Pattern Controller (TPC)
10.2.3
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PBDDR, see section 7.12, Port B.
10.2.4
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 7.12, Port B.
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Section 10 Programmable Timing Pattern Controller (TPC)
10.2.5
Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The
address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output
trigger or different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group
1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
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Section 10 Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Address H'FFFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Rev. 6.00 Mar 18, 2005 page 340 of 970
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Next data 3 to 0
These bits store the next output
data for TPC output group 0
Section 10 Programmable Timing Pattern Controller (TPC)
10.2.6
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
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Section 10 Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Address H'FFFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR11
NDR10
NDR9
NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
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Next data 11 to 8
These bits store the next output
data for TPC output group 2
Section 10 Programmable Timing Pattern Controller (TPC)
10.2.7
Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
Bit
7
6
5
4
3
2
1
0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
0
1
Description
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
(Initial value)
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.2.8
Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8) on a bit-by-bit basis.
Bit
7
6
5
4
3
2
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
0
NDER8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically
transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
0
1
Description
TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0)
TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
Rev. 6.00 Mar 18, 2005 page 344 of 970
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(Initial value)
Section 10 Programmable Timing Pattern Controller (TPC)
10.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match Group 2 compare
event that triggers
match select 1 and 0
TPC output group 3 These bits select
(TP15 to TP12)
the compare match
event that triggers
TPC output group 2
(TP11 to TP8)
Group 1 compare
match select 1 and 0
These bits select
the compare match
Group 0 compare
event that triggers
match select 1 and 0
TPC output group 1
These bits select
(TP7 to TP4)
the compare match
event that triggers
TPC output group 0
(TP3 to TP0)
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Section 10 Programmable Timing Pattern Controller (TPC)
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7
G3CMS1
Bit 6
G3CMS0
0
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 0
1
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 1
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 2
1
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16bit timer channel 2
(Initial value)
1
Description
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5
G2CMS1
Bit 4
G2CMS0
0
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 2
(Initial value)
1
Description
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Section 10 Programmable Timing Pattern Controller (TPC)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3
G1CMS1
Bit 2
G1CMS0
0
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 2
(Initial value)
1
Description
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1
G0CMS1
Bit 0
G0CMS0
0
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 2
(Initial value)
1
Description
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Section 10 Programmable Timing Pattern Controller (TPC)
10.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
3
2
G3NOV G2NOV
1
0
G1NOV G0NOV
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP15 to TP12)
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP11 to TP8 )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP7 to TP4 )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP3 to TP0 )
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in
general register A (GRA). The output values change at compare match A and B.
For details see section 10.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
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Section 10 Programmable Timing Pattern Controller (TPC)
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12).
Bit 3
G3NOV
Description
0
Normal TPC output in group 3 (output values change at compare match A in the
selected 16-bit timer channel)
(Initial value)
1
Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare
match A and B in the selected 16-bit timer channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2
G2NOV
Description
0
Normal TPC output in group 2 (output values change at compare match A in the
selected 16-bit timer channel)
(Initial value)
1
Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare
match A and B in the selected 16-bit timer channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1
G1NOV
Description
0
Normal TPC output in group 1 (output values change at compare match A in the
selected 16-bit timer channel)
(Initial value)
1
Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare
match A and B in the selected 16-bit timer channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0
G0NOV
Description
0
Normal TPC output in group 0 (output values change at compare match A in the
selected 16-bit timer channel)
(Initial value)
1
Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare
match A and B in the selected 16-bit timer channel)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.3
Operation
10.3.1
Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 10.2 illustrates the TPC output operation. Table 10.3 summarizes the TPC operating
conditions.
DDR
NDER
Q
Q
Output trigger signal
C
Q
DR
D
Q NDR
D
Internal
data bus
TPC output pin
Figure 10.2 TPC Output Operation
Table 10.3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
0
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
1
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 10.3.4, Non-Overlapping TPC Output.
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Section 10 Programmable Timing Pattern Controller (TPC)
10.3.2
Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 10.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
N+1
N
GRA
Compare
match A signal
n
NDRB
PBDR
m
n
TP8 to TP15
m
n
Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.3.3
Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 10.4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
16-bit timer
setup
Port and
TPC setup
16-bit timer
setup
Select GR functions
1
1.
Set TIOR to make GRA an output compare
register (with output inhibited).
Set GRA value
2
2.
Set the TPC output trigger period.
Select counting operation
3
3.
Select interrupt request
4
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the
counter clear source with bits CCLR1 and
CCLR0.
4.
Enable the IMFA interrupt in TISRA.
Set initial output data
5
5.
Select port output
6
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Enable TPC output
7
6.
Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
Select TPC output trigger
8
7.
Set the NDER bits of the pins to be used
for TPC output to 1.
Set next TPC output data
9
8.
Select the 16-bit timer compare match
event to be used as the TPC output trigger
in TPCR.
Start counter
10
9.
Set the next TPC output values in the NDR
bits.
Compare match?
No
Yes
Set next TPC output data
11
10. Set the STR bit to 1 in TSTR to start the
timer counter.
11. At each IMFA interrupt, set the next output
values in the NDR bits.
Figure 10.4 Setup Procedure for Normal TPC Output (Example)
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Section 10 Programmable Timing Pattern Controller (TPC)
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
GRA
Time
H'0000
NDRB
80
PBDR
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
TP15
TP14
TP13
TP12
TP11
1. The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output
compare register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt.
2. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
3. The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB
contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt
service routine writes the next output data (H'C0) in NDRB.
4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts.
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.3.4
Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 10.6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
16-bit timer
setup
Select GR functions
1
1. Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
Set GR values
2
2. Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
Select counting operation
3
Select interrupt requests
4
Set initial output data
5
Set up TPC output
6
Enable TPC transfer
7
6. Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
Select TPC transfer trigger
8
7. Set the NDER bits of the pins to be used for
TPC output to 1.
Select non-overlapping groups
9
Set next TPC output data
10
8. In TPCR, select the 16-bit timer compare
match event to be used as the TPC output
trigger.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TISRA.
Port and
TPC setup
16-bit timer
setup
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
9. In TPMR, select the groups that will operate
in non-overlap mode.
11
Start counter
Compare match A?
No
Yes
Set next TPC output data
10. Set the next TPC output values in the NDR
bits.
11. Set the STR bit to 1 in TSTR to start the timer
counter.
12. At each IMFA interrupt, write the next output
value in the NDR bits.
12
Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example)
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Section 10 Programmable Timing Pattern Controller (TPC)
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
Time
NDRB
95
PBDR
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
1. The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are
output compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable
IMFA interrupts.
2. H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits
G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in
NDRB.
3. The timer counter in this 16-bit timer channel is started. When GRB occurs, outputs change from 1 to 0.
When GRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA).
The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
4. Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.3.5
TPC Output Triggering by Input Capture
TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA
functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output
will be triggered by the input capture signal. Figure 10.8 shows the timing.
φ
TIOC pin
Input capture
signal
N
NDR
DR
M
N
Figure 10.8 TPC Output Triggering by Input Capture (Example)
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Section 10 Programmable Timing Pattern Controller (TPC)
10.4
Usage Notes
10.4.1
Operation of TPC Output Pins
TP0 to TP15 are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit
timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the status of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
10.4.2
Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 10.9 illustrates the non-overlapping TPC output operation.
DDR
NDER
Q
Q
Compare match A
Compare match B
C
Q
DR
D
Q NDR
D
TPC output pin
Figure 10.9 Non-Overlapping TPC Output
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Section 10 Programmable Timing Pattern Controller (TPC)
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR. The next data must be written before the next compare match B occurs.
Figure 10.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output
0/1 output
0 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
Figure 10.10 Non-Overlapping Operation and NDR Write Timing
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Section 11 Watchdog Timer
Section 11 Watchdog Timer
11.1
Overview
The H8/3062 Group has an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the H8/3062 chip if a system
crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer
operation, an interval timer interrupt is requested at each TCNT overflow.
11.1.1
Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
• Watchdog timer reset signal resets the entire H8/3062 internally, and can also be output
externally.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire H8/3062 internally. An external reset signal can be output from the RESO pin to
reset other system devices simultaneously. In the versions with on-chip flash memory, the
RESO pin functions as the FWE pin, and therefore there is no function for outputting a reset
signal externally.
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Section 11 Watchdog Timer
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the WDT.
Overflow
TCNT
Interrupt signal
(interval timer)
Interrupt
control
TCSR
Reset control
Internal
data bus
Internal clock sources
φ/2
RSTCSR
Reset
(internal, external)
Read/
write
control
φ/32
φ/64
Clock
Clock
selector
φ/128
φ/256
φ/512
Legend:
TCNT
: Timer counter
TCSR
: Timer control/status register
RSTCSR : Reset control/status register
φ/2048
φ/4096
Figure 11.1 WDT Block Diagram
11.1.3
Pin Configuration
Table 11.1 describes the WDT output pin*.
Note: * Not present in the versions with on-chip flash memory.
Table 11.1 WDT Pin
Name
Abbreviation
I/O
Function
Reset output
RESO
Output*
External output of the watchdog timer reset signal
Note: * Open-drain output
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Section 11 Watchdog Timer
11.1.4
Register Configuration
Table 11.2 summarizes the WDT registers.
Table 11.2 WDT Registers
Address*1
Write*2
H'FFF8C
H'FFF8E
Read
Name
Abbreviation
R/W
Initial Value
*3
H'FFF8C
Timer control/status register
TCSR
R/(W)
H'18
H'FFF8D
Timer counter
TCNT
R/W
H'00
RSTCSR
R/(W)*3
H'3F
H'FFF8F
Reset control/status register
Notes: 1. Lower 20 bits of the address in advanced mode
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
11.2
Register Descriptions
11.2.1
Timer Counter (TCNT)
TCNT is an 8-bit readable and writable up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: The method for writing to TCNT is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Rewriting.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
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Section 11 Watchdog Timer
11.2.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and
clock source.
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/(W)*
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Notes: The method for writing to TCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Rewriting.
* Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
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Section 11 Watchdog Timer
Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF
0
1
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
(Initial value)
[Setting condition]
Set when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer: requests interval timer interrupts
1
Watchdog timer: generates a reset signal
(Initial value)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear
the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1,
TME should be cleared to 0.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT is counting
(Initial value)
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
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Section 11 Watchdog Timer
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2
CKS2
Bit 1
CKS1
0
0
1
1
0
1
11.2.3
Bit 0
CKS0
Description
0
φ/2
1
φ /32
0
φ /64
1
φ /128
0
φ /256
1
φ /512
0
φ /2048
1
φ /4096
(Initial value)
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST
RSTOE
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/(W)*
R/W
—
—
—
—
—
—
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Rewriting.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
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Section 11 Watchdog Timer
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3062 chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Bit 7
WRST
Description
0
[Clearing conditions]
1
•
Reset signal at RES pin.
•
Read WRST when WRST =1, then write 0 in WRST.
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the versions with on-chip flash memory.
Bit 6
RSTOE Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
11.2.4
Notes on Register Rewriting
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 11.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
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Section 11 Watchdog Timer
15
TCNT write
Address
H'FFF8C*
H'5A
15
TCSR write
Address
8 7
H'FFF8C*
0
Write data
8 7
H'A5
0
Write data
Note: * Lower 20 bits of the address in advanced mode
Figure 11.2 Format of Data Written to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To
write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the
write data. Writing this word transfers a write data value into the RSTOE bit.
Writing 0 in WRST bit
Address
H'FFF8E*
Writing to RSTOE bit
Address
15
8 7
H'A5
15
H'FFF8E*
0
H'00
8 7
H'5A
0
Write data
Note: * Lower 20 bits of the address in advanced mode
Figure 11.3 Format of Data Written to RSTCSR
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Section 11 Watchdog Timer
Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address
H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR.
These registers are therefore read like other registers. Byte transfer instructions can be used for
reading. Table 11.3 lists the read addresses of TCNT, TCSR, and RSTCSR.
Table 11.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*
Register
H'FFF8C
TCSR
H'FFF8D
TCNT
H'FFF8F
RSTCSR
Note: * Lower 20 bits of the address in advanced mode
11.3
Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
11.3.1
Watchdog Timer Operation
Figure 11.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3062 is internally reset for a duration of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR. Note that there is no RESO pin in the versions with onchip flash memory.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
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Section 11 Watchdog Timer
WDT overflow
H'FF
TME set to 1
TCNT count
value
H'00
OVF = 1
Start
H'00 written
in TCNT
Internal
reset signal
Reset
H'00 written
in TCNT
518 states
RESO
132 states
Figure 11.4 Operation in Watchdog Timer Mode
11.3.2
Interval Timer Operation
Figure 11.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
H'FF
TCNT
count value
Time t
H'00
WT/ IT = 0
TME = 1
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Figure 11.5 Interval Timer Operation
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Section 11 Watchdog Timer
11.3.3
Timing of Setting of Overflow Flag (OVF)
Figure 11.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT
overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval
timer interrupt is generated in interval timer operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 11.6 Timing of Setting of OVF
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Section 11 Watchdog Timer
11.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 11.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3062 chip. This internal reset signal clears OVF to 0, but the WRST bit
remains set to 1. The reset routine must therefore clear the WRST bit.
φ
H'FF
TCNT
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset
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Section 11 Watchdog Timer
11.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 11.8.
CPU: TCNT write cycle
T1
T2
T3
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 11.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
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Section 11 Watchdog Timer
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Section 12 Serial Communication Interface
Section 12 Serial Communication Interface
12.1
Overview
The H8/3062 Group has a serial communication interface (SCI) with two independent channels.
The two channels have identical functions. The SCI can communicate in both asynchronous and
synchronous mode. It also has a multiprocessor communication function for serial communication
among two or more processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details, see section 21.6, Module Standby Function.
The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification
Card) standard. This function supports serial communication with a smart card. Switching
between the normal serial communication interface and the smart card interface is carried out by
means of a register setting.
12.1.1
Features
SCI features are listed below.
• Selection of synchronous or asynchronous mode for serial communication
Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous communication.
It can also communicate with two or more other processors using the multiprocessor
communication function. There are 12 selectable serial data transfer formats.
 Data length:
7 or 8 bits
 Stop bit length:
1 or 2 bits
 Parity:
even/odd/none
 Multiprocessor bit:
1 or 0
 Receive error detection: parity, overrun, and framing errors
 Break detection:
by reading the RxD level directly when a framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function.
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Section 12 Serial Communication Interface
•
•
•
•
•
There is a single serial data communication format.
 Data length:
8 bits
 Receive error detection: overrun errors
Full-duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
The following settings can be made for the serial data to be transferred
 LSB-first or MSB-first transfer
 Inversion of data logic level
Built-in baud rate generator with selectable bit rates
Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin
Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently.
Features of the smart card interface are listed below.
• Asynchronous communication
 Data length: 8 bits
 Parity bits generated and checked
 Error signal output in receive mode (parity error)
 Error signal detect and automatic data retransmit in transmit mode
 Supports both direct convention and inverse convention
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested
independently.
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Section 12 Serial Communication Interface
12.1.2
Block Diagram
Bus interface
Figure 12.1 shows a block diagram of the SCI.
Module data bus
RDR
TDR
SSR
BRR
SCR
RxD
RSR
TSR
φ
SMR
Baud rate
generator
SCMR
Transmit/receive
control
TxD
Parity generate
Parity check
SCK
Internal data bus
φ/ 4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Legend:
RSR :
RDR :
TSR :
TDR :
SMR :
SCR :
SSR :
BRR :
SCMR :
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Smart card mode register
Figure 12.1 SCI Block Diagram
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Section 12 Serial Communication Interface
12.1.3
Pin Configuration
The SCI has serial pins for each channel as listed in table 12.1.
Table 12.1 SCI Pins
Channel
Name
Abbreviation
I/O
Function
0
Serial clock pin
SCK0
Input/output
SCI0 clock input/output
Receive data pin
RxD0
Input
SCI0 receive data input
Transmit data pin
TxD0
Output
SCI0 transmit data output
1
Serial clock pin
SCK1
Input/output
SCI1 clock input/output
Receive data pin
RxD1
Input
SCI1 receive data input
Transmit data pin
TxD1
Output
SCI1 transmit data output
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Section 12 Serial Communication Interface
12.1.4
Register Configuration
The SCI has internal registers as listed in table 12.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, control the transmitter and receiver
sections, and specify switching between the serial communication interface and smart card
interface.
Table 12.2 SCI Registers
Channel
Address*1
Name
Abbreviation
R/W
Initial Value
0
H’FFFB0
Serial mode register
SMR
R/W
H'00
H’FFFB1
Bit rate register
BRR
R/W
H'FF
H’FFFB2
Serial control register
SCR
R/W
H'00
H’FFFB3
Transmit data register
TDR
R/W
1
H'FF
*2
H’FFFB4
Serial status register
SSR
R/(W)
H'84
H’FFFB5
Receive data register
RDR
R
H'00
H’FFFB6
Smart card mode register
SCMR
R/W
H'F2
H’FFFB8
Serial mode register
SMR
R/W
H'00
H’FFFB9
Bit rate register
BRR
R/W
H'FF
H’FFFBA
Serial control register
SCR
R/W
H'00
H’FFFBB
Transmit data register
TDR
R/W
H'FF
H'84
H’FFFBC
Serial status register
SSR
R/(W)*2
H’FFFBD
Receive data register
RDR
R
H'00
H’FFFBE
Smart card mode register
SCMR
R/W
H'F2
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
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Section 12 Serial Communication Interface
12.2
Register Descriptions
12.2.1
Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When one byte of data has been received, it is
automatically transferred to RDR. The CPU cannot read or write RSR directly.
12.2.2
Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
When the SCI has received one byte of serial data, it transfers the received data from RSR into
RDR for storage, completing the receive operation. RSR is then ready to receive the next data.
This double-buffering allows data to be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
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Section 12 Serial Communication Interface
12.2.3
Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,
the SCI does not load the TDR contents into TSR. The CPU cannot read or write RSR directly.
12.2.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
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Section 12 Serial Communication Interface
12.2.5
Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock
source for the baud rate generator.
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Clock select 1/0
These bits select the
baud rate generator's
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
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Section 12 Serial Communication Interface
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Selects whether the
SCI operates in asynchronous or synchronous mode.
Bit 7
C/A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Selects GSM mode for the smart card
interface.
Bit 7
GM
Description
0
The TEND flag is set 12.5 etu after the start bit
1
The TEND flag is set 11.0 etu after the start bit
(Initial value)
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bit 6—Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In
synchronous mode, the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
1
7-bit data*
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode,
the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE
0
1
Description
Parity bit not added or checked
Parity bit added and checked*
(Initial value)
Note: * When PE bit is set to 1, an even or odd parity bit is added to transmit data according to the
even or odd parity mode selection by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
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Section 12 Serial Communication Interface
Bit 4—Parity Mode (O/E): Specifies whether even parity or odd parity is used for parity addition
and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit
addition and checking, in asynchronous mode. The O/E bit setting is ignored in synchronous
mode, or when parity addition and checking is disabled in asynchronous mode.
Bit 4
O/E
0
1
Description
1
Even parity*
Odd parity*2
(Initial value)
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
0
1
Description
1 stop bit*1
2 stop bits*2
(Initial value)
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.
2. Two stop bits (with value 1) are added to the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the
next incoming character.
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Section 12 Serial Communication Interface
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 12.3.3,
Multiprocessor Communication.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. Four clock sources can be selected by the CKS1 and CKS0 bits: φ, φ/4,
φ/16, and φ/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see section
12.2.8, Bit Rate Register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
φ
0
1
φ/4
1
0
φ/16
1
1
φ/64
(Initial value)
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Section 12 Serial Communication Interface
12.2.6
Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RxI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TxI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
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Section 12 Serial Communication Interface
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
1
Transmit-data-empty interrupt request (TXI) is enabled
(Initial value)
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to
RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE
Description
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled*
(Initial value)
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,
PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5
TE
0
1
Description
Transmitting disabled*1
Transmitting enabled*2
(Initial value)
Notes: 1. The TDRE flag is fixed at 1 in SSR.
2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to
0 after writing of transmit data into TDR. Select the transmit format in SMR before
setting the TE bit to 1.
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Section 12 Serial Communication Interface
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
0
1
Description
Receiving disabled*1
Receiving enabled*2
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in
SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
1
•
The MPIE bit is cleared to 0
•
MPB = 1 in received data
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the
FER and ORER flags to be set.
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Section 12 Serial Communication Interface
Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
Transmit-end interrupt requests (TEI) are disabled*
Transmit-end interrupt requests (TEI) are enabled*
0
1
(Initial value)
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): The function of these bits differs for the
normal serial communication interface and for the smart card interface. Their function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the
SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings
of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or
serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 12.9 in
section 12.3, Operation.
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
Asynchronous mode
Synchronous mode
Internal clock, SCK pin available for generic input/output*1
Internal clock, SCK pin used for serial clock output*1
0
1
Asynchronous mode
Internal clock, SCK pin used for clock output*2
Synchronous mode
1
0
Asynchronous mode
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input*3
Synchronous mode
1
1
Asynchronous mode
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input*3
Synchronous mode
External clock, SCK pin used for serial clock input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
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Section 12 Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in
SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output
pin.
SMR
GM
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
0
SCK pin available for generic input/output
0
0
1
SCK pin used for clock output
1
0
0
SCK pin output fixed low
1
0
1
SCK pin used for clock output
1
1
0
SCK pin output fixed high
1
1
1
SCK pin used for clock output
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(Initial value)
Section 12 Serial Communication Interface
12.2.7
Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the
operating status of the SCI.
Bit
Initial value
Read/Write
5
7
6
TDRE
RDRF
1
0
*1
R/(W)
4
ORER FER/ERS
0
*1
R/(W)
R/(W)
0
*1
*1
R/(W)
3
2
1
0
PER
TEND
MPB
MPBT
0
1
0
0
R
R
R/W
R/(W)*1
Multiprocessor bit transfer
Value of multiprocessor bit
to be transmitted
Multiprocessor bit
Stores the received
multiprocessor bit value
Transmit end*2
Status flag indicating end of transmission
Parity error
Status flag indicating detection of a receive parity
error
Framing error (FER)/Error signal status (ERS)*2
Status flag indicating detection of a receive framing error,
or flag indicating detection of an error signal
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from
TDR into TSR and new data can be written in TDR
Notes: 1. Only 0 can be written, to clear the flag.
2. Function differs between the normal serial communication interface and the smart card interface.
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Section 12 Serial Communication Interface
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1.
The TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial data can be written in TDR.
Bit 7
TDRE
Description
0
TDR contains valid transmit data
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1
TDR does not contain valid transmit data
[Setting conditions]
• The chip is reset or enters standby mode
(Initial value)
•
The TE bit in SCR is cleared to 0
•
TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
0
Description
RDR does not contain new receive data
[Clearing conditions]
• The chip is reset or enters standby mode
•
1
(Initial value)
Read RDRF when RDRF = 1, then write 0 in RDRF
RDR contains new receive data
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is
still set to 1 when reception of the next data ends, an overrun error will occur and the
receive data will be lost.
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Section 12 Serial Communication Interface
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER
0
Description
1
Receiving is in progress or has ended normally*
[Clearing conditions]
• The chip is reset or enters standby mode
•
1
(Initial value)
Read ORER when ORER = 1, then write 0 in ORER
A receive overrun error occurred*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data prior to the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
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Section 12 Serial Communication Interface
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data
reception ended abnormally due to a framing error in asynchronous mode.
Bit 4
FER
0
Description
1
Receiving is in progress or has ended normally*
[Clearing conditions]
• The chip is reset or enters standby mode
•
1
(Initial value)
Read FER when FER = 1, then write 0 in FER
A receive framing error occurred
[Setting condition]
The stop bit at the end of the receive data is checked for a value of 1, and is
found to be 0.*2
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked for a value of 1. The
second stop bit is not checked. When a framing error occurs the SCI transfers the
receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue
while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled.
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal
sent back from the receiving side during transmission. Framing errors are not detected in smart
card interface mode.
Bit 4
ERS
0
Description
Normal reception, no error signal*
[Clearing conditions]
• The chip is reset or enters standby mode
•
1
(Initial value)
Read ERS when ERS = 1, then write 0 in ERS
An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
Note: * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
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Section 12 Serial Communication Interface
Bit 3—Parity Error (PER): Indicates that reception of data with parity added ended abnormally
due to a parity error in asynchronous mode.
Bit 3
PER
0
Description
1
Receiving is in progress or has ended normally*
[Clearing conditions]
• The chip is reset or enters standby mode
•
1
(Initial value)
Read PER when PER = 1, then write 0 in PER
A receive parity error occurred*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0): Indicates that when
the last bit of a serial character was transmitted TDR did not contain valid transmit data, so
transmission has ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1
End of transmission
[Setting conditions]
• The chip is reset or enters standby mode
(Initial value)
•
The TE bit in SCR is cleared to 0
•
TDRE is 1 when the last bit of a 1-byte serial transmit character is
transmitted
Rev. 6.00 Mar 18, 2005 page 393 of 970
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Section 12 Serial Communication Interface
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates that when the last bit of a
serial character was transmitted TDR did not contain valid transmit data, so transmission has
ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
1
End of transmission
[Setting conditions]
• The chip is reset or enters standby mode
(Initial value)
•
The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0
•
TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0)
or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot
be written.
Bit 1
MPB
Description
0
Multiprocessor bit value in receive data is 0*
1
Multiprocessor bit value in receive data is 1
(Initial value)
Note: * If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains
its previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.
The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not
selected, or when the SCI cannot transmit.
Bit 0
MPBT
Description
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
Rev. 6.00 Mar 18, 2005 page 394 of 970
REJ09B0215-0600
(Initial value)
Section 12 Serial Communication Interface
12.2.8
Bit Rate Register (BRR)
BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS0 and CKS1 in SMR.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 12.3 shows examples of BRR settings in asynchronous mode. Table 12.4 shows examples
of BRR settings in synchronous mode.
Rev. 6.00 Mar 18, 2005 page 395 of 970
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Section 12 Serial Communication Interface
Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bit/s)
n
N
110
1
141 0.03
1
148 -0.04
1
174 -0.26
1
212 0.03
150
1
103 0.16
1
108 0.21
1
127 0.00
1
155 0.16
300
0
207 0.16
0
217 0.21
0
255 0.00
1
77
600
0
103 0.16
0
108 0.21
0
127 0.00
0
155 0.16
1200
0
51
0.16
0
54
-0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
-2.48
0
15
0.00
0
19
-2.34
9600
0
6
-6.99
0
6
-2.48
0
7
0.00
0
9
-2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
-2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
-18.62
0
1
-14.67
0
1
0.00
—
—
—
Error (%) n
N
Error (%) n
N
Error (%) n
N
Error (%)
0.16
φ (MHz)
3.6864
4
Bit Rate
(bit/s)
n
N
Error (%) n
110
2
64
0.70
150
1
191 0.00
300
1
95
0.00
600
0
1200
2400
4.9152
N
Error (%) n
2
70
0.03
1
207 0.16
1
103 0.16
191 0.00
0
0
95
0.00
0
47
0.00
5
N
Error (%) n
2
86
0.31
2
88
-0.25
1
255 0.00
2
64
0.16
1
127 0.00
1
129 0.16
207 0.16
0
255 0.00
1
64
0
103 0.16
0
127 0.00
0
129 0.16
0
51
0
63
0
64
0.16
0.00
N
Error (%)
0.16
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
-1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
-6.99
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
-1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
Rev. 6.00 Mar 18, 2005 page 396 of 970
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Section 12 Serial Communication Interface
φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bit/s)
n
N
110
2
106 -0.44
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103 0.16
300
1
155 0.16
1
159 0.00
1
191 0.00
1
207 0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103 0.16
1200
0
155 0.16
0
159 0.00
0
191 0.00
0
207 0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103 0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
-2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
-2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
-2.34
0
4
0.00
0
5
0.00
0
6
-6.99
Error (%) n
N
2
Error (%) n
108 0.08
N
2
Error (%) n
130 -0.07
N
2
Error (%)
141 0.03
φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bit/s)
n
N
110
2
174 -0.26
2
177 -0.25
2
212 0.03
2
217 0.08
150
2
127 0.00
2
129 0.16
2
155 0.16
2
159 0.00
300
1
255 0.00
2
64
0.16
2
77
0.16
2
79
600
1
127 0.00
1
129 0.16
1
155 0.16
1
159 0.00
1200
0
255 0.00
1
64
0.16
1
77
0.16
1
79
2400
0
127 0.00
0
129 0.16
0
155 0.16
0
159 0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
-1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
-2.34
0
19
0.00
31250
0
9
-1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
-2.34
0
9
0.00
Error (%) n
N
Error (%) n
N
Error (%) n
N
Error (%)
0.00
0.00
Rev. 6.00 Mar 18, 2005 page 397 of 970
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Section 12 Serial Communication Interface
φ (MHz)
13
14
Bit Rate
(bit/s)
n
N
110
2
230 -0.08
2
248 -0.17
Error (%) n
N
14.7456
Error (%) n
16
N
Error (%) n
N
Error (%)
3
64
0.70
3
70
0.03
150
2
168 0.16
2
181 0.16
2
191 0.00
2
207 0.16
300
2
84
2
90
0.16
2
95
0.00
2
103 0.16
600
1
168 0.16
1
181 0.16
1
191 0.00
1
207 0.16
1200
1
84
1
90
0.16
1
95
0.00
1
103 0.16
2400
0
168 0.16
0
181 0.16
0
191 0.00
0
207 0.16
4800
0
84
-0.43
0
90
0.16
0
95
0.00
0
103 0.16
9600
0
41
0.76
0
45
-0.93
0
47
0.00
0
51
0.16
19200
0
20
0.76
0
22
-0.93
0
23
0.00
0
25
0.16
31250
0
12
0.00
0
13
0.00
0
14
-1.70
0
15
0.00
38400
0
10
-3.82
0
10
3.57
0
11
0.00
0
12
0.16
-0.43
-0.43
φ (MHz)
18
20
25
Bit Rate
(bit/s)
n
N
Error (%) n
N
Error (%) n
N
110
3
79
-0.12
3
88
-0.25
3
110 -0.02
150
2
233 0.16
3
64
0.16
3
80
300
2
116 0.16
2
129 0.16
2
162 0.15
600
1
233 0.16
2
64
0.16
2
80
1200
1
116 0.16
1
129 0.16
1
162 0.15
2400
0
233 0.16
1
64
0.16
1
80
4800
0
116 0.16
0
129 0.16
0
162 0.15
9600
0
58
-0.69
0
64
0.16
0
80
-0.47
19200
0
28
1.02
0
32
-1.36
0
40
-0.76
31250
0
17
0.00
0
19
0.00
0
24
0.00
38400
0
14
-2.34
0
15
1.73
0
19
1.73
Rev. 6.00 Mar 18, 2005 page 398 of 970
REJ09B0215-0600
Error (%)
-0.47
-0.47
-0.47
Section 12 Serial Communication Interface
Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode
φ (MHz)
Bit
2
Rate
(bit/s) n
N
n
N
n
N
n
N
n
N
n
N
n
N
n
N
n
N
110
3
70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
250
2
124 2
249 3
124 —
—
3
202 3
249 —
—
—
—
—
—
500
1
249 2
124 2
249 —
—
3
101 3
124 3
140 3
155 —
—
1k
1
124 1
249 2
124 —
—
2
202 2
249 3
69
77
97
2.5k
0
199 1
99
199 1
249 2
80
99
2
112 2
124 2
155
5k
0
99
0
199 1
99
1
124 1
162 1
199 1
224 1
249 2
77
10k
0
49
0
99
0
199 0
249 1
80
99
1
112 1
124 1
155
25k
0
19
0
39
0
79
0
99
0
129 0
159 0
179 0
199 0
249
50k
4
8
1
10
13
16
2
1
18
20
3
25
3
0
9
0
19
0
39
0
49
0
64
0
79
0
89
0
99
0
124
100k 0
4
0
9
0
19
0
24
—
—
0
39
0
44
0
49
0
62
250k 0
1
0
3
0
7
0
9
0
12
0
15
0
17
0
19
0
24
500k 0
0*
0
1
0
3
0
4
—
—
0
7
0
8
0
9
—
—
0
0*
0
1
—
—
—
—
0
3
0
4
0
4
—
—
2M
0
0*
—
—
0
1
—
—
—
—
—
—
—
—
0
—
0*
—
2.5M
—
—
—
—
0*
—
—
—
—
—
—
—
—
—
—
—
—
1M
4M
0
Note: Settings with an error of 1% or less are recommended.
Legend:
Blank : No setting available
—
: Setting possible, but error occurs
*
: Continuous transmission/reception not possible
Rev. 6.00 Mar 18, 2005 page 399 of 970
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Section 12 Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
N=
φ
64 ×
22n–1
×B
× 106 – 1
Synchronous mode:
N=
B:
N:
φ:
n:
φ
8 × 22n–1 × B
× 106 – 1
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
System clock frequency (MHz)
Baud rate generator input clock (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
φ × 106
(N + 1) × B × 64 × 22n–1
Rev. 6.00 Mar 18, 2005 page 400 of 970
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– 1 × 100
Section 12 Serial Communication Interface
Table 12.5 shows the maximum bit rates in asynchronous mode for various system clock
frequencies. Tables 12.6 and 12.7 show the maximum bit rates with external clock input.
Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
20
625000
0
0
25
781250
0
0
Rev. 6.00 Mar 18, 2005 page 401 of 970
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Section 12 Serial Communication Interface
Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
20
5.0000
312500
25
6.2500
390625
Rev. 6.00 Mar 18, 2005 page 402 of 970
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Section 12 Serial Communication Interface
Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
25
4.1667
4166666.7
12.3
Operation
12.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses. A smart card interface is also supported as a serial
communication function for an IC card interface.
Selection of asynchronous or synchronous mode and the transmission format for the normal serial
communication interface is made in SMR, as shown in table 12.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 12.9.
For details of the procedures for switching between LSB-first and MSB-first mode and inverting
the data logic level, see section 13.2.1, Smart Card Mode Register (SCMR).
For selection of the smart card interface format, see section 13.3.3, Data Format.
Rev. 6.00 Mar 18, 2005 page 403 of 970
REJ09B0215-0600
Section 12 Serial Communication Interface
Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
 When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate (The on-chip baud rate generator is not used).
Synchronous Mode
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal to external devices.
 When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
Smart Card Interface
• One frame consists of 8-bit data and a parity bit.
• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between
the end of the parity bit and the start of he next frame (elementary time units: time for transfer
of 1 bit).
• In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning
10.5 etu after the start bit.
• In transmitting, if an error signal is received, the same data is automatically transmitted again
after at least 2 etu.
• Only asynchronous communication is supported. There is no synchronous communication
function.
For details of smart card interface operation, see section 13, Smart Card Interface.
Rev. 6.00 Mar 18, 2005 page 404 of 970
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Section 12 Serial Communication Interface
Table 12.8 SMR Settings and Serial Communication Formats
SMR Settings
SCI Communication Format
Bit 7
C/A
Bit 6
CHR
Bit 2
MP
Bit 5
PE
Bit 3
STOP
0
0
0
0
0
1
1
Mode
Data
Length
Asynchronous 8-bit data
mode
Multiprocessor
Bit
Parity Bit
Stop Bit
Length
Absent
1 bit
Absent
2 bits
0
Present
1
1
0
2 bits
0
7-bit data
Absent
1
1
1
0
1
1
—
—
—
0
—
1
—
0
—
1
—
—
1 bit
2 bits
Present
1
0
1 bit
1 bit
2 bits
Asynchronous 8-bit data
mode (multiprocessor
7-bit data
format)
Present Absent
1 bit
2 bits
1 bit
2 bits
Synchronous
mode
8-bit data
Absent
None
Table 12.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
SCI Transmit/Receive clock
Bit 7
C/A
Bit 1 Bit 0
CKE1 CKE0 Mode
Clock Source SCK Pin Function
0
0
0
1
1
Asynchronous Internal
mode
0
0
0
1
1
0
Synchronous
mode
Outputs clock with frequency matching the
bit rate
External
Inputs clock with frequency 16 times the bit
rate
Internal
Outputs the serial clock
External
Inputs the serial clock
1
1
SCI does not use the SCK pin
1
Rev. 6.00 Mar 18, 2005 page 405 of 970
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Section 12 Serial Communication Interface
12.3.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
one or two stop bits. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full-duplex communication
is possible. The transmitter and the receiver are both double-buffered, so data can be written and
read while transmitting and receiving are in progress, enabling continuous transmitting and
receiving.
Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and one or two stop bits (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Idle (mark) state
(LSB)
1
Serial
data
0
D0
1
(MSB)
D1
Start
bit
D2
D3
D4
D5
D6
Transmit or receive data
7 or 8 bits
1 bit
One unit of data (character or frame)
D7
0/1
Parity
bit
1 bit,
or
none
1
1
Stop bit(s)
1 or 2 bits
Figure 12.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)
Communication Formats
Table 12.10 shows the 12 communication formats that can be selected in asynchronous mode. The
format is selected by settings in SMR.
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Section 12 Serial Communication Interface
Table 12.10 Serial Communication Formats (Asynchronous Mode)
SMR Settings
Serial Communication Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P STOP
1
1
0
1
S
7-bit data
P STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S
:
STOP :
P
:
MPB :
2
3
4
5
6
7
8
9
10
11
12
STOP
Start bit
Stop bit
Parity bit
Multiprocessor bit
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Section 12 Serial Communication Interface
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see
table 12.9.
When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit
rate.
When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 12.3
so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1frame
Figure 12.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or
RDR, which retain their previous contents.
When an external clock is used the clock should not be stopped during initialization or subsequent
operation, since operation will be unreliable in this case.
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Section 12 Serial Communication Interface
Figure 12.4 shows a sample flowchart for initializing the SCI.
Start of initialization
Clear TE and RE bits
to 0 in SCR
Set CKE1 and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
(1)
(1) Set the clock source in SCR. Clear the
RIE, TIE, TEIE, MPIE, TE, and RE bits to
0*. If clock output is selected in
asynchronous mode, clock output starts
immediately after the setting is made in
SCR.
(2) Select the communication format in SMR.
Select communication format
in SMR
(2)
Set value in BRR
(3)
Wait
No
1-bit interval elapsed?
Yes
Set TE or RE bit to 1 in SCR
Set the RIE, TIE, TEIE, and
MPIE bits
(4)
(3) Write the value corresponding to the bit
rate in BRR.
This step is not necessary when an
external clock is used.
(4) Wait for at least the interval required to
transmit or receive one bit, then set the
TE or RE bit to 1 in SCR*. Set the RIE,
TIE, TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI
to use the TxD or RxD pin.
<End of initialization>
Note: * In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0
or set to 1 simultaneously.
Figure 12.4 Sample Flowchart for SCI Initialization
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Section 12 Serial Communication Interface
Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
(1)
Initialize
Start transmitting
(2)
Read TDRE flag in SSR
(2) SCI status check and transmit data
write:
read SSR and check that the TDRE
flag is set to 1, then write transmit data
in TDR and clear the TDRE flag to 0.
No
TDRE= 1
(1) SCI initialization:
the transmit data output function of
the TxD pin is selected automatically.
After the TE bit is set to 1, one frame
of 1s is output, then transmission is
possible.
Yes
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
(3) To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the
TDRE flag to 0.
No
All data transmitted?
Yes
(3)
Read TEND flag in SSR
TEND= 1
No
(4) To output a break signal at the end of
serial transmission:
set the DDR bit to 1 and clear the DR
bit to 0, then clear the TE bit to 0 in
SCR.
Yes
Output break signal?
No
(4)
Yes
Clear DR bit to 0 and set
DDR bit to 1
Clear TE bit to 0 in SCR
<End>
Figure 12.5 Sample Flowchart for Transmitting Serial Data
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Section 12 Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin.
 Start bit: One 0 bit is output.
 Transmit data: 7 or 8 bits are output, LSB first.
 Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
 Stop bit(s): One or two 1 bits (stop bits) are output.
 Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
1
0
Parity Stop Start
bit
bit
bit
Data
Start bit
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark) state
TDRE
TEND
1 frame
TXI interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI interrupt
request
TEI interrupt
request
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)
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Section 12 Serial Communication Interface
Receiving Serial Data (Asynchronous Mode): Figure 12.7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
(1)
Initialize
Start receiving
Read ORER, PER, and FER
flags in SSR
(2)
Yes
PER∨FER∨OPER= 1
(3)
(1) SCI initialization:
the receive data input function of the RxD
pin is selected automatically.
(2)(3) Receive error handling and break detection:
if a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if
any of these flags remains set to 1. When a
framing error occurs, the RxD pin can be
read to detect the break state.
Error handling
No
(continued on next page)
Read RDRF flag in SSR
No
(4)
SCI status check and receive data read:
read SSR, check that the RDRF flag is set
to 1, then read receive data from RDR and
clear the RDRF flag to 0. Notification that
the RDRF flag has changed from 0 to 1 can
also be given by the RXI interrupt.
(5)
To continue receiving serial data:
check the RDRF flag, read RDR, and clear
the RDRF flag to 0 before the stop bit of the
current frame is received.
RDRF= 1
Yes
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
(4)
All data received?
(5)
Yes
Clear RE bit to 0 in SCR
<End>
Figure 12.7 Sample Flowchart for Receiving Serial Data
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Section 12 Serial Communication Interface
(3)
Error handling
No
ORER= 1
Yes
Overrun error handling
No
FER= 1
Yes
Break?
Yes
No
Framing error handling
No
Clear RE bit to 0 in SCR
PER= 1
Yes
Parity error handling
Clear ORER, PER, and FER flags
to 0 in SSR
<End>
Figure 12.7 Sample Flowchart for Receiving Serial Data (cont)
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Section 12 Serial Communication Interface
In receiving, the SCI operates as follows:
• The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
synchronizes internally and starts receiving.
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
 Parity check: The number of 1s in the receive data must match the even or odd parity
setting of in the O/E bit in SMR.
 Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
checked.
 Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
from RSR into RDR.
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If
one of the checks fails (receive error*), the SCI operates as shown in table 12.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flags to 0.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 12.11 Receive Error Conditions
Receive
Error
Abbreviation
Condition
Data Transfer
Overrun
error
ORER
Receiving of next data ends while
RDRF flag is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing
error
FER
Stop bit is 0
Receive data is transferred from
RSR to RDR
Parity
error
PER
Parity of received data differs from
even/odd parity setting in SMR
Receive data is transferred from
RSR to RDR
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Section 12 Serial Communication Interface
Figure 12.8 shows an example of SCI receive operation in asynchronous mode.
1
Start
bit
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
Start
bit
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark) state
RDRF
FER
RXI interrupt
request
1 frame
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI interrupt
request
Figure 12.8 Example of SCI Receive Operation
(8-Bit Data with Parity and One Stop Bit)
12.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 12.9 shows an example of communication among different processors using a
multiprocessor format.
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Section 12 Serial Communication Interface
Communication Formats
Four formats are available. Parity bit settings are ignored when a multiprocessor format is
selected. For details see table 12.10.
Clock
See the description of asynchronous mode.
Transmitting
processor
Serial communication line
Serial data
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID=01)
(ID=02)
(ID=03)
(ID=04)
H'AA
H'01
(MPB=1)
ID-sending cycle:
receiving processor address
(MPB=0)
Data-sending cycle:
data sent to receiving processor
specified by ID
Legend:
MPB : Multiprocessor bit
Figure 12.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data: Figure 12.10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
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Section 12 Serial Communication Interface
(1)
Initialize
Start transmitting
Read TDRE flag in SSR
TDRE= 1
(2)
No
(2) SCI status check and transmit data
write:
read SSR, check that the TDRE flag is
1, then write transmit data in TDR.
Also set the MPBT flag to 0 or 1 in
SSR. Finally, clear the TDRE flag to 0.
(3) To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the TDRE
flag to 0.
Yes
Write transmit data in TDR
and set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
(1) SCI initialization:
the transmit data output function of
the TxD pin is selected automatically.
No
(3)
(4) To output a break signal at the end of
serial transmission:
set the DDR bit to 1 and clear the DR
bit to 0, then clear the TE bit to 0 in
SCR.
Yes
Read TEND flag in SSR
TEND= 1
No
Yes
Output break signal?
No
(4)
Yes
Clear DR bit to 0 and set DDR to 1
Clear TE bit to 0 in SCR
<End>
Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
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Section 12 Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin.
 Start bit: One 0 bit is output.
 Transmit data: 7 or 8 bits are output, LSB first.
 Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
 Stop bit(s): One or two 1 bits (stop bits) are output.
 Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 12.11 shows an example of SCI transmit operation using a multiprocessor format.
1
Start
bit
0
Data
D0
D1
Multiprocessor Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Multiprocessor Stop
bit
bit
D7
0/1
1
Idle (mark)
state
TDRE
TEND
TXI interrupt TXI interrupt handler
writes data in TDR and
request
clears TDRE flag to 0
TXI interrupt
request
TEI interrupt
request
1 frame
Figure 12.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
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Section 12 Serial Communication Interface
(1)
Initialize
(1) SCI initialization:
the receive data input function of the
RxD pin is selected automatically.
Start receiving
(2) ID receive cycle:
set the MPIE bit to 1 in SCR.
(2)
Set MPIE bit to 1 in SCR
(3) SCI status check and ID check:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR
and compare it with the processor's
own ID. If the ID does not match, set
the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches,
clear the RDRF flag to 0.
Read ORER and FER flags
in SSR
FER∨ORER= 1
Yes
No
Read RDRF flag in SSR
No
(3)
(4) SCI status check and data receiving:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR.
RDRF= 1
(5) Receive error handling and break
detection:
if a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After executing the
necessary error handling, clear the
ORER and FER flags both to 0.
Receiving cannot resume while either
the ORER or FER flag remains set to
1. When a framing error occurs, the
RxD pin can be read to detect the
break state.
Yes
Read RDRF flag in SSR
No
Own ID?
Yes
Read ORER and FER flags
in SSR
FER∨ORER= 1
Yes
No
(4)
Read RDRF flag in SSR
RDRF= 1
No
Yes
Read receive data from RDR
No
Finished receiving?
Yes
Clear RE bit to 0 in SCR
(5)
Error handling
(continued on next page)
<End>
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data
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Section 12 Serial Communication Interface
(5)
Error handling
No
ORER= 1
Yes
Overrun error handling
No
FER= 1
Yes
Break?
Yes
No
Clear RE bit to 0 in SCR
Framing error handling
Clear ORER, PER, and FER
flags to 0 in SSR
<End>
Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
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Section 12 Serial Communication Interface
Figure 12.13 shows an example of SCI receive operation using a multiprocessor format.
1
Start
bit
0
Stop
MPB bit
Data (ID1)
D0
D1
D7
1
Start
bit
0
1
Stop
MPB bit
Data (data1)
D0
D1
D7
1
0
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
MPB detection
MPIE = 0
RXI interrupt request
(multiprocessor interrupt)
RXI interrupt handler reads
RDR data and clears
RDRF flag to 0
Not own ID, so MPIE
bit is set to 1 again
No RXI interrupt
request, RDR not
updated
a. Own ID does not match data
1
Start
bit
0
Data (ID2)
D0
D1
MPB
D7
1
Stop
bit
1
Start
bit
Data (data2)
0
D0
D1
Stop
bit
MPB
D7
0
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
MPB detection
MPIE = 0
ID1
ID2
RXI interrupt request
(multiprocessor interrupt)
RXI interrupt handler
reads RDR data and
clears RDRF flag to 0
Data2
Own ID, so receiving MPIE bit is set to
continues, with data 1 again
received by RXI
interrupt handler
b. Own ID matches data
Figure 12.13 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
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Section 12 Serial Communication Interface
12.3.4
Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so fullduplex communication is possible. The transmitter and the receiver are also double-buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 12.14 shows the general format in synchronous serial communication.
One unit (character or frame) of transfer data
*
*
Serial clock
LSB
Bit 0
Serial data
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Don't care
Note: * High except in continuous transmitting or receiving
Figure 12.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous
mode the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format
The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added.
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Section 12 Serial Communication Interface
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
See table 12.6 for details of SCI clock source selection.
When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. If receiving in single-character units is
required, an external clock should be selected.
Transmitting and Receiving Data
SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or
RDR, which retain their previous contents.
Figure 12.15 shows a sample flowchart for initializing the SCI.
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Section 12 Serial Communication Interface
Start of initialization
(1) Set the clock source in SCR. Clear the
RIE, TIE, TEIE, MPIE, TE, and RE bits to
0*.
Clear TE and RE bits to 0 in SCR
Set RIE, TIE, MPIE, CKE1 and
CKE0 bits in SCR (leaving TE and (1)
RE bits cleared to 0)
Select communication format
in SMR
Set value in BRR
Wait
1-bit interval elapsed?
(2) Set the communication format in SMR.
(3) Write the value corresponding to the bit rate
in BRR.
This step is not necessary when an
external clock is used.
(2)
(3)
Yes
(4) Wait for at least the interval required to
transmit or receive one bit, then set the TE
or RE bit to 1 in SCR*. Set the RIE, TIE,
TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI to
use the TxD or RxD pin.
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and MPIE
bits as necessary
(4)
<Start transmitting or receiving>
Note: * In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0
or set to 1 simultaneously.
Figure 12.15 Sample Flowchart for SCI Initialization
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Section 12 Serial Communication Interface
Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
(1)
Initialize
Start transmitting
Read TDRE flag in SSR
TDRE= 1
(2)
No
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
No
(2) SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit data in
TDR and clear the TDRE flag to 0.
(3) To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the TDRE
flag to 0.
Yes
All data transmitted?
(1) SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
(3)
Yes
Read TEND flag in SSR
No
TEND= 1
Yes
Clear TE bit to 0 in SCR
<End>
Figure 12.16 Sample Flowchart for Serial Transmitting
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Section 12 Serial Communication Interface
In transmitting serial data, the SCI operates as follows.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is output
from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds
the TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI)
is requested at this time.
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 12.17 shows an example of SCI transmit operation.
Transmit direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request
TXI interrupt handler TXI interrupt
writes data in TDR
request
and clears TDRE
flag to 0
1 frame
Figure 12.17 Example of SCI Transmit Operation
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TEI interrupt
request
Section 12 Serial Communication Interface
Receiving Serial Data (Synchronous Mode): Figure 12.18 shows a sample flowchart for
receiving serial data and indicates the procedure to follow. When switching from asynchronous to
synchronous mode. make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or
PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be
disabled.
(1)
Initialize
(1)
Start receiving
Read ORER flag in SSR
(2)(3) Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the
necessary error handling, clear the
ORER flag to 0. Neither transmitting
nor receiving can resume while the
ORER flag remains set to 1.
(2)
Yes
ORER= 1
(3)
No
Error handling
(4)
SCI status check and receive data
read: read SSR, check that the RDRF
flag is set to 1, then read receive data
from RDR and clear the RDRF flag to
0. Notification that the RDRF flag
has changed from 0 to 1 can also be
given by the RXI interrupt.
(5)
To continue receiving serial data:
check the RDRF flag, read RDR, and
clear the RDRF flag to 0 before the
MSB (bit 7) of the current frame is
received.
(continued on next page)
Read RDRF flag in SSR
No
(4)
RDRF= 1
Yes
Read receive data from
RDR, and clear RDRF
flag to 0 in SSR
No
SCI initialization: the receive data
input function of the RxD pin is
selected automatically.
Finished receiving?
(5)
Yes
Clear RE bit to 0 in SCR
<End>
Figure 12.18 Sample Flowchart for Serial Receiving
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Section 12 Serial Communication Interface
(3)
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
<End>
Figure 12.18 Sample Flowchart for Serial Receiving (cont)
In receiving, the SCI operates as follows:
• The SCI synchronizes with serial clock input or output and synchronizes internally.
• Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table
12.11.
When a receive error has been identified in the error check, subsequent transmit and receive
operations are disabled.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a
receive-error interrupt (ERI) is requested.
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Section 12 Serial Communication Interface
Figure 12.19 shows an example of SCI receive operation.
Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI interrupt
request
Overrun error,
ERI interrupt
request
1 frame
Figure 12.19 Example of SCI Receive Operation
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Section 12 Serial Communication Interface
Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Initialize
(1) SCI initialization: the transmit data output function of
the TxD pin and the read data input function of the
TxD pin are selected, enabling simultaneous
transmitting and receiving.
(1)
Start of transmitting and receiving
Read TDRE flag in SSR
No
(2) SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
Notification that the TDRE flag has changed from 0
to 1 can also be given by the TXI interrupt.
(2)
TDRE= 1
(3) Receive error handling: if a receive error occurs,
read the ORER flag in SSR, then after executing the
necessary error handling, clear the ORER flag to 0.
Neither transmitting nor receiving can resume while
the ORER flag remains set to 1.
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
(4) SCI status check and receive data read: read SSR,
check that the RDRF flag is 1, then read receive
data from RDR and clear the RDRF flag to 0.
Notification that the RDRF flag has changed from 0
to 1 can also be given by the RXI interrupt.
Read ORER flag in SSR
ORER= 1
Yes
(3)
No
Error handling
Read RDRF flag in SSR
No
(4)
(5) To continue transmitting and receiving serial data:
check the RDRF flag, read RDR, and clear the
RDRF flag to 0 before the MSB (bit 7) of the current
frame is received. Also check that the TDRE flag is
set to 1, indicating that data can be written, write
data in TDR, then clear the TDRE flag to 0 before
the MSB (bit 7) of the current frame is transmitted.
RDRF= 1
Yes
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
End of transmitting
and receiving?
(5)
Yes
Clear TE and RE bits to 0 in SCR
<End>
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving,
clear both the TE bit and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 12.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
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Section 12 Serial Communication Interface
12.4
SCI Interrupts
The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 12.12 lists the interrupt
sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE,
and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller.
A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested
when the TEND flag is set to 1 in SSR.
An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR.
Table 12.12 SCI Interrupt Sources
Interrupt Source
Description
Priority
ERI
Receive error (ORER, FER, or PER)
High
RXI
Receive data register full (RDRF)
TXI
Transmit data register empty (TDRE)
TEI
Transmit end (TEND)
Low
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Section 12 Serial Communication Interface
12.5
Usage Notes
12.5.1
Notes on Use of SCI
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 12.13 shows the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs the RSR
contents are not transferred to RDR, so receive data is lost.
Table 12.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR → RDR
Receive Errors
1
1
0
0
×
0
0
1
0
Framing error
0
0
0
1
Parity error
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
1
1
1
1
×
Overrun error + framing error +
parity error
Overrun error
Framing error + parity error
Legend:
: Receive data is transferred from RSR to RDR.
×: Receive data is not transferred from RSR to RDR.
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Section 12 Serial Communication Interface
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
DR and DDR bits. This feature can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an input/output outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note
that clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 12.21.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode
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Section 12 Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 –
1
) – (L – 0.5) F –
D – 0.5
2N
M:
N:
D:
L:
F:
(1 + F) × 100%
. . . . . . . . (1)
N
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 –
1
2 × 16
= 46.875%
) × 100%
. . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of an External Clock Source:
• When an external clock source is used for the serial clock, after updates TDR, allow an
inversion of at least five system clock (φ) cycles before input of the serial clock to start
transmitting. If the serial clock is input within four states of the TDR update, a malfunction
may occur (See figure 12.22).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
Note: In operation with an external clock source, be sure that t > 4 states.
Figure 12.22 Example of Synchronous Transmission
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D6
D7
Section 12 Serial Communication Interface
Switching from SCK Pin Function to Port Pin Function:
• Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 12.23)
Half-cycle low-level output
SCK/port
1. End of transmission
Data
TE
C/A
Bit 6
4. Low-level output
Bit 7
2. TE = 0
3. C/A = 0
CKE1
CKE0
Figure 12.23 Operation when Switching from SCK Pin Function to Port Pin Function
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Section 12 Serial Communication Interface
• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily
places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an
external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
High-level outputTE
SCK/port
1. End of transmission
Data
TE
Bit 6
Bit 7
2. TE = 0
4. C/A = 0
C/A
3. CKE1 = 1
CKE1
5. CKE1 = 0
CKE0
Figure 12.24 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
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Section 13 Smart Card Interface
Section 13 Smart Card Interface
13.1
Overview
The SCI supports an IC card (smart card) interface handling ISO/IEC7816-3 (Identification Card)
character transmission as a serial communication interface expansion function.
Switchover between the normal serial communication interface and the smart card interface is
controlled by a register setting.
13.1.1
Features
Features of the smart card interface supported by the H8/3062 Group are listed below.
• Asynchronous communication
 Data length: 8 bits
 Parity bit generation and checking
 Transmission of error signal (parity error) in receive mode
 Error signal detection and automatic data retransmission in transmit mode
 Direct convention and inverse convention both supported
• Built-in baud rate generator allows any bit rate to be selected
• Three interrupt sources
 There are three interrupt sources—transmit-data-empty, receive-data-full, and
transmit/receive error—that can issue requests independently.
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Section 13 Smart Card Interface
13.1.2
Block Diagram
Bus interface
Figure 13.1 shows a block diagram of the smart card interface.
Module data bus
RxD
RDR
TDR
RSR
TSR
TxD
Parity generation
SCMR
SSR
SCR
SMR
Transmission/
reception
control
BRR
φ
Baud rate
generator
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
Legend:
SCMR : Smart card mode register
RSR : Receive shift register
RDR : Receive data register
TSR : Transmit shift register
TDR : Transmit data register
SMR : Serial mode register
SCR : Serial control register
SSR : Serial status register
BRR : Bit rate register
TXI
RXI
ERI
Figure 13.1 Block Diagram of Smart Card Interface
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Internal
data bus
Section 13 Smart Card Interface
13.1.3
Pin Configuration
Table 13.1 shows the smart card interface pins.
Table 13.1 Smart Card Interface Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCK
I/O
Clock input/output
Receive data pin
RxD
Input
Receive data input
Transmit data pin
TxD
Output
Transmit data output
13.1.4
Register Configuration
The smart card interface has the internal registers listed in table 13.2. The BRR, TDR, and RDR
registers have their normal serial communication interface functions, as described in section 12,
Serial Communication Interface.
Table 13.2 Smart Card Interface Registers
Channel
Address*1 Name
Abbreviation
R/W
Initial Value
0
H'FFFB0
Serial mode register
SMR
R/W
H'00
H'FFFB1
Bit rate register
BRR
R/W
H'FF
H'FFFB2
Serial control register
SCR
R/W
H'00
1
H'FFFB3
Transmit data register
TDR
H'FFFB4
Serial status register
SSR
R/W
H'FF
R/(W)*2 H'84
H'FFFB5
Receive data register
RDR
R
H'00
H'FFFB6
Smart card mode register
SCMR
R/W
H'F2
H'FFFB8
Serial mode register
SMR
R/W
H'00
H'FFFB9
Bit rate register
BRR
R/W
H'FF
H'FFFBA
Serial control register
SCR
R/W
H'00
H'FFFBB
Transmit data register
TDR
R/W
H'FF
*2
H'FFFBC
Serial status register
SSR
R/(W)
H'84
H'FFFBD
Receive data register
RDR
R
H'00
H'FFFBE
Smart card mode register
SCMR
R/W
H'F2
Notes: 1. Lower 20 bits of the address in advanced mode
2. Only 0 can be written in bits 7 to 3, to clear the flags.
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Section 13 Smart Card Interface
13.2
Register Descriptions
This section describes the new or modified registers and bit functions in the smart card interface.
13.2.1
Smart Card Mode Register (SCMR)
SCMR is an 8-bit readable/writable register that selects smart card interface functions.
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W
R/W
—
R/W
Bit
Reserved bits
Reserved bit
Smart card interface
mode select
Enables or disables
the smart card interface
function
Smart card data invert
Inverts data logic levels
Smart card data transfer direction
Selects the serial/parallel conversion format
SCMR is initialized to H'F2 by a reset and in standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format*1.
Bit 3
SDIR
Description
0
TDR contents are transmitted LSB-first
Receive data is stored LSB-first in RDR
1
TDR contents are transmitted MSB-first
Receive data is stored MSB-first in RDR
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(Initial value)
Section 13 Smart Card Interface
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used in combination with the SDIR bit to communicate with inverse-convention
cards*2. The SINV bit does not affect the logic level of the parity bit. For parity settings, see
section 13.3.4, Register Settings.
Bit 2
SINV
Description
0
Unmodified TDR contents are transmitted
(Initial value)
Receive data is stored unmodified in RDR
1
Inverted TDR contents are transmitted
Receive data is inverted before storage in RDR
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0
SMIF
Description
0
Smart card interface function is disabled
1
Smart card interface function is enabled
(Initial value)
Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used
with the normal serial communication interface. Note that when the communication
format data length is set to 7 bits and MSB-first mode is selected for the serial data to
be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data
are valid.
2. The data logic level inversion function can also be used with the normal serial
communication interface. Note that, when inverting the serial data to be transferred,
parity transmission and parity checking is based on the number of high-level periods at
the serial data I/O pin, and not on the register value.
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Section 13 Smart Card Interface
13.2.2
Serial Status Register (SSR)
The function of SSR bit 4 is modified in smart card interface mode. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Transmit end
Status flag indicating end
of transmission
Error signal status (ERS)
Status flag indicating that an error
signal has been received
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detect framing errors.
Bit 4
ERS
Description
0
Indicates normal transmission, with no error signal returned
(Initial value)
[Clearing conditions]
1
•
The chip is reset, or enters standby mode or module stop mode
•
Software reads ERS while it is set to 1, then writes 0.
Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
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Section 13 Smart Card Interface
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are
modified as follows.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing condition]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
1
End of transmission
[Setting conditions]
(Initial value)
•
The chip is reset or enters standby mode.
•
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
•
TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
Note: etu: Elementary time unit (time for transfer of 1 bit)
13.2.3
Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit
7
6
5
4
3
2
1
0
GM
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
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Section 13 Smart Card Interface
Bit 7
GM
Description
0
Normal smart card interface mode operation
1
•
The TEND flag is set 12.5 etu after the beginning of the start bit.
•
Clock output on/off control only. (Initial value)
GSM mode smart card interface mode operation
•
The TEND flag is set 11.0 etu after the beginning of the start bit.
•
Clock output on/off and fixed-high/fixed-low control.
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 12.2.5,
Serial Mode Register (SMR).
13.2.4
Serial Control Register (SCR)
The function of SCR bits 1 and 0 is modified in smart card interface mode.
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 12.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
0
Internal clock/SCK pin is I/O port
1
Internal clock/SCK pin is clock output
0
Internal clock/SCK pin is fixed at low output
1
Internal clock/SCK pin is clock output
0
Internal clock/SCK pin is fixed at high output
1
Internal clock/SCK pin is clock output
1
1
Rev. 6.00 Mar 18, 2005 page 444 of 970
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(Initial value)
Section 13 Smart Card Interface
13.3
Operation
13.3.1
Overview
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: time for transfer of 1 bit)
is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for 1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
13.3.2
Pin Connections
Figure 13.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to VCC with a resistor.
When the smart card uses the clock generated on the smart card interface, the SCK pin output is
input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is
unnecessary.
The reset signal should be output from one of the H8/3062 Group’s generic ports.
In addition to these pin connections. power and ground connections will normally also be
necessary.
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Section 13 Smart Card Interface
VCC
TxD
RxD
I/O
Data line
SCK
H8/3062 Group Px (port)
chip
Clock line
Reset line
CLK
RST
Smart card
Card-processing device
Figure 13.2 Smart Card Interface Connection Diagram
Note: Setting both TE and RE to 1 without connecting a smart card enables closed
transmission/reception, allowing self-diagnosis to be carried out.
13.3.3
Data Format
Figure 13.3 shows the smart card interface data format. In reception in this mode, a parity check is
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting
device to request retransmission of the data. In transmission, the error signal is sampled and the
same data is retransmitted.
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Section 13 Smart Card Interface
No parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D7
Dp
Output from transmitting device
Parity error
Ds
D0
D1
D2
D3
D4
D5
D6
DE
Output from transmitting device
Legend:
Ds
D0 to D7
Dp
DE
:
:
:
:
Output from
receiving
device
Start bit
Data bits
Parity bit
Error signal
Figure 13.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor.
2. The transmitting device starts transfer of one frame of data. The data frame starts with a start
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
3. With the smart card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
4. The receiving device carries out a parity check. If there is no parity error and the data is
received normally, the receiving device waits for reception of the next data. If a parity error
occurs, however, the receiving device outputs an error signal (DE, low-level) to request
retransmission of the data. After outputting the error signal for the prescribed length of time,
the receiving device places the signal line in the high-impedance state again. The signal line is
pulled high again by a pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data
frame. If it receives an error signal, however, it returns to step 2 and transmits the same data
again.
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Section 13 Smart Card Interface
13.3.4
Register Settings
Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described in this section.
Table 13.3 Smart Card Interface Register Settings
Bit
Register Address*1 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMR
H'FFFB0
GM
0
1
O/E
1
0
CKS1
CKS0
BRR
H'FFFB1
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
SCR
H'FFFB2
TIE
RIE
TE
RE
0
0
BRR1
BRR0
2
*
CKE1
CKE0
TDR
H'FFFB3
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
H'FFFB4
TDRE
RDRF
ORER
ERS
PER
TEND
0
0
RDR
H'FFFB5
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
SCMR
H'FFFB6
—
—
—
—
SDIR
SINV
—
SMIF
Notes: —: Unused bit.
1. Lower 20 bits of the address in advanced mode
2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card
interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the
direct convention type, or set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section
13.3.5, Clock.
Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 13.3.5, Clock, for
the method of calculating the value to be set.
Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial
communication functions. See section 12, Serial Communication Interface, for details. The CKE1
and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock
output, set these bits to 01. Clock output is performed when the GM bit is set to 1 in SMR. Clock
output can also be fixed low or high.
Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to
0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention
type. To use the smart card interface, set the SMIF bit to 1.
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Section 13 Smart Card Interface
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
2. Inverse Convention (SDIR = SINV = O/E = 1)
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3062 Group, inversion specified by the SINV bit applies only to the data bits, D7 to
D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies
to both transmission and reception.
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Section 13 Smart Card Interface
13.3.5
Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 13.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B=
φ
× 106
1488 × 22n–1 × (N + 1)
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 13.4
Table 13.4 n-Values of CKS1 and CKS0 Settings
n
CKS1
CKS0
0
0
0
1
2
1
1
0
3
1
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
φ (MHz)
N
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
25.00
0
9600.0
13440.9
14400.0
17473.1
19200.0
21505.4
24193.5
33602.2
1
4800.0
6720.4
7200.0
8736.6
9600.0
10752.7
12096.8
16801.1
2
3200.0
4480.3
4800.0
5824.4
6400.0
7168.5
8064.5
11200.7
Note: Bit rates are rounded off to two decimal places.
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Section 13 Smart Card Interface
The following equation calculates the bit rate register (BRR) setting from the operating frequency
and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
N=
φ
1488 × 22n–1 × B
× 106 – 1
Table 13.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)
φ (MHz)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
25.0
bit/s
N Error
N Error
N Error
N Error
N Error
N Error
N Error
N Error
9600
0 0.00
1 30
1 25
1 8.99
1 0.00
1 12.01
2 15.99
3 12.49
Table 13.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode)
φ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
20.00
26882
0
0
25.00
33602
0
0
The bit rate error is given by the following equation:
Error (%) =
φ
1488 ×
22n-1
× B × (N + 1)
× 106 – 1
× 100
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Section 13 Smart Card Interface
13.3.6
Transmitting and Receiving Data
Initialization: Before transmitting or receiving data, the smart card interface must be initialized as
described below. Initialization is also necessary when switching from transmit mode to receive
mode, or vice versa.
1. Clear the TE and RE bits to 0 in the serial control register (SCR).
2. Clear error flags ERS, PER, and ORER to 0 in the serial status register (SSR).
3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial
mode register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to
1.
4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR).
When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI
pin functions and go to the high-impedance state.
5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).
6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the
CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
Transmitting Serial Data: As data transmission in smart card mode involves error signal
sampling and retransmission processing, the processing procedure is different from that for the
normal SCI. Figure 13.5 shows a sample transmission processing flowchart.
1.
2.
3.
4.
Perform smart card interface mode initialization as described in Initialization above.
Check that the ERS error flag is cleared to 0 in SSR.
Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR.
Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
5. To continue transmitting data, go back to step 2.
6. To end transmission, clear the TE bit to 0.
The above processing may include interrupt handling.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in
transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are
enabled, a transmit/receive-error interrupt (ERI) will be requested.
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Section 13 Smart Card Interface
The timing of TEND flag setting depends on the GM bit in SMR.
Figure 13.4 shows timing of TEND flag setting.
For details, see Interrupt Operations in this section.
Serial data
Dp
Ds
DE
Guard time
(1) GM = 0
TEND
(2) GM = 1
TEND
12.5 etu
11.0 etu
Figure 13.4 Timing of TEND Flag Setting
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Section 13 Smart Card Interface
Start
Initialization
Start transmitting
No
FER/ERS = 0?
Yes
Error handling
No
TEND = 1?
Yes
Write transmit data in TDR,
and clear TDRE flag
to 0 in SSR
No
All data transmitted?
Yes
No
FER/ERS = 0?
Yes
Error handling
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 13.5 Sample Transmission Processing Flowchart
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Section 13 Smart Card Interface
TDR
1. Data write
Data 1
2. Transfer from TDR to TSR
Data 1
3. Serial data output
Data 1
TSR
(shift register)
Data 1
Data remains in TDR.
Data 1
I/O signal
output
In case of normal transmission : TEND flag is set.
In case of transmit error
: ERS flag is set.
Steps 2 and 3 above are repeated until the
TEND flag is set.
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has
been completed.
Figure 13.6 Relation Between Transmit Operation and Internal Registers
I/O data
Ds
Da
Db
Dc
Dd
De
Df
Dg
Dh
Dp
DE
Guard time
TXI (TEND
interrupt)
12.5 etu
When GM = 0
11.0 etu
When GM = 1
Figure 13.7 Timing of TEND Flag Setting
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Section 13 Smart Card Interface
Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 13.8 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
6. To end reception, clear the RE bit to 0.
Start
Initialization
Start receiving
ORER = 0
and PER = 0?
No
Yes
Error handling
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag to 0 in SSR
No
All data received?
Yes
Clear RE bit to 0
Figure 13.8 Sample Reception Processing Flowchart
The above procedure may include interrupt handling.
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Section 13 Smart Card Interface
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception
and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will
be requested.
For details, see Interrupt Operations in this section.
If a parity error occurs during reception and the PER flag is set to 1, the received data is
transferred to RDR, so the erroneous data can be read.
Switching Modes: When switching from receive mode to transmit mode, first confirm that the
receive operation has been completed, then start from initialization, clearing RE to 0 and setting
TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been
completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND
flag can be used to check that the transmit operation has been completed.
Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means
of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified
width in this case.
Figure 13.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the
CKE0 bit is controlled.
Specified pulse
width
Specified pulse
width
CKE1 value
SCK
SCR write
(CKE0 = 0)
SCR write
(CKE0 = 1)
Figure 13.9 Timing for Fixing Cock Output
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Section 13 Smart Card Interface
Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty
(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt
request (TEI) is not available in smart card mode.
A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested
when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or
ERS flag is set to 1 in SSR. These relationships are shown in table 13.8.
Table 13.8 Smart Card Interface Mode Operating States and Interrupt Sources
Operating State
Transmit Mode
Receive Mode
Flag
Enable Bit
Interrupt Source
Normal operation
TEND
TIE
TXI
Error
ERS
RIE
ERI
Normal operation
RDRF
RIE
RXI
Error
PER, ORER
RIE
ERI
Examples of Operation in GSM Mode: When switching between smart card interface mode and
software standby mode, use the following procedures to maintain the clock duty cycle.
• Switching from smart card interface mode to software standby mode
1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed
output state in software standby mode.
2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 in the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output
is fixed at the specified level.
5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
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Section 13 Smart Card Interface
• Returning from software standby mode to smart card interface mode
1'. Clear the software standby state.
2'. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby
(the current P94 pin state).
3'. Set smart card interface mode and output the clock. Clock signal generation is started with the
normal duty cycle.
Software
standby
Normal operation
1 2 3
4
5 6
Normal operation
1' 2' 3'
Figure 13.10 Procedure for Stopping and Restarting the Clock
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
potential.
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit to 1 in SCR to start clock output.
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Section 13 Smart Card Interface
13.4
Usage Notes
The following points should be noted when using the SCI as a smart card interface.
Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart
card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer
rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing
is shown in figure 13.11.
372 clocks
186 clocks
0
185
185
371 0
371 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.11 Receive Data Sampling Timing in Smart Card Interface Mode
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Section 13 Smart Card Interface
The receive margin can therefore be expressed as follows.
Receive margin in smart card interface mode:
M = (0.5 –
1
) – (L – 0.5) F –
2N
M:
N:
D:
L:
F:
D – 0.5
(1 + F) × 100%
N
Receive margin (%)
Ratio of clock frequency to bit rate (N = 372)
Clock duty cycle (L = 0 to 1.0)
Frame length (L =10)
Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.
When D = 0.5 and F = 0:
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as
described below.
• Retransmission when SCI is in Receive Mode
Figure 13.12 illustrates retransmission when the SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit is automatically set to
1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit
should be cleared to 0 in SSR before the next parity bit sampling timing.
2. The RDRF bit in SSR is not set for the frame in which the error has occurred.
3. If an error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.
4. If no error is found when the received parity bit is checked, the receive operation is assumed to
have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE
bit in SCR is set to the enable state, an RXI interrupt is requested.
5. When a normal frame is received, the data pin is held in three-state at the error signal
transmission timing.
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Section 13 Smart Card Interface
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Frame n+1
Retransmitted frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 13.12 Retransmission in SCI Receive Mode
• Retransmission when SCI is in Transmit Mode
Figure 13.13 illustrates retransmission when the SCI is in transmit mode.
6. If an error signal is sent back from the receiving device after transmission of one frame is
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested.
Frame n
Frame n+1
Retransmitted frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
Transfer from TDR to TSR
Transfer from TDR to TSR
TEND
[7]
[9]
ERS
[6]
[8]
Figure 13.13 Retransmission in SCI Transmit Mode
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Section 13 Smart Card Interface
The smart card interface installed in the H8/3062 Group supports an IC card (smart card) interface
with provision for ISO/IEC7816-3 T=0 (character transmission). Therefore, block transfer
operations are not supported (error signal transmission, detection, and automatic data
retransmission are not performed).
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Section 13 Smart Card Interface
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Section 14 A/D Converter
Section 14 A/D Converter
14.1
Overview
The H8/3062 Group includes a 10-bit successive-approximations A/D converter with a selection
of up to eight analog input channels.
When the A/D converter is not used, it can be halted independently to conserve power. For details
see section 21.6, Module Standby Function.
The H8/3062 Group supports 70/134-state conversion as a high-speed conversion mode. Note that
it differs in this respect from the H8/3048 Group, which supports 134/266-state conversion.
14.1.1
Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the VREF pin.
• High-speed conversion
Conversion time: minimum 5.36 µs per channel
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous A/D conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• Three conversion start sources
The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare
match.
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
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Section 14 A/D Converter
14.1.2
Block Diagram
Figure 14.1 shows a block diagram of the A/D converter.
Internal
data bus
AVSS
AN 0
ADCR
ADCSR
ADDRD
–
AN 2
AN 4
ADDRC
+
AN 1
AN 3
ADDRB
10-bit D/A
ADDRA
VREF
Successiveapproximations register
AVCC
Bus interface
Module data bus
Analog
multiplexer
AN 5
φ/4
Comparator
Control circuit
Sample-andhold circuit
φ/8
AN 6
AN 7
ADI
interrupt signal
ADTRG
Compare match A0
ADTE
8-bit timer 8TCSR0
Legend:
ADCR :
ADCSR :
ADDRA :
ADDRB :
ADDRC :
ADDRD :
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 14.1 A/D Converter Block Diagram
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Section 14 A/D Converter
14.1.3
Pin Configuration
Table 14.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided
into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power
supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.
Table 14.1 A/D Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Reference voltage pin
VREF
Input
Analog reference voltage
Analog input pin 0
AN0
Input
Group 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin
ADTRG
Input
Group 1 analog inputs
External trigger input for starting A/D
conversion
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Section 14 A/D Converter
14.1.4
Register Configuration
Table 14.2 summarizes the A/D converter’s registers.
Table 14.2 A/D Converter Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'FFFE0
A/D data register A H
ADDRAH
R
H'00
H'FFFE1
A/D data register A L
ADDRAL
R
H'00
H'FFFE2
A/D data register B H
ADDRBH
R
H'00
H'FFFE3
A/D data register B L
ADDRBL
R
H'00
H'FFFE4
A/D data register C H
ADDRCH
R
H'00
H'FFFE5
A/D data register C L
ADDRCL
R
H'00
H'FFFE6
A/D data register D H
ADDRDH
R
H'00
H'FFFE7
A/D data register D L
ADDRDL
R
H'00
H'00
H'7E
H'FFFE8
A/D control/status register
ADCSR
R/(W)*2
H'FFFE9
A/D control register
ADCR
R/W
Notes: 1. Lower 20 bits of the address in advanced mode
2. Only 0 can be written in bit 7, to clear the flag.
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Section 14 A/D Converter
14.2
Register Descriptions
14.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
ADDRn
14
12
10
8
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
—
—
—
—
—
15
Bit
13
11
9
7
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
(n = A to D)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 14.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD)
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
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Section 14 A/D Converter
14.2.2
A/D Control/Status Register (ADCSR)
Bit
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel select 2 to 0
These bits select analog
input channels
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing condition]
Read ADF when ADF =1, then write 0 in ADF.
1
[Setting conditions]
• Single mode: A/D conversion ends
•
Scan mode: A/D conversion ends in all selected channels
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(Initial value)
Section 14 A/D Converter
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE
Description
0
A/D end interrupt request (ADI) is disabled
1
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit
timer compare match.
Bit 5
ADST
Description
0
A/D conversion is stopped
1
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
(Initial value)
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 14.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS
Description
0
Conversion time = 134 states (maximum)
1
Conversion time = 70 states (maximum)
(Initial value)
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Section 14 A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0 (Initial value)
AN0
1
AN1
AN0, AN1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
0
AN4
AN4
1
AN5
AN4, AN5
1
0
AN6
AN4 to AN6
1
AN7
AN4 to AN7
1
1
14.2.3
A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W
—
—
—
—
—
—
R/W
Reserved bits
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a
reset and in standby mode.
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Section 14 A/D Converter
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger or 8-bit timer compare match.
Bit 7
TRGE
0
1
Description
Starting of A/D conversion by an external trigger or 8-bit timer compare match is
disabled
(Initial value)
A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or
by an 8-bit timer compare match
External trigger pin and 8-bit timer selection is performed by the 8-bit timer. For details, see
section 9, 8-Bit Timers.
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Reserved: This bit can be read or written, but must not be set to 1.
14.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 14.2 shows the data flow for access to an A/D data register.
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Section 14 A/D Converter
Upper-byte read
Module data bus
CPU
(H'AA)
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower-byte read
CPU
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
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Section 14 A/D Converter
14.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
14.4.1
Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF flag is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 14.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
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Note: * Vertical arrows ( ) indicate instructions executed by software.
ADDRD
ADDRC
ADDRB
A/D conversion (2)
* Set
A/D conversion result (1)
* Read conversion result
Idle
State of channel 3
(AN 3)
ADDRA
Idle
State of channel 2
(AN 2)
Idle
* Clear
State of channel 1
(AN 1)
A/D conversion (1)
* Set
Idle
Idle
A/D conversion
starts
State of channel 0
(AN 0)
ADF
ADST
ADIE
* Set
A/D conversion result (2)
* Read conversion result
Idle
* Clear
Section 14 A/D Converter
Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Section 14 A/D Converter
14.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 14.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested when A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
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Figure 14.4 Example of A/D Converter Operation (Scan Mode,
Channels AN0 to AN2 Selected)
Idle
Idle
Idle
A/D conversion (1)
Set
Transfer
Idle
A/D conversion (3)
Idle
Idle
A/D conversion result (3)
A/D conversion result (2)
A/D conversion result (4)
Idle
Clear
Idle
*1
A/D conversion (5)*2
A/D conversion time
A/D conversion (4)
A/D conversion result (1)
A/D conversion (2)
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
ADDRD
ADDRC
ADDRB
ADDRA
State of channel 3
(AN 3)
State of channel 2
(AN 2)
State of channel 1
(AN 1)
State of channel 0
(AN 0)
ADF
ADST
*1
Continuous A/D conversion
*1
Clear
Section 14 A/D Converter
Section 14 A/D Converter
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D
conversion timing. Table 14.4 indicates the A/D conversion time.
As indicated in figure 14.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 14.4.
In scan mode, the values given in table 14.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when
CKS = 1.
(1)
φ
Address bus
(2)
Write signal
Input sampling
timing
ADF
tD
t SPL
t CONV
Legend:
(1)
: ADCSR write cycle
(2)
: ADCSR address
tD
: Synchronization delay
t SPL : Input sampling time
t CONV : A/D conversion time
Figure 14.5 A/D Conversion Timing
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Section 14 A/D Converter
Table 14.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol
Min
Typ
Max
Min
Typ
Max
Synchronization delay
tD
6
—
9
4
—
5
Input sampling time
tSPL
—
31
—
—
15
—
A/D conversion time
tCONV
131
—
134
69
—
70
Note: Values in the table are numbers of states.
14.4.4
External Trigger Input Timing
A/D conversion can be externally triggered When the TRGE bit is set to 1 in ADCR and the 8-bit
timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-tolow transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1
by software. Figure 14.6 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 14.6 External Trigger Input Timing
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Section 14 A/D Converter
14.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
14.6
Usage Notes
When using the A/D converter, note the following points:
1. Analog Input Voltage Range
During A/D conversion, the voltages input to the analog input pins ANn should be in the range
AVSS ≤ ANn ≤ VREF.
2. Relationships of AVCC and AVSS to VCC and VSS
AVCC, AVSS, VCC, and VSS should be related as follows: AVSS = VSS. AVCC and AVSS must not
be left open, even if the A/D converter is not used.
3. VREF Programming Range
The reference voltage input at the VREF pin should be in the range VREF ≤ AVCC.
4. Note on Board Design
In board layout, separate the digital circuits from the analog circuits as much as possible.
Particularly avoid layouts in which the signal lines of digital circuits cross or closely approach
the signal lines of analog circuits. Induction and other effects may cause the analog circuits to
operate incorrectly, or may adversely affect the accuracy of A/D conversion.
The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply
voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The
analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the
board.
5. Note on Noise
To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to
AN7) and analog reference voltage pin (VREF), connect a protection circuit like the one in
figure 14.7 between AVCC and AVSS. The bypass capacitors connected to AVCC and VREF and
the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If filter capacitors
like the ones in figure 14.7 are connected, the voltage values input to the analog input pins
(AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if A/D
conversion is frequently performed in scan mode so that the current that charges and
discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater
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Section 14 A/D Converter
than that input to the analog input pins via input impedance (Rin). The circuit constants should
therefore be selected carefully.
AV CC
VREF
Rin*2
*1
100 Ω
AN0 to AN7
*1
0.1 µF
AV SS
Notes: 1.
10 µF
0.01 µF
2. Rin: input impedance
Figure 14.7 Example of Analog Input Protection Circuit
Table 14.5 Analog Input Pin Ratings
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
—
10*
kΩ
Allowable signal-source impedance
Note: * When conversion time = 134 states, VCC = 4.0 V to 5.5 V, and φ ≤ 13 MHz. For details, see
section 22. Electrical Characteristics.
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Section 14 A/D Converter
10 kΩ
AN0 to AN7
To A/D converter
20 pF
Figure 14.8 Analog Input Pin Equivalent Circuit
Note: Numeric values are approximate, except in table 14.5.
6. A/D Conversion Accuracy Definitions
A/D conversion accuracy in the H8/3062 Group is defined as follows:
• Resolution
Digital output code length of A/D converter
• Offset error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from minimum voltage value 0000000000 to 0000000001 (figure
14.10)
• Full-scale error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from 1111111110 to 1111111111 (figure 14.10)
• Quantization error
Intrinsic error of the A/D converter; 1/2 LSB (figure 14.9)
• Nonlinearity error
Deviation from ideal A/D conversion characteristic in range from zero volts to full scale,
exclusive of offset error, full-scale error, and quantization error.
• Absolute accuracy
Deviation of digital value from analog input value, including offset error, full-scale error,
quantization error, and nonlinearity error.
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Section 14 A/D Converter
Digital
output
111
Ideal A/D conversion
characteristic
110
101
100
011
010
Quantization error
001
000
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
Analog input
voltage
Figure 14.9 A/D Converter Accuracy Definitions (1)
Full-scale
error
Digital
output
Ideal A/D
conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog input
voltage
Figure 14.10 A/D Converter Accuracy Definitions (2)
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Section 14 A/D Converter
7. Allowable Signal-Source Impedance
The analog inputs of the H8/3062 Group are designed to assure accurate conversion of input
signals with a signal-source impedance not exceeding 10 kΩ. The reason for this rating is that
it enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge
within the sampling time. If the sensor output impedance exceeds 10 kΩ, charging may be
inadequate and the accuracy of A/D conversion cannot be guaranteed.
If a large external capacitor is provided in single mode, then the internal 10-kΩ input
resistance becomes the only significant load on the input. In this case the impedance of the
signal source is not a problem.
A large external capacitor, however, acts as a low-pass filter. This may make it impossible to
track analog signals with high dv/dt (e.g. a variation of 5 mV/µs) (figure 14.11). To convert
high-speed analog signals or to use scan mode, insert a low-impedance buffer.
8. Effect on Absolute Accuracy
Attaching an external capacitor creates a coupling with ground, so if there is noise on the
ground line, it may degrade absolute accuracy. The capacitor must be connected to an
electrically stable ground, such as AVSS.
If a filter circuit is used, be careful of interference with digital signals on the same board, and
make sure the circuit does not act as an antenna.
H8/3062 Group
Sensor output impedance
Sensor
input
10 kΩ
Up to 10 kΩ
Low-pass
filter
C up to 0.1 µF
Equivalent circuit of
A/D converter
Cin =
15 pF
20 pF
Figure 14.11 Analog Input Circuit (Example)
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Section 14 A/D Converter
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Section 15 D/A Converter
Section 15 D/A Converter
15.1
Overview
The H8/3062 Group includes a D/A converter with two channels.
15.1.1
Features
D/A converter features are listed below.
•
•
•
•
•
Eight-bit resolution
Two output channels
Conversion time: maximum 10 µs (with 20-pF capacitive load)
Output voltage: 0 V to VREF
D/A outputs can be sustained in software standby mode
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Section 15 D/A Converter
15.1.2
Block Diagram
Bus interface
Figure 15.1 shows a block diagram of the D/A converter.
Module data bus
DACR
DADR1
8-bit D/A
DA 0
DADR0
AVCC
DASTCR
VREF
DA 1
AVSS
Control circuit
Legend:
DACR
DADR0
DADR1
DASTCR
:
:
:
:
D/A control register
D/A data register 0
D/A data register 1
D/A standby control register
Figure 15.1 D/A Converter Block Diagram
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Internal
data bus
Section 15 D/A Converter
15.1.3
Pin Configuration
Table 15.1 summarizes the D/A converter's input and output pins.
Table 15.1 D/A Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVSS
Input
Analog power supply and reference
voltage
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Analog output pin 0
DA0
Output
Analog output, channel 0
Analog output pin 1
DA1
Output
Analog output, channel 1
Reference voltage input pin
VREF
Input
Analog reference voltage
15.1.4
Register Configuration
Table 15.2 summarizes the D/A converter's registers.
Table 15.2 D/A Converter Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF9C
D/A data register 0
DADR0
R/W
H'00
H'FFF9D
D/A data register 1
DADR1
R/W
H'00
H'FFF9E
D/A control register
DACR
R/W
H'1F
H'EE01A
D/A standby control register
DASTCR
R/W
H'FE
Note: * Lower 20 bits of the address in advanced mode
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Section 15 D/A Converter
15.2
Register Descriptions
15.2.1
D/A Data Registers 0 and 1 (DADR0, DADR1)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the
data to be converted. When analog output is enabled, the D/A data register values are constantly
converted and output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset and in standby mode.
When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers
are not initialized in software standby mode.
15.2.2
D/A Control Register (DACR)
Bit
7
6
5
4
3
2
1
0
DAOE1
DAOE0
DAE
—
—
—
—
—
Initial value
0
0
0
1
1
1
1
1
Read/Write
R/W
R/W
R/W
—
—
—
—
—
D/A enable
Controls D/A conversion
D/A output enable 0
Controls D/A conversion and analog output
D/A output enable 1
Controls D/A conversion and analog output
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in standby mode.
When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers
are not initialized in software standby mode.
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Section 15 D/A Converter
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1
Description
0
DA1 analog output is disabled
1
Channel-1 D/A conversion and DA1 analog output are enabled
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0
Description
0
DA0 analog output is disabled
1
Channel-0 D/A conversion and DA0 analog output are enabled
Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.
When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0
and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.
Output of the conversion results is always controlled independently by DAOE0 and DAOE1.
Bit 7
DAOE1
Bit 6
Bit 5
DAOE0 DAE
Description
0
0
—
D/A conversion is disabled in channels 0 and 1
0
1
0
D/A conversion is enabled in channel 0
0
1
1
D/A conversion is enabled in channels 0 and 1
1
0
0
D/A conversion is disabled in channel 0
D/A conversion is disabled in channel 1
D/A conversion is enabled in channel 1
1
0
1
D/A conversion is enabled in channels 0 and 1
1
1
—
D/A conversion is enabled in channels 0 and 1
When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in
ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D
and D/A conversion.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
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Section 15 D/A Converter
15.2.3
D/A Standby Control Register (DASTCR)
DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software
standby mode.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DASTE
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
Reserved bits
D/A standby enable
Enables or disables D/A output
in software standby mode
DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—D/A Standby Enable (DASTE): Enables or disables D/A output in software standby
mode.
Bit 0
DASTE
Description
0
D/A output is disabled in software standby mode
1
D/A output is enabled in software standby mode
15.3
(Initial value)
Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
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Section 15 D/A Converter
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 15.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
converted result is output after the conversion time.
The output value is
DADR contents
× VREF
256
Output of this conversion result continues until the value in DADR0 is modified or the
DAOE0 bit is cleared to 0.
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
the conversion time.
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
Conversion data 1
DADR0
Conversion data 2
DAOE0
DA 0
Conversion
result 2
Conversion
result 1
High-impedance state
t DCONV
t DCONV
Legend:
t DCONV : D/A conversion time
Figure 15.2 Example of D/A Converter Operation
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Section 15 D/A Converter
15.4
D/A Output Control
In the H8/3062 Group, D/A converter output can be enabled or disabled in software standby mode.
When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby
mode. The D/A converter registers retain the values they held prior to the transition to software
standby mode.
When D/A output is enabled in software standby mode, the reference supply current is the same as
during normal operation.
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Section 16 RAM
Section 16 RAM
16.1
Overview
The H8/3062 Group has high-speed static RAM on-chip. The RAM is connected to the CPU by a
16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM
useful for rapid data transfer.
The on-chip RAM can be enabled or disabled with the RAM enable bit (RAME) in the system
control register (SYSCR). When the on-chip RAM is disabled, that area is assigned to external
space in the expanded modes. The on-chip RAM specifications for the product lineup are shown
in table 16.1.
Table 16.1 H8/3062 Group On-Chip RAM Specifications
H8/3062
F-ZTAT
R-Mask
Version
RAM size
H8/3062
F-ZTAT
B-Mask
Version
H8/3062 Masked
ROM Version,
H8/3062 Masked
ROM B-Mask
Version
H8/3061 Masked
ROM Version,
H8/3061 Masked
ROM B-Mask
Version
H8/3060 Masked
ROM Version,
H8/3060 Masked
ROM B-Mask
Version
H8/3064
F-ZTAT
B-Mask
Version
H8/3064
Masked
ROM
B-Mask
Version
4 kbytes
2 kbytes
8 kbytes
Address Modes
assign- 1, 2, 7
ment
H'FEF20 to H'FFF1F
H'FF720
to
H'FFF1F
H'FDF20
to
H'FFF1F
Modes
3, 4, 5
H'FEF20 to H'FFF1F
H'FFF720
to
H'FFFF1F
H'FFDF20
to
H'FFFF1F
Mode
6
H'FEF20 to H'FFF1F
H'F720
to
H'FF1F
H'FD20
to
H'FF1F
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Section 16 RAM
16.1.1
Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'FEF20*
H'FEF21*
H'FEF22*
H'FEF23*
SYSCR
On-chip RAM
H'FFF1E*
Even addresses
Legend:
SYSCR: System control register
H'FFF1F*
Odd addresses
Note: * This example is of the H8/3062 masked ROM version operating in mode 7. The lower
20 bits of the address are shown.
Figure 16.1 RAM Block Diagram
16.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.2 gives the address and initial value of
SYSCR.
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Section 16 RAM
Table 16.2 System Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'EE012
System control register
SYSCR
R/W
H'09
Note: * Lower 20 bits of the address in advanced mode
16.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable bit
Enables or
disables
on-chip RAM
Software standby
output port enable
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
(Initial value)
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Section 16 RAM
16.3
Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to the addresses shown in
table 16.1 are directed to the on-chip RAM. In modes 1 to 5 (expanded modes), when the RAME
bit is cleared to 0, the off-chip address space is accessed. In mode 6, 7 (single-chip mode), when
the RAME bit is cleared to 0, the on-chip RAM is not accessed: read access always results in H'FF
data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Section 17 ROM
[H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.1
Overview
The H8/3062F-ZTAT R-mask version have 128 kbytes of on-chip flash memory. The H8/3062
(masked ROM version) has 128 kbytes of on-chip masked ROM, the H8/3061 (masked ROM
version) has 96 kbytes, and the H8/3060 (masked ROM version) has 64 kbytes. The ROM is
connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two
states, enabling rapid data transfer.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) as shown in
table 17.1.
The on-chip flash memory product (H8/3062F-ZTAT R-mask version) can be erased and
programmed on-board, as well as with a special-purpose PROM programmer.
Table 17.1 Operating Modes and ROM
Mode Pins
Mode
MD2
MD1
MD0
On-Chip ROM
Mode 1
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
0
1
Disabled (external
address area)
Mode 2
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
1
0
Mode 3
(expanded 16-Mbyte mode with on-chip ROM disabled)
0
1
1
Mode 4
(expanded 16-Mbyte mode with on-chip ROM disabled)
1
0
0
Mode 5
(expanded 16-Mbyte mode with on-chip ROM enabled)
1
0
1
Mode 6
(single-chip normal mode)
1
1
0
Mode 7
(single-chip advanced mode)
1
1
1
Enabled
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.2
Overview of Flash Memory (H8/3062F-ZTAT R-Mask Version)
17.2.1
Features
The features of the flash memory in the H8/3062F-ZTAT R-mask version are summarized below.
• Four flash memory operating modes
 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed in block units, with
the blocks to be erased specified by setting the corresponding register bits. The flash memory
is divided into three 32-kbyte blocks, one 28-kbyte block, and four 1-kbyte blocks.
• Programming/erase times
The flash memory programming time is 10 ms (typ) for simultaneous 32-byte programming,
equivalent approximately to 300 µs (typ) per byte, and the erase time is 100 ms (typ) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
For data transfer in boot mode, the chip’s bit rate can be automatically adjusted to match the
transfer bit rate of the host (9600 or 4800 bps).
• Protect modes
There are three protect modes—hardware, software, and error—which allow protected status
to be designated for flash memory program/erase/verify operations.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• PROM mode
Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as
well as in on-board programming mode.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.2.2
Block Diagram
Figure 17.1 shows a block diagram of the flash memory.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
FLMCR
EBR
Bus interface/controller
RAMCR
Operating
mode
FWE pin*1
Mode pins
FLMSR
H'00000
H'00001
H'00002
H'00003
On-chip Flash memory
(128 kbytes)
H'1FFFC
Legend:
FLMCR
EBR
RAMCR
FLMSR
H'1FFFD
H'1FFFE
H'1FFFF
even address odd address
:
:
:
:
Flash memory control register*2
Erase block register*2
RAM control register*2
Flash memory status register*2
Notes: 1. Functions as the FWE pin in the versions with on-chip flash memory, and as the RESO
pin in the versions with on-chip masked ROM.
2. The registers that control the flash memory (FLMCR, EBR, RAMCR, and FLMSR) are
used only in the versions with on-chip flash memory. They are not provided in the
versions with on-chip masked ROM. Reading the corresponding addresses in a
masked ROM version will always return 1s, and writes to these addresses are
Figure 17.1 Block Diagram of Flash Memory
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.2.3
Pin Configuration
The flash memory is controlled by means of the pins shown in table 17.2.
Table 17.2 Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Flash write enable
FWE*
Input
Flash program/erase protection by hardware
Mode 2
MD2
Input
Sets operating mode of H8/3062F-ZTAT
R-mask version
Mode 1
MD1
Input
Sets operating mode of H8/3062F-ZTAT
R-mask version
Mode 0
MD0
Input
Sets operating mode of H8/3062F-ZTAT
R-mask version
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
Notes: The transmit data pin and receive data pin are used in boot mode.
* In the versions with on-chip masked ROM, the FWE pin functions as the RESO pin.
17.2.4
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 17.3.
Table 17.3 Flash Memory Registers
Register Name
Abbreviation
R/W
Initial Value
Address*1
Flash memory control register
FLMCR
R/W
H'00*2
H'EE030
Erase block register
EBR
R/W
H'00
H'EE032
RAM control register
RAMCR
R/W
H'F1
H'EE077
Flash memory status register
FLMSR
R
H'7F
H'EE07D
Notes: FLMCR, EBR, RAMCR, and FLMSR are 8-bit registers, and should be accessed by byte
access. These registers are used only in the versions with on-chip flash memory. Reading
the corresponding addresses in a version with on-chip masked ROM will always return 1s,
and writes to these addresses are disabled.
1. Lower 20 bits of address in advanced mode
2. When a high level is input to the FWE pin, the initial value is H'80.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.3
Flash Memory Register Descriptions
17.3.1
Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the
corresponding bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the
PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1,
then setting the ESU bit, and finally setting the E bit. FLMCR is initialized by a reset, and in
hardware standby mode and software standby mode. Its initial value is H'80 when a high level is
input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin must be fixed
low, as flash memory on-board programming is not supported. Therefore, bits in this register
cannot be set to 1 in mode 6. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. When setting bits 6 to 0 in this register to 1, each bit should be set individually.
Writes to bits ESU, PSU, EV, and PV in FLMCR are enabled only when FWE = 1 and SWE = 1;
writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when
FWE = 1, SWE = 1, and PSU = 1.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Bit
Initial value
Modes 1
to 4, and 6 Read/Write
Modes 5
and 7
7
6
5
4
3
2
1
0
FWE
SWE
ESU
PSU
EV
PV
E
P
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Initial value
1/0
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program mode
Selects program
mode transition
or clearing
Erase mode
Selects erase mode
transition or clearing
Program-verify mode
Selects program-verify mode
transition or clearing
Erase-verify mode
Selects erase-verify mode transition or clearing
Program setup
Prepares for a transition to program mode
Erase setup
Prepares for a transition to erase mode
Software write enable
Enables or disables programming/erasing
Flash write enable
Sets hardware protection against flash memory programming/erasing
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing. See section 17.9, Flash Memory Programming and Erasing Precautions, for
more information on the use of this bit.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
Bit 6—Software Write Enable (SWE)*1 *2: Enables or disables flash memory programming and
erasing. This bit should be set before setting FLMCR bits 5 to 0 and EBR bits 7 to 0 (Do not set
the ESU, PSU, EV, PV, E, or P bit at the same time).
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Bit 6
SWE
Description
0
Programming/erasing disabled
1
Programming/erasing enabled
(Initial value)
[Setting condition]
When FWE = 1
Bit 5—Erase Setup (ESU)*1: Prepares for a transition to erase mode (Do not set the SWE, PSU,
EV, PV, E, or P bit at the same time).
Bit 5
ESU
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 4—Program Setup (PSU)*1: Prepares for a transition to program mode (Do not set the SWE,
ESU, EV, PV, E, or P bit at the same time).
Bit 4
PSU
Description
0
Program setup cleared
1
Program setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 3—Erase-Verify Mode (EV)*1: Selects erase-verify mode transition or clearing (Do not set
the SWE, ESU, PSU, PV, E, or P bit at the same time).
Bit 3
EV
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Bit 2—Program-Verify Mode (PV)*1: Selects program-verify mode transition or clearing (Do
not set the SWE, ESU, PSU, EV, E, or P bit at the same time).
Bit 2
PV
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 1—Erase Mode (E)*1 *3: Selects erase mode transition or clearing (Do not set the SWE, ESU,
PSU, EV, PV, or P bit at the same time).
Bit 1
E
Description
0
Erase mode cleared
1
Transition to erase mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
Bit 0—Program 1 (P)*1 *3: Selects program mode transition or clearing (Do not set the SWE,
ESU, PSU, EV, PV, or E bit at the same time).
Bit 0
P
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Notes: 1. Do not set multiple bits simultaneously.
Do not cut VCC when a bit is set.
2. The SWE bit must not be set or cleared at the same time as other bits (ESU, PSU, EV,
PV, E, or P).
3. P bit and E bit setting should be carried out in accordance with the program/erase
algorithm shown in section 17.5, Flash Memory Programming/Erasing.
See section 17.9, Flash Memory Programming and Erasing Precautions, for more
information on the use of these bits.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.3.2
Erase Block Register (EBR)
EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not
input to the FWE pin, or when the SWE bit in FLMCR is 0 when a high level is applied to the
FWE pin. When a bit is set in EBR, the corresponding block can be erased. Other blocks are eraseprotected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits
in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block
configuration is shown in table 17.4. To erase all the blocks, erase each block sequentially.
The H8/3062F-ZTAT R-mask version does not support the on-board programming mode in mode
6, so bits in this register cannot be set to 1 in mode 6.
Bit
Initial value
Modes 1
to 4, and 6 Read/Write
Modes 5
and 7
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 to 0—Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
corresponding block (EB7 to EB0) for erasure.
Bits 7–0
EB7–EB0
Description
0
Corresponding block (EB7 to EB0) not selected
1
Corresponding block (EB7 to EB0) selected
(Initial value)
Note: When not performing an erase, clear all EBR bits to 0.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Table 17.4 Flash Memory Erase Blocks
Block (Size)
Address
EB0 (1 kbyte)
H'000000–H'0003FF
EB1 (1 kbyte)
H'000400–H'0007FF
EB2 (1 kbyte)
H'000800–H'000BFF
EB3 (1 kbyte)
H'000C00–H'000FFF
EB4 (28 kbytes)
H'001000–H'007FFF
EB5 (32 kbytes)
H'008000–H'00FFFF
EB6 (32 kbytes)
H'010000–H'017FFF
EB7 (32 kbytes)
H'018000–H'01FFFF
17.3.3
RAM Control Register (RAMCR)
RAMCR selects the RAM area to be used when emulating real-time flash memory programming.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
RAMS
RAM2
RAM1
—
Modes 1
Initial value
1
1
1
1
0
0
0
1
to 4
Read/Write
—
—
—
—
R
R
R
—
Modes 5
Initial value
1
1
1
1
0
0
0
1
to 7
Read/Write
—
—
—
—
R/W*
R/W*
R/W*
—
Reserved bits
Reserved bit
RAM2, RAM1
Used together with bit 3 to select
a flash memory area
RAM select
Used together with bits 2 and 1 to select
a flash memory area
Note: * Cannot be set to 1 in mode 6.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Bit 3—RAM Select (RAMS): Used with bits 2 to 1 to reassign an area to RAM (see table 17.5).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled*. In modes other than 5 to 7, 0 is always read and writing is disabled.
This bit is initialized by a reset and in hardware standby mode. It is not initialized in software
standby mode.
When bit 3 is set, all flash-memory blocks are protected from programming and erasing.
Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 17.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled*. In modes other than 5 to 7, 0 is always read and writing is disabled.
These bits are initialized by a reset and in hardware standby mode. They are not initialized in
software standby mode.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
Note: * Flash memory emulation by RAM is not supported for mode 6 (single chip normal mode),
so programming is possible, but do not set 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set
to 1.
Table 17.5 RAM Area Setting
Bit 3
Bit 2
Bit 1
RAM Area
RAMS
RAM2
RAM1
RAM Emulation Status
H’FFF000–H’FFF3FF
0
0/1
0/1
No emulation
H’000000–H’0003FF
1
0
0
Mapping RAM
H’000400–H’0007FF
1
0
1
H’000800–H’000BFF
1
1
0
H’000C00–H’000FFF
1
1
1
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
ROM area
RAM area
H'000000
H'FFEF20
EB0
ROM blocks
EB0–EB3
(H'000000–
H'000FFF)
H'0003FF
H'000400
H'FFEFFF
H'FFF000
ROM selection
area
EB1
H'0007FF
H'000800
H'000BFF
H'000C00
Mapping RAM
EB2
Actual RAM
H'FFF3FF
H'FFF400
RAM selection
area
RAM
overlap area
(H'FFF000–
H'FFF3FF)
H'FFFF1F
EB3
H'000FFF
Figure 17.2 Example of ROM Area/RAM Area Overlap
17.3.4
Flash Memory Status Register (FLMSR)
FLMSR is used to detect flash memory errors.
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R
—
—
—
—
—
—
—
Reserved bits
Flash memory error (FLER)
Status flag indicating detection of an error during
flash memory programming or erasing
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during flash memory
programming or erasing. When FLER is set to 1, flash memory is placed in the error-protection
state.
Bit 7
FLER
Description
0
1
Flash memory program/erase protection (error protection* ) is disabled (Initial value)
[Clearing condition]
WDT reset, reset by RES pin, or hardware standby mode
1
An error has occurred during flash memory programming/erasing, and error
protection*1 has been enabled
[Setting conditions]
1. When flash memory is read*2 during programming/erasing (including a vector read
or instruction fetch, but excluding a read in a RAM area overlapped onto flash
memory space)
2. Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
3
handling)*
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Notes: 1. For details of error protection, see section 17.6.3, Error Protection.
2. An undefined value will be read in this case.
3. Before a stack or vector read is performed in exception handling.
Bits 6 to 0—Reserved: Read-only bits, always read as 1.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.4
On-Board Programming Mode
When pins are set to on-board programming mode and a reset-start is executed, the chip enters the
on-board programming state in which on-chip flash memory programming, erasing, and verifying
can be carried out. There are two operating modes in this mode—boot mode and user program
mode—set by the mode pins (MD2–MD0) and the FWE pin. The pin settings for entering each
mode are shown in table 17.6. Boot mode and user program mode cannot be used in mode 6 (onchip ROM enabled) in the H8/3062F-ZTAT R-mask version. For notes on FWE pin application
and disconnection, see section 17.9, Flash Memory Programming and Erasing Precautions.
Table 17.6 On-Board Programming Mode Settings
Mode
Boot mode
User program mode
FWE
MD2
MD1
MD0
Notes
*1
*2
0
1
0: VIL
Mode 7
0*2
1
1
1: VIH
Mode 5
1
0
1
Mode 7
1
1
1
Mode 5
1
0
Notes: 1. For the High level input timing, see items 6 and 7 of Notes on Using the Boot Mode.
2. In boot mode, the MD2 setting should be the inverse of the input.
In boot mode in the H8/3062F-ZTAT R-mask version, the values in mode select bits 2
to 0 (MDS2 to MDS0) in the mode control register (MDCR) are the inverse of the levels
at the mode pins (MD2 to MD0). Note that this specification differs from that for H8/300H
Series microcomputer H8/3039F-ZTAT.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
On-Board Programming Modes
• Boot mode
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
Host
2. Programming control program transfer
When boot mode is entered, the boot program in
the H8/3062F-ZTAT R-mask version (originally
incorporated in the chip) is started, an SCI
communication check is carried out, and the
boot program required for flash memory erasing
is automatically transferred to the RAM boot
program area.
Host
Programming control
program
New application
program
New application
program
H8/3062F-ZTAT R-mask version
H8/3062F-ZTAT R-mask version
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
Boot program area
Application
program
(old version)
Application
program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
Host
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Host
New application
program
H8/3062F-ZTAT R-mask version
H8/3062F-ZTAT R-mask version
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
prewrite-erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Figure 17.3 Boot Mode
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
• User program mode
1. Initial state
(1) The program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When the FWE pin is driven high, user software
confirms this fact, executes the transfer program
in the flash memory, and transfers the
programming/erase control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
H8/3062F-ZTAT R-mask version
H8/3062F-ZTAT R-mask version
SCI
Boot program
Flash memory
RAM
SCI
Boot program
RAM
Flash memory
Transfer
program
Transfer
program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
H8/3062F-ZTAT R-mask version
H8/3062F-ZTAT R-mask version
SCI
Boot program
Flash memory
RAM
Transfer Program
SCI
Boot program
RAM
Flash memory
Transfer Program
Programming/
erase control program
Flash memory
erase
Programming/
erase control program
New application
program
Program execution state
Figure 17.4 User Program Mode (Example)
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.4.1
Boot Mode
When boot mode is used, a flash memory programming control program must be prepared
beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode.
When a reset-start is executed after setting the pins of the H8/3062F-ZTAT R-mask version to
boot mode, the boot program already incorporated in the MCU is activated, the low period of the
data sent from the host is first measured, and the bit rate register (BRR) value determined. It is
then possible to receive a user program from off-chip using the on-chip serial communication
interface (SCI) in the H8/3062F-ZTAT R-mask version, and the received user program is written
into the on-chip RAM.
Control then branches to the start address H'FFF400 of the on-chip RAM, the program written in
RAM is executed, and flash memory programming/erasing can be carried out.
Figure 17.5 shows a system configuration diagram when using boot mode, and figure 17.6 shows
the boot program mode execution procedure.
H8/3062F-ZTAT R-mask version
Flash memory
Host
Reception of programming data
Transmission of verify data
RXD1
SCI1
TXD1
On-chip RAM
Figure 17.5 System Configuration When Using Boot Mode
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
1. Set the MCU to boot mode and execute reset-start.
Start
1
Set pins to boot mode and
execute reset-start
2
Host transmits data (H'00)
continuously at prescribed bit rate
2. Set the host to the prescribed bit rate (4800/9600)
and have it transmit H'00 data continuously using a
transfer data format of 8-bit data plus 1 stop bit.
3. The MCU repeatedly measures the low period at the
RXD1 pin and calculates the asynchronous
communication bit rate used by the host.
4. After SCI bit rate adjustment is completed, the MCU
transmits one H'00 data byte to indicate the end of
adjustment.
MCU measures low period
of H'00 data transmitted by host
3
5. On receiving the one-byte data indicating
completion of bit rate adjustment, the host should
confirm normal reception of this indication and
transmit one H'55 data byte.
MCU calculates bit rate and sets
value in bit rate register
4
After bit rate adjustment,
MCU transmits one H'00 data byte to
host to indicate end of adjustment
5
Host confirms normal reception of bit
rate adjustment end indication (H'00),
and transmits one H'55 data byte
6
After receiving H'55, MCU transmits
H'AA to host, and receives, as 2
bytes, number of program bytes (N)
to be transferred to on-chip RAM*1
6. After transmitting H'55, the host receives H'AA and
transmits the number of user program bytes to be
transferred. The number of bytes should be sent as
two bytes, upper byte followed by lower byte. The
host should then transmit sequentially the program
set by the user.
The MCU transmits the received byte count and
user program sequentially to the host, one byte at a
time, as verify data (echo-back).
7. The MCU sequentially writes the received user
program to on-chip RAM area H'FFF400–H'FFFF1F.
8. Before executing the transferred user program, the
MCU branches to the RAM boot program area
(H'FFEF20–H'FFF3FF) and checks for the presence
of data written in the flash memory. If data has been
written in the flash memory, the MCU erases all
blocks.
MCU transfers user program
to RAM*2
7
MCU calculates remaining bytes
to be transferred (N = N – 1)
Transfer end byte count
N = 0?
No
Yes
MCU branches to RAM boot program
area (H'FFEF20–H'FFF3FF), then
checks flash memory user area data
8
Yes
9
No
All data = H'FF?
Delete all flash memory
blocks*3
MCU transmits H'AA, then branches
to RAM area address H'FFF400
and executes user program
transferred to RAM
9. The MCU transmits H'AA, then branches to on-chip
RAM area address H'FFF400 and executes the user
program written in that area.
Notes: 1. The size of the RAM area available to the
user is 2.8 kbytes. The number of bytes to
be transferred must not exceed 2.8 kbytes.
The transfer byte count must be sent as two
bytes, upper byte followed by lower byte.
Example of transfer byte count: for 256
bytes (H'0100), upper byte = H'01, lower
byte = H'00
2. The part of the user program that controls
the flash memory should be set in the
program in accordance with the flash
memory programming/erasing algorithm
described later in this section.
3. If a memory cell does not operate normally
and cannot be erased, the MCU will transmit
one H'FF byte as an erase error and halt the
erase operation and subsequent operations.
Figure 17.6 Boot Mode Execution Procedure
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Automatic SCI Bit Rate Adjustment:
Start
bit
D0
D1
D2
D3
D4
D5
D6
Low period (9 bits) measured (H'00 data)
D7
Stop
bit
High period
(1 or more bits)
Figure 17.7 Measurement of Low Period of Host’s Transmit Data
When boot mode is initiated, the MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host (figure 17.7). The SCI
transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The MCU calculates the
bit rate of the transmission from the host from the measured low period, and transmits one H'00
byte to the host to indicate the end of bit rate adjustment. The host should confirm that this
adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the
MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the
above operations. Depending on the host’s transmission bit rate and the MCU’s system clock
frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure
correct SCI operation, the host’s transfer bit rate should be set to 4800 or 9600 bps*1.
Table 17.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU bit rate is possible. The boot program should be executed within this
system clock range*2.
Table 17.7 System Clock Frequencies for which Automatic Adjustment of MCU Bit Rate is
Possible
Host Bit Rate (bps)
System Clock Frequency for which Automatic Adjustment
of MCU Bit Rate is Possible (MHz)
9600
8 to 20
4800
4 to 20
Notes: 1. Use a host bit rate setting of 4800, or 9600 bps only. No other setting should be used.
2. Although the MCU may also perform automatic bit rate adjustment with bit rate and
system clock combinations other than those shown in table 17.7, a degree of error will
arise between the bit rates of the host and the MCU, and subsequent transfer will not be
performed normally. Therefore, only a combination of bit rate and system clock
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
frequency within one of the ranges shown in table 17.7 can be used for boot mode
execution.
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the user program is transferred via the SCI, as
shown in figure 17.8. The boot program area becomes available when a transition is made to the
execution state for the user program transferred to RAM.
H'FFEF20
Boot program
area
H'FFF3FF
H'FFF400
User program
transfer area
H'FFFF1F
Note: The boot program area cannot be used until a transition is made to the execution state
for the user program transferred to RAM. Note also that the boot program remains in
this area in RAM even after control branches to the user program.
Figure 17.8 RAM Areas in Boot Mode
Notes on Use of Boot Mode:
1. When the H8/3062F-ZTAT R-mask version MCU comes out of reset in boot mode, it
measures the low period of the input at the SCI’s RXD1 pin.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD1 and TXD1 lines should be pulled up on the board.
5. Before branching to the user program the MCU terminates transmit and receive operations by
the on-chip SCI (channel 1) (by clearing the RE and TE bits to 0 in the serial control register
(SCR)), but the adjusted bit rate value remains set in the bit rate register (BRR). The transmit
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
data output pin, TXD1, goes to the high-level output state (P91DDR = 1 in P9DDR, P91DR = 1
in P9DR).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode
setting conditions shown in table 17.6, and then executing a reset-start.
On reset release (a low-to-high transition)*1, the MCU latches the current mode pin states
internally and maintains the boot mode state. Boot mode can be cleared by driving the FWE
pin low, then executing reset release*1, but the following points must be noted.
a. When switching from boot mode to normal mode, the boot mode state within the chip must
first be cleared by reset input via the RES pin. The RES pin must be held low for at least 20
system clock cycles*3.
b. Do not change the input levels at the mode pins (MD2 to MD0) or the FWE pin while in
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. If a watchdog timer reset occurs in the boot mode state, the MCU’s
internal state will not be cleared, and the on-chip boot program will be restarted regardless
of the mode pin settings.
c. The FWE pin must not be driven low while the boot program is running or flash memory is
being programmed or erased*2.
7. If the mode pin and FWE pin input levels are changed from 0 V to VCC or from VCC to 0 V
during a reset (while a low level is being input to the RES pin), the microcomputer’s operating
mode will change. As a result, the state of ports with multiplexed address functions and bus
control output pins (CSn, AS, RD, HWR, LWR) will also change. Therefore, care must be
taken to make pin settings to prevent these pins from being used directly as output signal pins
during a reset, or to prevent collision with signals outside the MCU.
Rev. 6.00 Mar 18, 2005 page 519 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
H8/3062F-ZTAT
R-mask version
CSn
MD2
MD1
MD0
FWE
External
memory,
etc.
System
control
unit
RES
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS)
with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 17.9, Flash
Memory Programming and Erasing Precautions.
3. See section 4.2.2, Reset Sequence, and section 17.9, Flash Memory Programming and
Erasing Precautions. The reset period during operation is a minimum of 10 system
clock cycles for the H8/3062, H8/3061, and H8/3060 (versions with on-chip masked
ROM), but a minimum of 20 system clock cycles for the H8/3062F-ZTAT R-mask
version.
17.4.2
User Program Mode
When the H8/3062F-ZTAT R-mask version is set to user program mode, its flash memory can be
programmed and erased by executing a user program. Therefore, on-board reprogramming of the
on-chip flash memory can be carried out by providing on-board means of FWE control and supply
of programming data, and storing a program/erase control program in part of the program area as
necessary.
To select user program mode, select a mode that enables the on-chip ROM (mode 5 or 7), and
apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 5 and 7.
Flash memory programming and erasing should not be carried out in mode 6. When mode 6 is set,
the FWE pin must be driven low.
Rev. 6.00 Mar 18, 2005 page 520 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
The flash memory itself cannot be read while being programmed or erased, so the control program
that performs programming should be placed in external memory or transferred to RAM and
executed there.
Figure 17.9 shows the execution procedure when user program mode is entered during program
execution in RAM. It is also possible to start from user program mode in a reset-start.
1
MD2 to MD0 = 101, 111
2
Reset-start
3
Transfer on-board programming
program to RAM
4
Branch to program in RAM
5
FWE = high
(user program mode)
6
Execute on-board programming
program in RAM
(flash memory rewriting)
7
Clear SWE bit, then release FWE
(user program mode clearing)
8
Execute user application program
in flash memory
Procedure:
A program that executes operations 3 to 8
below must be written into flash memory by the
user beforehand.
1. Set the mode pins to an on-chip ROM
enabled mode (mode 5 or 7).
2. Start the CPU with a reset. (The CPU can
also be started from user program mode by
applying a high level to the FWE pin during
the reset, i.e. while the RES pin is low*.)
3. Transfer the on-board programming
program to RAM.
4. Branch to the program in RAM.
5. Apply a high level to the FWE pin*.
(Transition to user program mode)
6. Check that the FWE pin is high, then
execute the on-board programming
program in RAM. As a result, rewriting of
the user application program in flash
memory is performed.
7. After rewriting, clear the SWE bit. Drive the
FWE pin from high to low, and clear user
program mode*.
8. On completion of programming, branch to
the user application program in flash
memory and run the program.
Note: * For further information on FWE application and disconnection, see section 17.9, Flash
Memory Programming and Erasing Precautions.
Figure 17.9 User Program Mode Execution Procedure (Example)
Rev. 6.00 Mar 18, 2005 page 521 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Notes: 1. Do not apply a constant high level to the FWE pin. To prevent inadvertent
programming or erasing due to program runaway, etc., apply a high level to the FWE
pin only when the flash memory is programmed or erased (including execution of flash
memory emulation using RAM). Memory cells may not operate normally if
overprogrammed or overerased due to program runaway, etc. Also, while a high level
is applied to the FWE pin, the watchdog timer should be activated to prevent
overprogramming or overerasing due to program runaway, etc.
2. Flash memory rewriting should not be carried out in mode 6. When mode 6 is set, the
FWE pin must be driven low.
17.5
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR.
The state transitions made by the various FLMCR bit settings are shown in figure 17.10. The flash
memory cannot be read while being programmed or erased. Therefore, the program (user
program) that controls flash memory programming/erasing should be located and executed in onchip RAM or external memory.
See section 17.9, Flash Memory Programming and Erasing Precautions, for points to note
concerning programming and erasing, and section 22.2.6, Flash Memory Characteristics, for the
wait times after setting or clearing FLMCR bits.
Notes: 1. Operation is not guaranteed if setting/clearing of the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR is executed by a program in flash memory.
2. When programming or erasing, set the FWE pin input level to the high level, and set
FWE to 1 (programming/erasing will not be executed if FWE = 0).
Rev. 6.00 Mar 18, 2005 page 522 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
*3
E=1
Erase setup
state
Erase mode
E=0
Normal mode
FWE = 1
ESU = 1
ESU = 0
*1
FWE = 0
EV = 1
*2
On-board
SWE = 1
Software
programming mode
programming
Software programming
enable
disable state
SWE = 0
state
Erase-verify
mode
EV = 0
PSU = 1
*4
P=1
PSU = 0
Program
setup state
Program mode
P=0
PV = 1
PV = 0
Program-verify
mode
Notes: 1.
: Normal mode
: On-board programming mode
2. Do not make a state transition by setting or clearing multiple bits simultaneously.
3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing
through the software programming enable state.
4. After a transition from program mode to the program setup state, do not enter program mode without
passing through the software programming enable state.
Figure 17.10 FLMCR Bit Settings and State Transitions
17.5.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 17.11 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes
at a time.
The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in the flash memory control
register (FLMCR) and the maximum number of programming operations (N) are shown in table
22.20 in section 22.2.6, Flash Memory Characteristics.
Rev. 6.00 Mar 18, 2005 page 523 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Following the elapse of (x) µs or more after the SWE bit is set to 1 in FLMCR, 32-byte data is
written consecutively to the write addresses. The lower 8 bits of the first address written to must
be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers
are performed. The program address and program data are latched in the flash memory. A 32-byte
data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must
be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (y + z + α + ß) µs as the WDT overflow period. Preparation for entering
program mode (program setup) is performed next by setting the PSU bit in FLMCR. The
operating mode is then switched to program mode by setting the P bit in FLMCR after the elapse
of at least (y) µs. The time during which the P bit is set is the flash memory programming time.
Make a program setting so that the time for one programming operation is within the range of (z)
µs.
The wait time after P bit setting must be changed according to the number of reprogramming
loops. For details, see section 22.2.6, Flash Memory Characteristics.
17.5.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
Clear the P bit in FLMCR, then wait for at least ( α ) µs before clearing the PSU bit to exit
program mode. After exiting program mode, the watchdog timer setting is also cleared. The
operating mode is then switched to program-verify mode by setting the PV bit in FLMCR. Before
reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to
be read. The dummy write should be executed after the elapse of (γ ) µs or more. When the flash
memory is read in this state (verify data is read in 16-bit units), the data at the latched address is
read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the
originally written data is compared with the verify data, and reprogram data is computed (see
figure 17.11) and transferred to RAM. After verification of 32 bytes of data has been completed,
exit program-verify mode, wait for at least (η) µs, then determine whether 32-byte programming
has finished. If reprogramming is necessary, set program mode again, and repeat the
program/program-verify sequence as before. The maximum number of repetitions of the
program/program-verify sequence is indicated by the maximum number of programming
operations (N).
Note: A 32-byte area to store program data and a 32-byte area to store reprogram data are
required in RAM.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Start
*1
Set SWE bit in FLMCR
Wait (x) µs
*6
Store 32-byte write data in write data area
and reprogram data area
Programming operation counter n ← 1
Consecutively write 32-byte data in
reprogram data area in RAM to flash memory
Notes: 1. Programming should be performed in the erased state (Perform
32-byte programming on memory after all 32 bytes have been
erased).
2. Data transfer is performed by byte transfer (word transfer is not
possible), with the write start address at a 32-byte boundary.
The lower 8 bits of the first address written to must be H'00,
H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data
transfer must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
3. Verify data is read in 16-bit (word) units (Byte-unit reading is
also possible).
4. Reprogram data is determined by the computation shown in the
table below (comparison of data stored in the program data
area with verify data). Programming of reprogram data 0 bits is
executed in the next programming loop. Therefore, even bits for
which programming has been completed will be programmed
again if the result of the subsequent verify operation is NG.
5. An area for storing write data (32 bytes) and an area for storing
reprogram data (32 bytes) must be provided in RAM. The
contents of the latter are rewritten in accordance with the
reprogramming data computation.
6. The values of x, y, z, α, β, γ, ε, η, and N are shown in section
22.2.6, Flash Memory Characteristics.
7. The value of z depends on the number of reprogramming loops
(n). Details are given in section 20.2.6, Flash Memory
Characteristics.
*2
Enable WDT
Set PSU bit in FLMCR
Wait (y) µs
*6
Set P bit in FLMCR
Wait (z) µs
Start of programming
*6 *7
Clear P bit in FLMCR
Wait (α) µs
End of programming
*6
Clear PSU bit in FLMCR
Wait (β) µs
*6
Disable WDT
Set PV bit in FLMCR
Wait (γ) µs
*6
Set verify start address
Programming end flag ← 0
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
Programming OK?
*6
*3
NG
OK
Programming end
flag ← 1 (unfinished)
Reprogram data computation
*4
Transfer computation result to reprogram
data area
*5
Write
Data
Verify
Data
Reprogram
Data
Comments
0
0
1
Programming completed
0
1
0
Programming incomplete; reprogram
1
0
1
—
1
1
1
Still in erased state; no action
RAM
Increment verify address
Program data storage
area (32 bytes)
No
32-byte
data verification completed?
Yes
Clear PV bit in FLMCR
Wait (η) µs
*6
Reprogram
Programming end flag = 0?
No
Reprogram data storage
area (32 bytes)
n←n+1
*6
Yes
n > N?
No
Yes
Clear SWE bit in FLMCR
Clear SWE bit in FLMCR
End of programming
Programming failure
Figure 17.11 Program/Program-Verify Flowchart (32-byte Programming)
Rev. 6.00 Mar 18, 2005 page 525 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.5.3
Erase Mode
When erasing flash memory, the single-block erase flowchart shown in figure 17.12 should be
followed.
The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in the flash memory control
register (FLMCR) and the maximum number of erase operations (N) are shown in table 22.20 in
section 22.2.6, Flash Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register (EBR) at least (x) µs after setting the SWE bit to 1 in FLMCR. Next, the
watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value
greater than ( z ) ms + (y + α + ß) µs as the WDT overflow period. Preparation for entering erase
mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is
then switched to erase mode by setting the E bit in FLMCR after the elapse of at least (y) µs. The
time during which the E bit is set is the flash memory erase time. Ensure that the erase time does
not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
17.5.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least ( α ) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the
EV bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of (y) µs
or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the
erase/erase-verify sequence as before. The maximum number of repetitions of the erase/eraseverify sequence is indicated by the maximum number of erase operations (N).
Rev. 6.00 Mar 18, 2005 page 526 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Start
*1
Set SWE bit in FLMCR
Wait (x) µs
*2
Erase counter n ← 1
*4
*5
Set EBR
Enable WDT
Set ESU bit in FLMCR
Wait (y) µs
*2
Set E bit in FLMCR
Wait (z) ms
Start of erase
*2
Clear E bit in FLMCR
Wait (α) µs
End of erase
*2
Clear ESU bit in FLMCR
Wait (β) µs
*2
Disable WDT
Set EV bit in FLMCR
Wait (γ) µs
*2
Set block start address
to verify address
Increment
verify address
H'FF dummy write to verify address
Wait (ε) µs
*2
Read verify data
*3
Verify data = all 1s?
No
YES
No
Last address of block?
Yes
Clear EV bit in FLMCR
Wait (η) µs
Re-erase
n←n+1
*2
*2
Clear EV bit in FLMCR
Wait (η) µs
*2
No
n>N?
Yes
Notes: 1.
2.
3.
4.
5.
Clear SWE bit in FLMCR
Clear SWE bit in FLMCR
End of erasing
Erase failure
Preprogramming (setting erase block data to all 0s) is not necessary.
The values of x, y, z, α, β, γ, ε, η, and N are shown in section 22.2.6, Flash Memory Characteristics.
Verify data is read in 16-bit (word) units (Byte-unit reading is also possible).
Set only one bit in EBR two or more bits must not be set simultaneously.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 17.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.6
Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error
protection.
17.6.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in the flash memory control register
(FLMCR) and the erase block register (EBR). In the case of error protection, the P bit and E bit
can be set, but a transition is not made to program mode or erase mode (See table 17.8).
Table 17.8 Hardware Protection
Function
Item
Description
Program
Erase
Verify*1
FWE pin
protection
•
When a low level is input to the FWE
pin, FLMCR and EBR are initialized,
and the program/erase-protected
state is entered*4.
Not
2
possible*
Not
3
possible*
Not
possible
Reset/standby
protection
•
In a reset (including a WDT overflow
reset) and in standby mode, FLMCR
and EBR are initialized, and the
program/erase-protected state is
entered.
Not
possible
Not
possible*3
Not
possible
•
In a reset via the RES pin, the reset
state is not entered unless the RES
pin is held low until oscillation
stabilizes after powering on (The
minimum oscillation stabilization time
is 20ms). In the case of a reset
during operation, hold the RES pin
low for at least 20 system clock
5
cycles* .
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Function
Item
Description
Program
Erase
Verify*1
Error protection
•
Not
possible
Not
possible*3
Possible
When a microcomputer operation
error (error generation (FLER=1))
was detected while flash memory
was being programmed/erased, error
protection is enabled. At this time,
the FLMCR and EBR settings are
held, but programming/erasing is
aborted at the time the error was
generated. Error protection is
released only by a reset via the RES
pin or a WDT reset, or in the
hardware standby mode.
Notes: 1.
2.
3.
4.
Two modes: program-verify and erase-verify
The RAM area that overlapped flash memory is deleted.
All blocks become unerasable and specification by block is impossible.
For more information, see section 17.9, Flash Memory Programming and Erasing
Precautions.
5. See section 4.2.2, Reset Sequence and section 17.9, Flash Memory Programming and
Erasing Precautions. The H8/3062F-ZTAT R-mask version require a minimum reset
time during operation of 20 system clocks.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.6.2
Software Protection
Software protection can be implemented by setting the RAMS bit in the RAM control register
(RAMCR) and the erase block register (EBR). With software protection, setting the P or E bit in
the flash memory control register (FLMCR) does not cause a transition to program mode or erase
mode (See table 17.9).
Table 17.9 Software Protection
Functions
Description
Program
Emulation
protection*2
•
Setting the RAMS bit 1 in RAMCR places
all blocks in the program/erase-protected
state.
Not
Not
possible*2 possible*3
Possible
Block
specification
protection
•
Erase protection can be set for individual
4
blocks by settings in EBR* . However,
protection against programming is
disabled.
—
Possible
•
Setting EBR to H'00 places all blocks in
the erase-protected state.
Notes: 1.
2.
3.
4.
Erase
1
Verify*
Item
Not
possible
Two modes: program-verify and erase-verify
A RAM area overlapping flash memory can be programmed.
All blocks are unerasable and block-by-block specification is not possible.
When not erasing, set EBR to H'00.
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.6.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing*1, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
the flash memory status register (FLMSR)*2 and the error protection state is entered. FLMCR and
EBR settings*3 are retained, but program mode or erase mode is aborted at the point at which the
error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit in
FLMCR. However, PV and EV bit setting is enabled, and a transition can be made to verify mode.
Error protection is released only by a RES pin reset, and a WDT reset, or in hardware standby
mode.
Figure 17.13 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P bit or E bit is set to 1 in FLMCR. Note that NMI input
is disabled in this state. For details see section 17.6.4, NMI Input Disabling Conditions.
2. For details of FLER bit setting conditions, see section 17.3.4, Flash Memory Status
Register (FLMSR).
3. FLMCR and EBR can be written to. However, registers will be initialized if a
transition is made to software standby mode in the error protection state.
Rev. 6.00 Mar 18, 2005 page 531 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Memory read verify
mode
Reset or hardware
standby or software
standby
RD VF PR ER FLER = 0
P = 1 or
E=1
Reset release
and hardware
standby release and
software standby release
P = 0 and
E=0
Program mode
Erase mode
RD VF PR ER INIT FLER = 0
RD VF PR ER FLER = 0
Error
occurrence
Error occurrence
(software standby)
Software
standby mode
RD VF PR ER FLER= 1
:
:
:
:
Memory read possible
Verify-read possible
Programming possible
Erasing possible
Reset or hardware
standby
Reset or hardware
standby
Error protection mode
RD
VF
PR
ER
Reset or standby
(hardware protection)
Reset or hardware standby
Software standby
mode release
RD
VF
PR
ER
INIT
:
:
:
:
:
Error protection mode
(software standby)
RD VF PR ER INIT FLER = 1
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Register (FLMCR, EBR) initialization state
Figure 17.13 Flash Memory State Transitions (Modes 5 and 7 (On-Chip ROM Enabled),
High Level Applied to FWE Pin)
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.
To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in
accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,
and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog
timer or other means. There may also be cases where the flash memory is in an erroneous
programming or erroneous erasing state at the point of transition to this protection mode, or where
programming or erasing is not properly carried out because of an abort. In cases such as these, a
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
forced recovery (program rewrite) must be executed using boot mode. However, it may also
happen that boot mode cannot be normally initiated because of overprogramming or overerasing.
17.6.4
NMI Input Disabling Conditions
NMI input is disabled when flash memory is being programmed or erased and while the boot
program is executing in boot mode (until a branch is made to the on-chip RAM area)*1, to give
priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly*2, possibly resulting in MCU runaway.
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests (exception handling and bus release),
including NMI, must therefore be restricted inside and outside the MCU during FWE application.
NMI input is also disabled in the error protection state and while the P or E bit remains set in
FLMCR during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
H'FFEF20 to H'FFF3FF (This branch takes place immediately after transfer of the user
program is completed). Consequently, after the branch to the RAM area, NMI input is
enabled except during programming and erasing. Interrupt requests must therefore be
disabled inside and outside the MCU until the user program has completed initial
programming (including the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased, correct read data will
not be obtained (undetermined values will be returned).
• If the NMI entry in the vector table has not been programmed yet, NMI exception
handling will not be executed correctly.
Rev. 6.00 Mar 18, 2005 page 533 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.7
Flash Memory Emulation in RAM
As flash memory programming and erasing takes time, it may be difficult to carry out tuning by
writing parameters and other data in real time. In this case, real-time programming of flash
memory can be emulated by overlapping part of RAM (H'FFF000 to H'FFF3FF) onto a small
block area in flash memory. This RAM area change is executed by means of bits 3 to 1 in the
RAM control register (RAMCR). After the RAM area change, access is possible both from the
area overlapped onto flash memory and from the original area (H'FFF000 to H'FFF3FF). For
details of RAMCR and the RAM area setting method, see section 17.3.3, RAM Control Register
(RAMCR).
Example of Emulation of Real-Time Flash Memory Programming: In the following example,
RAM area H'FFF000 to H'FFF3FF is overlapped onto flash memory area EB2 (H'000800 to
H'000BFF).
Procedure:
H'000000
1. Part of RAM (H'FFF000 to
H'FFF3FF) is overlapped onto the
area (EB2) requiring real-time
programming (RAMCR bits 3 to 1
are set to 1, 1, 0, and the flash
memory area to be overlapped
(EB2) is selected).
Flash memory
space
Block area
Overlapping ram
EB2 H'000800
area H'000BFF
H'000FFF
*
(Mapping RAM
area)
Real-time programming is
performed using the overlapping
RAM.
3. The programmed data is checked,
then RAM overlapping is cleared
(RAMS bit is cleared).
H'FFEF20
On-chip RAM
area
H'FFEFFF
H'FFF000
H'FFF3FF
H'FFF400
2.
4. The data written in RAM area
H'FFF000 to H'FFF3FF is written to
flash memory space.
(Actual RAM
area)
H'FFFF1F
Note: * When part of RAM (H'FFF000 to H'FFF3FF) is overlapped onto a flash memory small block area,
the flash memory in the overlapped area cannot be accessed. It can be accessed when the overlapping
is cleared.
Figure 17.14 Example of RAM Overlap Operation
Rev. 6.00 Mar 18, 2005 page 534 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Notes on Use of Emulation in RAM:
1. Flash write enable (FWE) application and releasing
As in on-board program mode, care is required when applying and releasing FWE to prevent
erroneous programming or erasing. To prevent erroneous programming and erasing due to
program runaway during FWE application, in particular, the watchdog timer should be set
when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is
being used. For details, see section 17.9, Flash Memory Programming and Erasing
Precautions.
2. NMI input disabling conditions
When the emulation function is used, NMI input is disabled when the P bit or E bit is set to 1
in FLMCR, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode,
when a high level is not being input to the FWE pin, or when the SWE bit in FLMCR is 0
while a high level is being input to the FWE pin.
Rev. 6.00 Mar 18, 2005 page 535 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.8
Flash Memory PROM Mode
The H8/3062F-ZTAT R-mask version have a PROM mode as well as the on-board programming
modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be
freely programmed using a general-purpose PROM writer that supports the Renesas
microcomputer device type with 128-kbyte on-chip flash memory.
17.8.1
Socket Adapters and Memory Map
In PROM mode using a PROM writer, memory reading (verification) and writing and flash
memory initialization (total erasure) can be performed. For these operations, a special socket
adapter is mounted in the PROM writer. The socket adapter product codes are given in table
17.10. In the H8/3062F-ZTAT R-mask version PROM mode, only the socket adapters shown in
this table should be used.
Table 17.10 H8/3062F-ZTAT R-Mask Version Socket Adapter Product Codes
Product Code
Package
Socket Adapter
Product Code
HD64F3062RF
100-pin QFP (FP-100B)
ME3067ESHF1H
HD64F3062RTE
100-pin TQFP (TFP-100B)
ME3067ESNF1H
HD64F3062RFP
100-pin QFP (FP-100A)
ME3067ESFF1H
HD64F3062RF
100-pin QFP (FP-100B)
HF306BQ100D3201
HD64F3062RTE
100-pin TQFP (TFP-100B)
HF306XT100D3201
HD64F3062RFP
100-pin QFP (FP-100A)
HF306AQ100D3201
Rev. 6.00 Mar 18, 2005 page 536 of 970
REJ09B0215-0600
Manufacturer
MINATO
ELECTRONICS INC.
DATA I/O JAPAN CO.
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Figure 17.15 shows the memory map in PROM mode.
MCU mode
H'000000
H8/3062F-ZTAT
R-mask version
PROM mode
H'00000
On-chip ROM
H'01FFFF
H'1FFFF
Figure 17.15 Memory Map in PROM Mode
17.8.2
Notes on Use of PROM Mode
1. A write to a 128-byte programming unit in PROM mode should be performed once only.
Erasing must be carried out before reprogramming an address that has already been
programmed.
2. When using a PROM writer to reprogram a device on which on-board programming/erasing
has been performed, it is recommended that erasing be carried out before executing
programming.
3. The memory is initially in the erased state when the device is shipped by Renesas. For samples
for which the erasure history is unknown, it is recommended that erasing be executed to check
and correct the initialization (erase) level.
4. The H8/3062F-ZTAT R-mask version do not support a product identification mode as used
with general-purpose EPROMs, and therefore the device name cannot be set automatically in
the PROM writer.
5. Refer to the instruction manual provided with the socket adapter, or other relevant
documentation, for information on PROM writers and associated program versions that are
compatible with the PROM mode of the H8/3062F-ZTAT R-mask version.
Rev. 6.00 Mar 18, 2005 page 537 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.9
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
PROM mode are summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 128-kbyte on-chip flash
memory.
Do not select the HN28F101 setting for the PROM programmer. An incorrect setting will result in
application of a high level to the FWE pin, damaging the device.
2. Powering on and off (see figures 17.16 to 17.18)
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low
before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in
the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery. Failure to do so may result in overprogramming or overerasing
due to MCU runaway, and loss of normal memory cell operation.
3. FWE application/disconnection (see figures 17.16 to 17.18)
FWE application should be carried out when MCU operation is in a stable condition. If MCU
operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to prevent
unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
If FWE is applied when the MCU’s VCC power supply is not within its rated voltage range,
MCU operation will be unstable and flash memory may be erroneously programmed or erased.
• Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time).
When VCC power is turned on, hold the RES pin low for the duration of the oscillation settling
time (tOSC1 = 20 ms) before applying FWE. Do not apply FWE when oscillation has stopped or
is unstable.
Rev. 6.00 Mar 18, 2005 page 538 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
• In boot mode, apply and disconnect FWE during a reset.
In a transition to boot mode, FWE = 1 input and MD2 to MD0 setting should be performed
while the RES input is low. FWE and MD2 to MD0 pin input must satisfy the mode
programming setup time (tMDS) with respect to the reset release timing. When making a
transition from boot mode to another mode, also, a mode programming setup time is necessary
with respect to the reset release timing.
In a reset during operation, the RES pin must be held low for a minimum of 20 system clock
cycles.
• In user program mode, FWE can be switched between high and low level regardless of RES
input.
FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
During FWE application, the program execution state must be monitored using the watchdog
timer or some other means.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR are
cleared.
Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when
applying or disconnecting FWE.
4. Do not apply a constant high level to the FWE pin
To prevent erroneous programming or erasing due to program runaway, etc., apply a high level to
the FWE pin only when programming or erasing flash memory (including execution of flash
memory emulation using RAM). A system configuration in which a high level is constantly
applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the
watchdog timer should be activated to prevent overprogramming or overerasing due to program
runaway, etc.
5. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
PSU or ESU bit in FLMCR, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
Rev. 6.00 Mar 18, 2005 page 539 of 970
REJ09B0215-0600
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
6. Do not set or clear the SWE bit during execution of a program in flash memory.
Clear the SWE bit before executing a program or reading data in flash memory. When the SWE
bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for
verify operations (verification during programming/erasing).
Similarly, when using the RAM emulation function while a high level is being input to the FWE
pin, the SWE bit must be cleared before executing a program or reading data in flash memory.
However, the RAM area overlapping flash memory space can be read and written to regardless of
whether the SWE bit is set or cleared.
7. Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled during FWE application to give priority
to program/erase operations (including emulation in RAM).
Bus release must also be disabled.
8. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 32-byte programming
unit block. In PROM mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
• Use byte access on the registers that control the flash memory (FLMCR, EBR, FLMSR, and
RAMCR).
Rev. 6.00 Mar 18, 2005 page 540 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Wait time: Programming/
x erasing possible
φ
Min 0 µs
tOSC1
VCC
tMDS
FWE
Min 0 µs
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
See section 22.2.6, Flash Memory Characteristics.
Figure 17.16 Power-On/Off Timing (Boot Mode)
Rev. 6.00 Mar 18, 2005 page 541 of 970
REJ09B0215-0600
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
Wait time:
x
Programming/
erasing possible
φ
Min 0 µs
tOSC1
VCC
FWE
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
See section 22.2.6, Flash Memory Characteristics.
Figure 17.17 Power-On/Off Timing (User Program Mode)
Rev. 6.00 Mar 18, 2005 page 542 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
ProgramWait ming/
time: erasing
x possible
ProgramWait ming/
Wait
time: erasing time:
possible
x
x
Programming/
erasing
possible
ProgramWait ming/
time: erasing
x possible
φ
tOSC1
VCC
Min 0µs
FWE
*2
tMDS
tMDS
MD2 to MD0
tMDS
tRESW
RES
SWE
cleared
SWE set
SWE bit
Mode
change*1
Boot
mode
Mode
User
change*1 mode
User program mode
User
mode
User program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The state of ports with multiplexed address functions and bus control output pins
(CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),
and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the mode programming setup time tMDS must be
satisfied with respect to RES clearance timing.
3. See section 22.2.6, Flash Memory Characteristics.
Figure 17.18 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
Rev. 6.00 Mar 18, 2005 page 543 of 970
REJ09B0215-0600
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.10
Masked ROM (H8/3062 Masked ROM Version, H8/3061 Masked
ROM Version, H8/3060 Masked ROM Version) Overview
17.10.1 Block Diagram
Figure 17.19 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'00000
H'00001
H'00002
H'00003
On-chip ROM
H'1FFFE
H'1FFFF
Even addresses
Odd addresses
Figure 17.19 ROM Block Diagram (H8/3062 Masked ROM Version)
Rev. 6.00 Mar 18, 2005 page 544 of 970
REJ09B0215-0600
Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
17.11
Notes on Ordering Masked ROM Version Chips
When ordering H8/3062, H8/3061, and H8/3060 with masked ROM, note the following.
1. When ordering by means of an EPROM, use a 128-kbyte one.
2. Fill all unused addresses with H'FF as shown in figure 17.20 to make the ROM data size 128kbytes for the H8/3062, H8/3061, and H8/3060 masked ROM versions, which incorporate
different sizes of ROM. This applies to ordering by means of an EPROM and by means of data
transmission.
HD6433062
(ROM: 128 kbytes)
Addresses:
H'00000 to 1FFFF
HD6433060
(ROM: 64 kbytes)
Addresses:
H'00000 to 0FFFF
HD6433061
(ROM: 96 kbytes)
Addresses:
H'00000 to 17FFF
H'00000
H'00000
H'00000
H'0FFFF
H'10000
H'17FFF
H'18000
Not used*
Not used*
H'1FFFF
H'1FFFF
H'1FFFF
Note: * Write H'FF in all addresses in these areas.
Figure 17.20 Masked ROM Addresses and Data
3. The flash memory control registers (FLMCR, EBR, RAMCR, FLMSR, FLMCR1, FLMCR2,
EBR1, and EBR2) used by the versions with on-chip flash memory are not provided in the
masked ROM versions. Reading the corresponding addresses in a masked ROM version will
always return 1s, and writes to these addresses are disabled. This must be borne in mind when
switching from a flash memory version to a masked ROM version.
Rev. 6.00 Mar 18, 2005 page 545 of 970
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Section 17 ROM [H8/3062F-ZTAT R-Mask Version, On-Chip Masked ROM Models]
4. 5 V operation models of the H8/3064F-ZTAT B-mask version and H8/3062F-ZTAT B-mask
version with on-chip flash memory have a VCL pin that requires the connection of an external
capacitor. Care is therefore necessary regarding board design when switching to a masked
ROM version.
17.12
Notes when Converting the F-ZTAT Application Software to the
Masked ROM Versions
Please note the following when converting the F-ZTAT application software to the masked ROM
versions.
The values read from the internal registers for the flash ROM in the masked ROM version and
F-ZTAT version differ as follows.
Status
Register
Bit
Value
F-ZTAT Version
Masked ROM Version
FLMCR1
FWE
0
Application software running
—
(Is not read out)
1
Programming
Application software running
(This bit is always read as 1)
Note: This difference applies to all the F-ZTAT versions and all the masked ROM versions that
have different ROM size.
Rev. 6.00 Mar 18, 2005 page 546 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Section 18 H8/3064 Internal Voltage
Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.1
Overview
The H8/3064F-ZTAT B-mask version has 256 kbytes of on-chip flash memory. The H8/3064
masked ROM B-mask version has 256 kbytes of on-chip masked ROM. The flash memory is
connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two
states, enabling rapid data transfer.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) as shown in
table 18.1.
The on-chip flash memory product (H8/3064F-ZTAT B-mask version) can be erased and
programmed on-board, as well as with a special-purpose PROM programmer.
Table 18.1 Operating Modes and ROM
Mode Pins
Mode
MD2
MD1
MD0
On-Chip ROM
Mode 1
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
0
1
Disabled (external
address area)
Mode 2
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
1
0
Mode 3
(expanded 16-Mbyte mode with on-chip ROM disabled)
0
1
1
Mode 4
(expanded 16-Mbyte mode with on-chip ROM disabled)
1
0
0
Mode 5
(expanded 16-Mbyte mode with on-chip ROM enabled)
1
0
1
Mode 6
(single-chip normal mode)
1
1
0
Mode 7
(single-chip advanced mode)
1
1
1
Enabled
Rev. 6.00 Mar 18, 2005 page 547 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.1.1
Differences from H8/3062F-ZTAT R-Mask Version and H8/3064F-ZTAT B-Mask
Version
Table 18.2 Differences from H8/3062F-ZTAT R-Mask Version and H8/3064F-ZTAT
B-Mask Version
Item
Size
H8/3062F-ZTAT R-Mask Version
128 kbytes
H8/3064F-ZTAT B-Mask Version
256 kbytes
Operating frequency
1 to 20 MHz
2 to 25 MHz
Program/erase voltage
Supplied from VCC
Supplied from VCC
Programming Programming 32-byte simultaneous programming
unit
Erasing
128-byte simultaneous programming
Write pulse
application
method
150 µs × 4 + 500 µs × 399
30 µs × 6 + 200 µs × 994
1
(with 10 µs additional programming)*
Block
configuration
8 blocks
1 kbyte × 4, 28 kbytes × 1,
32 kbytes × 3
12 blocks
4 kbytes × 8, 32 kbytes × 1,
64 kbytes × 3
EBR
configuration
EBR: H'EE032
EBR1: H'EE032
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
3
2
EBR2: H'EE033
RAM
emulation
Flash error
5
4
—
—
EB11 EB10
1
0
EB9
EB8
1 kbyte (H'FF000 to H'FF3FF)
4 kbytes (H'FE000 to H'FEFFF)
Applicable
blocks
EB0 to EB3
EB0 to EB7
RAMCR
configuration
RAMCR: H'EE077
FLER bit
7
6
5
4
—
—
—
—
RAMCR: H'EE077
3
2
1
RAMS RAM2 RAM1
0
7
6
5
4
—
—
—
—
—
FLMSR: H'EE07D
3
2
1
0
RAMS RAM2 RAM1 RAM0
FLMCR2: H'EE031
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
FLER
—
—
—
—
—
—
—
2
tcswe specification must be met*
Bit rate
9,600 bps, 4,800 bps
19,200 bps, 9,600 bps, 4,800 bps
Boot area
H'FFEF20 to H'FFF3FF
H'FFDF20 to H'FFE71F
User area
H'FFF400 to H'FFFF1F
H'FFE720 to H'FFFF1F
PROM mode
Notes:
6
—
RAM area
Flash
Wait after
—
memory
SWE clearing
characteristics
Boot mode
7
—
Use of PROM writer supporting
Use of PROM writer supporting
Renesas microcomputer device type
Renesas microcomputer device type
with 128 kbytes on-chip flash memory
with 256 kbytes on-chip flash memory
1. See section 18.6, Flash Memory Programming/Erasing, for details of the H8/3064F-ZTAT B-mask
version program/erase algorithms.
2. See section 22.3.6, Flash Memory Characteristics, for details of the H8/3064F-ZTAT B-mask
version flash memory characteristics.
Rev. 6.00 Mar 18, 2005 page 548 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.2
Features
The H8/3064F-ZTAT B-mask version has 256 kbytes of on-chip flash memory.
The features of the flash memory are summarized below.
• Four flash memory operating modes
 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erasing is performed in block units. To
erase the entire flash memory, each block must be erased in turn. In block erasing, 4-kbyte, 32kbyte, and 64-kbyte blocks can be set arbitrarily.
• Programming/erase times
The flash memory programming time is 10 ms (typ) for simultaneous 128-byte programming,
equivalent approximately to 80 µs (typ) per byte, and the erase time is 100 ms (typ) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
For data transfer in boot mode, the H8/3064F-ZTAT B-mask version chip’s bit rate can be
automatically adjusted to match the transfer bit rate of the host.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are three protect modes—hardware, software, and error—which allow protected status
to be designated for flash memory program/erase/verify operations.
• PROM mode
Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as
well as in on-board programming mode.
Rev. 6.00 Mar 18, 2005 page 549 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.2.1
Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
EBR1
Bus interface/controller
Operating
mode
EBR2
RAMCR
Flash memory
(256 kbytes)
Legend:
FLMCR1
FLMCR2
EBR1
EBR2
RAMCR
:
:
:
:
:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM control register
Figure 18.1 Block Diagram of Flash Memory
Rev. 6.00 Mar 18, 2005 page 550 of 970
REJ09B0215-0600
FWE pin
Mode pins
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.2.2
Pin Configuration
The flash memory is controlled by means of the pins shown in table 18.3.
Table 18.3 Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Flash write enable
FWE
Input
Flash program/erase protection by hardware
Mode 2
MD2
Input
Sets H8/3064F-ZTAT B-mask version
operating mode
Mode 1
MD1
Input
Sets H8/3064F-ZTAT B-mask version
operating mode
Mode 0
MD0
Input
Sets H8/3064F-ZTAT B-mask version
operating mode
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
18.2.3
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 18.4.
Table 18.4 Flash Memory Registers
Register Name
Abbreviation
R/W
Initial Value
Address*1
Flash memory control register 1
FLMCR1
R/W
H'00*2
H'EE030
Flash memory control register 2
FLMCR2
R
H'00
H'EE031
Erase block register 1
EBR1
R/W
H'00
H'EE032
Erase block register 2
EBR2
R/W
H'00
H'EE033
RAM control register
RAMCR
R/W
H'F0
H'EE077
Notes: FLMCR1, FLMCR2, EBR1, EBR2, and RAMCR are 8-bit registers, and should be
accessed by byte access. These registers are used only in the versions with on-chip flash
memory, and are not provided in the versions with on-chip masked ROM. Reading the
corresponding addresses in a masked ROM version will always return 1s, and writes to
these addresses are invalid.
1. Lower 20 bits of address in advanced mode
2. When a high level is input to the FWE pin, the initial value is H'80.
Rev. 6.00 Mar 18, 2005 page 551 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.3
Register Descriptions
18.3.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
SWE
ESU
PSU
EV
PV
E
P
Initial value
FWE
—*
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control.
Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting
the SWE bit when FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000
to H'3FFFF is entered by setting the SWE bit when FWE = 1, then setting the PSU bit, and finally
setting the P bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting the SWE bit
when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a
reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a
high level is input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin
must be fixed low since flash memory on-board programming modes are not supported. When the
on-chip flash memory is disabled, a read access to this register will return H'00, and writes are
invalid.
When setting bits 6 to 0 in this register, one bit must be set one at a time. Writes to the SWE bit in
FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE
= 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to
the P bit only when FWE = 1, SWE = 1, and PSU = 1.
Notes: 1. The programming and erase flowcharts must be followed when setting the bits in this
register to prevent erroneous programming or erasing.
2. Transitions are made to program mode, erase mode, program-verify mode, and eraseverify mode according to the settings in this register. When reading flash memory as
normal on-chip ROM, bits 6 to 0 in this register must be cleared.
Rev. 6.00 Mar 18, 2005 page 552 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming and
erasing (This bit should be set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0).
Bit 6
SWE
Description
0
Programming/erasing disabled
1
Programming/erasing enabled
(Initial value)
[Setting condition]
When FWE = 1
Note: Do not execute a SLEEP instruction while the SWE bit is set to 1.
Bit 5—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1 (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time).
Bit 5
ESU
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
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REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Bit 4—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1 (Do not set the SWE, ESU, EV, PV, E, or P bit at the same
time).
Bit 4
PSU
Description
0
Program setup cleared
1
Program setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 3—Erase-Verify Mode (EV): Selects erase-verify mode transition or clearing (Do not set the
SWE, ESU, PSU, PV, E, or P bit at the same time).
Bit 3
EV
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 2—Program-Verify Mode (PV): Selects program-verify mode transition or clearing (Do not
set the SWE, ESU, PSU, EV, E, or P bit at the same time).
Bit 2
PV
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
Rev. 6.00 Mar 18, 2005 page 554 of 970
REJ09B0215-0600
(Initial value)
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Bit 1—Erase Mode (E): Selects erase mode transition or clearing (Do not set the SWE, ESU,
PSU, EV, PV, or P bit at the same time).
Bit 1
E
Description
0
Erase mode cleared
1
Transition to erase mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
Note: Do not access the flash memory while the E bit is set.
Bit 0—Program (P): Selects program mode transition or clearing (Do not set the SWE, ESU,
PSU, EV, PV, or E bit at the same time).
Bit 0
P
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Note: Do not access the flash memory while the P bit is set.
Rev. 6.00 Mar 18, 2005 page 555 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.3.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When
the on-chip flash memory is disabled, a read will return H'00.
Note: FLMCR2 is a read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
Bit 7
FLER
Description
0
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset (RES pin or WDT reset) or hardware standby mode
1
(Initial value)
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting conditions]
•
When flash memory is read during programming/erasing (including a vector read or
instruction fetch, but excluding a read of the RAM area overlapping flash memory
space)
•
Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
handling)
•
When a SLEEP instruction (including software standby) is executed during
programming/erasing
•
When the bus is released during programming/erasing
Bits 6 to 0—Reserved: These bits are always read as 0.
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REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.3.3
Erase Block Register 1 (EBR1)
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one bit can be set in EBR1 and EBR2 together; do not set two or
more bits at the same time. When the on-chip flash memory is disabled, a read access to this
register will return H'00, and erasing is disabled.
The flash memory block configuration is shown in table 18.5. To erase the entire flash memory,
each block must be erased in turn.
As the H8/3064F-ZTAT B-mask version does not support on-board programming modes in mode
6, EBR1 register bits cannot be set to 1 in this mode.
18.3.4
Erase Block Register 2 (EBR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
EB11
EB10
EB9
EB8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when a
low level is input to the FWE pin. When a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set, it is initialized to bit 0. When a bit in EBR2 is set to 1, the corresponding
block can be erased. Other blocks are erase-protected. Only one bit can be set in EBR1 and EBR2
together; do not set two or more bits at the same time. When the on-chip flash memory is disabled,
a read will return H'00, and erasing is disabled.
The flash memory block configuration is shown in table 18.5. To erase the entire flash memory,
each block must be erased in turn.
Rev. 6.00 Mar 18, 2005 page 557 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
As the H8/3064F-ZTAT B-mask version does not support on-board programming modes in mode
6, EBR2 register bits cannot be set to 1 in this mode.
Note: Bits 7 to 4 in this register are read-only. These bits must not be set to 1. If bits 7 to 4 are
set when an EBR1/EBR2 bit is set, EBR1/EBR2 will be initialized to H'00.
Table 18.5 Flash Memory Erase Blocks
Block (Size)
Addresses
EB0 (4 kbytes)
H'000000 to H'000FFF
EB1 (4 kbytes)
H'001000 to H'001FFF
EB2 (4 kbytes)
H'002000 to H'002FFF
EB3 (4 kbytes)
H'003000 to H'003FFF
EB4 (4 kbytes)
H'004000 to H'004FFF
EB5 (4 kbytes)
H'005000 to H'005FFF
EB6 (4 kbytes)
H'006000 to H'006FFF
EB7 (4 kbytes)
H'007000 to H'007FFF
EB8 (32 kbytes)
H'008000 to H'00FFFF
EB9 (64 kbytes)
H'010000 to H'01FFFF
EB10 (64 kbytes)
H'020000 to H'02FFFF
EB11 (64 kbytes)
H'030000 to H'03FFFF
18.3.5
RAM Control Register (RAMCR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
RAMS
RAM2
RAM1
RAM0
Initial value
1
1
1
1
0
0
0
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
RAMCR specifies the area of flash memory to be overlapped with part of RAM when emulating
realtime flash memory programming. RAMCR is initialized to H'00 by a reset and in hardware
standby mode. RAMCR settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 18.6. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Rev. 6.00 Mar 18, 2005 page 558 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Bit 3
RAMS
Description
0
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
1
(Initial value)
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together
with bit 3 to select the flash memory area to be overlapped with RAM (See table 18.6).
Table 18.6 Flash Memory Area Divisions
RAM Area
Block Name
RAMS
RAM2
RAM1
RAM0
H'FFE000 to H'FFEFFF
4-kbyte RAM area
0
*
*
*
H'000000 to H'000FFF
EB0 (4 kbytes)
1
0
0
0
H'001000 to H'001FFF
EB1 (4 kbytes)
1
0
0
1
H'002000 to H'002FFF
EB2 (4 kbytes)
1
0
1
0
H'003000 to H'003FFF
EB3 (4 kbytes)
1
0
1
1
H'004000 to H'004FFF
EB4 (4 kbytes)
1
1
0
0
H'005000 to H'005FFF
EB5 (4 kbytes)
1
1
0
1
H'006000 to H'006FFF
EB6 (4 kbytes)
1
1
1
0
H'007000 to H'007FFF
EB7 (4 kbytes)
1
1
1
1
*: Don’t care
Note: Flash memory emulation by RAM is not supported in mode 6 (single-chip normal mode);
therefore, although these bits can be written, they should not be set to 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to
1.
Rev. 6.00 Mar 18, 2005 page 559 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.4
Overview of Operation
18.4.1
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
H8/3064F-ZTAT B-mask version enters one of the operating modes shown in figure 18.2. In user
mode, flash memory can be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and PROM
mode.
Boot mode and user program mode cannot be used in the H8/3064F-ZTAT B-mask version’s
mode 6 (normal mode with on-chip ROM enabled).
Rev. 6.00 Mar 18, 2005 page 560 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Reset state
*3
*1
User mode
with on-chip ROM
enabled
RES = 0
RES = 0
*2
*4
RES = 0
FWE = 0
*5
RES = 0
*4
PROM mode
User program
mode
*1
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is not
accessing the flash memory.
1. RAM emulation possible
2. The H8/3064F-ZTAT is placed in PROM mode by means of a dedicated PROM writer.
3. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 0) (1, 1, 1)
FWE = 0
4. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 1)
FWE = 1
5. MD2, MD1, MD0 (0, 0, 1) (0, 1, 1)
FWE = 1
Figure 18.2 Flash Memory Related State Transitions
State transitions between the normal and user modes and on-board programming mode are
performed by changing the FWE pin level from high to low or from low to high. To prevent
misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory
control register (FLMCR1) should be cleared to 0 before making such a transition. After the bits
are cleared, a wait time is necessary. Normal operation is not guaranteed if this wait time is
insufficient.
Rev. 6.00 Mar 18, 2005 page 561 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.4.2
On-Board Programming Modes
Example of Boot Mode Operation
1. Initial state
The old program version or data remains
written in the flash memory. The user should
prepare the programming control program and
new application program beforehand in the
host.
Host
2. Programming control program transfer
When boot mode is entered, the boot program
in the H8/3064F-ZTAT B-mask version
(originally incorporated in the chip) is started
and the programming control program in the
host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically
transferred to the RAM boot program area.
Host
Programming control
program
New application
program
New application
program
H8/3064F-ZTAT B-mask version
H8/3064F-ZTAT B-mask version
SCI
Boot program
Flash memory
Flash memory
RAM
SCI
Boot program
RAM
Boot program area
Application
program
(old version)
Application
program
(old version)
3. Flash memory initialization
The erase program in the boot program area
(in RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard
Host
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into
the flash memory.
Host
New application
program
H8/3064F-ZTAT B-mask version
H8/3064F-ZTAT B-mask version
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
prewrite-erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Rev. 6.00 Mar 18, 2005 page 562 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Example of User Program Mode Operation
1. Initial state
The FWE assessment program that confirms
that user program mode has been entered, and
the program that will transfer the programming/
erase control program from flash memory to
on-chip RAM should be written into the flash
memory by the user beforehand. The
programming/erase control program should be
prepared in the host or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software recognizes this fact, executes the
transfer program in the flash memory, and
transfers the programming/erase control
program to RAM.
Host
Host
Programming/erase
control program
New application
program
New application
program
H8/3064F-ZTAT B-mask version
H8/3064F-ZTAT B-mask version
SCI
Boot program
Flash memory
Flash memory
RAM
SCI
Boot program
FWE assessment program
FWE assessment program
Transfer program
Transfer program
RAM
Programming/erase
control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks.
Do not write to unerased blocks.
Host
Host
New application
program
H8/3064F-ZTAT B-mask version
H8/3064F-ZTAT B-mask version
SCI
Boot program
Flash memory
RAM
Flash memory
FWE assessment program
FWE assessment program
Transfer program
Transfer program
Programming/erase
control program
Flash memory
erase
SCI
Boot program
RAM
Programming/erase
control program
New application
program
Program execution state
Rev. 6.00 Mar 18, 2005 page 563 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.4.3
Flash Memory Emulation in RAM
In the H8/3064F-ZTAT B-mask version, flash memory programming can be emulated in real time
by overlapping the flash memory with part of RAM (“overlap RAM”). When the emulation block
set in RAMCR is accessed while the emulation function is being executed, data written in the
overlap RAM is read.
Emulation should be performed in user mode or user program mode.
SCI
Flash memory
RAM
Emulation block
Overlap RAM
Application program
(Emulation is performed on data written
in RAM)
Execution state
Figure 18.3 Reading Overlap RAM Data in User Mode/User Program Mode
When overlap RAM data is confirmed, clear the RAMS bit to cancel RAM overlap, and actually
perform writes to the flash memory in user program mode.
When the programming control program is transferred to RAM in on-board programming mode,
ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in
the overlap RAM to be rewritten.
Rev. 6.00 Mar 18, 2005 page 564 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
SCI
RAM
Flash memory
Program data
Overlap RAM
(program data)
Application program
Programming control program
Execution state
Figure 18.4 Writing Overlap RAM Data in User Program Mode
18.4.4
Block Configuration
The flash memory in the H8/3064F-ZTAT B-mask version is divided into three 64-kbyte blocks,
one 32-kbyte block, and eight 4-kbyte blocks. Erasing can be carried out in block units.
Address H'00000
4 kbytes × 8
32 kbytes
64 kbytes
256 kbytes
64 kbytes
64 kbytes
Address H'3FFFF
Rev. 6.00 Mar 18, 2005 page 565 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.5
On-Board Programming Mode
When pins are set to on-board programming mode and a reset-start is executed, the chip enters the
on-board programming state in which on-chip flash memory programming, erasing, and verifying
can be carried out. There are two operating modes in this mode—boot mode and user program
mode. The pin settings for entering each mode are shown in table 18.7. For a diagram of the
transitions to the various flash memory modes, see figure 18.2.
Boot mode and user program mode cannot be used in the H8/3064F-ZTAT B-mask version’s
mode 6 (on-chip ROM enabled).
Table 18.7 On-Board Programming Mode Settings
Mode
FWE
MD2
MD1
MD0
Boot mode
1*1
0*2
0
1
User program mode
Mode 5
Mode 7
0*2
1
1
Mode 5
1
0
1
Mode 7
1
1
1
Notes: 1. For the High level input timing, see items 6 and 7 of “Notes on Using the Boot Mode” in
section 18.5.1.
2. In boot mode, the MD2 setting should be the inverse of the input.
In the boot mode in the H8/3064F-ZTAT B-mask version, the levels of the mode pins
(MD2 to MD0) are reflected in mode select bits 2 to 0 (MDS2 to MDS0) in the mode
control register (MDCR).
Rev. 6.00 Mar 18, 2005 page 566 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.5.1
Boot Mode
When boot mode is used, a flash memory programming control program must be prepared
beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode.
When a reset-start is executed after setting the H8/3064F-ZTAT B-mask version’s pins to boot
mode, the boot program already incorporated in the MCU is activated, and the programming
control program prepared beforehand in the host is transmitted sequentially to the H8/3064FZTAT B-mask version, using the SCI. In the H8/3064F-ZTAT B-mask version, the programming
control program received via the SCI is written into the programming control program area in onchip RAM. After the transfer is completed, control branches to the start address (H'FFE720) of the
programming control program area and the programming control program execution state is
entered (flash memory programming/erasing can be performed).
Figure 18.5 shows a system configuration diagram when using boot mode, and figure 18.6 shows
the boot program mode execution procedure.
H8/3064F-ZTAT B-mask version
Flash memory
Host
Reception of programming data
Transmission of verify data
RxD1
SCI1
TxD1
On-chip RAM
Figure 18.5 System Configuration When Using Boot Mode
Rev. 6.00 Mar 18, 2005 page 567 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Start
Set pins to boot program mode and execute reset-start
Host transfers data (H'00) continuously at prescribed bit rate
H8/3064F-ZTAT B-mask version measure low period of H'00 data
transmitted by host
H8/3064F-ZTAT B-mask version calculate bit rate and sets value
in bit rate register
After bit rate adjustment, H8/3064F-ZTAT B-mask version
transmit one H'00 data byte to host to indicate end of adjustment
Host confirms normal reception of bit rate adjustment end
indication (H'00), and transmits one H'55 data byte
After receiving H'55, H8/3064F-ZTAT B-mask version transmit
one H'AA byte to host
Host transmits number of programming control program bytes (N),
upper byte followed by lower byte
H8/3064F-ZTAT B-mask version transmit received number of
bytes to host as verify data (echo-back)
n=1
Host transmits programming control program sequentially in byte
units
H8/3064F-ZTAT B-mask version transmit received programming
control program to host as verify data (echo-back)
n+1→n
Transfer received programming control program to on-chip RAM
n = N?
No
Yes
End of transmission
Check flash memory data, and if data has already been written,
erase all blocks
After confirming that all flash memory data has been erased,
H8/3064F-ZTAT B-mask version transmit one H'AA byte to host
Execute programming control program transferred to on-chip
RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error
indication, and the erase operation and subsequent operations are halted.
Figure 18.6 Boot Mode Execution Procedure
Rev. 6.00 Mar 18, 2005 page 568 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Automatic SCI Bit Rate Adjustment:
Start
bit
D0
D1
D2
D3
D4
D5
D6
Low period (9 bits) measured (H'00 data)
D7
Stop
bit
High period
(1 or more bits)
When boot mode is initiated, the H8/3064F-ZTAT B-mask version measure the low period of the
asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI
transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The H8/3064F-ZTAT Bmask version calculate the bit rate of the transmission from the host from the measured low
period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host
should confirm that this adjustment end indication (H'00) has been received normally, and
transmit one H'55 byte to the H8/3064F-ZTAT B-mask version. If reception cannot be performed
normally, initiate boot mode again (reset), and repeat the above operations. Depending on the
host’s transmission bit rate and the H8/3064F-ZTAT B-mask version’s system clock frequency,
there will be a discrepancy between the bit rates of the host and the H8/3064F-ZTAT B-mask
version. To ensure correct SCI operation, the host’s transfer bit rate should be set to 4800, 9600, or
19,200 bps*.
Table 18.8 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the H8/3064F-ZTAT B-mask version bit rate is possible. The boot program should
be executed within this system clock range.
Table 18.8 System Clock Frequencies for which Automatic Adjustment of H8/3064F-ZTAT
B-mask version Bit Rate is Possible
Host Bit Rate
(bps)
System Clock Frequency for which Automatic Adjustment of
H8/3064F-ZTAT B-Mask Version Bit Rate is Possible (MHz)
19,200
16 to 25
9,600
8 to 25
4,800
4 to 25
Note: * Only use a setting of 4800, 9600, or 19200 bps for the host’s bit rate. No other settings can
be used.
Although the H8/3064F-ZTAT B-mask version may also perform automatic bit rate
adjustment with bit rate and system clock combinations other than those shown in table
Rev. 6.00 Mar 18, 2005 page 569 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.8, a degree of error will arise between the bit rates of the host and the H8/3064F-ZTAT
B-mask version, and subsequent transfer will not be performed normally. Therefore, only
a combination of bit rate and system clock frequency within one of the ranges shown in
table 18.8 can be used for boot mode execution.
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the user program is transferred via the SCI, as
shown in figure 18.7. The boot program area becomes available when a transition is made to the
execution state for the user program transferred to RAM.
H'FFDF20
Boot program
area
H'FFE71F
H'FFE720
User program
transfer area
H'FFFF1F
Note: The boot program area cannot be used until a transition is made to the execution state
for the user program transferred to RAM. Note also that the boot program remains in
this area in RAM even after control branches to the user program.
Figure 18.7 RAM Areas in Boot Mode
Notes on Use of Boot Mode:
1. When the H8/3064F-ZTAT B-mask version chip comes out of reset in boot mode, it measures
the low period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After
the reset ends, it takes about 100 states for the chip to get ready to measure the low period of
the RxD1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
Rev. 6.00 Mar 18, 2005 page 570 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RxD1 and TxD1 lines should be pulled up on the board.
5. Before branching to the user program the H8/3064F-ZTAT B-mask version terminates
transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits
to 0 in the serial control register (SCR)), but the adjusted bit rate value remains set in the bit
rate register (BRR). The transmit data output pin, TxD1, goes to the high-level output state
(P91DDR = 1 in P9DDR, P91DR = 1 in P9DR).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode
setting conditions shown in table 18.6, and then executing a reset-start.
a. When switching from boot mode to normal mode, the boot mode state within the chip must
first be cleared by reset input via the RES pin*1. The RES pin must be held low for at least
20 system clock cycles*3.
b. Do not change the input levels of the mode pins (MD2 to MD0) or the FWE pin in boot
mode. To change the mode, the RES pin must first be driven low to set the reset state. Also,
if a watchdog timer reset occurs in the boot mode state, the MCU’s internal state will not
be cleared, and the on-chip boot program will be restarted regardless of the mode pin
states.
c. The FWE pin must not be driven low while the boot program is running or flash memory is
being programmed or erased*2.
7. If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output signals (CSn, AS, RD,
LWR, HWR) may also change according to the change in the MCU’s operating mode.
Therefore, care must be taken to make pin settings to prevent these pins from being used
directly as output signal pins during a reset, or to prevent collision with signals outside the
MCU.
Rev. 6.00 Mar 18, 2005 page 571 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
H8/3064F-ZTAT
B-mask version
CSn
MD2
MD1
MD0
FWE
External
memory,
etc.
System
control
unit
RES
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS)
with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 18.11,
Flash Memory Programming and Erasing Precautions.
3. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming and
Erasing Precautions. The H8/3064F-ZTAT B-mask version requires a minimum of 20
system clock cycles for a reset during operation.
18.5.2
User Program Mode
When set to user program mode, the H8/3064F-ZTAT B-mask version can program and erase its
flash memory by executing a user program/erase control program. Therefore, on-board
reprogramming of the on-chip flash memory can be carried out by providing on-board means of
FWE control and supply of programming data, and storing a program/erase control program in
part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip ROM (mode 5 or 7), and
apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 5 and 7.
Flash memory programming/erasing should not be carried out in mode 6. When mode 6 is set, the
FWE pin must be driven low.
Rev. 6.00 Mar 18, 2005 page 572 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
The flash memory itself cannot be read while being programmed or erased, so the program that
performs programming should be placed in external memory or transferred to RAM and executed
there.
Figure 18.8 shows the execution procedure when user program mode is entered during program
execution in RAM. It is also possible to start from user program mode in a reset-start.
Write FWE assessment program and transfer
program (and programming/erase control
program if necessary) beforehand
MD2 to MD0 = 101 or 111
Reset-start
Transfer programming/erase control
program to RAM
Branch to programming/erase control
program in RAM area
FWE = High
(user program mode)
Execute programming/erase control
program in RAM
(flash memory rewriting)
Clear SWE bit, then release FWE
(user program mode clearing)
Branch to application program
in flash memory
Notes: 1. Do not apply a constant high level to the FWE pin. A high level should be applied to the
FWE pin only when programming or erasing flash memory (including execution of flash
memory emulation by RAM). Also, while a high level is applied to the FWE pin, the
watchdog timer should be activated to prevent overprogramming or overerasing due to
program runaway, etc.
2. For further information on FWE application and disconnection, see section 18.11, Flash
Memory Programming and Erasing Precautions.
3. In order to execute a normal read of flash memory in user program mode, the
programming/erase program must not be executing. It is thus necessary to ensure that
bits 6 to 0 in FLMCR1 are cleared to 0.
Figure 18.8 Example of User Program Mode Execution Procedure
Rev. 6.00 Mar 18, 2005 page 573 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.6
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses
H'000000 to H'03FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(user program) that controls flash memory programming/erasing should be located and executed in
on-chip RAM or external memory.
See section 18.11, Flash Memory Programming and Erasing Precautions, for points to be noted
when programming or erasing the flash memory. In the following operation descriptions, wait
times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of
the wait times, see section 22.3.6, Flash Memory Characteristics.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR1 is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming must be executed in the erased state. Do not perform additional
programming on addresses that have already been programmed.
Rev. 6.00 Mar 18, 2005 page 574 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
*3
E=1
Erase setup
state
Erase mode
E=0
Normal mode
FWE = 1
ESU = 1
ESU = 0
*1
FWE = 0
EV = 1
*2
On-board
SWE = 1
Software
programming mode
programming
Software programming
enable
disable state
SWE = 0
state
Erase-verify
mode
EV = 0
PSU = 1
*4
P=1
PSU = 0
Program
setup state
Program mode
P=0
PV = 1
PV = 0
Program-verify
mode
Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads
can be performed during the programming/erasing process.
1.
: Normal mode
: On-board programming mode
2. Do not make a state transition by setting or clearing multiple bits simultaneously.
3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing
through the software programming enable state.
4. After a transition from program mode to the program setup state, do not enter program mode without
passing through the software programming enable state.
Figure 18.9 FLMCR1 Bit Settings and State Transitions
Rev. 6.00 Mar 18, 2005 page 575 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.6.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 18.10 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes
at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 22.30 in section 22.3.6,
Flash Memory Characteristics.
Following the elapse of (tsswe) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data
is written consecutively to the write addresses. The lower 8 bits of the first address written to must
be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation for
entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.
The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the
elapse of at least (tspsu) µs. The time during which the P bit is set is the flash memory
programming time. Make a program setting so that the time for one programming operation is
within the range of (tsp) µs.
The wait time after P bit setting must be changed according to the degree of progress through the
programming operation. For details see “Notes on Program/Program-Verify Procedure” in section
18.6.2.
18.6.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least
(tcp) µs before clearing the PSU bit to exit program mode. After exiting program mode, the
watchdog timer setting is also cleared. The operating mode is then switched to program-verify
mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of (tspv) µs or more. When the flash memory is read in this state (verify data is read
Rev. 6.00 Mar 18, 2005 page 576 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
in 16-bit units), the data at the latched address is read. Wait at least (tspvr) µs after the dummy write
before performing this read operation. Next, the originally written data is compared with the verify
data, and reprogram data is computed (see figure 18.10) and transferred to RAM. After
verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least
(tcpv) µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode
again, and repeat the program/program-verify sequence as before. The maximum number of
repetitions of the program/program-verify sequence is indicated by the maximum programming
count (N). Leave a wait time of at least (tcswe) µs after clearing SWE.
Notes on Program/Program-Verify Procedure
1. The program/program-verify procedure for the H8/3064F-ZTAT B-mask version uses a 128byte-unit programming algorithm.
Note that this is different from the procedure in the H8/3062F-ZTAT R-mask version (32-byteunit programming).
In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must
be H'00 or H'80.
2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer
should be used.
128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write
H'FF data to the extra addresses.
3. Verify data is read in word units.
4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is
set. In the H8/3064F-ZTAT B-mask version, write pulses should be applied as follows in the
program/program-verify procedure to prevent voltage stress on the device and loss of write
data reliability.
a. After write pulse application, perform a verify-read in program-verify mode and apply a
write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write
bits in the 128-byte write data are read as 0 in the verify-read operation, the
program/program-verify procedure is completed. In the H8/3064F-ZTAT B-mask version,
the number of loops in reprogramming processing is guaranteed not to exceed the
maximum value of the maximum programming count (N).
b. After write pulse application, a verify-read is performed in program-verify mode, and
programming is judged to have been completed for bits read as 0. The following processing
is necessary for programmed bits.
When programming is completed at an early stage in the program/program-verify
procedure:
Rev. 6.00 Mar 18, 2005 page 577 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
If programming is completed in the 1st to 6th reprogramming processing loop, additional
programming should be performed on the relevant bits. Additional programming should
only be performed on bits which first return 0 in a verify-read in certain reprogramming
processing.
When programming is completed at a late stage in the program/program-verify procedure:
If programming is completed in the 7th or later reprogramming processing loop, additional
programming is not necessary for the relevant bits.
c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing
should be executed. If a bit for which programming has been judged to be completed is
read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.
5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed
according to the degree of progress through the program/program-verify procedure. For
detailed wait time specifications, see section 22.3.6, Flash Memory Characteristics.
Item
Symbol
Item
Symbol
Wait time after
P bit setting
tsp
When reprogramming loop count (n) is 1 to 6
tsp30
When reprogramming loop count (n) is 7 or more
In case of additional programming processing*
tsp200
tsp10
Note: * Additional programming processing is necessary only when the reprogramming loop count
(n) is 1 to 6.
6. The program/program-verify flowchart for the H8/3064F-ZTAT B-mask version is shown in
figure 18.10.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown
below.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
Rev. 6.00 Mar 18, 2005 page 578 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Reprogram Data Computation Table
(D)
Result of Verify-Read
after Write Pulse
(X)
Application (V)
Result of Operation
0
0
1
Programming completed: reprogramming
processing not to be executed
0
1
0
Programming incomplete: reprogramming
processing to be executed
1
0
1

1
1
1
Still in erased state: no action
Comments
Legend:
(D): Source data of bits on which programming is executed
(X): Source data of bits on which reprogramming is executed
Additional-Programming Data Computation Table
(X')
Result of Verify-Read
after Write Pulse
(Y)
Application (V)
Result of Operation
0
0
0
Programming by write pulse application
judged to be completed: additional
programming processing to be executed
0
1
1
Programming by write pulse application
incomplete: additional programming
processing not to be executed
1
0
1
Programming already completed:
additional programming processing not to
be executed
1
1
1
Still in erased state: no action
Comments
Legend:
(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop
(Y): Data of bits on which additional programming is executed
7. It is necessary to execute additional programming processing during the course of the
H8/3064F-ZTAT B-mask version program/program-verify procedure. However, once 128byte-unit programming is finished, additional programming should not be carried out on the
same address area. When executing reprogramming, an erase must be executed first. Note that
normal operation of reads, etc., is not guaranteed if additional programming is performed on
addresses for which a program/program-verify operation has finished.
Rev. 6.00 Mar 18, 2005 page 579 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Start of programming
Write pulse application subroutine
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
START
Sub-Routine Write Pulse
Set SWE bit in FLMCR1
WDT enable
Wait (tsswe) µs
Set PSU bit in FLMCR1
Wait (tspsu) µs
*7
*4
n= 1
Start of programming
Set P bit in FLMCR1
*7
Store 128-byte program data in program
data area and reprogram data area
m= 0
Wait (tsp) µs
*5*7
Consecutively write 128-byte data in reprogram
data area in RAM to flash memory
Programming halted
Clear P bit in FLMCR1
*1
Sub-Routine-Call
Wait (tcp) µs
*7
See Note *6 for pulse width
Write pulse
Set PV bit in FLMCR1
Clear PSU bit in FLMCR1
Wait (tcpsu) µs
Wait (tspv) µs
*7
*7
H'FF dummy write to verify address
Disable WDT
Wait (tspvr) µs
End Sub
n←n+1
*7
Read verify data
*2
Write data =
verify data?
NG
Increment address
Note *6: Write Pulse Width
Number of Writes (n)
Write Time (tsp) µs
1
2
3
4
5
6
7
8
9
10
11
12
13
30
30
30
30
30
30
200
200
200
200
200
200
200
998
999
1000
200
200
200
m=1
OK
NG
6≥n?
OK
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
*4
*3
Transfer reprogram data to reprogram data area
NG
*4
128-byte
data verification completed?
OK
Clear PV bit in FLMCR1
Reprogram
Wait (tcpv) µs
Note: Use a 10 µs write pulse for additional programming.
*7
NG
6 ≥ n?
OK
Consecutively write 128-byte data in additionalprogramming data area in RAM to flash memory
RAM
Program data storage
area (128 bytes)
*1
Sub-Routine-Call
Write Pulse (Additional programming)
Reprogram data storage
area (128 bytes)
*7
NG
m= 0 ?
n ≥ N?
NG
OK
Clear SWE bit in FLMCR1
OK
Clear SWE bit in FLMCR1
Additional-programming
data storage area
(128 bytes)
Wait (tcswe) µs
Wait (tcswe) µs
End of programming
Programming failure
*7
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are
programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in RAM. The contents of the reprogram data
area and additional-programming data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 µs
write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 22.3.6, Flash Memory.
Reprogram Data Computation Table
Additional-Programming Data Computation Table
Original Data
Verify Data
Reprogram Data
(D)
0
0
(V)
0
1
(X)
1
0
1
1
0
1
1
1
Comments
Programming completed
Reprogram Data
(X')
Verify Data
Additional(V)
Programming Data (Y)
Programming incomplete; reprogram
0
0
1
0
1
0
0
1
1
Still in erased state; no action
1
1
1
Comments
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming)
Rev. 6.00 Mar 18, 2005 page 580 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.6.3
Erase Mode
When erasing flash memory, the single-block erase flowchart shown in figure 18.11 should be
followed.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in table 22.30 in section 22.3.6, Flash
Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (tsswe) µs after setting the SWE bit to 1 in
FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program
runaway, etc. Set a value greater than (tse) ms + (tsesu + tce + tcesu) µs as the WDT overflow period.
Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in
FLMCR1. The operating mode is then switched to erase mode by setting the E bit in FLMCR1
after the elapse of at least (tsesu) µs. The time during which the E bit is set is the flash memory
erase time. Ensure that the erase time does not exceed (tse) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
18.6.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the
EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) µs
or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (tsevr) µs after the dummy write before performing this
read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is
completed, exit erase-verify mode, and wait for at least (tcev) µs. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) µs.
Rev. 6.00 Mar 18, 2005 page 581 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and
repeat the erase/erase-verify sequence as before.
Start
*1
Perform erasing in block units.
Set SWE bit in FLMCR1
Wait (tsswe) µs
*5
n=1
Set EBR1 or EBR2
*3, *4
Enable WDT
Set ESU bit in FLMCR1
Wait (tsesu) µs
*5
Start of erase
Set E bit in FLMCR1
Wait (tse) ms
*5
Clear E bit in FLMCR1
End of erase
Wait (tce) µs
*5
Clear ESU bit in FLMCR1
Wait (tcesu) µs
*5
Disable WDT
Set EV bit in FLMCR1
Wait (tsev) µs
n←n+1
*5
Set block start address as verify address
H'FF dummy write to verify address
Wait (tsevr) µs
*5
*2
Read verify data
Increment
address
Verify data = all 1s?
No
Yes
No
Last address of block?
Re-erase
Yes
Clear EV bit in FLMCR1
Wait (tcev) µs
Clear EV bit in FLMCR1
*5
Wait (tcev) µs
*5
*5
n ≥ N?
Yes
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
Wait (tcswe) µs
End of erasing
Notes: 1.
2.
3.
4.
5.
No
*5
Wait (tcswe) µs
*5
Erase failure
Prewriting (setting erase block data to all 0s) is not necessary.
Verify data is read in 16-bit (word) units.
Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
The wait times and the value of N are shown in section 22.3.6, Flash Memory Characteristics.
Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Rev. 6.00 Mar 18, 2005 page 582 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.7
Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error
protection.
18.7.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and
erase block registers 1 and 2 (EBR1, EBR2) are reset. In the error protection state, the FLMCR1,
EBR1, and EBR2 settings are retained; the P bit and E bit can be set, but a transition is not made
to program mode or erase mode (See table 18.9).
Table 18.9 Hardware Protection
Function
Item
Description
Program
Erase
Verify
FWE pin
protection
•
When a low level is input to the FWE pin,
FLMCR1, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
Not
possible*1
Not
possible*3
Not
possible
Reset/
standby
protection
•
In a reset (including a WDT overflow reset)
and in standby mode, FLMCR1, FLMCR2,
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
Not
possible
Not
possible*3
Not
possible
•
In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on.
In the case of a reset during operation, hold
the RES pin low for the RES pulse width
specified in the AC Characteristics section*4.
•
When a microcomputer operation error
(error generation (FLER = 1)) was
detected while flash memory was being
programmed/erased, error protection is
enabled. At this time, the FLMCR1, EBR1,
and EBR2 settings are held, but
programming/erasing is aborted at the
time the error was generated. Error
protection is released only by a reset via
the RES pin or a WDT reset, or in the
hardware standby mode.
Not
possible
Not
possible*3
Possible*2
Error
protection
Rev. 6.00 Mar 18, 2005 page 583 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Notes: 1. The RAM area that overlapped flash memory is deleted.
2. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify operation on the block being erased.
3. All blocks are unerasable and block-by-block specification is not possible.
4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming
and Erasing Precautions. The H8/3064F-ZTAT B-mask version requires a minimum of
20 system clock cycles for a reset during operation.
18.7.2
Software Protection
Software protection can be implemented by setting the erase block register 1 (EBR1), erase block
register 2 (EBR2), and the RAMS bit in the RAM control register (RAMCR). With software
protection, setting the P or E bit in the flash memory control register 1 (FLMCR1) does not cause
a transition to program mode or erase mode (See table 18.10).
Table 18.10 Software Protection
Functions
Item
Description
Program
Erase
Verify
Block
protection
•
Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2
2
(EBR2)* . However, programming
protection is disabled.
—
Not
possible
Possible
•
Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
•
Setting the RAMS bit 1 in RAMCR places
all blocks in the program/erase-protected
state.
Not
possible*1
Possible
Not
possible*3
Emulation
protection
Notes: 1. The RAM area overlapping flash memory can be written to.
2. When not erasing, set EBR1 and EBR2 to H'00.
3. All blocks are unerasable and block-by-block specification is not possible.
Rev. 6.00 Mar 18, 2005 page 584 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.7.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing*1, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1,
FLMCR2, EBR1, and EBR2 settings*3 are retained, but program mode or erase mode is aborted at
the point at which the error occurred. Program mode or erase mode cannot be re-entered by resetting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can
be made to verify mode*2.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after the start of exception handling during programming/erasing (excluding
reset, illegal instruction, trap instruction, and division-by-zero exception handling)
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a RES pin or WDT reset, or in hardware standby mode.
Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
in this state.
2. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify on the block being erased.
3. FLMCR1, EBR1, and EBR2 can be written to. However, the registers are initialized if
a transition is made to software standby mode while in the error protection state.
Figure 18.12 shows the flash memory state transition diagram.
Rev. 6.00 Mar 18, 2005 page 585 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Program mode
Erase mode
Reset or standby
(hardware protection)
RES = 0 or STBY = 0
RD VF PR ER INIT FLER = 0
RD VF PR ER FLER = 0
Error occurrence
(software standby)
RES = 0 or
STBY = 0
Error
occurrence
RES = 0 or
STBY = 0
Software
standby mode
Error protection mode
RD VF PR ER FLER = 1
Software standby
mode release
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
(software standby)
RD VF PR ER INIT FLER = 1
FLMCR1, EBR1, EBR2
initialization state
RD
VF
PR
ER
:
:
:
:
Memory read possible
Verify-read possible
Programming possible
Erasing possible
RD
VF
PR
ER
INIT
:
:
:
:
:
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Register initialization state
Figure 18.12 Flash Memory State Transitions
(When High Level is Applied to FWE Pin in Mode 5 or 7 (On-Chip ROM Enabled))
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.
To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in
accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,
and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog
timer or other means. There may also be cases where the flash memory is in an erroneous
programming or erroneous erasing state at the point of transition to this protection mode, or where
programming or erasing is not properly carried out because of an abort. In cases such as these, a
forced recovery (program rewrite) must be executed using boot mode. However, it may also
happen that boot mode cannot be normally initiated because of overprogramming or overerasing.
Rev. 6.00 Mar 18, 2005 page 586 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.8
Flash Memory Emulation in RAM
Making a setting in the RAM control register (RAMCR) enables part of RAM to be overlapped
onto the flash memory area so that data to be written to flash memory can be emulated in RAM in
real time. After the RAMCR setting has been made, accesses can be made from the flash memory
area or the RAM area overlapping flash memory. Emulation can be performed in user mode and
user program mode. Figure 18.13 shows an example of emulation of realtime flash memory
programming.
Start of emulation program
Set RAMCR
Write tuning data to overlap RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMCR
Write to flash memory emulation block
End of emulation program
Figure 18.13 Flowchart of Flash Memory Emulation in RAM
Rev. 6.00 Mar 18, 2005 page 587 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
This area can be accessed
from both the RAM area
and flash memory area
H'00000
EB0
H'01000
EB1
H'02000
EB2
H'03000
EB3
H'04000
EB4
H'05000
EB5
H'06000
EB6
H'07000
EB7
H'08000
H'FFE000
H'FFEFFF
Flash memory
EB8 to EB11
On-chip RAM
H'FFFF1F
H'3FFFF
Figure 18.14 Example of RAM Overlap Operation
Rev. 6.00 Mar 18, 2005 page 588 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Example of Flash Memory Block Area EB0 Overlapping
1. Set bits RAMS and RAM2 to RAM0 in RAMCR to 1,0, 0, 0, to overlap part of RAM onto the
area (EB0) for which realtime programming is required.
2. Realtime programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting
the P or E bit in FLMCR1 will not cause a transition to program mode or erase mode.
When actually programming or erasing a flash memory area, the RAMS bit should be
cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
3. Block area EB0 contains the vector table. When performing RAM emulation, the
vector table is needed in the overlap RAM.
4. As in on-board programming mode, care is required when applying and releasing FWE
to prevent erroneous programming or erasing. To prevent erroneous programming and
erasing due to program runaway during FWE application, in particular, the watchdog
timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while
the emulation function is being used.
5. When the emulation function is used, NMI input is prohibited when the P bit or E bit is
set to 1 in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby
mode, when a high level is not being input to the FWE pin, or when the SWE bit in
FLMCR1 is 0 while a high level is being input to the FWE pin.
Rev. 6.00 Mar 18, 2005 page 589 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.9
NMI Input Disabling Conditions
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode*1, to give priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly*2, possibly resulting in MCU runaway.
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests (exception handling and bus
release), including NMI, must therefore be restricted inside and outside the MCU during FWE
application. NMI input is also disabled in the error protection state and while the P or E bit
remains set in FLMCR1 during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
(This branch takes place immediately after transfer of the user program is completed).
Consequently, after the branch to the RAM area, NMI input is enabled except during
programming and erasing. Interrupt requests must therefore be disabled inside and
outside the MCU until the user program has completed initial programming (including
the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P bit or E bit
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the entry in the interrupt vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 6.00 Mar 18, 2005 page 590 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.10
Flash Memory PROM Mode
The H8/3064F-ZTAT B-mask version have a PROM mode as well as the on-board programming
modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be
freely programmed using a general-purpose PROM writer that supports the Renesas
microcomputer device type with 256-kbyte on-chip flash memory.
18.10.1 Socket Adapters and Memory Map
In PROM mode using a PROM writer, memory reading (verification) and writing and flash
memory initialization (total erasure) can be performed. For these operations, a special socket
adapter is mounted in the PROM writer. The socket adapter product codes are given in table
18.11. In the H8/3064F-ZTAT B-mask version PROM mode, only the socket adapters shown in
this table should be used.
Table 18.11 H8/3064F-ZTAT B-Mask Version Socket Adapter Product Codes
Product Code
Package
Socket Adapter
Product Code
HD64F3064BF
100-pin QFP (FP-100B)
ME3064ESHF1H
HD64F3064BTE
100-pin TQFP (TFP-100B)
ME3064ESNF1H
HD64F3064BFP
100-pin QFP (FP-100A)
ME3064ESFF1H
HD64F3064BF
100-pin QFP (FP-100B)
HF306BQ100D4001
HD64F3064BTE
100-pin TQFP (TFP-100B)
HF306BT100D4001
HD64F3064BFP
100-pin QFP (FP-100A)
HF306AQ100D4001
Manufacturer
MINATO
ELECTRONICS INC.
DATA I/O JAPAN CO.
Figure 18.15 shows the memory map in PROM mode.
MCU mode
H'000000
H8/3064F-ZTAT
B-mask version
PROM mode
H'00000
On-chip ROM
H'03FFFF
H'3FFFF
Figure 18.15 Memory Map in PROM Mode
Rev. 6.00 Mar 18, 2005 page 591 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.10.2 Notes on Use of PROM Mode
1. A write to a 128-byte programming unit in PROM mode should be performed once only.
Erasing must be carried out before reprogramming an address that has already been
programmed.
2. When using a PROM writer to reprogram a device on which on-board programming/erasing
has been performed, it is recommended that erasing be carried out before executing
programming.
3. The memory is initially in the erased state when the device is shipped by Renesas. For samples
for which the erasure history is unknown, it is recommended that erasing be executed to check
and correct the initialization (erase) level.
4. The H8/3064F-ZTAT B-mask version does not support a product identification mode as used
with general-purpose EPROMs, and therefore the device name cannot be set automatically in
the PROM writer.
5. Refer to the instruction manual provided with the socket adapter, or other relevant
documentation, for information on PROM writers and associated program versions that are
compatible with the PROM mode of the H8/3064F-ZTAT B-mask version.
18.11
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
PROM mode are summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip
flash memory.
2. Powering on and off (See figures 18.16 to 18.18)
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin
low before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory
in the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a
power failure and subsequent recovery. Failure to do so may result in overprogramming or
overerasing due to MCU runaway, and loss of normal memory cell operation.
Rev. 6.00 Mar 18, 2005 page 592 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
3. FWE application/disconnection
FWE application should be carried out when MCU operation is in a stable condition. If MCU
operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to
prevent unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
If FWE is applied when the MCU’s VCC power supply is not within its rated voltage range,
MCU operation will be unstable and flash memory may be erroneously programmed or
erased.
• Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling
time).
When VCC power is turned on, hold the RES pin low for the duration of the oscillation
settling time before applying FWE. Do not apply FWE when oscillation has stopped or is
unstable.
• In boot mode, apply and disconnect FWE during a reset.
In a transition to boot mode, FWE = 1 input and MD2 to MD0 setting should be performed
while the RES input is low. FWE and MD2 to MD0 pin input must satisfy the mode
programming setup time (tMDS) with respect to the reset release timing. When making a
transition from boot mode to another mode, also, a mode programming setup time is
necessary with respect to the reset release timing.
In a reset during operation, the RES pin must be held low for a minimum of 20 system
clock cycles.
• In user program mode, FWE can be switched between high and low level regardless of
RES input.
FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
During FWE application, the program execution state must be monitored using the
watchdog timer or some other means.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 are
cleared.
Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when
applying or disconnecting FWE.
4. Do not apply a constant high level to the FWE pin.
T prevent erroneous programming or erasing due to program runaway, etc., apply a high level
to the FWE pin only when programming or erasing flash memory (including execution of flash
memory emulation using RAM). A system configuration in which a high level is constantly
Rev. 6.00 Mar 18, 2005 page 593 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin,
the watchdog timer should be activated to prevent overprogramming or overerasing due to
program runaway, etc.
5. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
PSU or ESU bit in FLMCR1, the watchdog timer should be set beforehand as a precaution
against program runaway, etc.
Also note that access to the flash memory space by means of a MOV instruction, etc., is not
permitted while the P bit or E bit is set.
6. Do not set or clear the SWE bit during execution of a program in flash memory.
Clear the SWE bit before executing a program or reading data in flash memory. When the
SWE bit is set, data in flash memory can be rewritten, but flash memory should only be
accessed for verify operations (verification during programming/erasing).
Similarly, when using the RAM emulation function while a high level is being input to the
FWE pin, the SWE bit must be cleared before executing a program or reading data in flash
memory. However, the RAM area overlapping flash memory space can be read and written to
regardless of whether the SWE bit is set or cleared.
A wait time is necessary after the SWE bit is cleared. For details see table 22.30 in section
22.3.6, Flash Memory Characteristics.
7. Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled during FWE application to give
priority to program/erase operations (including emulation in RAM).
Bus release must also be disabled.
8. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
9. Before programming, check that the chip is correctly mounted in the PROM writer.
Overcurrent damage to the device can result if the index marks on the PROM writer socket,
socket adapter, and chip are not correctly aligned.
10. Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
Rev. 6.00 Mar 18, 2005 page 594 of 970
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
11. A wait time of 100 µs or more is necessary when performing a read after a transition to
normal mode from program, erase, or verify mode.
12. Use byte access on the registers that control the flash memory (FLMCR1, FLMCR2,
EBR1, EBR2, and RAMCR).
Wait time:
x
Programming/
erasing
possible
Wait time:
y
φ
Min 0 µs
tOSC1
VCC
tMDS
FWE
Min 0 µs
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
See section 22.3.6, Flash Memory Characteristics.
Figure 18.16 Power-On/Off Timing (Boot Mode)
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REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
Wait time:
x
Programming/
erasing
possible
Wait time:
y
φ
Min 0 µs
tOSC1
VCC
FWE
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
See section 22.3.6, Flash Memory Characteristics.
Figure 18.17 Power-On/Off Timing (User Program Mode)
Rev. 6.00 Mar 18, 2005 page 596 of 970
REJ09B0215-0600
Programming/
erasing possible
Wait time: x
Wait time: x
Programming/
erasing possible
Wait time: y
Wait time: x
Programming/
erasing possible
Wait time: y
Wait time: y
Wait time: x
Programming/
erasing possible
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
φ
tOSC1
VCC
Min 0µs
FWE
*2
tMDS
tMDS
MD2 to MD0
tMDS
tRESW
RES
SWE
cleared
SWE set
SWE bit
Mode
change*1
Boot
mode
Mode
User
change*1 mode
User program mode
User
mode
User program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The state of ports with multiplexed address functions and bus control output pins
(CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),
and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the mode programming setup time tMDS must be
satisfied with respect to RES clearance timing.
3. See section 22.3.6, Flash Memory Characteristics.
Figure 18.18 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
Rev. 6.00 Mar 18, 2005 page 597 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.12
Masked ROM (H8/3064 Masked ROM B-Mask Version) Overview
18.12.1 Block Diagram
Figure 18.19 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'00000
H'00001
H'00002
H'00003
On-chip ROM
H'3FFFE
H'3FFFF
Even addresses
Odd addresses
Figure 18.19 ROM Block Diagram (H8/3064 Masked ROM B-Mask Version)
Rev. 6.00 Mar 18, 2005 page 598 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.13
Notes on Ordering Masked ROM Version Chips
When ordering H8/3064 with masked ROM, note the following.
1. When ordering by means of an EPROM, use a 512-kbyte one.
2. Fill all unused addresses with H'FF as shown in figure 18.20 to make the ROM data size 512kbytes for the H8/3064 masked ROM version. This applies to ordering by means of an
EPROM and by means of data transmission.
HD6433064B
(ROM: 256 kbytes)
Addresses:
H'00000–7FFFF
H'00000
H'3FFFF
H'40000
Not used*
H'7FFFF
Note: * Write H'FF in all addresses in this.
Figure 18.20 Masked ROM Addresses and Data
3. The flash memory control registers (FLMCR, EBR, RAMCR, FLMSR, FLMCR1, FLMCR2,
EBR1, and EBR2) used by the versions with on-chip flash memory are not provided in the
masked ROM version. Reading the corresponding addresses in a masked ROM version will
always return 1s, and writes to these addresses are disabled. This must be borne in mind when
switching from a flash memory version to a masked ROM version.
Rev. 6.00 Mar 18, 2005 page 599 of 970
REJ09B0215-0600
Section 18 H8/3064 Internal Voltage Step-Down Version ROM
[H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version]
18.14
Notes when Converting the F-ZTAT Application Software to the
Masked ROM Version
Please note the following when converting the F-ZTAT application software to the masked ROM
version.
The values read from the internal registers for the flash ROM in the masked ROM version and
F-ZTAT version differ as follows.
Status
Register
Bit
Value
F-ZTAT Version
Masked ROM Version
FLMCR1
FWE
0
Application software running
—
(Is not read out)
1
Programming
Application software running
(This bit is always read as 1)
Note: This difference applies to all the F-ZTAT versions and all the masked ROM versions that
have different ROM size.
Rev. 6.00 Mar 18, 2005 page 600 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Section 19 H8/3062 Internal Voltage
Step-Down Version ROM
[H8/3062F-ZTAT B-Mask Version, Masked ROM B-Mask Versions
of H8/3062, H8/3061, and H8/3060]
19.1
Overview
The H8/3062F-ZTAT B-mask version has 128 kbytes of on-chip flash memory. The masked ROM
B-mask versions of H8/3062, H8/3061, H8/3060 have 128 kbytes, 96 kbytes, 64 kbytes of on-chip
masked ROM, respectively. The flash memory is connected to the CPU by a 16-bit data bus. The
CPU accesses both byte data and word data in two states, enabling rapid data transfer.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) as shown in
table 19.1.
The on-chip flash memory product (H8/3062F-ZTAT B-mask version) can be erased and
programmed on-board, as well as with a special-purpose PROM programmer.
Table 19.1 Operating Modes and ROM
Mode Pins
Mode
MD2
MD1
MD0
On-Chip ROM
Mode 1
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
0
1
Disabled (external
address area)
Mode 2
(expanded 1-Mbyte mode with on-chip ROM disabled)
0
1
0
Mode 3
(expanded 16-Mbyte mode with on-chip ROM disabled)
0
1
1
Mode 4
(expanded 16-Mbyte mode with on-chip ROM disabled)
1
0
0
Mode 5
(expanded 16-Mbyte mode with on-chip ROM enabled)
1
0
1
Mode 6
(single-chip normal mode)
1
1
0
Mode 7
(single-chip advanced mode)
1
1
1
Enabled
Rev. 6.00 Mar 18, 2005 page 601 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.1.1
Differences from H8/3062F-ZTAT R-Mask Version and H8/3062F-ZTAT B-Mask
Version
Table 19.2 Differences from H8/3062F-ZTAT R-Mask Version and H8/3062F-ZTAT
B-Mask Version
Item
Size
H8/3062F-ZTAT R-Mask Version
128 kbytes
H8/3062F-ZTAT B-Mask Version
128 kbytes
Operating frequency
1 to 20 MHz
2 to 25 MHz
Program/erase voltage
Supplied from VCC
Supplied from VCC
Programming Programming 32-byte simultaneous programming
unit
Erasing
RAM
emulation
Flash error
128-byte simultaneous programming
Write pulse
application
method
150 µs × 4 + 500 µs × 399
30 µs × 6 + 200 µs × 994
1
(with 10 µs additional programming)*
Block
configuration
8 blocks
1 kbyte × 4, 28 kbytes × 1,
32 kbytes × 3
8 blocks
1 kbyte × 4, 28 kbytes × 1,
32 kbytes × 3
EBR
configuration
EBR: H'EE032
EBR: H'EE032
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
RAM area
1 kbyte (H'FF000 to H'FF3FF)
1 kbyte (H'FF000 to H'FF3FF)
Applicable
blocks
EB0 to EB3
EB0 to EB3
RAMCR
configuration
RAMCR: H'EE077
FLER bit
7
6
5
4
—
—
—
—
RAMCR: H'EE077
3
2
1
RAMS RAM2 RAM1
0
7
6
5
4
—
—
—
—
—
FLMSR: H'EE07D
3
2
1
RAMS RAM2 RAM1
FLMCR2: H'EE031
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
FLER
—
—
—
—
—
—
—
2
Flash
Wait after
—
memory
SWE clearing
characteristics
tcswe specification must be met*
Boot mode
19,200 bps, 9,600 bps, 4,800 bps
Bit rate
9,600 bps, 4,800 bps
Boot area
H'FFEF20 to H'FFF3FF
H'FFEF20 to H'FFF51F
User area
H'FFF400 to H'FFFF1F (2.8 kbytes)
H'FFF520 to H'FFFF1F (2.5 kbytes)
Programming control program No
identification function
PROM mode
Notes:
0
—
Yes
Use of PROM writer supporting
Use of PROM writer supporting
Renesas microcomputer device type
Renesas microcomputer device type
with 128 kbytes on-chip flash memory
with 128 kbytes on-chip flash memory
1. See section 19.6, Flash Memory Programming/Erasing, for details of the H8/3062F-ZTAT B-mask
version program/erase algorithms.
2. See section 22.5.6, Flash Memory Characteristics, for details of the H8/3062F-ZTAT B-mask
version flash memory characteristics.
Rev. 6.00 Mar 18, 2005 page 602 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.2
Features
The H8/3062F-ZTAT B-mask version has 128 kbytes of on-chip flash memory.
The features of the flash memory are summarized below.
• Four flash memory operating modes
 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erasing is performed in block units. To
erase the entire flash memory, each block must be erased in turn. In block erasing, 1-kbyte, 28kbyte, and 32-kbyte blocks can be set arbitrarily.
• Programming/erase times
The flash memory programming time is 10 ms (typ) for simultaneous 128-byte programming,
equivalent approximately to 80 µs (typ) per byte, and the erase time is 100 ms (typ) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board. A
function is also provided specially in boot mode for identifying a program transferred from the
host side.:
 Boot mode
 User program mode
• Automatic bit rate adjustment
For data transfer in boot mode, the H8/3062F-ZTAT B-mask version chip’s bit rate can be
automatically adjusted to match the transfer bit rate of the host.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are three protect modes—hardware, software, and error—which allow protected status
to be designated for flash memory program/erase/verify operations.
Rev. 6.00 Mar 18, 2005 page 603 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
• PROM mode
Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as
well as in on-board programming mode.
19.2.1
Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
EBR
Bus interface/controller
Operating
mode
RAMCR
Flash memory
(128 kbytes)
Legend:
FLMCR1
FLMCR2
EBR
RAMCR
:
:
:
:
Flash memory control register 1
Flash memory control register 2
Erase block register
RAM control register
Figure 19.1 Block Diagram of Flash Memory
Rev. 6.00 Mar 18, 2005 page 604 of 970
REJ09B0215-0600
FWE pin
Mode pins
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.2.2
Pin Configuration
The flash memory is controlled by means of the pins shown in table 19.3.
Table 19.3 Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Flash write enable
FWE
Input
Flash program/erase protection by hardware
Mode 2
MD2
Input
Sets H8/3062F-ZTAT B-mask version
operating mode
Mode 1
MD1
Input
Sets H8/3062F-ZTAT B-mask version
operating mode
Mode 0
MD0
Input
Sets H8/3062F-ZTAT B-mask version
operating mode
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
19.2.3
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19.4.
Table 19.4 Flash Memory Registers
Register Name
Abbreviation
R/W
Initial Value
Address*1
Flash memory control register 1
FLMCR1
R/W
H'00*2
H'EE030
Flash memory control register 2
FLMCR2
R
H'00
H'EE031
Erase block register
EBR
R/W
H'00
H'EE032
RAM control register
RAMCR
R/W
H'F1
H'EE077
Notes: FLMCR1, FLMCR2, EBR, and RAMCR are 8-bit registers, and should be accessed by byte
access. These registers are used only in the versions with on-chip flash memory, and are
not provided in the versions with on-chip masked ROM. Reading the corresponding
addresses in a masked ROM version will always return 1s, and writes to these addresses
are invalid.
1. Lower 20 bits of address in advanced mode
2. When a high level is input to the FWE pin, the initial value is H'80.
Rev. 6.00 Mar 18, 2005 page 605 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.3
Register Descriptions
19.3.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
SWE
ESU
PSU
EV
PV
E
P
Initial value
FWE
—*
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control.
Program-verify mode or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting
the SWE bit when FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000
to H'1FFFF is entered by setting the SWE bit when FWE = 1, then setting the PSU bit, and finally
setting the P bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting the SWE bit
when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a
reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a
high level is input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin
must be fixed low since flash memory on-board programming modes are not supported. When the
on-chip flash memory is disabled, a read access to this register will return H'00, and writes are
invalid.
When setting bits 6 to 0 in this register, one bit must be set one at a time. Writes to the SWE bit in
FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE
= 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to
the P bit only when FWE = 1, SWE = 1, and PSU = 1.
Notes: 1. The programming and erase flowcharts must be followed when setting the bits in this
register to prevent erroneous programming or erasing.
2. Transitions are made to program mode, erase mode, program-verify mode, and eraseverify mode according to the settings in this register. When reading flash memory as
normal on-chip ROM, bits 6 to 0 in this register must be cleared.
Rev. 6.00 Mar 18, 2005 page 606 of 970
REJ09B0215-0600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming and
erasing (This bit should be set when setting bits 5 to 0 and EBR bits 7 to 0).
Bit 6
SWE
Description
0
Programming/erasing disabled
1
Programming/erasing enabled
(Initial value)
[Setting condition]
When FWE = 1
Note: Do not execute a SLEEP instruction while the SWE bit is set to 1.
Bit 5—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1 (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time).
Bit 5
ESU
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Rev. 6.00 Mar 18, 2005 page 607 of 970
REJ09B0215-0600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Bit 4—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1 (Do not set the SWE, ESU, EV, PV, E, or P bit at the same
time).
Bit 4
PSU
Description
0
Program setup cleared
1
Program setup
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 3—Erase-Verify Mode (EV): Selects erase-verify mode transition or clearing (Do not set the
SWE, ESU, PSU, PV, E, or P bit at the same time).
Bit 3
EV
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
When FWE = 1 and SWE = 1
Bit 2—Program-Verify Mode (PV): Selects program-verify mode transition or clearing (Do not
set the SWE, ESU, PSU, EV, E, or P bit at the same time).
Bit 2
PV
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
Rev. 6.00 Mar 18, 2005 page 608 of 970
REJ09B0215-0600
(Initial value)
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Bit 1—Erase Mode (E): Selects erase mode transition or clearing (Do not set the SWE, ESU,
PSU, EV, PV, or P bit at the same time).
Bit 1
E
Description
0
Erase mode cleared
1
Transition to erase mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
Note: Do not access the flash memory while the E bit is set.
Bit 0—Program (P): Selects program mode transition or clearing (Do not set the SWE, ESU,
PSU, EV, PV, or E bit at the same time).
Bit 0
P
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Note: Do not access the flash memory while the P bit is set.
Rev. 6.00 Mar 18, 2005 page 609 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.3.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When
the on-chip flash memory is disabled, a read will return H'00.
Note: FLMCR2 is a read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
Bit 7
FLER
Description
0
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset (RES pin or WDT reset) or hardware standby mode
1
(Initial value)
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting conditions]
•
When flash memory is read during programming/erasing (including a vector read or
instruction fetch, but excluding a read of the RAM area overlapping flash memory
space)
•
Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
handling)
•
When a SLEEP instruction (including software standby) is executed during
programming/erasing
•
When the bus is released during programming/erasing
Bits 6 to 0—Reserved: These bits are always read as 0.
Rev. 6.00 Mar 18, 2005 page 610 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.3.3
Erase Block Register (EBR)
EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not
input to the FWE pin, or when the SWE bit in FLMCR1 is 0 when a high level is applied to the
FWE pin. When a bit is set in EBR, the corresponding block can be erased. Other blocks are eraseprotected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits
in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR1 is set. The flash memory block
configuration is shown in table 19.5. To erase all the blocks, erase each block sequentially.
The H8/3062F-ZTAT B-mask version does not support the on-board programming mode in mode
6, so bits in this register cannot be set to 1 in mode 6.
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
Modes 1
to 4, and 6 Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Modes 5
and 7
Bits 7 to 0—Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
corresponding block (EB7 to EB0) for erasure.
Bits 7–0
EB7–EB0
Description
0
Corresponding block (EB7 to EB0) not selected
1
Corresponding block (EB7 to EB0) selected
(Initial value)
Note: When not performing an erase, clear all EBR bits to 0.
Rev. 6.00 Mar 18, 2005 page 611 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Table 19.5 Flash Memory Erase Blocks
Block (Size)
Address
EB0 (1 kbyte)
H'000000 to H'0003FF
EB1 (1 kbyte)
H'000400 to H'0007FF
EB2 (1 kbyte)
H'000800 to H'000BFF
EB3 (1 kbyte)
H'000C00 to H'000FFF
EB4 (28 kbytes)
H'001000 to H'007FFF
EB5 (32 kbytes)
H'008000 to H'00FFFF
EB6 (32 kbytes)
H'010000 to H'017FFF
EB7 (32 kbytes)
H'018000 to H'01FFFF
19.3.4
RAM Control Register (RAMCR)
RAMCR selects the RAM area to be used when emulating real-time flash memory programming.
Bit
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
RAMS
RAM2
RAM1
—
1
1
1
1
0
0
0
1
—
—
—
—
R
R
R
—
1
1
1
1
0
0
0
1
—
R/W*
R/W*
R/W*
—
—
—
—
Reserved bits
Reserved bit
RAM2, RAM1
Used together with bit 3 to select
a flash memory area
RAM select
Used together with bits 2 and 1 to select
a flash memory area
Note: * Cannot be set to 1 in mode 6.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Rev. 6.00 Mar 18, 2005 page 612 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Bit 3—RAM Select (RAMS): Used with bits 2 to 1 to reassign an area to RAM (see table 19.6).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled*. In modes other than 5 to 7, 0 is always read and writing is disabled.
This bit is initialized by a reset and in hardware standby mode. It is not initialized in software
standby mode.
When 1 is written to the RAMS bit, all flash memory blocks are protected from programming and
erasing.
Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (See
table 19.6). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled*. In modes other than 5 to 7, 0 is always read and writing is disabled.
These bits are initialized by a reset and in hardware standby mode. They are not initialized in
software standby mode.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
Note: * Flash memory emulation by RAM is not supported for mode 6 (single chip normal mode),
so programming is possible, but do not set 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set
to 1.
Table 19.6 RAM Area Setting
Bit 3
Bit 2
Bit 1
RAM Area
RAMS
RAM2
RAM1
RAM Emulation Status
H’FFF000 to H’FFF3FF
0
0/1
0/1
No emulation
H’000000 to H’0003FF
1
0
0
Mapping RAM
H’000400 to H’0007FF
1
0
1
H’000800 to H’000BFF
1
1
0
H’000C00 to H’000FFF
1
1
1
Rev. 6.00 Mar 18, 2005 page 613 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
ROM area
RAM area
H'FFEF20
H'000000
EB0
ROM blocks
EB0–EB3
(H'000000 to
H'000FFF)
H'0003FF
H'000400
H'FFEFFF
H'FFF000
EB1
H'0007FF
H'000800
H'000BFF
H'000C00
Mapping RAM
EB2
H'000FFF
ROM selection
area
RAM selection
area
Actual RAM
H'FFF3FF
H'FFF400
RAM
overlap area
(H'FFF000 to
H'FFF3FF)
H'FFFF1F
EB3
Figure 19.2 Example of ROM Area/RAM Area Overlap
19.4
Overview of Operation
19.4.1
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
H8/3062F-ZTAT B-mask version enters one of the operating modes shown in figure 19.3. In user
mode, flash memory can be read but not programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and PROM
mode.
Boot mode and user program mode cannot be used in the H8/3062F-ZTAT B-mask version’s
mode 6 (normal mode with on-chip ROM enabled).
Rev. 6.00 Mar 18, 2005 page 614 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Reset state
*3
*1
User mode
with on-chip ROM
enabled
RES = 0
RES = 0
*2
*4
RES = 0
FWE = 0
*5
RES = 0
*4
PROM mode
User program
mode
*1
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is not
accessing the flash memory.
1. RAM emulation possible
2. The H8/3062F-ZTAT B-mask version is placed in PROM mode by means of a dedicated
PROM writer.
3. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 0) (1, 1, 1)
FWE = 0
4. MD2, MD1, MD0 = (1, 0, 1) (1, 1, 1)
FWE = 1
5. MD2, MD1, MD0 (0, 0, 1) (0, 1, 1)
FWE = 1
Figure 19.3 Flash Memory Related State Transitions
State transitions between the normal and user modes and on-board programming mode are
performed by changing the FWE pin level from high to low or from low to high. To prevent
misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory
control register (FLMCR1) should be cleared to 0 before making such a transition. After the bits
are cleared, a wait time is necessary. Normal operation is not guaranteed if this wait time is
insufficient.
Rev. 6.00 Mar 18, 2005 page 615 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.4.2
On-Board Programming Modes
Example of Boot Mode Operation
1. Initial state
The old program version or data remains
written in the flash memory. The user should
prepare the programming control program and
new application program beforehand in the
host.
Host
2. Programming control program transfer
When boot mode is entered, the boot program
in the H8/3062F-ZTAT B-mask version
(originally incorporated in the chip) is started
and the programming control program in the
host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically
transferred to the RAM boot program area.
Host
Programming control
program
New application
program
New application
program
H8/3062F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
SCI
Boot program
Flash memory
Flash memory
RAM
SCI
Boot program
RAM
Boot program area
Application
program
(old version)
Application
program
(old version)
3. Flash memory initialization
The erase program in the boot program area
(in RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard
Host
Programming control
program
4. Writing new application program
An identification check is carried out to see if
the programming control program is compatible
with the H8/3062F-ZTAT B-mask version.
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into
the flash memory.
Host
New application
program
H8/3062F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
SCI
Boot program
Flash memory
RAM
Boot program area
Flash memory
prewrite-erase
Programming control
program
SCI
Boot program
Flash memory
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Rev. 6.00 Mar 18, 2005 page 616 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Example of User Program Mode Operation
1. Initial state
The FWE assessment program that confirms
that user program mode has been entered, and
the program that will transfer the programming/
erase control program from flash memory to
on-chip RAM should be written into the flash
memory by the user beforehand. The
programming/erase control program should be
prepared in the host or in the flash memory.
Host
2. Programming/erase control program transfer
When user program mode is entered, user
software recognizes this fact, executes the
transfer program in the flash memory, and
transfers the programming/erase control
program to RAM.
Host
Programming/erase
control program
New application
program
New application
program
H8/3062F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
SCI
Boot program
Flash memory
Flash memory
RAM
FWE assessment program
Transfer program
SCI
Boot program
RAM
FWE assessment program
Transfer program
Programming/erase
control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks.
Do not write to unerased blocks.
Host
Host
New application
program
H8/3062F-ZTAT B-mask version
H8/3062F-ZTAT B-mask version
SCI
Boot program
Flash memory
RAM
FWE assessment program
Transfer program
Flash memory
RAM
FWE assessment program
Transfer program
Programming/erase
control program
Flash memory
erase
SCI
Boot program
Programming/erase
control program
New application
program
Program execution state
Rev. 6.00 Mar 18, 2005 page 617 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.4.3
Flash Memory Emulation in RAM
In the H8/3062F-ZTAT B-mask version, flash memory programming can be emulated in real time
by overlapping the flash memory with part of RAM (“overlap RAM”). When the emulation block
set in RAMCR is accessed while the emulation function is being executed, data written in the
overlap RAM is read.
Emulation should be performed in user mode or user program mode.
SCI
Flash memory
RAM
Emulation block
Overlap RAM
Application program
(Emulation is performed on data written
in RAM)
Execution state
Figure 19.4 Reading Overlap RAM Data in User Mode/User Program Mode
When overlap RAM data is confirmed, clear the RAMS bit to cancel RAM overlap, and actually
perform writes to the flash memory in user program mode.
When the programming control program is transferred to RAM in on-board programming mode,
ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in
the overlap RAM to be rewritten.
Rev. 6.00 Mar 18, 2005 page 618 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
SCI
Flash memory
RAM
Program data
Overlap RAM
(program data)
Application program
Programming control program
Execution state
Figure 19.5 Writing Overlap RAM Data in User Program Mode
19.4.4
Block Configuration
The flash memory in the H8/3062F-ZTAT B-mask version is divided into three 32-kbyte blocks,
one 28-kbyte block, and four 1-kbyte blocks. Erasing can be carried out in block units.
Address H'00000
1 kbyte × 4
28 kbytes
32 kbytes
128 kbytes
32 kbytes
32 kbytes
Address H'1FFFF
Rev. 6.00 Mar 18, 2005 page 619 of 970
REJ09B0215-0600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.5
On-Board Programming Mode
When pins are set to on-board programming mode and a reset-start is executed, the chip enters the
on-board programming state in which on-chip flash memory programming, erasing, and verifying
can be carried out. There are two operating modes in this mode—boot mode and user program
mode. The pin settings for entering each mode are shown in table 19.7. For a diagram of the
transitions to the various flash memory modes, see figure 19.3.
Boot mode and user program mode cannot be used in the H8/3062F-ZTAT B-mask version’s
mode 6 (on-chip ROM enabled).
Table 19.7 On-Board Programming Mode Settings
Mode
FWE
MD2
MD1
MD0
Boot mode
1*1
0*2
0
1
User program mode
Mode 5
Mode 7
0*2
1
1
Mode 5
1
0
1
Mode 7
1
1
1
Notes: 1. For the High level input timing, see items 6 and 7 of “Notes on Using the Boot Mode” in
section 18.5.1.
2. In boot mode, the MD2 setting should be the inverse of the input.
In the boot mode in the H8/3062F-ZTAT B-mask version, the levels of the mode pins
(MD2 to MD0) are reflected in mode select bits 2 to 0 (MDS2 to MDS0) in the mode
control register (MDCR).
Rev. 6.00 Mar 18, 2005 page 620 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.5.1
Boot Mode
When boot mode is used, a flash memory programming control program must be prepared
beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode.
When a reset-start is executed after setting the H8/3062F-ZTAT B-mask version’ pins to boot
mode, the boot program already incorporated in the MCU is activated, and the programming
control program prepared beforehand in the host is transmitted sequentially to the H8/3062FZTAT B-mask version, using the SCI. In the H8/3062F-ZTAT B-mask version, the programming
control program received via the SCI is written into the programming control program area in onchip RAM. After the transfer is completed, an identification check (ID code check) is carried out
to see if the programming control program is compatible with the H8/3062F-ZTAT B-mask
version. If the ID code matches, control branches to the start address (H'FFF520) of the
programming control program area and the programming control program execution state is
entered (flash memory programming/erasing can be performed).
Figure 19.6 shows a system configuration diagram when using boot mode, and figure 19.7 shows
the boot program mode execution procedure.
H8/3062F-ZTAT B-mask version
Flash memory
Host
Reception of programming data
Transmission of verify data
RxD1
SCI1
TxD1
On-chip RAM
Figure 19.6 System Configuration When Using Boot Mode
Rev. 6.00 Mar 18, 2005 page 621 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Start
Set pins to boot program mode and execute reset-start
Host transfers data (H'00) continuously at prescribed
bit rate
H8/3062F-ZTAT B-mask version measures low period
of H'00 data transmitted by host
H8/3062F-ZTAT B-mask version calculates bit rate and
sets value in bit rate register
After bit rate adjustment, H8/3062F-ZTAT B-mask
version transmits one H'00 data byte to host to indicate
end of adjustment
Host confirms normal reception of bit rate adjustment
end indication (H'00), and transmits one H'55 data byte
After receiving H'55, H8/3062F-ZTAT B-mask version
transmits one H'AA byte to host
Host transmits number of programming control program
bytes (N), upper byte followed by lower byte
H8/3062F-ZTAT B-mask version transmits received
number of bytes to host as verify data (echo-back)
n=1
Host transmits programming control program
sequentially in byte units
H8/3062F-ZTAT B-mask version transmits received
programming control program to host as verify data
(echo-back)
n+1→n
Transfer received programming control program to
on-chip RAM
n = N?
No
Yes
End of transmission
Check flash memory data, and if data has already been
written, erase all blocks
Confirm that all flash memory data has been erased
Check ID code at beginning of user program transfer
area
(Match)
Transmit one H'AA byte to host
(Mismatch)
Transmit H'FF as
error notification
Execute programming control program transferred to
on-chip RAM
Notes: 1. If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error
indication, and the erase operation and subsequent operations are halted.
2. Shading indicates a difference from the H8/3062F-ZTAT R-mask version.
Figure 19.7 Boot Mode Execution Procedure
Rev. 6.00 Mar 18, 2005 page 622 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Automatic SCI Bit Rate Adjustment:
Start
bit
D0
D1
D2
D3
D4
D5
D6
Low period (9 bits) measured (H'00 data)
D7
Stop
bit
High period
(1 or more bits)
When boot mode is initiated, the H8/3062F-ZTAT B-mask version measures the low period of the
asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI
transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The H8/3062F-ZTAT Bmask version calculates the bit rate of the transmission from the host from the measured low
period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host
should confirm that this adjustment end indication (H'00) has been received normally, and
transmit one H'55 byte to the H8/3062F-ZTAT B-mask version. If reception cannot be performed
normally, initiate boot mode again (reset), and repeat the above operations. Depending on the
host’s transmission bit rate and the H8/3062F-ZTAT B-mask version’s system clock frequency,
there will be a discrepancy between the bit rates of the host and the H8/3062F-ZTAT B-mask
version. To ensure correct SCI operation, the host’s transfer bit rate should be set to 4800, 9600, or
19,200 bps*.
Table 19.8 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the H8/3062F-ZTAT B-mask version bit rate is possible. The boot program should
be executed within this system clock range.
Table 19.8 System Clock Frequencies for which Automatic Adjustment of H8/3062F-ZTAT
B-Mask Version Bit Rate is Possible
Host Bit Rate (bps)
System Clock Frequency for which Automatic Adjustment of
H8/3062F-ZTAT B-Mask Version Bit Rate is Possible (MHz)
19,200
16 to 25
9,600
8 to 25
4,800
4 to 25
Note: * Only use a setting of 4800, 9600, or 19200 for the host’s bit rate. No other settings can be
used.
Although the H8/3062F-ZTAT B-mask version may also perform automatic bit rate
adjustment with bit rate and system clock combinations other than those shown in table
Rev. 6.00 Mar 18, 2005 page 623 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.8, a degree of error will arise between the bit rates of the host and the MCU, and
subsequent transfer will not be performed normally. Therefore, only a combination of bit
rate and system clock frequency within one of the ranges shown in table 19.8 can be used
for boot mode execution.
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the user program is transferred via the SCI, as
shown in figure 19.8. The boot program area becomes available when a transition is made to the
execution state for the user program transferred to RAM.
H'FFEF20
Boot program
area
ID code area
(8 bytes)
H'FFF51F
H'FFF520
User program
transfer area
H'FFFF1F
Note: The boot program area cannot be used until a transition is made to the execution state
for the user program transferred to RAM. Note also that the boot program remains in
this area in RAM even after control branches to the user program.
Figure 19.8 RAM Areas in Boot Mode
In boot mode in the H8/3062F-ZTAT B-mask version, the contents of the 8-byte ID code area
shown below are checked to determine whether the program is a programming control program
compatible with the H8/3062F-ZTAT B-mask version.
H'FFF520
40
FE
61
66
33
30
36
32
(Product ID code)
H'FFF528…
Programming control program instruction codes
If an original programming control program is used in boot mode, the 8-byte ID code shown
above should be added at the beginning of the program.
Rev. 6.00 Mar 18, 2005 page 624 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Notes on Use of Boot Mode:
1. When the H8/3062F-ZTAT B-mask version chip comes out of reset in boot mode, it measures
the low period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After
the reset ends, it takes about 100 states for the chip to get ready to measure the low period of
the RxD1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RxD1 and TxD1 lines should be pulled up on the board.
5. Before branching to the user program the H8/3062F-ZTAT B-mask version terminates
transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits
to 0 in the serial control register (SCR)), but the adjusted bit rate value remains set in the bit
rate register (BRR). The transmit data output pin, TxD1, goes to the high-level output state
(P91DDR = 1 in P9DDR, P91DR = 1 in P9DR).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by setting pins MD0 to MD2 and FWE in accordance with the mode
setting conditions shown in table 19.6, and then executing a reset-start.
a. When switching from boot mode to normal mode, the boot mode state within the chip must
first be cleared by reset input via the RES pin*1. The RES pin must be held low for at least
20 system clock cycles*2.
b. Do not change the input levels of the mode pins (MD2 to MD0) or the FWE pin in boot
mode. To change the mode, the RES pin must first be driven low to set the reset state. Also,
if a watchdog timer reset occurs in the boot mode state, the MCU’s internal state will not
be cleared, and the on-chip boot program will be restarted regardless of the mode pin
states.
c. The FWE pin must not be driven low while the boot program is running or flash memory is
being programmed or erased*3.
7. If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output signals (CSn, AS, RD,
LWR, HWR) may also change according to the change in the MCU’s operating mode.
Therefore, care must be taken to make pin settings to prevent these pins from being used
Rev. 6.00 Mar 18, 2005 page 625 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
directly as output signal pins during a reset, or to prevent collision with signals outside the
MCU.
H8/3062F-ZTAT
B-mask version
CSn
MD2
MD1
MD0
FWE
External
memory,
etc.
System
control
unit
RES
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS)
with respect to the reset release timing.
2. See section 4.2.2, Reset Sequence, and section 19.11, Flash Memory Programming and
Erasing Precautions. The H8/3062F-ZTAT B-mask version requires a minimum of 20
system clock cycles for a reset during operation.
3. For further information on FWE application and disconnection, see section 19.11,
Flash Memory Programming and Erasing Precautions.
19.5.2
User Program Mode
When set to user program mode, the H8/3062F-ZTAT B-mask version can program and erase its
flash memory by executing a user program/erase control program. Therefore, on-board
reprogramming of the on-chip flash memory can be carried out by providing on-board means of
FWE control and supply of programming data, and storing a program/erase control program in
part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip ROM (mode 5 or 7), and
apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 5 and 7.
Flash memory programming/erasing should not be carried out in mode 6. When mode 6 is set, the
FWE pin must be driven low.
Rev. 6.00 Mar 18, 2005 page 626 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
The flash memory itself cannot be read while being programmed or erased, so the program that
performs programming should be placed in external memory or transferred to RAM and executed
there.
Figure 19.9 shows the execution procedure when user program mode is entered during program
execution in RAM. It is also possible to start from user program mode in a reset-start.
Write FWE assessment program and transfer
program (and programming/erase control
program if necessary) beforehand
MD2 to MD0 = 101 or 111
Reset-start
Transfer programming/erase control
program to RAM
Branch to programming/erase control
program in RAM area
FWE = High
(user program mode)
Execute programming/erase control
program in RAM
(flash memory rewriting)
Clear SWE bit, then release FWE
(user program mode clearing)
Branch to application program
in flash memory
Notes: 1. Do not apply a constant high level to the FWE pin. A high level should be applied to the
FWE pin only when programming or erasing flash memory (including execution of flash
memory emulation by RAM). Also, while a high level is applied to the FWE pin, the
watchdog timer should be activated to prevent overprogramming or overerasing due to
program runaway, etc.
2. For further information on FWE application and disconnection, see section 19.11, Flash
Memory Programming and Erasing Precautions.
3. In order to execute a normal read of flash memory in user program mode, the
programming/erase program must not be executing. It is thus necessary to ensure that
bits 6 to 0 in FLMCR1 are cleared to 0.
Figure 19.9 Example of User Program Mode Execution Procedure
Rev. 6.00 Mar 18, 2005 page 627 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.6
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses
H'000000 to H'01FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(user program) that controls flash memory programming/erasing should be located and executed in
on-chip RAM or external memory.
See section 19.11, Flash Memory Programming and Erasing Precautions, for points to be noted
when programming or erasing the flash memory. In the following operation descriptions, wait
times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of
the wait times, see section 22.5.6, Flash Memory Characteristics.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR1 is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (Programming/erasing will not be
executed if FWE = 0).
3. Programming must be executed in the erased state. Do not perform additional
programming on addresses that have already been programmed.
Rev. 6.00 Mar 18, 2005 page 628 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
*3
E=1
Erase setup
state
Erase mode
E=0
Normal mode
FWE = 1
ESU = 1
ESU = 0
*1
FWE = 0
EV = 1
*2
On-board
SWE = 1
Software
programming mode
programming
Software programming
enable
disable state
SWE = 0
state
Erase-verify
mode
EV = 0
PSU = 1
*4
P=1
PSU = 0
Program
setup state
Program mode
P=0
PV = 1
PV = 0
Program-verify
mode
Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads
can be performed during the programming/erasing process.
1.
: Normal mode
: On-board programming mode
2. Do not make a state transition by setting or clearing multiple bits simultaneously.
3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing
through the software programming enable state.
4. After a transition from program mode to the program setup state, do not enter program mode without
passing through the software programming enable state.
Figure 19.10 FLMCR1 Bit Settings and State Transitions
Rev. 6.00 Mar 18, 2005 page 629 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.6.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 19.11 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes
at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 22.40 in section 22.5.6,
Flash Memory Characteristics.
Following the elapse of (tsswe) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data
is written consecutively to the write addresses. The lower 8 bits of the first address written to must
be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation for
entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.
The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the
elapse of at least (tspsu) µs. The time during which the P bit is set is the flash memory
programming time. Make a program setting so that the time for one programming operation is
within the range of (tsp) µs.
The wait time after P bit setting must be changed according to the degree of progress through the
programming operation. For details see “Notes on Program/Program-Verify Procedure” below.
19.6.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least
(tcp) µs before clearing the PSU bit to exit program mode. After exiting program mode, the
watchdog timer setting is also cleared. The operating mode is then switched to program-verify
mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of (tspv) µs or more. When the flash memory is read in this state (verify data is read
in 16-bit units), the data at the latched address is read. Wait at least (tspvr) µs after the dummy write
Rev. 6.00 Mar 18, 2005 page 630 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
before performing this read operation. Next, the originally written data is compared with the verify
data, and reprogram data is computed (see figure 19.11) and transferred to RAM. After
verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least
(tcpv) µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode
again, and repeat the program/program-verify sequence as before. The maximum number of
repetitions of the program/program-verify sequence is indicated by the maximum programming
count (N). Leave a wait time of at least (tcswe) µs after clearing SWE.
Notes on Program/Program-Verify Procedure
1. The program/program-verify procedure for the H8/3062F-ZTAT B-mask version uses a 128byte-unit programming algorithm.
Note that this is different from the procedure in the H8/3062F-ZTAT R-mask version (32-byteunit programming).
In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must
be H'00 or H'80.
2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer
should be used.
128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write
H'FF data to the extra addresses.
3. Verify data is read in word units.
4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is
set. In the H8/3062F-ZTAT B-mask version, write pulses should be applied as follows in the
program/program-verify procedure to prevent voltage stress on the device and loss of write
data reliability.
a. After write pulse application, perform a verify-read in program-verify mode and apply a
write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write
bits in the 128-byte write data are read as 0 in the verify-read operation, the
program/program-verify procedure is completed. In the H8/3062F-ZTAT B-mask version,
the number of loops in reprogramming processing is guaranteed not to exceed the
maximum value of the maximum programming count (N).
b. After write pulse application, a verify-read is performed in program-verify mode, and
programming is judged to have been completed for bits read as 0. The following processing
is necessary for programmed bits.
When programming is completed at an early stage in the program/program-verify
procedure:
Rev. 6.00 Mar 18, 2005 page 631 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
If programming is completed in the 1st to 6th reprogramming processing loop, additional
programming should be performed on the relevant bits. Additional programming should
only be performed on bits which first return 0 in a verify-read in certain reprogramming
processing.
When programming is completed at a late stage in the program/program-verify procedure:
If programming is completed in the 7th or later reprogramming processing loop, additional
programming is not necessary for the relevant bits.
c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing
should be executed. If a bit for which programming has been judged to be completed is
read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.
5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed
according to the degree of progress through the program/program-verify procedure. For
detailed wait time specifications, see section 22.5.6, Flash Memory Characteristics.
Item
Symbol
Item
Symbol
Wait time after
P bit setting
tsp
When reprogramming loop count (n) is 1 to 6
tsp30
When reprogramming loop count (n) is 7 or more
In case of additional programming processing*
tsp200
tsp10
Note: * Additional programming processing is necessary only when the reprogramming loop count
(n) is 1 to 6.
6. The program/program-verify flowchart for the H8/3062F-ZTAT B-mask version is shown in
figure 19.11.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown
below.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
Rev. 6.00 Mar 18, 2005 page 632 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Reprogram Data Computation Table
(D)
Result of Verify-Read
after Write Pulse
(X)
Application (V)
Result of Operation
0
0
1
Programming completed: reprogramming
processing not to be executed
0
1
0
Programming incomplete: reprogramming
processing to be executed
1
0
1

1
1
1
Still in erased state: no action
Comments
Legend:
(D): Source data of bits on which programming is executed
(X): Source data of bits on which reprogramming is executed
Additional-Programming Data Computation Table
(X')
Result of Verify-Read
after Write Pulse
(Y)
Application (V)
Result of Operation
0
0
0
Programming by write pulse application
judged to be completed: additional
programming processing to be executed
0
1
1
Programming by write pulse application
incomplete: additional programming
processing not to be executed
1
0
1
Programming already completed:
additional programming processing not to
be executed
1
1
1
Still in erased state: no action
Comments
Legend:
(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop
(Y): Data of bits on which additional programming is executed
7. It is necessary to execute additional programming processing during the course of the
H8/3062F-ZTAT B-mask version program/program-verify procedure. However, once 128byte-unit programming is finished, additional programming should not be carried out on the
same address area. When executing reprogramming, an erase must be executed first. Note that
normal operation of reads, etc., is not guaranteed if additional programming is performed on
addresses for which a program/program-verify operation has finished.
Rev. 6.00 Mar 18, 2005 page 633 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Start of programming
Write pulse application subroutine
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
START
Sub-Routine Write Pulse
Set SWE bit in FLMCR1
WDT enable
Wait (tsswe) µs
Set PSU in FLMCR1
Wait (tspsu) µs
*7
*4
n= 1
Start of programming
Set P bit in FLMCR1
*7
Store 128-byte program data in program
data area and reprogram data area
m= 0
Wait (tsp) µs
*5 *7
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Programming halted
Clear P bit in FLMCR1
*1
Sub-Routine-Call
Wait (tcp) µs
*7
See Note 6 for pulse width
Write pulse
Set PV bit in FLMCR1
Clear PSU bit in FLMCR1
Wait (tcpsu) µs
Wait (tspv) µs
*7
*7
H'FF dummy write to verify address
Disable WDT
End Sub
Wait (tspvr) µs
*7
Read verify data
*2
Write data =
verify data?
NG
n←n+1
Increment address
Note 6: Write Pulse Width
Number of Writes n
Write Time (tsp) µs
1
2
3
4
5
6
7
8
9
10
11
12
13
30
30
30
30
30
30
200
200
200
200
200
200
200
998
999
1000
200
200
200
m=1
OK
NG
6≥n?
OK
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
*4
*3
Transfer reprogram data to reprogram data area
NG
*4
128-byte
data verification completed?
OK
Clear PV bit in FLMCR1
Reprogram
Wait (tcpv) µs
Note: Use a 10 µs write pulse for additional programming.
*7
NG
6 ≥ n?
OK
Successively write 128-byte data from additional*1
programming data area in RAM to flash memory
RAM
Program data storage
area (128 bytes)
Sub-Routine-Call
Write Pulse (Additional programming)
Reprogram data storage
area (128 bytes)
*7
NG
m= 0 ?
n ≥ N?
NG
OK
Clear SWE bit in FLMCR1
OK
Clear SWE bit in FLMCR1
Additional-programming
data storage area
(128 bytes)
Wait (tcswe) µs
Wait (tcswe) µs
End of programming
Programming failure
*7
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (longword) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are
programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 µs
write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 22.5.6, Flash Memory.
Additional-Programming Data Computation Table
Reprogram Data Computation Table
Original Data
Verify Data
Reprogram Data
(D)
0
0
(V)
0
1
(X)
1
0
1
1
0
1
1
1
Comments
Programming completed
Reprogram Data
(X')
Verify Data
Additional(V)
Programming Data (Y)
Programming incomplete; reprogram
0
0
1
0
1
0
0
1
1
Still in erased state; no action
1
1
1
Comments
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
Figure 19.11 Program/Program-Verify Flowchart (128-Byte Programming)
Rev. 6.00 Mar 18, 2005 page 634 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.6.3
Erase Mode
When erasing flash memory, the single-block erase flowchart shown in figure 19.12 should be
followed.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in table 22.40 in section 22.5.6, Flash
Memory Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register (EBR) at least (tsswe) µs after setting the SWE bit to 1 in FLMCR1. Next, the
watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value
greater than (tse) ms + (tsesu + tce + tcesu) µs as the WDT overflow period. Preparation for entering
erase mode (erase setup) is performed next by setting the ESU bit in FLMCR1. The operating
mode is then switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least
(tsesu) µs. The time during which the E bit is set is the flash memory erase time. Ensure that the
erase time does not exceed (tse) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
19.6.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (tce) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the
EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be
made to the addresses to be read. The dummy write should be executed after the elapse of (tsev) µs
or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (tsevr) µs after the dummy write before performing this
read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is
completed, exit erase-verify mode, and wait for at least (tcev) µs. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (tcswe) µs.
Rev. 6.00 Mar 18, 2005 page 635 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
If erasing multiple blocks, set a single bit in EBR for the next block to be erased, and repeat the
erase/erase-verify sequence as before.
Start
*1
Perform erasing in block units.
Set SWE bit in FLMCR1
Wait (tsswe) µs
*5
n=1
Set EBR
*3, *4
Enable WDT
Set ESU bit in FLMCR1
Wait (tsesu) µs
*5
Start of erase
Set E bit in FLMCR1
Wait (tse) ms
*5
Clear E bit in FLMCR1
Erase halted
Wait (tce) µs
*5
Clear ESU bit in FLMCR1
Wait (tcesu) µs
*5
Disable WDT
Set EV bit in FLMCR1
Wait (tsev) µs
n←n+1
*5
Set block start address as verify address
H'FF dummy write to verify address
Wait (tsevr) µs
*5
Read verify data
Increment
address
Verify data = all 1s?
*2
No
Yes
No
Last address of block?
Yes
Clear EV bit in FLMCR1
*5
Wait (tcev) µs
Clear EV bit in FLMCR1
*5
n ≥ N?
Clear SWE bit in FLMCR1
Notes: 1.
2.
3.
4.
5.
*5
Wait (tcev) µs
*5
No
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) µs
Wait (tcswe) µs
End of erasing
Erase failure
*5
Prewriting (setting erase block data to all 0s) is not necessary.
Verify data is read in 16-bit (word) units.
Make only a single-bit specification in the erase block register (EBR). Two or more bits must not be set simultaneously.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
The wait times and the value of N are shown in section 22.5.6, Flash Memory Characteristics.
Figure 19.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.7
Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error
protection.
19.7.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and
erase block register (EBR) are reset. In the error protection state, the FLMCR1 and EBR settings
are retained; the P bit and E bit can be set, but a transition is not made to program mode or erase
mode (See table 19.9).
Table 19.9 Hardware Protection
Function
Item
Description
Program
Erase
Verify
FWE pin
protection
•
When a low level is input to the FWE pin,
FLMCR1 and EBR are initialized, and the
program/erase-protected state is entered.
Not
possible*1
Not
possible*3
Not
possible
Reset/
standby
protection
•
In a reset (including a WDT overflow reset)
and in standby mode, FLMCR1 and EBR
are initialized, and the program/eraseprotected state is entered.
Not
possible
Not
3
possible*
Not
possible
•
In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on.
In the case of a reset during operation, hold
the RES pin low for the RES pulse width
specified in the AC Characteristics section*4.
•
When a microcomputer operation error
(error generation (FLER = 1)) was detected
while flash memory was being
programmed/erased, error protection is
enabled. At this time, the FLMCR1 and
EBR settings are held, but
programming/erasing is aborted at the time
the error was generated. Error protection is
released only by a reset via the RES pin or
a WDT reset, or in the hardware standby
mode.
Not
possible
Not
possible*3
Possible*2
Error
protection
Rev. 6.00 Mar 18, 2005 page 637 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Notes: 1. The RAM area that overlapped flash memory is deleted.
2. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify operation on the block being erased.
3. All blocks are unerasable and block-by-block specification is not possible.
4. See section 4.2.2, Reset Sequence, and section 19.11, Flash Memory Programming
and Erasing Precautions. The H8/3062F-ZTAT B-mask version requires a minimum of
20 system clock cycles for a reset during operation.
19.7.2
Software Protection
Software protection can be implemented by setting the erase block register (EBR) and the RAMS
bit in the RAM control register (RAMCR). With software protection, setting the P or E bit in the
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode (See table 19.10).
Table 19.10 Software Protection
Functions
Item
Description
Block
protection
•
—
Erase protection can be set for individual
blocks by settings in erase block register
2
(EBR)* . However, programming protection
is disabled.
•
Setting EBR to H'00 places all blocks in the
erase-protected state.
•
Setting the RAMS bit 1 in RAMCR places
all blocks in the program/erase-protected
state.
Emulation
protection
Program
Not
1
possible*
Erase
Verify
Not
possible
Possible
Possible
Not
3
possible*
Notes: 1. The RAM area overlapping flash memory can be written to.
2. When not erasing, set EBR to H'00.
3. All blocks are unerasable and block-by-block specification is not possible.
Rev. 6.00 Mar 18, 2005 page 638 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.7.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing*1, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1,
FLMCR2, and EBR settings*3 are retained, but program mode or erase mode is aborted at the
point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting
the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can be made
to verify mode*2.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after the start of exception handling during programming/erasing (excluding
reset, illegal instruction, trap instruction, and division-by-zero exception handling)
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a RES pin or WDT reset, or in hardware standby mode.
Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
in this state.
2. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify on the block being erased.
3. FLMCR1 and EBR can be written to. However, the registers are initialized if a
transition is made to software standby mode while in the error protection state.
Figure 19.13 shows the flash memory state transition diagram.
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Program mode
Erase mode
Reset or standby
(hardware protection)
RES = 0 or STBY = 0
RD VF PR ER INIT FLER = 0
RD VF PR ER FLER = 0
Error occurrence
(software standby)
RES = 0 or
STBY = 0
Error
occurrence
RES = 0 or
STBY = 0
Software
standby mode
Error protection mode
RD VF PR ER FLER = 1
Software standby
mode release
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
(software standby)
RD VF PR ER INIT FLER = 1
FLMCR1, EBR
initialization state
RD
VF
PR
ER
:
:
:
:
Memory read possible
Verify-read possible
Programming possible
Erasing possible
RD
VF
PR
ER
INIT
:
:
:
:
:
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Register initialization state
Figure 19.13 Flash Memory State Transitions
(When High Level is Applied to FWE Pin in Mode 5 or 7 (On-Chip ROM Enabled))
The error protection function is invalid for abnormal operations other than the FLER bit setting
conditions. Also, if a certain time has elapsed before this protection state is entered, damage may
already have been caused to the flash memory. Consequently, this function cannot provide
complete protection against damage to flash memory.
To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in
accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied,
and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog
timer or other means. There may also be cases where the flash memory is in an erroneous
programming or erroneous erasing state at the point of transition to this protection mode, or where
programming or erasing is not properly carried out because of an abort. In cases such as these, a
forced recovery (program rewrite) must be executed using boot mode. However, it may also
happen that boot mode cannot be normally initiated because of overprogramming or overerasing.
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.8
Flash Memory Emulation in RAM
As flash memory programming and erasing takes time, it may be difficult to carry out tuning by
writing parameters and other data in real time. In this case, real-time programming of flash
memory can be emulated by overlapping part of RAM (H'FFF000 to H'FFF3FF) onto a small
block area in flash memory. This RAM area change is executed by means of bits 3 to 1 in the
RAM control register (RAMCR). After the RAM area change, access is possible both from the
area overlapped onto flash memory and from the original area (H'FFF000 to H'FFF3FF). For
details of RAMCR and the RAM area setting method, see section 19.3.4, RAM Control Register
(RAMCR).
Example of Emulation of Real-Time Flash Memory Programming: In the following example,
RAM area H'FFF000 to H'FFF3FF is overlapped onto flash memory area EB2 (H'FFF000 to
H'FFF3FF).
Procedure:
H'000000
1. Part of RAM (H'FFF000 to H'FFF3FF)
is overlapped onto the area (EB2)
requiring real-time programming
(RAMCR bits 3 to 1 are set to 1, 1, 0,
and the flash memory area to be
overlapped (EB2) is selected).
Flash memory
space
Block area
Overlapping ram
EB2 H'000800
area H'000BFF
H'000FFF
*
(Mapping RAM
area)
H'FFEF20
2.
Real-time programming is performed
using the overlapping RAM.
3. The programmed data is checked,
then RAM overlapping is cleared
(RAMS bit is cleared).
4. The data written in RAM area
H'FFF000 to H'FFF3FF is written to
flash memory space.
On-chip RAM
area
H'FFEFFF
H'FFF000
H'FFF3FF
H'FFF400
(Actual RAM
area)
H'FFFF1F
Note: * When part of RAM (H'FFF000 to H'FFF3FF) is overlapped onto a flash memory small block area, the flash
memory in the overlapped area cannot be accessed. It can be accessed when the overlapping is
cleared.
Figure 19.14 Example of RAM Overlap Operation
Rev. 6.00 Mar 18, 2005 page 641 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Notes on Use of Emulation in RAM:
1. Flash write enable (FWE) application and releasing
As in on-board program mode, care is required when applying and releasing FWE to prevent
erroneous programming or erasing. To prevent erroneous programming and erasing due to
program runaway during FWE application, in particular, the watchdog timer should be set
when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is
being used. For details, see section 19.11, Flash Memory Programming and Erasing
Precautions.
2. NMI input disabling conditions
When the emulation function is used, NMI input is disabled when the P bit or E bit is set to 1
in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby mode,
when a high level is not being input to the FWE pin, or when the SWE bit in FLMCR1 is 0
while a high level is being input to the FWE pin.
3. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of
the value of RAM2 to RAM0 (emulation protection). In this state, setting the P or E bit in
FLMCR1 will not cause a transition to program mode or erase mode. When actually
programming or erasing a flash memory area, the RAMS bit should be cleared to 0.
4. A RAM area cannot be erased by execution of software in accordance with the erase algorithm
while flash memory emulation in RAM is being used.
5. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlap RAM.
Rev. 6.00 Mar 18, 2005 page 642 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.9
NMI Input Disabling Conditions
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode*1, to give priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly*2, possibly resulting in MCU runaway.
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests (exception handling and bus
release), including NMI, must therefore be restricted inside and outside the MCU during FWE
application. NMI input is also disabled in the error protection state and while the P or E bit
remains set in FLMCR1 during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
(This branch takes place immediately after transfer of the user program is completed).
Consequently, after the branch to the RAM area, NMI input is enabled except during
programming and erasing. Interrupt requests must therefore be disabled inside and
outside the MCU until the user program has completed initial programming (including
the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P bit or E bit
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the entry in the interrupt vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 6.00 Mar 18, 2005 page 643 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.10
Flash Memory PROM Mode
The H8/3062F-ZTAT B-mask version has a PROM mode as well as the on-board programming
modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be
freely programmed using a general-purpose PROM writer that supports the Renesas
microcomputer device type with 128-kbyte on-chip flash memory.
19.10.1 Socket Adapters and Memory Map
In PROM mode using a PROM writer, memory reading (verification) and writing and flash
memory initialization (total erasure) can be performed. For these operations, a special socket
adapter is mounted in the PROM writer. The socket adapter product codes are given in table
19.11. In the H8/3062F-ZTAT B-mask version PROM mode, only the socket adapters shown in
this table should be used.
Table 19.11 H8/3062F-ZTAT B-Mask Version Socket Adapter Product Codes
Product Code
Package
Socket Adapter
Product Code
HD64F3062BF
100-pin QFP (FP-100B)
ME3064ESHF1H
HD64F3062BTE 100-pin TQFP (TFP-100B)
ME3064ESNF1H
HD64F3062BFP 100-pin QFP (FP-100A)
ME3064ESFF1H
HD64F3062BF
HF306BQ100D4001
100-pin QFP (FP-100B)
HD64F3062BTE 100-pin TQFP (TFP-100B)
HF306BT100D4001
HD64F3062BFP 100-pin QFP (FP-100A)
HF306AQ100D4001
Manufacturer
MINATO ELECTRONICS
INC.
DATA I/O JAPAN CO.
Figure 19.15 shows the memory map in PROM mode.
MCU mode
H'000000
H8/3062F-ZTAT
B-mask version
PROM mode
H'00000
On-chip ROM
H'01FFFF
H'1FFFF
Figure 19.15 Memory Map in PROM Mode
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.10.2 Notes on Use of PROM Mode
1. A write to a 128-byte programming unit in PROM mode should be performed once only.
Erasing must be carried out before reprogramming an address that has already been
programmed.
2. When using a PROM writer to reprogram a device on which on-board programming/erasing
has been performed, it is recommended that erasing be carried out before executing
programming.
3. The memory is initially in the erased state when the device is shipped by Renesas. For samples
for which the erasure history is unknown, it is recommended that erasing be executed to check
and correct the initialization (erase) level.
4. The H8/3062F-ZTAT B-mask version does not support a product identification mode as used
with general-purpose EPROMs, and therefore the device name cannot be set automatically in
the PROM writer.
5. Refer to the instruction manual provided with the socket adapter, or other relevant
documentation, for information on PROM writers and associated program versions that are
compatible with the PROM mode of the H8/3062F-ZTAT B-mask version.
19.11
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
PROM mode are summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 128-kbyte on-chip
flash memory.
2. Powering on and off (See figures 19.16 to 19.18)
Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin
low before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory
in the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a
power failure and subsequent recovery. Failure to do so may result in overprogramming or
overerasing due to MCU runaway, and loss of normal memory cell operation.
Rev. 6.00 Mar 18, 2005 page 645 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
3. FWE application/disconnection
FWE application should be carried out when MCU operation is in a stable condition. If MCU
operation is not stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to
prevent unintentional programming or erasing of flash memory:
• Apply FWE when the VCC voltage has stabilized within its rated voltage range.
If FWE is applied when the MCU’s VCC power supply is not within its rated voltage range,
MCU operation will be unstable and flash memory may be erroneously programmed or
erased.
• Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling
time).
When VCC power is turned on, hold the RES pin low for the duration of the oscillation
settling time before applying FWE. Do not apply FWE when oscillation has stopped or is
unstable.
• In boot mode, apply and disconnect FWE during a reset.
In a transition to boot mode, FWE = 1 input and MD2 to MD0 setting should be performed
while the RES input is low. FWE and MD2 to MD0 pin input must satisfy the mode
programming setup time (tMDS) with respect to the reset release timing. When making a
transition from boot mode to another mode, also, a mode programming setup time is
necessary with respect to the reset release timing.
In a reset during operation, the RES pin must be held low for a minimum of 20 system
clock cycles.
• In user program mode, FWE can be switched between high and low level regardless of
RES input.
FWE input can also be switched during execution of a program in flash memory.
• Do not apply FWE if program runaway has occurred.
During FWE application, the program execution state must be monitored using the
watchdog timer or some other means.
• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 are
cleared.
Make sure that the SWE, ESU, PSU, EV, PV, E, and P bits are not set by mistake when
applying or disconnecting FWE.
4. Do not apply a constant high level to the FWE pin.
T prevent erroneous programming or erasing due to program runaway, etc., apply a high level
to the FWE pin only when programming or erasing flash memory (including execution of flash
memory emulation using RAM). A system configuration in which a high level is constantly
Rev. 6.00 Mar 18, 2005 page 646 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin,
the watchdog timer should be activated to prevent overprogramming or overerasing due to
program runaway, etc.
5. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
PSU or ESU bit in FLMCR1, the watchdog timer should be set beforehand as a precaution
against program runaway, etc.
Also note that access to the flash memory space by means of a MOV instruction, etc., is not
permitted while the P bit or E bit is set.
6. Do not set or clear the SWE bit during execution of a program in flash memory.
Clear the SWE bit before executing a program or reading data in flash memory. When the
SWE bit is set, data in flash memory can be rewritten, but flash memory should only be
accessed for verify operations (verification during programming/erasing).
Similarly, when using the RAM emulation function while a high level is being input to the
FWE pin, the SWE bit must be cleared before executing a program or reading data in flash
memory. However, the RAM area overlapping flash memory space can be read and written to
regardless of whether the SWE bit is set or cleared.
A wait time is necessary after the SWE bit is cleared. For details see table 22.40 in section
22.5.6, Flash Memory Characteristics.
7. Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled during FWE application to give
priority to program/erase operations (including emulation in RAM).
Bus release must also be disabled.
8. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
9. Before programming, check that the chip is correctly mounted in the PROM writer.
Overcurrent damage to the device can result if the index marks on the PROM writer socket,
socket adapter, and chip are not correctly aligned.
10. Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
11. A wait time of 100 µs or more is necessary when performing a read after a transition to
normal mode from program, erase, or verify mode.
12. Use byte access on the registers that control the flash memory (FLMCR1, FLMCR2,
EBR, and RAMCR).
Wait time:
x
Programming/
erasing
possible
Wait time:
y
φ
Min 0 µs
tOSC1
VCC
tMDS
FWE
Min 0 µs
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
2. See section 22.5.6, Flash Memory Characteristics.
Figure 19.16 Power-On/Off Timing (Boot Mode)
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Wait time:
x
Programming/
erasing
possible
Wait time:
y
φ
Min 0 µs
tOSC1
VCC
FWE
MD2 to MD0*1
tMDS
RES
SWE set
SWE cleared
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off
by pulling the pins up or down.
See section 22.5.6, Flash Memory Characteristics.
Figure 19.17 Power-On/Off Timing (User Program Mode)
Rev. 6.00 Mar 18, 2005 page 649 of 970
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Programming/
erasing possible
Wait time: x
Wait time: x
Programming/
erasing possible
Wait time: y
Wait time: x
Programming/
erasing possible
Wait time: y
Wait time: y
Wait time: x
Programming/
erasing possible
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
φ
tOSC1
VCC
Min 0µs
FWE
*2
tMDS
tMDS
MD2 to MD0
tMDS
tRESW
RES
SWE
cleared
SWE set
SWE bit
Mode
change*1
Boot
mode
Mode
User
change*1 mode
User program mode
User
mode
User program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The state of ports with multiplexed address functions and bus control output pins
(CSn, AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),
and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the mode programming setup time tMDS must be
satisfied with respect to RES clearance timing.
3. See section 22.5.6, Flash Memory Characteristics.
Figure 19.18 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.12
Masked ROM (H8/3062 Masked ROM B-Mask Version, H8/3061
Masked ROM B-Mask Version, H8/3060 Masked ROM B-Mask
Version) Overview
19.12.1 Block Diagram
Figure 19.19 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'00000
H'00001
H'00002
H'00003
On-chip ROM
H'1FFFE
H'1FFFF
Even addresses
Odd addresses
Figure 19.19 ROM Block Diagram (H8/3062 Masked ROM B-Mask Version)
Rev. 6.00 Mar 18, 2005 page 651 of 970
REJ09B0215-0600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.13
Notes on Ordering Masked ROM Version Chips
When ordering H8/3062, H8/3061, and H8/3060 with masked ROM, note the following.
1. When ordering by means of an EPROM, use a 128-kbyte one.
2. Fill all unused addresses with H'FF as shown in figure 19.20 to make the ROM data size 128kbytes for the H8/3062, H8/3061, and H8/3060 masked ROM versions, which incorporate
different sizes of ROM. This applies to ordering by means of an EPROM and by means of data
transmission.
HD6433062B
(ROM: 128 kbytes)
Addresses:
H'00000 to 1FFFF
HD6433060B
(ROM: 64 kbytes)
Addresses:
H'00000 to 0FFFF
HD6433061B
(ROM: 96 kbytes)
Addresses:
H'00000 to 17FFF
H'00000
H'00000
H'00000
H'0FFFF
H'10000
H'17FFF
H'18000
Not used*
Not used*
H'1FFFF
H'1FFFF
H'1FFFF
Note: * Write H'FF in all addresses in these areas.
Figure 19.20 Masked ROM Addresses and Data
3. The flash memory control registers (FLMCR, EBR, RAMCR, FLMSR, FLMCR1, FLMCR2,
EBR1, and EBR2) used by the versions with on-chip flash memory are not provided in the
masked ROM versions. Reading the corresponding addresses in a masked ROM version will
always return 1s, and writes to these addresses are disabled. This must be borne in mind when
switching from a flash memory version to a masked ROM version.
Rev. 6.00 Mar 18, 2005 page 652 of 970
REJ09B0215-0600
Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
19.14
Notes when Converting the F-ZTAT Application Software to the
Masked ROM Versions
Please note the following when converting the F-ZTAT application software to the masked ROM
versions.
The values read from the internal registers for the flash ROM in the masked ROM version and
F-ZTAT version differ as follows.
Status
Register
Bit
Value
F-ZTAT Version
Masked ROM Version
FLMCR1
FWE
0
Application software running
—
(Is not read out)
1
Programming
Application software running
(This bit is always read as 1)
Note: This difference applies to all the F-ZTAT versions and all the masked ROM versions that
have different ROM size.
Rev. 6.00 Mar 18, 2005 page 653 of 970
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Section 19 H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version,
Masked ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]
Rev. 6.00 Mar 18, 2005 page 654 of 970
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Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
20.1
Overview
The H8/3062 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ)
and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides
the clock frequency to generate the system clock (φ). The system clock is output at the φ pin*1 and
furnished as a master clock to prescalers that supply clock signals to the on-chip supporting
modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency
divider by settings in a division control register (DIVCR)*2. Power consumption in the chip is
reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 21.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where, EXTAL : Frequency of crystal resonator or external clock signal
n
: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Rev. 6.00 Mar 18, 2005 page 655 of 970
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Section 20 Clock Pulse Generator
20.1.1
Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
CPG
XTAL
Oscillator
EXTAL
Duty
adjustment
circuit
Frequency
divider
φ
Prescalers
Division
control
register
Data bus
φ pin
φ/2 to φ/4096
Figure 20.1 Block Diagram of Clock Pulse Generator
20.2
Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
20.2.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 20.2.
Damping resistance Rd should be selected according to table 20.1 (1), and external capacitances
CL1 and CL2 according to table 20.1 (2). An AT-cut parallel-resonance crystal should be used.
CL1
EXTAL
XTAL
Rd
CL2
Figure 20.2 Connection of Crystal Resonator (Example)
Rev. 6.00 Mar 18, 2005 page 656 of 970
REJ09B0215-0600
Section 20 Clock Pulse Generator
If a crystal resonator with a frequency higher than 20 MHz is connected, the external load
capacitance values in table 20.1 (2) should not exceed 10 [pF]. Also, in order to improve the
accuracy of the oscillation frequency, a thorough study of oscillation matching evaluation, etc.,
should be carried out when deciding the circuit constants.
Table 20.1 (1)
Damping Resistance Value
Frequency f (MHz)
Damping
Resistance
Value
2
Rd (Ω)
1k
2 < f ≤ 4 4 < f ≤8 8 < f ≤ 10 10 < f ≤ 13 13 < f ≤ 16 16 < f ≤ 18 18 < f ≤ 25
500
200
0
0
0
0
0
Note: A crystal resonator between 2 MHz and 25 MHz can be used. If the chip is to be operated
at less than 2 MHz, the on-chip frequency divider should be used (A crystal resonator of
less than 2 MHz cannot be used).
Table 20.1 (2)
External Capacitance Values
External Capacitance Value
Frequency f (MHz)
CL1 = CL2 (pF)
5 V Version
Low-Voltage Version
20 < f ≤ 25
2 ≤ f ≤ 20
2 ≤ f ≤ 13
10
10 to 22
10 to 22
Note: * Conditions for the H8/3064F-ZTAT B-mask version and H8/3062F-ZTAT B-mask version.
Crystal Resonator: Figure 20.3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 20.2.
CL
L
Rs
XTAL
EXTAL
C0
AT-cut parallel-resonance type
Figure 20.3 Crystal Resonator Equivalent Circuit
Rev. 6.00 Mar 18, 2005 page 657 of 970
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Section 20 Clock Pulse Generator
Table 20.2 Crystal Resonator Parameters
Frequency (MHz)
Rs max (Ω
Ω)
2
4
8
10
12
16
18
20
25
500
120
80
70
60
50
40
40
40
Co (pF)
7 pF max
Use a crystal resonator with a frequency equal to the system clock frequency (φ).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 20.4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
Avoid
Signal A
CL2
Signal B
H8/3062 Group
XTAL
EXTAL
CL1
Figure 20.4 Oscillator Circuit Block Board Design Precautions
Rev. 6.00 Mar 18, 2005 page 658 of 970
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Section 20 Clock Pulse Generator
20.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
20.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray
capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in
configuration b instead, and hold the external clock high in standby mode.
External clock input
EXTAL
XTAL
Open
a. XTAL pin left open
External clock input
EXTAL
XTAL
b. Complementary clock input at XTAL pin
Figure 20.5 External Clock Input (Examples)
Rev. 6.00 Mar 18, 2005 page 659 of 970
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Section 20 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 20.3 shows the clock timing, figure 20.6
shows the external clock input timing, and figure 20.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (tDEXT) has passed after the clock input. The system
must remain reset with the reset signal low during tDEXT, while the clock output is unstable.
Table 20.3 (1)
Clock Timing for On-Chip Flash Memory Versions
VCC = 3.0 V
to 5.5 V
VCC = 5.0 V
± 10%
Item
Symbol Min
Max
Min
External clock input low
pulse width
tEXL
30
—
30
External clock input high tEXH
pulse width
External clock rise time
tEXr
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
Unit
Test Conditions
tcyc / 2 - 5 —
ns
φ > 8 MHz
—
55
—
ns
φ ≤ 8 MHz
30
—
tcyc / 2 - 5 —
ns
φ > 8 MHz
30
—
55
—
ns
φ ≤ 8 MHz
—
8
—
5
ns
tEXf
—
8
—
5
ns
tCL
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
80
—
ns
φ < 5 MHz
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
80
—
ns
φ < 5 MHz
500
—
500
—
µs
Figure 20.7
tCH
tDEXT*
Max
Note: * tDEXT includes a RES pulse width (tRESW ). tRESW = 20 tcyc
Rev. 6.00 Mar 18, 2005 page 660 of 970
REJ09B0215-0600
Figure
20.6
Figure
22.17
Section 20 Clock Pulse Generator
Table 20.3 (2)
Clock Timing for On-Chip Masked ROM Versions
VCC = 2.7 V
to 5.5 V
VCC = 3.0 V
to 5.5 V
VCC = 5.0 V
± 10%
Item
Symbol Min
Max
Min
Max
Min
External clock
input low pulse
width
tEXL
40
—
30
—
tcyc / 2 - 5 —
ns
40
—
30
—
55
—
ns
φ > 8 MHz Figure
φ ≤ 8 MHz 20.6
External clock
input high pulse
width
tEXH
40
—
30
—
tcyc / 2 - 5 —
ns
φ > 8 MHz
40
—
30
—
55
—
ns
φ ≤ 8 MHz
External clock
rise time
tEXr
—
10
—
8
—
5
ns
External clock
fall time
tEXf
—
10
—
8
—
5
ns
Clock low pulse
width
tCL
0.4
0.6
0.4
0.6
0.4
0.6
tcyc
80
—
80
—
80
—
ns
φ ≥ 5 MHz Figure
φ < 5 MHz 22.17
0.4
0.6
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
80
—
80
—
ns
φ < 5 MHz
500
—
500
—
500
—
µs
Figure 20.7
Clock high pulse tCH
width
External clock
output settling
delay time
tDEXT*
Max Unit Test Conditions
Note: * tDEXT includes the RES pulse width (tRESW ). tRESW = 10 tcyc
tEXH
tEXL
VCC × 0.7
EXTAL
VCC × 0.5
0.3 V
tEXr
tEXf
Figure 20.6 External Clock Input Timing
Rev. 6.00 Mar 18, 2005 page 661 of 970
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Section 20 Clock Pulse Generator
VCC
STBY
VIH
EXTAL
φ (internal or
external)
RES
tDEXT
Figure 20.7 External Clock Output Settling Delay Timing
20.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
20.4
Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
20.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
Rev. 6.00 Mar 18, 2005 page 662 of 970
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Section 20 Clock Pulse Generator
20.5.1
Register Configuration
Table 20.4 summarizes the frequency division register.
Table 20.4 Frequency Division Register
Address*
Name
Abbreviation
R/W
Initial Value
H'EE01B
Division control register
DIVCR
R/W
H'FC
Note: * Lower 20 bits of the address in advanced mode.
20.5.2
Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DIV1
DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
R/W
R/W
Reserved bits
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1
Bit 0
DIV0
Frequency Division Ratio
0
0
1/1
0
1
1/2
1
0
1/4
1
1
1/8
(Initial value)
Rev. 6.00 Mar 18, 2005 page 663 of 970
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Section 20 Clock Pulse Generator
20.5.3
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in the AC electrical characteristics. Note that φmin = lower limit of the
operating frequency range. Ensure that φ is not below this lower limit.
Table 20.5 shows the operating frequency ranges of the various models in the H8/3062 Group.
Table 20.5 Comparison of H8/3062 Group Operating Frequency Ranges
H8/3062
F-ZTAT
R-Mask
Version
Guaranteed 4.5 to 5.5 V
operating
frequency
3.0 to 5.5 V
range
2.7 to 5.5 V
Crystal oscillation range
H8/3062
F-ZTAT
B-Mask
Version
H8/3062
Masked
ROM
Version
H8/3061
Masked
ROM
Version
H8/3060
Masked
ROM
Version
H8/3064 FZTAT
B-Mask
Version
1M to 20 MHz
2M to
25 MHz
1M to 20 MHz
2M to
25 MHz
1M to
13 MHz
—
1M to 13 MHz
—
1M to 10 MHz
—
2M to 20 MHz
2M to
25 MHz
—
2M to 20 MHz
2M to
25 MHz
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 21.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Rev. 6.00 Mar 18, 2005 page 664 of 970
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Section 21 Power-Down State
Section 21 Power-Down State
21.1
Overview
The H8/3062 Group has a power-down state that greatly reduces power consumption by halting
the CPU, and a module standby function that reduces power consumption by selectively halting
on-chip modules.
The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, and A/D
converter.
Table 21.1 indicates the methods of entering and exiting the power-down modes and module
standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.
Rev. 6.00 Mar 18, 2005 page 665 of 970
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Halted
and
reset
Halted
and
reset
Halted*1 Halted*1 Halted*1 Halted*1 Halted*1 Active
and
and
and
and
and
reset
reset
reset
reset
reset
Undetermined
—
Halted
Active
Active
Corresponding
bit set to 1 in
MSTCRH and
MSTCRL
Module
standby
Rev. 6.00 Mar 18, 2005 page 666 of 970
REJ09B0215-0600
Halted
and
reset
Halted
and
reset
Halted
and
reset
—
• NMI
• IRQ0 to IRQ2
• RES
• STBY
• Interrupt
• RES
• STBY
Exiting
Conditions
—
High
impedance*1
• STBY
• RES
• Clear MSTCR
bit to 0*4
• STBY
High
impedance • RES
Held
Held
φ output
High
output
I/O
Ports
φ clock
Output*3
Held*2 High
impedance
Held
Held
RAM
Legend:
SYSCR
SSBY
MSTCRH
MSTCRL
:
:
:
:
System control register
Software standby bit
Module standby control register H
Module standby control register L
Notes: 1. State in which the corresponding MSTCR bit was set to 1. For details see section 21.2.2, Module Standby Control Register H (MSTCRH) and section
21.2.3, Module Standby Control Register L (MSTCRL).
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
3. When P67 is used as the φ output pin.
4. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR
bit to 0, then set up the module registers again.
Halted
and
reset
Halted
and
reset
Halted
Halted
and
reset
Low input at
STBY pin
Halted
and
reset
Hardware
standby
mode
Halted
and
reset
Halted
and
reset
Halted
and
reset
Held
Halted
Active
Halted
Active
SLEEP instruction executed
while SSBY = 1
in SYSCR
Active
Software
standby
mode
Active
Active
Other
Modules
Active
A/D
Held
SCI1
Halted
SCI0
Active
CPU
Clock
State
SLEEP instruction executed
while SSBY = 0
in SYSCR
8-Bit
Timer
16-Bit
Timer
CPU
Registers
Sleep
mode
Mode
Entering
Conditions
Section 21 Power-Down State
Table 21.1 Power-Down State and Module Standby Function
Section 21 Power-Down State
21.2
Register Configuration
The H8/3062 Group has a system control register (SYSCR) that controls the power-down state,
and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module
standby function. Table 21.2 summarizes these registers.
Table 21.2 Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'EE012
System control register
SYSCR
R/W
H'09
H'EE01C
Module standby control register H
MSTCRH
R/W
H'78
H'EE01D
Module standby control register L
MSTCRL
R/W
H'00
Note: * Lower 20 bits of the address in advanced mode
21.2.1
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Software standby
output port enable
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time of the CPU
and peripheral functions
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1
(SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3,
System Control Register (SYSCR).
Rev. 6.00 Mar 18, 2005 page 667 of 970
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Section 21 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an extern
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