MP38671 10A, 25V, 600KHz Step-Down Converter with Synchronizable Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP38671 is a monolithic step-down switch mode converter with a built in internal power MOSFET. It achieves 10A continuous output current over a wide input supply range with excellent load and line regulation. • • • • • Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP38671 requires a minimum number of readily available standard external components and is available in a space saving 3 x4mm 14-pin QFN package. • • • • • • • Wide 4.5V to 25V Operating Input Range 10A Continuous Output Current 60mΩ Internal Power MOSFET Switch Power Good Indicator Synchronous Gate Driver Delivers up to 95% Efficiency Fixed 600KHz Frequency Synchronizable to >1MHz External Clock Cycle-by-Cycle Over Current Protection Thermal Shutdown Output Adjustable from 0.8V to 15V Stable with Low ESR Output Ceramic Capacitor Available in a 3x4mm 14-Pin QFN Package APPLICATIONS • • • • • Point of Load Regulator in Distributed Power System Digital Set Top Boxes Personal Video Recorders Broadband Communications Flat Panel Television and Monitors For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 4, 5, 6 12 IN BST SW VCC 11 8, 9, 10 95 90 MP38671 2 100 PG BG EN/SYNC GND FB 13 85 80 OFF ON 3 14 MP38671 Rev. 1.1 9/21/2011 1 75 70 0 2 4 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 6 8 10 1 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ORDERING INFORMATION Part Number* MP38671DL Package 3x4 QFN14 Top Marking Free Air Temperature (TA) 3867 -40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP38671DL–Z); For RoHS Compliant Packaging, add suffix –LF (e.g. MP MP38671DL–LF–Z) PACKAGE REFERENCE TOP VIEW FB 1 14 GND PG 2 13 BG EN/SYNC 3 12 VCC IN 4 11 BST IN 5 10 SW IN 6 9 SW N/C 7 8 SW EXPOSED PAD ON BACKSIDE CONNECT TO GND ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VIN...................................... 28V VSW..................... -0.3V (-5V for < 10ns) to 29V VBS..................................................................... All Other Pins .................................–0.3V to +6V Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature.............. –65°C to +150°C Recommended Operating Conditions (3) Supply Voltage VIN..........................4.5V to 25V Output Voltage VOUT ......................0.8V to 15V Maximum Junction Temp. (TJ) ................+125°C MP38671 Rev. 1.1 9/21/2011 Thermal Resistance (4) θJA θJC 3x4 QFN14 .............................. 48....... 11.... °C/W Notes: VSW + 6V 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD5 1-7, 4-layer PCB.. The exposed pad must be thermally connected to a ground plane (or most negative supply plane in split-supply applications). www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 2 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameters Feedback Voltage Feedback Current Switch On Resistance (5) Switch Leakage Current Limit (5) Oscillator Frequency Fold-back Frequency Maximum Duty Cycle Minimum On Time (5) Under Voltage Lockout Threshold Rising Under Voltage Lockout Threshold Hysteresis EN Input Low Voltage En Input High Voltage Symbol Condition VFB 4.5V ≤ VIN ≤ 25V IFB VFB = 0.8V RDS(ON) VEN = 0V, VSW = 0V fSW 400 85 tON 3.9 Typ 0.808 10 60 0 12 600 150 90 100 4.1 880 Max 0.828 10 800 4.3 0.4 1.2 VEN = 2V VEN = 0V VEN = 0V VEN = 2V, VFB = 1V EN Input Current Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown BG Driver Bias Supply Voltage Gate Driver Sink Impedance (5) Gate Driver Source Impedance (5) Gate Drive Current Sense Trip Threshold Power Good Threshold Power Good Threshold Hysteresis PG Pin Level Soft Start Time VFB = 0.6V VFB = 0V VFB = 0.6V Min 0.788 VCC RSINK RSOURCE VSW 2 0 0 4.5 0.69 VPG TSS 150 5 1 4 20 0.74 40 PG Sink 4mA 1 1.5 Units V nA mΩ μA A KHz KHz % ns V mV V V μA 10 1.1 0.79 0.4 5 μA mA °C V Ω Ω mV V mV V ms Notes: 5) Guaranteed by design. MP38671 Rev. 1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 3 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER PIN FUNCTIONS Pin # 1 2 3 4, 5, 6 7 8, 9, 10 11 12 13 14 Name Description Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage. To prevent current limit run away during a short circuit fault condition FB the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 250mV. Power Good Indicator. Connect this pin to VCC or VOUT by a 100kΩ pull-up resistor. The output of this pin is low if the output voltage is 10% less than the nominal voltage, PG otherwise it is an open drain. EN/SYNC On/Off Control and External Frequency Synchronization Input. Supply Voltage. The MP38671 operates from a +4.5V to +25V unregulated input. C1 is IN needed to prevent large voltage spikes from appearing at the input. N/C No Connect. SW Switch Output. Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply BST voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver. VCC BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor. BG Gate Driver Output. Connect this pin to the synchronous MOSFET Gate. Ground. This pin is the voltage reference for the regulated output voltage. For this reason GND, care must be taken in its layout. This node should be placed outside of the M2 to C1 Exposed ground path to prevent switching current spikes from inducing voltage noise into the part. pad The exposed pad and GND pin must be connected to the same ground plane. MP38671 Rev. 1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 4 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, TA = +26ºC, unless otherwise noted. 5.5 3.5 3.0 5.0 2.0 1.5 1.0 VCC (V) 2.5 4.5 4.0 0.5 0 MP38671 Rev. 1.1 9/21/2011 3.5 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 5 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, TA = +26ºC, unless otherwise noted. Latch Off with Output Short Circuit VOUT 2V/div VSW 10V/div IINDUCTOR 5A/div Power Up Power Up No Load Full Load VIN 2V/div VSW 10V/div VIN 2V/div VSW 10V/div VOUT 5V/div VOUT 5V/div IINDUCTOR 5A/div IINDUCTOR 5A/div 2ms/div 2ms/div Enable Startup Enable Startup Input Ripple Voltage No Load Full Load IOUT=10A VOUT 2V/div VOUT 2V/div VSW 10V/div VSW 10V/div VEN 10V/div VEN 10V/div IINDUCTOR 10A/div IINDUCTOR 10A/div 1ms/div VSW 10V/div 1ms/div Output Ripple Voltage 400ns/div Load Transient Response IOUT=10A VOUT 20mV/div VIN 200mV/div VOUT 100mV/div VSW 10V/div IINDUCTOR 10A/div MP38671 Rev. 1.1 9/21/2011 IINDUCTOR 5A/div www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 6 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER OPERATION IN CURRENT SENSE AMPLIFIER D + -- x40 REGULATOR BST EN/SYNC REGULATOR OSCILLATOR 600KHz S + -- DRIVER R CURRENT LIMIT COMPARATOR VCC Q R Q VCC SW VCC REFERENCE VBG FB DRIVER + -- ERROR AMPLIFIER BG + -- PWM COMPARATOR PG VBG POWER GOOD GND Figure 1—Functional Block Diagram The MP38671 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power MOSFET and a gate driver for a low-side external MOSFET. It achieves 10A continuous output current over a wide input supply range with excellent load and line regulation. It provides a single highly efficient solution with current mode control for fast loop response and easy compensation. The MP38671 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. MP38671 Rev. 1.1 9/21/2011 Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.8V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases. Since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external MOSFET selection, a 1uF ceramic capacitor for decoupling purpose is required. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 7 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER Enable/Synch Control The MP38671 has a dedicated Enable/Synch control pin (EN/SYNC). By pulling it high or low, the IC can be enabled and disabled by EN. Tie EN to VIN for automatic start up. To disable the part, EN must be pulled low for at least 5µs. The MP38671 can be synchronized to external clock range from 300KHz up to 1.4MHz through the EN/SYNC pin. The internal clock rising edge is synchronized to the external clock rising edge. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP38671 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.0V while its falling threshold is a consistent 3.2V. Internal Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V to 1.2V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. Over-Current-Protection (OCP) The MP38671 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 30% below the reference. Once a output UV is triggered, the MP38671 enters latch off mode. Mode is especially useful to ensure system safety under fault condition. The MP38671 exits the latch off mode once the EN or input power is re-cycled. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150°C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 140°C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally (Figure 2). Even at no load condition, as long as VIN is 3V higher than VOUT, C4 will have enough voltage provided by VIN through M2, M1, C4, L1 and C2. If (VIN-VSW) is more than 5V, U2 will regulate M1 to maintain a 5V BST voltage across C4. D1 VIN M1 + 5V + -- BST U2 -- C4 VOUT SW L1 C2 Figure 2—Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Four events can shut down the chip: OCP, EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. MP38671 Rev. 1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 8 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see the schematic on front page). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 to be around 40.2kΩ for optimal transient response. R2 is then given by: R2 = R1 VOUT −1 0 .8 V VOUT (V) R1 (kΩ) R2 (kΩ) 1.2 1.8 2.5 40.2 (1%) 40.2 (1%) 40.2 (1%) 80.6 (1%) 32.4 (1%) 19.1 (1%) Selecting the Inductor A 1µH to 10µH inductor with a DC current rating of at least 25% higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 10mΩ. For most designs, the inductance value can be derived from the following equation. VOUT × (VIN − VOUT ) VIN × ΔIL × fOSC Where ΔIL is the inductor ripple current. Choose inductor ripple current to be approximately 30% of the maximum load current, 10A. The maximum inductor peak current is: IL(MAX ) = ILOAD + ΔI L 2 Under light load conditions below 100mA, larger inductance is recommended for improving efficiency. MP38671 Rev. 1.1 9/21/2011 Table 2 lists example synchronous MOSFETs and manufacturers. Table 2—Synchronous MOSFET Selection Guide Table 1—Resistor Selection for Common Output Voltages L1 = Synchronous MOSFET The external synchronous MOSFET is used to freewheel the inductor current when the internal high-side switch is off. It reduces the power loss significantly compared against a Schottky rectifier. Part No. Si7114 HAT2165 Manufacture Vishay Renesas Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22µF capacitor is sufficient. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛⎜ VOUT × 1− VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worse case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD 2 For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 9 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ΔVIN = ⎛ ILOAD V V × OUT × ⎜1 − OUT fS × C1 VIN ⎜⎝ VIN ⎞ ⎟⎟ ⎠ Selecting the Output Capacitor The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ΔVOUT = VOUT ⎛ V × ⎜ 1 − OUT fS × L1 ⎝ VIN ⎞ ⎞ ⎛ 1 ⎟ ⎟ × ⎜ RESR + 8 × fS × C2 ⎠ ⎠ ⎝ Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT ⎛ ⎞ V = × ⎜ 1 − OUT ⎟ 2 VIN ⎠ 8 × fS × L1× C2 ⎝ VOUT In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT ⎛ V × ⎜ 1 − OUT fS × L1 ⎝ VIN ⎞ ⎟ × RESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP38671 can be optimized for a wide range of capacitance and ESR values. PCB Layout The high current paths (GND, IN and SW) should be placed very close to the device with short, direct and wide traces. The input capacitor needs to be as close as possible to the IN and GND pins. The external feedback resistors should be placed next to the FB pin. Keep the switching node SW short and away from the feedback network. External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external BST diode are: z VOUT=5V or 3.3V; and z Duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Figure 3 External BST Diode IN4148 BST MP38671 SW CBST L + COUT 5V or 3.3V Figure 3—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. MP38671 Rev. 1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 10 MP38671 – 10A, 25V, 600KHz STEP-DOWN WITH SYNCHRONOUS GATE DRIVER PACKAGE INFORMATION 3mm x 4mm QFN14 2.90 3.10 1.60 1.80 0.30 0.50 PIN 1 ID MARKING PIN 1 ID SEE DETAIL A 1 14 0.18 0.30 3.20 3.40 3.90 4.10 PIN 1 ID INDEX AREA 0.50 BSC 8 TOP VIEW 7 BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A 2.90 0.70 NOTE: 1.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE. 0.25 3.30 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP38671 Rev. 1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 11