Allegro A6217KLJTR-1-T Automotive-grade, constant-current pwm dimmable buck regulator led driver Datasheet

A6217 and A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
FEATURES AND BENEFITS
DESCRIPTION
• AEC-Q100 qualified
• 6 to 48 V supply voltage
• True average output current control
• 3 A maximum output over operating temperature range
(1.5 A for A6217-1)
• Cycle-by-cycle current limit
• Integrated MOSFET switch
• Enable / PWM dimming via direct logic input or power
supply voltage
• Internal control loop compensation
• Undervoltage lockout (UVLO) and thermal shutdown
protection
• Low power shutdown (1 µA typical)
• Robust protection against:
▫ Adjacent pin-to-pin short
▫ Pin-to-GND short
▫ Component open/short faults
• Enhancements over A6213:
▫ Dithering of switching frequency to reduce EMI
▫ Able to drive single white LED from 18 V supply at 2.2 MHz
▫ Smaller package option
The A6217 is a single IC switching regulator that provides
constant-current output to drive high-power LEDs. It integrates
a high-side N-channel DMOS switch for DC-to-DC step- down
(buck) conversion. A true average current is output using a
cycle-by-cycle, controlled on-time method.
PACKAGES:
10-pin DFN with
wettable flank
(suffix EJ)
Not to scale
Output current is user-selectable by an external current sense
resistor. Output voltage is automatically adjusted to drive
various numbers of LEDs in a single string. This ensures the
optimal system efficiency.
LED dimming is accomplished by a direct logic input pulsewidth-modulation (PWM) signal at the enable pin.
The device is provided in a 3 mm × 3 mm wettable flank 10-pin
DFN (suffix EJ) or an 8-pin narrow SOIC (suffix LJ), both with
exposed pad for enhanced thermal dissipation. Both packages
are lead (Pb) free, with 100% matte-tin leadframe plating.
APPLICATIONS:
Automotive lighting
• Daytime running lights
• Front and rear fog lights
• Turn/stop lights
• Map light
• Dimmable interior lights
8-pin SOICN
(suffix LJ)
TYPICAL APPLICATION CIRCUIT
VIN (6 to 48 V)
GND
C1
Enable/PWM Dimming
(100 Hz to 2 kHz)
A6217
1, 2
9,10
SW
VIN
(EJ)
R1 3
8 C4
TON
BOOT
4
7
EN
PAD GND
5
VCC 6
CS
LED+
D1
...
EN
L1
C5
LED–
RSENSE
A6217-DS
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
SELECTION GUIDE
Maximum Output
Current (A)
Part Number
A6217KEJTR-J
A6217KEJTR-1-J
Packing
3
Wettable flank 10-pin DFN with exposed thermal pad
Contact Factory
1.5
Wettable flank 10-pin DFN with exposed thermal pad
Contact Factory
3
8-pin SOICN with exposed thermal pad
3000 pieces per 13-in. reel
1.5
8-pin SOICN with exposed thermal pad
3000 pieces per 13-in. reel
A6217KLJTR-T
A6217KLJTR-1-T
Package
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Supply Voltage
Notes
VIN
Bootstrap Drive Voltage
Rating
Unit
–0.3 to 50
V
VBOOT
–0.3 to VIN + 8
V
Switching Voltage
VSW
–1.5 to VIN + 0.3
V
Linear Regulator Terminal
VCC
–0.3 to 7
V
Enable and TON Voltage
VEN , VTON
–0.3 to VIN + 0.3
V
VCS
–0.3 to 7
V
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Current Sense Voltage
Maximum Junction Temperature
Storage Temperature
VCC to GND
THERMAL CHARACTERISTICS*: May require derating at maximum conditions; see application section for optimization
Characteristic
Symbol
Package Thermal Resistance
(Junction to Ambient)
RθJA
Package Thermal Resistance
(Junction to Pad)
RθJP
Value
Unit
DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard
Test Conditions*
45
ºC/W
SOICN-8 (LJ) package on 4-layer PCB based on JEDEC standard
35
ºC/W
2
ºC/W
*Additional thermal information available on the Allegro™ website.
Pinout Diagrams
Terminal List Table
Number
VIN
1
Function
EJ
LJ
9
SW
1, 2
1
VIN
Supply voltage input terminals
8
BOOT
3
2
TON
Regulator on-time setting resistor terminal;
determines the switching frequency of the converter
4
3
EN
Input for Enable and PWM dimming; rated up to
VIN and logic-level compatible
5
4
CS
Drive output current sense feedback
6
5
VCC
Internal linear regulator output; add filter capacitor
of 0.1 µF from this pin to GND
7
6
GND
Ground terminal
8
7
BOOT
DMOS gate driver bootstrap terminal
9, 10
8
SW
Switched output terminals
–
–
PAD
Exposed pad for enhanced thermal dissipation;
connect to GND
VIN
2
TON
3
EN
4
7
GND
CS
5
6
VCC
PAD
Name
10 SW
Package EJ Pinouts
VIN 1
8
SW
TON 2
7
BOOT
EN 3
6
GND
CS 4
5
VCC
PAD
Package LJ Pinouts
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
FUNCTIONAL BLOCK DIAGRAM
CVCC
CBOOT
VCC
VIN
VIN
BOOT
L1
LED String
D1
SW
VREG 5.3 V
VCC
UVLO
~VOUT
On-Time
Current
Generator
TON
Average
On-Time
Timer
Off-Time
Timer
Gate Drive
UVLO
Shutdown
RON
Dithering
(±5%)
Level Shift
EN
+
IC and Driver
Control Logic
CCOMP
0.2 V
Current Limit
Off-Time
Timer
–
–
Buck Switch
Current Sense
+
VIL = 0.4 V
VIH = 1.8 V
+
+
VCC UVLO
–
–
Thermal
Shutdown
ILIM
CS
PAD
GND
RSENSE
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
ELECTRICAL CHARACTERISTICS: Valid at VIN = 12 V, TJ = –40°C to 125°C, typical values at TJ = 25°C, unless otherwise noted
Characteristics
Input Supply Voltage
Symbol
Test Conditions
VIN
Min.
Typ.
Max.
Unit
6
–
48
V
VIN Undervoltage Lockout Threshold
VUVLO
VIN increasing
–
5.3
–
V
VIN Undervoltage Lockout Hysteresis
VUVLO_HYS
VIN decreasing
–
150
–
mV
VIN Pin Supply Current
IIN
VCS = 0.5 V, EN = High
–
2.5
–
mA
VIN Pin Standby Current
IINSB
VCS = 0.5 V, EN = high to low, within 10 ms
–
1
–
mA
VIN Pin Shutdown Current
IINSD
EN shorted to GND
Buck Switch Current Limit Threshold
ISWLIM
Buck Switch On-Resistance
RDS(on)
–
1
10
µA
A6217
3.0
4.0
5.0
A
A6217-1
1.9
2.2
2.7
A
–
0.25
0.4
Ω
VBOOT = VIN + 4.3 V, TA = 25°C, ISW = 1 A
BOOT Undervoltage Lockout Threshold
VBOOTUV
VBOOT to VSW increasing
2.7
3.5
4.3
V
BOOT Undervoltage Lockout Hysteresis
VBOTUVHYS
VBOOT to VSW decreasing
–
370
–
mV
VCS = 0 V
–
110
150
ns
Switching Minimum Off-Time
tOFFmin
Switching Minimum On-Time
tONmin
Selected On-Time
tON
VIN = 12 V, VOUT = 6 V, RON = 31.6 kΩ
–
75
100
ns
200
250
300
ns
Oscillator Frequency Dithering Range
fSW_DITH
RON = 31.6 kΩ
–
±5
–
%
Dithering Modulation Frequency
fSW_MOD
RON = 31.6 kΩ
–
11
–
kHz
187.5
200
210
mV
–
0.9
–
µA
5.1
5.4
5.7
V
5
20
–
mA
–
–
V
REGULATION COMPARATOR AND ERROR AMPLIFIER
Load Current Sense Regulation
Threshold [1]
VCSREG
VCS decreasing, SW turns on
Load Current Sense Bias Current
ICSBIAS
VCS = 0.2 V, EN = low
INTERNAL LINEAR REGULATOR
VCC Regulated Output
VCC Current Limit [2]
VCC
ICCLIM
0 mA < ICC < 5 mA, VIN > 6 V
VCC = 0 V
ENABLE INPUT
Logic High Voltage
Logic Low Voltage
VIH
VEN increasing
1.8
VIL
VEN decreasing
–
–
0.4
V
EN Pin Pull-Down Resistance
RENPD
VEN = 5 V
–
100
–
kΩ
Maximum PWM Dimming Off-Time
tPWML
Measured while EN = low, during dimming
control, and internal references are
powered on
(exceeding tPWML results in shutdown)
12
20
–
ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TSD
–
165
–
°C
Thermal Shutdown Hysteresis
TSDHYS
–
25
–
°C
In test mode, a ramp signal is applied at CS pin to determine the CS pin regulation threshold voltage. In actual application, the average CS pin
voltage is regulated at VCSREG regardless of ripple voltage.
2 The internal linear regulator is not designed to drive an external load
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
CHARACTERISTIC PERFORMANCE
C1,C2
C3
C4
Panel 1B. VIN = 12 V
Panel 1A. VIN = 7 V
Panel 1C. VIN = 18 V
Figure 1: Startup waveforms from off-state at various input voltages. Note that there is a fixed startup delay of ~70 µs before switching
starts. Subsequent rise time of the LED current depends on input/output voltages, inductor value, and switching frequency.
• Operating conditions: LED voltage = 3.5 V, LED current = 1.5 A, R1 = 73.2 kΩ (frequency = 1 MHz in steady state), L1 = 15 µH,
VIN = 7 V (panel 1A), 12 V (panel 1B), and 18 V (panel 1C)
• Oscilloscope settings: CH1 (Red) = VIN (5 V/div), CH2 (Blue) = VSW (5 V/div),
CH3 (Green) = iLED (500 mA/div), CH4 (Yellow) = Enable (5 V/div), time scale = 20 µs/div
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
C1,C2
C3
C4
Panel 2A. Duty cycle = 50% and time scale = 1 ms/div
Panel 2B. Duty cycle = 2% and time scale = 50 µs/div
Figure 2: PWM operation at various duty cycles; note that there is no startup delay during PWM dimming operation
• Operating conditions: PWM dimming at 200 Hz, VIN = 12 V, VOUT = 7 V, R1 = 73.2 kΩ, duty cycle = 50% (panel 2A) and 2% (panel 2B)
• CH1 (Red) = VIN (5 V/div), CH2 (Blue) = VOUT (5 V/div),
CH3 (Green) = iLED (500 mA/div), CH4 (Yellow) = Enable (5 V/div), time scale = 1 ms/div (panel 2A) and 50 µs/div (panel 2B)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
95
95
VIN = 24 V, VOUT = 15 V
VIN = 12 V, VOUT = 5.5 V
85
VIN = 12 V, VOUT = 3.5 V
80
fSW = 500 kHz
90
Efficiency, η (%)
Efficiency, η (%)
90
75
fSW = 1 MHz
85
fSW = 2 MHz
80
75
70
70
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
LED Current, iLED (A)
1.0
1.5
2.0
2.5
3.0
LED Current, iLED (A)
Figure 3: Efficiency versus LED Current at various LED voltages
Operating conditions: fSW = 1 MHz
Figure 4: Efficiency versus LED Current at various switching
frequencies. Operating conditions: VIN = 12 V, VOUT = 5.5 V
Normalize LED Current
1
0.1
0.01
VIN = 24 V, load = 2× LED
VIN = 12 V, load = 1× LED
VIN = 12 V, load = 2× LED
Ideal
0.001
0.1
1
10
PWM Dimming Duty Cycle (%)
100
Figure 5. Average LED Current versus PWM dimming percentage
Operating conditions: VIN = 12 or 24 V, VOUT = 3.7 V (1× LED) or 7 V (2× LED),
iLED = 1.5 A, RON = 73.2 kΩ, fSW = 1 MHz, L = 15 µH
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
FUNCTIONAL DESCRIPTION
The A6217 is a buck regulator designed for driving a high-current
LED string. It uses average current mode control to maintain
constant LED current and consistent brightness. The LED current
level is easily programmable by selection of an external sense
resistor, with a value determined as follows:
iLED = VCSREG / RSENSE
Switching Frequency
The A6217 operates in fixed on-time mode during switching. The
on-time (and hence switching frequency) is programmed using
an external resistor connected between the VIN and TON pins, as
given by the following equations:
tON = k × (RON + RINT ) × ( VOUT / VIN )
where VCSREG = 0.2 V typical.
fSW = 1 / [ k × (RON + RINT )] + c
where k = 0.014 and c = 0.09, with fSW in MHz, tON in µs, and
RON and RINT (internal resistance, 6 kΩ) in kΩ (see figure 6).
2.2
2.0
To minimize the peaks of switching frequency harmonics in EMC
measurement, a dithering feature is implemented. The dithering
range is internally set at ±5%. The actual switching frequency is
swept linearly between 0.95 × fSW and 1.05 × fSW, where fSW is
the programmed switching frequency. The rate of modulation for
fSW is fixed internally at ~11 kHz.
1.8
1.6
fSW (MHz)
1.4
1.2
1.0
Enable and Dimming
The IC is activated when a logic high signal is applied to the EN
(enable) pin. The buck converter ramps up the LED current to a
target level set by RSENSE.
0.8
0.6
0.4
0.2
0.0
0
20
40
60
80
100 120 140 160 180 200 220 240 260 280 300 320
RON (kΩ)
Figure 6: Average Switching Frequency versus RON Resistance
(VIN = 12 V, VOUT = ~7 V, iLED = 1 A)
• During SW on-time:
iRIPPLE = [(VIN – VOUT) / L] × tON = [(VIN – VOUT) / L] × tSW × D
where D = tON / tSW.
• During SW off-time:
iRIPPLE = [(VOUT – VD) / L] × tOFF = [(VOUT – VD) / L] × tSW × (1 – D)
Therefore (simplified equation for Output Voltage):
VOUT = VIN × D – VD × (1 – D)
If VD << VOUT , then VOUT ≈ VIN × D.
More precisely:
VOUT = (VIN – iav × RDS(on) ) × D – VD × (1 – D) – RL × iav
Where RL is the resistance fo the inductor.
CIN
VSW
VIN
0
–VD
t
iL
A6217
VIN
When the EN pin is forced from high to low, the buck converter
is turned off, but the IC remains in standby mode for up to 12 ms.
If EN goes high again within this period, the LED current is
turned on immediately. Active dimming of the LED is achieved
by sending a PWM (pulse-width modulation) signal to the EN
pin. The resulting LED brightness is proportional to the duty cycle
( tON / Period ) of the PWM signal. A practical range for PWM dim-
i(max)
MOS
SW
D
L
VOUT
iL
RSENSE
iRIPPLE
iav
i(min)
tON
tOFF
t
tSW
Figure 7: Simplified Buck Controller Equations
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
ming frequency is between 100 Hz (Period = 10 ms) and 2 kHz.
At a 200 Hz PWM frequency, the dimming duty cycle can be
varied from 100% down to 1% or lower.
If EN is low for more than 20 ms, the IC enters shutdown mode
to reduce power consumption. The next high signal on EN will
initialize a full startup sequence, which includes a startup delay
of approximately 70 µs. This startup delay is not present during
PWM operation.
The EN pin is high-voltage tolerant and can be directly connected
to a power supply. However, if EN is higher than the VIN voltage
at any time, a series resistor (1 kΩ) is required to limit the current
flowing into the EN pin. This series resistor is not necessary if
EN is driven from a logic input.
PWM Dimming Ratio
The brightness of the LED string can be reduced by adjusting the
PWM duty cycle at the EN pin as follows:
Dimming ratio = PWM on-time / PWM period
For example, by selecting a PWM period of 5 ms (200 Hz PWM
frequency) and a PWM on-time of 50 µs, a dimming ratio of 1%
can be achieved.
In an actual application, the minimum dimming ratio is determined by various system parameters, including: VIN , VOUT ,
inductance, LED current, switching frequency, and PWM
frequency. As a general guideline, the minimum PWM on-time
should be kept at 50 µs or longer. A shorter PWM on-time is
acceptable under more favorable operating conditions.
Output Voltage and Duty Cycle
Figure 7 provides simplified equations for approximating output
voltage. Essentially, the output voltage of a buck converter is
approximately given as:
VOUT = VIN × D – VD1 × (1 – D ) ≈ VIN × D, if VD1<< VOUT
D = tON / (tON + tOFF )
where D is the duty cycle, and VD1 is the forward drop of the
Schottky diode D1 (typically under 0.5 V).
Minimum and Maximum Output Voltages
For a given input voltage, the maximum output voltage depends
on the switching frequency and minimum tOFF . For example, if
tOFF(min) = 150 ns and fSW = 1 MHz, then the maximum duty
cycle is 85%. So for a 24 V input, the maximum output is 20.3 V.
This means up to 6 LEDs can be operated in series, assuming
Vf = 3.3 V or less for each LED.
The minimum output voltage depends on minimum tON and
switching frequency. For example, if the minimum tON = 100 ns
and fSW = 1 MHz, then the minimum duty cycle is 10%. That
means with VIN = 24 V, the minimum VOUT = 2.4 V (one LED).
To a lesser degree, the output voltage is also affected by other
factors such as LED current, on-resistance of the high-side
switch, DCR of the inductor, and forward drop of the low-side
diode. The more precise equation is shown in figure 7.
As a general rule, switching at lower frequencies allows a wider
range of VOUT , and hence more flexible LED configurations.
This is shown in figure 8.
Figure 9 shows how the minimum and maximum output volt-
16
9
14
8
7
12
6
VOUT (V)
VOUT (V)
10
VOUT(MAX) (V)
8
VOUT(MIN) (V)
6
5
VOUT(max) (V)
4
VOUT(min) (V)
3
2
4
1
2
0
0
0
0.2
0.4
0.6
0.8
1
1.2
Frequency (MHz)
1.4
1.6
1.8
2
Figure 8: Minimum and Maximum Output Voltage versus
Switching Frequency (VIN = 16 V, iLED = 1 A, minimum tON =
100 ns and tOFF = 150 ns)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
iLED (A)
Figure 9: Minimum and Maximum Output Voltage versus iLED
current (VIN = 9 V, fSW = 1 MHz, minimum tON = 100 ns and tOFF =
150 ns)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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9
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
ages vary with LED current (assuming RDS(on) = 0.4 Ω, inductor
DCR = 0.1 Ω, and diode Vf = 0.6 V).
If the required output voltage is lower than that permitted by the
minimum tON , the controller will automatically extend the tOFF ,
in order to maintain the correct duty cycle. This means that the
switching frequency will drop lower when necessary, while the
LED current is kept in regulation at all times.
Fault Handling
The A6217 is designed to handle the following faults:
• Pin-to-ground short
• Pin-to-neighboring pin short
• Pin open
• External component open or short
• Output short to GND
The waveform in Figure 10 illustrates how the A6217 responds
in the case in which the current sense resistor or the CS pin is
shorted to GND. Note that the SW pin overcurrent protection is
tripped at around 4.2 A, and the part shuts down immediately.
The part then goes through startup retry after approximately
360 µs of cool-down period.
VOUT
C1
A6217 tripped SW_ILIM at ~4.2 A
i_LED
C2
Sense Resistor
shorted during
normal operation
Cooldown
period
~ 360 µs
t
Figure 10: A6217 during fault condition where the sense resistor
or CS pin is shorted to GND. Ch1 = VOUT (5 V/div),
Ch2 = i_LED (500 mA/div), t = 200 µs/div.
C1
C2
C3
VEN
Negative voltage
developed at SW pin
during off-time
VSW
VOUT
iLED
C4
t
Figure 11: Startup waveform with a missing Schottky diode; shows
Enable, VEN (ch1, 5 V/div.), switch node, VSW (ch2, 5 V/div.),
output voltage, VOUT (ch3, 5 V/div.), LED current,
iLED (ch4, 500 mA/div.), t = 100 µs/div.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
Component Selections
The inductor is often the most critical component in a buck converter. Follow the procedure below to derive the correct parameters for the inductor:
1. Determine the saturation current of the inductor. This can be
done by simply adding 20% to the average LED current:
iSAT ≥ iLED × 1.2.
2. Determine the ripple current amplitude (peak-to-peak value). As
a general rule, ripple current should be kept between 10% and
30% of the average LED current:
0.1 < iRIPPLE(pk-pk) / iLED < 0.3.
3. Calculate the inductance based on the following equations:
L = (VIN – VOUT ) × D × t / iRIPPLE , and
D = (VOUT + VD1 ) / ( VIN + VD1 ) ,
where
D is the duty cycle,
t is the period 1/ fSW , and
VIN
2.0
1.8
Switching Frequency (MHz)
As another example, the waveform in Figure 11 shows the fault
case where external Schottky diode D1 is missing or open. As
LED current builds up, a larger-than-normal negative voltage is
developed at the SW node during off-time. This voltage trips the
missing Schottky detection function of the IC. The IC then shuts
down immediately, and waits for a cool-down period before retry.
1.6
1.4
1.2
L = 10 µH
1.0
L = 15 µH
0.8
L = 22 µH
0.6
L = 33 µH
0.4
L = 47 µH
0.2
0.0
0
0.5
1
LED Current (A)
1.5
2
Figure 12: Inductance selection based on iLED and fSW ;
VIN = 12 V, VOUT = 6 V, ripple current = 20%
VD1 is the forward voltage drop of the Schottky diode
D1 (see figure 7).
Inductor Selection Chart
The chart in Figure 12 summarizes the relationship between
LED current, switching frequency, and inductor value. Based on
VIN
L1
LED+
iRIPPLE
SW
D1
L1
LED+
iRIPPLE
SW
D1
VRIPPLE
...
...
CS
C1
CS
LED–
RSENSE
Without output capacitor:
Ripple current through LED string is proportional to ripple voltage
at CS pin.
VRIPPLE
LED–
RSENSE
With a small capacitor across LED string:
Ripple current through LED string is reduced, while ripple voltage
at CS pin remains high.
Figure 13. Ripple current and voltage, with and without shunt capacitor
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115 Northeast Cutoff
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11
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
this chart: Assuming LED current = 1 A and fSW =1 MHz, then
the minimum inductance required is L = 22 µH in order to keep
the ripple current at 30% or lower. (Note: VOUT = VIN / 2 is the
worst case for ripple current). If the switching frequency is lower,
then either a larger inductance must be used, or the ripple current
requirement has to be relaxed.
Additional Notes on Ripple Current
• For consistent switching frequency, it is recommended to
choose the inductor and switching frequency to ensure the inductor ripple current percentage is at least 10% over normal operating voltage range (ripple current is lowest at lowest VIN).
If ripple current is less than 10%, the switching frequency may
jitter due to insufficient ripple voltage at CS pin. However, the
average LED current is still regulated.
• There is no hard limit on the highest ripple current percentage
allowed. A 60% ripple current is still acceptable, as long as both
the inductor and LEDs can handle the peak current (average current × 1.3 in this case). However, care must be taken to ensure
the valley of the inductor ripple current never drops to zero at the
highest input voltage (which implies a 200% ripple current).
• In general, allowing a higher ripple current percentage enables
lower-inductance inductors to be used, which results in smaller
size and lower cost. The only downside is the core loss of the
inductor increases with larger ripple currents, but this is typically
a small factor.
• If lower ripple current is required for the LED string, one solution is to add a small capacitor (such as 2.2 µF) across the LED
string from LED+ to LED– . In this case, the inductor ripple current remains high while the LED ripple current is greatly reduced.
Output Filter Capacitor
The A6217 is designed to operate without an output filter capacitor, in order to save cost. Adding a large output capacitor is not
recommended.
In some applications, it may be required to add a small filter
capacitor (up to several µF) across the LED string (between
LED+ and LED–) to reduce output ripple voltage and current. It
is important to note that:
• The effectiveness of this filter capacitor depends on many factors, such as: switching frequency, inductors used, PCB layout,
LED voltage and current, and so forth.
• The addition of this filter capacitor introduces a longer delay
in LED current during PWM dimming operation. Therefore the
maximum PWM dimming ratio is reduced.
• The filter capacitor should NOT be connected between LED+
and GND. Doing so may create instability because the control
loop must detect a certain amount of ripple current at the CS pin
for regulation.
VIN
VIN
VOUT
VOUT
iLED
C1,C2
C3
VEN
C4
C1,C2
iLED
C3
VEN
C4
t
Panel 14A: Operation without using any output
capacitor across the LED string
t
Panel 14B: Operation with a 0.68 µF ceramic
capacitor connected across the LED string
Figure 14: Waveforms showing the effects of adding a small filter capacitor across the LED string
• Operating conditions: at 200 Hz, VIN = 24 V, VOUT = 15 V, fSW = 500 kHz, L = 10 µH, duty cycle = 50%
• CH1 (Red) = VIN (10 V/div), CH2 (Blue) = VOUT (10 V/div),
CH3 (Green) = iLED (500 mA/div), CH4 (Yellow) = Enable (5 V/div), time scale = 1 ms/div
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12
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
Application Circuit
The application circuit in Figure 15 shows a design for driving a
15 V LED string at 1.3 A (set by RSENSE ). The switching frequency is 500 kHz, as set by R1. A 0.68 µF ceramic capacitor is
added across the LED string to reduce the ripple current through
the LEDs (as shown in Figure 14B).
Suggested Components
Symbol
Part Number
Manufacturer
C1
EMZA500ADA470MF80G
United Chemi-Con
C2
UMK316BJ475KL-T
Taiyo Yuden
C3
CGA5L2X5R1H684K160AA
TDK
L1
NR8040T100M
Taiyo Yuden
D1
B250A-13-F
Diodes, Inc.
RSENSE
RL1632R-R150-F
Susumu
VIN = 24 to 48 V
GND
C1
47 µF
50 V
L1
10 µH / 2 A
C2
4.7µF
50V
1, 2
R1
4
5
VIN
TON
A6217
(EJ)
EN
CS
SW
8
BOOT
C4
0.1 µF
D1
60 V / 2 A
GND 7
PAD
C3
0.68 µF
50 V
6
VCC
LED+
C5
0.1 µF
LED
string
(≈15 V)
...
169 kΩ
EN
3
9,10
LED–
RSENSE
0.15 Ω
Figure 15: Application Circuit Diagram
Additional Application Circuits
The following are some application examples to expand the capability of the A6217:
• Figure 16 shows PWM dimming of LED current by pulsing the
power supply line
VBAT
• Figure 17 shows analog dimming of LED current by an external DC voltage
• Figure 18 shows thermal de-rating of LED current by an NTC
resistor
VIN
LED+
A6217 (EJ)
GND
1, 2
3
4
12 V
VBAT
10 kΩ
5
VIN
TON
SW
BOOT
EN
GND
CS
VCC
9,10
8
6
LED–
0
LED
Current
LED
String
(~6 V)
7
1A
VBAT pulsed on/off at 200 Hz, with duty cycle
between 1 % and 99%
RSENSE
0.2 Ω
0
Figure 16: PWM Dimming of LED Current by Using Pulsed Power Supply Line
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13
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
VIN = 12 V
GND
C1
47 µF
50 V
C2
4.7 µF
50 V
A6217 (EJ)
1, 2
EN
R1
3
200 kΩ
4
5
VCS = 0.2 V
Analog Dimming
Voltage: 0 to 5.2 V
ADIM
iLED
25 kΩ
L1
47 µH 2 A
SW
VIN
TON
BOOT
EN
GND
CS
VCC
9,10
C4
0.1 µF
8
7
LED+
D1
60 V 2 A
LED
String
(~6 V)
C3
open
6
C5
0.1 µF
1 kΩ
iLED:
1.04 A to 0 A
LED–
VSENSE:
0.22 V to 0 V
iADIM
RSENSE
0.2 Ω
iLED = (0.2 V – iADIM × 1000)/RSENSE
100%
iADIM = (VADIM – 0.2)/25 k
0
ADIM
0.2 V
5.2 V
Figure 17: Analog Dimming of LED Current with an External DC Voltage
GND
C1
47 µF
50 V
C2
4.7 µF
50 V
A6217 (EJ)
1, 2
R1
3
200 kΩ
4
NTC: VCS = 0.2 V
220 k @ 25ºC
22 k @ 100ºC 30 kΩ
5
VCC = 5.2 V
iADIM:
0.02 mA @ 25ºC
0.096 mA @ 100ºC
L1
47 µH 2 A
1 kΩ
VIN
TON
SW
BOOT
EN
GND
CS
VCC
9,10
8
C4
0.1 µF
LED+
0.9 A @ 25ºC
0.52 A @ 100ºC
D1
60 V 2 A
7
LED
String
(~6 V)
C3
open
6
C5
0.1 µF
LED–
VSENSE:
0.18 V @ 25ºC
0.104 V @ 100ºC
RSENSE
0.2 Ω
iLED = (0.2 V – iADIM × 1000)/RSENSE
iADIM = (VCC – 0.2)/(RNTC + 30 k)
Figure 18: Thermal Foldback of LED Current Using NTC Resistor
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115 Northeast Cutoff
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14
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
Component Placement and PCB Layout Guidelines
PCB layout is critical in designing any switching regulator. A
good layout reduces emitted noise from the switching device,
and ensures better thermal performance and higher efficiency.
The following guidelines help to obtain a high quality PCB
layout. Figure 19 shows an example for components placement.
Figure 20 shows the three critical current loops that should be
minimized and connected by relatively wide traces.
1) When the upper FET (integrated inside the A6217) is on, current flows from the input supply/capacitors, through the upper
FET, into the load via the output inductor, and back to ground as
shown in loop 1. This loop should have relatively wide traces.
Ideally this connection is made on both the top (component) layer
and via the ground plane.
2) When the upper FET is off, free-wheeling current flows from
ground through the asynchronous diode D1, into the load via the
output inductor, and back to ground as shown in loop 2. This loop
should also be minimized and have relatively wide traces. Ideally
this connection is made on both the top (component) layer and
via the ground plane.
3) The highest di/dt occurs at the instant the upper FET turns on
and the asynchronous diode D1 undergoes reverse recovery as
shown in loop 3. The ceramic input capacitors C2 must deliver
this high instantaneous current. C1 (electrolytic capacitor) should
not be too far off C2. Therefore, the loop from the ceramic input
capacitor through the upper FET and asynchronous diode to
ground should be minimized. Ideally this connection is made on
both the top (component) layer and via the ground plane.
4) The voltage on the SW node (pin 8) transitions from 0 V to
VIN very quickly and may cause noise issues. It is best to place
the asynchronous diode and output inductor close to the A6217 to
minimize the size of the SW polygon.
Keep sensitive analog signals (CS, and R1 of switching frequency setting) away from the SW polygon.
6) For accurate current sensing, the LED current sense resistor
RSENSE should be placed close to the IC.
7) Place the bootstrap capacitor C4 near the BOOT node (pin 7)
and keep the routing to this capacitor short.
8) When routing the input and output capacitors (C1, C2, and C3
if used), use multiple vias to the ground plane and place the vias
as close as possible to the A6217 pads.
9) To minimize PCB losses and improve system efficiency, the
input (VIN) and output (VOUT) traces should be wide and duplicated on multiple layers, if possible.
Loop 1
Loop 2
Loop 3
L1
SW
VIN
Figure 19: Example layout for the A6217 evaluation board
(package LJ)
CIN
D1
COUT
LED
Figure 20: Three different current loops in a buck converter
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15
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
10) Connection to the LED array should be kept short. Excessively long wires can cause ringing or oscillation. When the LED
array is separated from the converter board and an output capacitor is used, the capacitor should be placed on the converter board
to reduce the effect of stray inductance from long wires.
Thermal Dissipation
The amount of heat that can pass from the silicon of the A6217
to the surrounding ambient environment depends on the thermal
resistance of the structures connected to the A6217. The thermal
resistance, RθJA , is a measure of the temperature rise created by
power dissipation and is usually measured in degrees Celsius per
watt (°C/W).
The temperature rise, ΔT, is calculated from the power dissipated,
PD , and the thermal resistance, RθJA , as:
ΔT = PD × RθJA
A thermal resistance from silicon to ambient, RθJA , of approximately 35°C/W (LJ package) or 45°C/W (EJ package) can be
achieved by mounting the A6217 on a standard FR4 double-sided
printed circuit board (PCB) with a copper area of a few square
inches on each side of the board under the A6217. Additional
improvements in the range of 20% may be achieved by optimizing the PCB design.
Optimizing Thermal Layout
The features of the printed circuit board, including heat conduction and adjacent thermal sources such as other components,
have a very significant effect on the thermal performance of the
device. To optimize thermal performance, the following should
be taken into account:
• The device exposed thermal pad should be connected to as
much copper area as is available.
• Copper thickness should be as high as possible (for example,
2 oz. or greater for higher power applications).
• The greater the quantity of thermal vias, the better the dissipation. If the expense of vias is a concern, studies have shown
that concentrating the vias directly under the device in a tight
pattern, as shown in Figure 21, has the greatest effect.
• Additional exposed copper area on the opposite side of the
board should be connected by means of the thermal vias. The
copper should cover as much area as possible.
• Other thermal sources should be placed as remote from the
device as possible
• Place as many vias as possible to the ground plane around the
anode of the asynchronous diode.
Signal traces
LJ package
footprint
0.7 mm
0.7 mm
LJ package
exposed
thermal pad
Top-layer
exposed copper
Ø0.3 mm via
Figure 21: Suggested PCB layout for thermal optimization (maximum
available bottom-layer copper recommended)
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16
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-229)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
3.00 ±0.05
0.50
10
10
0.85
3.00 ±0.05
1.64 3.10
A
1
2
DETAIL A
10X
D
0.05
1
0.75 ±0.05
C
0.25 ±0.05
SEATING
PLANE
C
PCB Layout Reference View
0.05
0.00
0.5 BSC
1
2.38
C
0.40 ±0.10
0.08 REF
2
0.203 REF
0.40 ±0.10
0.05 REF
Detail A
1.65 ±0.10
B
0.05 REF
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
10
2.38 ±0.10
C Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Package EJ, 10-Pin DFN
with Exposed Thermal Pad and Wettable Flank
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17
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
4.90 ±0.10
0.65
8°
0°
1.75
0.25
0.17
B
2.41 NOM
3.90 ±0.10
6.00 ±0.20
2
1.27
0.40
3.30 NOM
0.51
0.31
1.27 BSC
2
SEATING
PLANE
PCB Layout Reference View
C
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.70 MAX
0.15
0.00
C
SEATING PLANE
GAUGE PLANE
Branded Face
0.10 C
1
5.60
3.30
0.25 BSC
8X
2.41
1.04 REF
A
1
1.27
8
8
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Package LJ, 8-Pin SOICN
with Exposed Thermal Pad
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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18
A6217 and
A6217-1
Automotive-Grade, Constant-Current
PWM Dimmable Buck Regulator LED Driver
Revision History
Number
Date
Description
–
August 8, 2016
Initial release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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19
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