Renesas ISL8200AMMRZ-T Complete current share 10a dc/dc power module Datasheet

DATASHEET
ISL8200AM
FN8271
Rev.7.00
Apr 27, 2018
Complete Current Share 10A DC/DC Power Module
The ISL8200AM is a simple and easy to use high power,
current-sharing DC/DC power module for datacom, telecom,
and FPGA power hungry applications. All that is needed is the
ISL8200AM, a few passive components, and one VOUT setting
resistor to have a complete 10A design ready for market.
Features
The ease of use practically eliminates design and
manufacturing risks while dramatically improving time to
market.
• Programmable phase shift (1- to 6-phase)
• Complete switch mode power supply in one package
• Patented current share architecture reduces layout
sensitivity when modules are paralleled
• Extremely low profile (2.2mm height)
Parallel up to six ISL8200AM modules to scale up to a 60A
solution for more output current (see Figure 7 on page 10).
The simplicity of the ISL8200AM is in its “off-the-shelf”,
unassisted implementation compared to a discrete
implementation. Patented current sharing in multiphase
operation greatly reduces ripple currents, BOM cost, and
complexity. For example, parallel two devices for 20A of
current and up to six for 60A of current. The output voltage can
be precisely regulated to as low as 0.6V with ±1% output
voltage regulation over line, load, and temperature variations.
• Input voltage range +3V to +20V at 10A, current share
up to 60A
• A single resistor sets VOUT from +0.6V to +6V
• Output overvoltage, overcurrent, and over-temperature
protection and undervoltage indication
• RoHS compliant
Applications
• Servers, telecom, and datacom applications
• Industrial and medical equipment
The ISL8200AM’s thermally enhanced, compact QFN package
operates at full load and over-temperature without requiring
forced air cooling. The package is so thin it can even fit on the
backside of the PCB. Easy access to all pins with few external
components reduces the PCB design to a component layer and
a simple ground layer.
• Point of load regulation
Complete Functional Schematic
ISL8200AM Package
• ISL8200AM product page
V0UT =
0.6V TO 6.0V
RSET
2.2mm
VSEN_REM-
ISHARE
PGND
PVCC
EN
FF
ISL8200AM
POWER MODULE
VOUT_SET
ISET
CIN2
CIN1
VOUT
PVIN
VIN
R2
R1
PVIN = 3V TO 20V
For a full list of related documents, visit our website
330µF
VIN = 4.5V TO 20V
Related Literature
PGND1
10µF
5k
NOTE: For input voltage higher than 4.5V, VIN can be tied to PVIN directly
15
m
m
15
mm
(see Figure 24 on page 13 for details).
FIGURE 1. COMPLETE 10A DESIGN, JUST SELECT RSET FOR THE
DESIRED VOUT
FN8271 Rev.7.00
Apr 27, 2018
FIGURE 2. THE 2.2mm HEIGHT IS IDEAL FOR THE BACKSIDE OF
PCB WHEN SPACE AND HEIGHT IS A PREMIUM
Page 1 of 25
ISL8200AM
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
TEMP.
RANGE (°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL8200AMIRZ
ISL8200AM
-40°C to +85°C
-
23 Ld QFN
L23.15x15
ISL8200AMIRZ-T
ISL8200AM
-40°C to +85°C
500
23 Ld QFN
L23.15x15
ISL8200AMMRZ
ISL8200AMM
-55°C to +125°C
-
23 Ld QFN
L23.15x15
ISL8200AMMRZ-T
ISL8200AMM
-55°C to +125°C
500
23 Ld QFN
L23.15x15
ISL8200AMEV1PHZ
Evaluation Board
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3) termination finish which is compatible with both SnPb and Pb-free soldering operations. RoHS
compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL8200AM product information page. For more information about MSL, see TB363.
Pinout Internal Circuit
VCC
PVCC
PVIN
21
14
17
RCC
ISL8200AM
MODULE
5
CF1
CF2
BOOT1
LDO
VIN 13
UGATE1
Q1
CBOOT1
EN 12
LOUT1
PHASE1
FF 11
19
VOUT
18
PGND
16
PHASE
20
OCSET
1
VOUT_SET
2
VSEN_REM-
330nH
VCC
PGOOD 22
RPG
10k
VCC
LGATE1
RCLK
10k
CLKOUT
8
PH_CNTRL
9
Q2
INTERNAL PGOOD
ISEN1A
VCC
RPHC
10k
RISEN-IN
CONTROLLER
2.2k
ISEN1B
ISET
5
CF3
ISHARE
COMP
6
ZCOMP1
CF4
FB1
ISHARE_BUS 10
VMON1
ISFETDRV
3
ZCOMP2
VSEN1+
FSYNC_IN
7
RFS
59k
VSEN1-
15
4
PGND1
PGND1
RCSR
CVSEN
ROS1
2.2k
FIGURE 3. PINOUT INTERNAL CIRCUIT
FN8271 Rev.7.00
Apr 27, 2018
Page 2 of 25
ISL8200AM
Pin Configuration
(1) VOUT_SET
(2) VSEN_REM-
(3) ISFETDRV
(4) PGND1
(5) ISET
(6) ISHARE
(7) FSYNC_IN
(8) CLKOUT
(9) PH_CNTRL
(10) ISHARE_BUS
(11) FF
ISL8200AM
(23 LD QFN)
TOP VIEW
(12) EN
(23) N.C.
(13) VIN
(22) PGOOD
(21) VCC
(14) PVCC
(20) OCSET
(15) PGND1
(16) PHASE
PD1
(17) PVIN
PD2
PD4
PD3
(18) PGND
(19) VOUT
Pin Descriptions
PIN #
PIN NAME
PIN DESCRIPTION
1
VOUT_SET
Analog voltage input. Used with VOUT to program the regulator output voltage. The typical input impedance of VOUT_SET with
respect to VSEN_REM- is 500kΩ. The typical voltage input is 0.6V.
2
VSEN_REM-
Analog voltage input. This pin is the negative input of standard unity gain operational amplifier for differential remote sense
for the regulator, and should connect to the negative rail of the load/processor. Connect a resistor from this pin to the
VOUT_SET pin for VOUT trimming.
3
ISFETDRV
4, 15
PGND1
Normal ground. All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drivers
and internal power circuitries as well as all analog signals. PGND and PGND1 should be connected together with a ground
plane.
5
ISET
Analog current output. This pin sources a 15µA offset current plus Channel 1’s average current. The voltage (VISET) set by an
external resistor (RISET) represents the average current level of the local active module. For full-scale current, RISET should
be ~10kΩ. The output current range is 15µA to 126µA typical.
The ISET and ISHARE pins are used for current sharing purposes with multiple ISL8200AM modules. In the single module
configuration, this pin can be tied to the ISHARE pin. In multiphase operation add an additional 10pF capacitor to the ISET
line if noise is a concern.
FN8271 Rev.7.00
Apr 27, 2018
Digital output. This pin is used to drive an optional NFET, which will connect ISHARE with the system ISHARE bus upon
completing a pre-bias start-up. The voltage output range is 0V to 5V.
Page 3 of 25
ISL8200AM
Pin Descriptions (Continued)
PIN #
PIN NAME
PIN DESCRIPTION
6
ISHARE
Analog current output. Cascaded system level overcurrent shutdown pin. Multi-module operation can be achieved by
connecting the ISHARE pin of two or more modules together. The common current share bus sums each of the modules'
average current contribution to the load to protect for an overcurrent condition at the load. The pin sources 15µA plus the
average module's output current. The shared bus voltage (VISHARE) is developed across an external resistor (RISHARE).
VISHARE represents the average current of all active channel(s) that are connected together.
The ISHARE bus voltage is compared with each module's internal reference voltage set by each module's RISET resistor. This
will generate an individual current share error signal in each cascaded controller. The share bus impedance RISHARE should
be set as RISET/NCTRL, RISET divided by the number of active current sharing controllers. The output current from this pin
generates a voltage across the external resistor. This voltage, VISHARE, is compared to an internal 1.2V threshold for average
overcurrent protection. For full-scale current, RISHARE should be ~10kΩ. Typically 10kΩ is used for RSHARE and RSET. The
output current range is 15µA to 126µA typical.
7
FSYNC_IN
Analog input control pin. An optional external resistor (RFS-ext) connected to this pin and ground will increase the oscillator
switching frequency. The module has an internal 59kΩ resistor connected to the FSYNC_In pin for a default frequency of
700kHz. The internal oscillator will lock to an external frequency source when connected to a square waveform. The external
source is typically the CLKOUT signal from another ISL8200AM or an external clock. The internal oscillator synchronizes with
the leading positive edge of the input signal. The input voltage range for the external source is 0V to 5V square wave. When
not synchronized to an external clock, a 100pF capacitor between FSYNC_IN and PGND1 is recommended.
8
CLKOUT
Digital voltage output. This pin provides a clock signal to synchronize with other ISL8200AM(s). When more than one
ISL8200AM is in the system, the two independent regulators can be programmed through PH_CNTRL for different degrees
of phase delay.
9
PH_CNTRL
Analog input. The voltage level on this pin is used to program the phase shift of the CLKOUT clock signal to synchronize with
other module(s).
10
ISHARE_BUS
Open pin until the first PWM pulse is generated. Then, through an internal FET, this pin connects the module’s ISHARE to the
system’s ISHARE bus after pre-bias is complete and soft-start is initiated.
11
FF
Analog voltage input. The voltage on this pin is fed into the controller, adjusting the sawtooth amplitude to generate the
feed-forward function. The input voltage range is 0.8V to VCC. Typically, FF is connected to EN.
12
EN
This is a double function pin:
Analog input voltage - The input voltage to this pin is compared with a precision 0.8V reference and enables the digital softstart. The input voltage range is 0V to VCC or VIN through a pull-up resistor maintaining a typical current of 5mA.
Analog voltage output - This pin can be used as a voltage monitor for input bus undervoltage lockout. The hysteresis levels
of the lockout can be programmed through this pin using a resistor divider network. Furthermore, during fault conditions
(such as overvoltage, overcurrent, and over-temperature), this pin is used to communicate the information to other cascaded
modules by pulling the wired OR low as it is an open drain. The output voltage range is 0V to VCC.
13
VIN
Analog voltage input. This pin should be tied directly to the input rail when using the internal linear regulator. It provides power
to the internal linear drive circuitry. When used with an external 5V supply, this pin should be tied directly to PVCC. The internal
linear device is protected against the reversed bias generated by the remaining charge of the decoupling capacitor at VCC
when losing the input rail. The input voltage range is 4.5V to 20V.
14
PVCC
Analog output. This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side
drives. Its operational voltage range is 4.5V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF.
16
PHASE
17
PVIN
Analog input. This input voltage is applied to the power FETs with the FETs ground being the PGND pin. It is recommended to
place 22µF of input decoupling capacitance directly between the PVIN pin and the PGND pin as close as possible to the
module. The input voltage range is 3V to 20V.
18
PGND
All voltage levels are referenced to this pad. This is the low-side MOSFET ground. PGND and PGND1 should be connected
together with a ground plane.
19
VOUT
Output voltage from the module. The output voltage range is 0.6V to 6V.
20
OCSET
Analog input. This pin is used with the PHASE pin to set the current limit of the module. The input voltage range is 0V to 30V.
21
VCC
Analog input. This pin provides bias power for the analog circuitry. Its operational range is 4.5V to 5.6V. In 3.3V applications,
VCC, PVCC, and VIN should be shorted to allow operation at the low end input as it relates to the VCC falling threshold limit.
This pin can be powered either by the internal linear regulator or by an external voltage source.
22
PGOOD
Analog output. This pin, pulled up to VCC using an internal 10kΩ resistor, provides a power-good signal when the output is
within 9% of a nominal output regulation point with 4% hysteresis (13%/9%) and when soft-start is complete. An external
pull-up is not required. PGOOD monitors the outputs (VMON1) of the internal differential amplifiers. The output voltage range
is a 0V to VCC.
FN8271 Rev.7.00
Apr 27, 2018
Analog output. This pin is the phase node of the regulator. The output voltage range is 0V to 30V.
Page 4 of 25
ISL8200AM
Pin Descriptions (Continued)
PIN #
PIN NAME
23
N.C.
PIN DESCRIPTION
Not internally connected
PD1 Phase Thermal Pad Used for both the PHASE pin (Pin 16) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PHASE Pin 16.
PD2
PVIN Thermal Pad Used for both the PVIN pin (Pin 17) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PVIN Pin 17.
PD3 PGND Thermal Pad Used for both the PGND pin (Pin 18) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to PGND Pin 18.
PD4
VOUT Thermal Pad Used for both the VOUT pin (Pin 19) and for heat removal connecting to heat dissipation layers using vias. Connect this pad
to a copper island on the PCB board with the same shape as the pad; this is electrically connected to VOUT Pin 19.
Typical Application Circuits
VIN
RSET
VOUT_SET
FF
2.2k
ISL8200AM
FSYNC_IN
PGOOD
CLKOUT
VCC
PVCC
PGND1
PGND
PHASE
OCSET
ISET
VCC
10µF
C209
RSET CAN CHANGE VOUT
Refer to Table 1
5k
ISHARE
ISFETDRV
RISHARE1
DO NOT TIE EN DIRECTLY TO A POWER SOURCE
PGOOD
PH_CNTRL
ISHARE_BUS
SET R1 AND R2 SO THAT
0.8V ≤ VEN ≤ 5.0V
GROUND
VSEN_REM-
EN
ISFETDRV1
VOUT
330µF
VOUT
VOUT
C9
22µF
PVIN
1nF
2.05k
R2
GROUND
C211
R1
8.25k
C203
270µF
C3
PVIN
FIGURE 4. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
FN8271 Rev.7.00
Apr 27, 2018
Page 5 of 25
22µF
C203
R1
PVIN
26.7k
270µF
C3
PVIN
VOUT
RSET1
VIN
1nF
C211
R2
2.61k
10k
VSEN_REM-
EN
ISL8200AM
FSYNC_IN
CLKOUT
PGOOD
PGOOD
2.2nF
PH_CNTRL
ISHARE_BUS
VCC
VCC1
PVCC
PGND1
PGND
PHASE
ISET
OCSET
ISFETDRV
ISHARE
ISFETDRV1
22µF
C303
PVIN
10µF
C209
10k
RISET1
RISHARE1 5k
ISHARE
VOUT
VIN
VOUT
RSET2
VOUT_SET
1nF
C311
FF
10k
VSEN_REM-
EN
ISL8200AM
FSYNC_IN
CLKOUT
PGOOD
PGOOD
PH_CNTRL
ISHARE_BUS
VCC
VCC2
PVCC
PGND1
PGND
PHASE
ISET
OCSET
ISFETDRV
ISHARE
ISFETDRV2
C9
100µF (x6)
VOUT_SET
FF
GROUND
VOUT
VOUT
Page 6 of 25
10µF
C309
10k
RISET2
ISHARE
FIGURE 5. TWO PHASE 20A 3.3V OUTPUT CIRCUIT
2.2nF
GROUND
ISL8200AM
FN8271 Rev.7.00
Apr 27, 2018
Typical Application Circuits (continued)
ISL8200AM
Absolute Maximum Ratings
Thermal Information
Input Voltage, PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage,
VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . . .
13
2
Maximum Storage Temperature Range . . . . . . . . . . . . . .-55°C to +150°C
Typical Reflow Profile . . . . . . . . . . . . . . . . . . . . . . See Figure 42 on page 21
Recommended Operating Conditions
Input Voltage
PVIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 20V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.6V
Boot to Phase Voltage
VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <6V
ISL8200AMIRZ Ambient Temperature Range . . . . . . . . . . -40°C to +85°C
ISL8200AMIRZ Junction Temperature Range . . . . . . . . .-40°C to +125°C
ISL8200AMMRZ Ambient Temperature Range . . . . . . . .-55°C to +125°C
ISL8200AMMRZ Junction Temperature Range . . . . . . . .-55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board (for example, 4-layer type without thermal
vias. See TB379) per JEDEC standards except that the top and bottom layers assume solid plains.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C for ISL8200AMIRZ and -55°C
to +125°C for ISL8200AMMRZ.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNIT
VCC SUPPLY CURRENT
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 20V; No Load; fSW = 700kHz
36
mA
Nominal Supply VIN Current
IQ_VIN
PVIN = VIN = 4.5V; No Load; fSW = 700kHz
27
mA
IVCC
EN = 0V, VCC = 2.97V
9
mA
IPVCC
PVCC = 4V to 5.6V
320
mA
Shutdown Supply VCC Current
INTERNAL LINEAR REGULATOR
Maximum Current
Saturated Equivalent Impedance
RLDO
P-Channel MOSFET (VIN = 5V)
PVCC Voltage Level (Note 8)
PVCC
IPVCC = 0mA, VIN = 12V, ISL8200AMIRZ
1
5.15
5.4
Ω
5.60
V
V
POWER-ON RESET (Note 8)
Rising VCC Threshold
ISL8200AMIRZ
2.85
2.97
ISL8200AMMRZ
2.85
2.98
Falling VCC Threshold
2.65
2.75
V
Rising PVCC Threshold
2.85
2.97
V
2.65
2.75
Falling PVCC Threshold
System Soft-start Delay
tSS_DLY
After PLL, VCC, and PVCC PORs, and EN above
their thresholds
384
V
Cycles
ENABLE (Note 8)
Turn-On Threshold Voltage
Hysteresis Sink Current
Undervoltage Lockout Hysteresis
IEN_HYS
VEN_HYS
0.75
0.8
0.86
V
ISL8200AMIRZ
21
30
35
µA
ISL8200AMMRZ
19
30
35
µA
VEN_RTH = 10.6V; VEN_FTH = 9V
RUP = 53.6kΩ, RDOWN = 5.23kΩ
FN8271 Rev.7.00
Apr 27, 2018
1.6
V
Page 7 of 25
ISL8200AM
Electrical Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C for ISL8200AMIRZ and -55°C
to +125°C for ISL8200AMMRZ. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
Sink Current
IEN_SINK
VEN = 1V, ISL8200AMIRZ
15.4
VEN = 1V, ISL8200AMMRZ
10
Sink Impedance
REN_SINK
VEN = 1V
TYP
(Note 6)
MAX
(Note 7)
UNIT
mA
mA
64
Ω
OSCILLATOR
Oscillator Frequency
FOSC
Total Variation (Note 8)
RFS = 59kΩFigure 35
700
kHz
VCC = 5V; ISL8200AMIRZ
-9
+9
%
VCC = 5V; ISL8200AMMRZ
-12
-12
%
1500
kHz
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 7)
Synchronization Frequency
VCC = 5.4V
PLL Locking Time
VCC = 5.4V; fSW = 700kHz, ISL8200AMIRZ
Input Signal Duty Cycle Range
FOSC
210
10
µs
90
%
PWM (Note 8)
Minimum PWM OFF Time
Current Sampling Blanking Time
tMIN_OFF
ISL8200AMIRZ
310
345
410
ns
ISL8200AMMRZ
310
345
425
ns
tBLANKING
175
ns
OUTPUT CHARACTERISTICS
Output Continuous Current Range
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
IOUT(DC)
VOUT/VIN
VOUT/IOUT
VOUT
PVIN = VIN = 12V, VOUT = 1.2V
0
10
A
VOUT = 1.2V, IOUT = 0A, PVIN = VIN = 3.5V to 20V
0.15
%
VOUT = 1.2V, IOUT = 10A, PVIN = VIN = 5V to 20V
0.15
%
IOUT = 0A to 10A, VOUT = 1.2V, PVIN = VIN = 12V
0.1
%
IOUT = 10A, VOUT = 1.2V, PVIN = VIN = 12V
27
mVP-P
IOUT = 0A, VOUT = 1.2V, PVIN = VIN = 12V
19
mVP-P
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step
VOUT-DP
IOUT = 0A to 5A. Current slew rate = 2.5A/µs,
PVIN = VIN = 12V, VOUT = 1.2V
45
mVP-P
Voltage Change for Negative Load Step
VOUT-DN
IOUT = 5A to 0A. Current slew rate = 2.5A/µs,
PVIN = VIN = 12V, VOUT = 1.2V
55
mVP-P
0.6
V
REFERENCE (Note 8)
Reference Voltage (Include Error and
Differential Amplifiers’ Offsets)
VREF
ISL8200AMIRZ
-0.75
0.75
%
ISL8200AMMRZ
-0.95
0.95
%
DIFFERENTIAL AMPLIFIER (Note 8)
DC Gain
Unity Gain Bandwidth
UG_DA
Unity Gain Amplifier
UGBW_DA
0
dB
5
MHz
VSEN+ Pins Input Current
IVSEN+
ISL8200AMIRZ
Maximum Source Current for Current
Sharing
IVSEN1-
VSEN1- source current for current sharing
when parallel multiple modules each of which
has its own voltage loop
350
µA
VVSEN+/IVSEN+, VVSEN+ = 0.6V,
ISL8200AMIRZ
-500
kΩ
Input Impedance
RVSEN+_to
_VSEN-
Output Voltage Swing
Input Common Mode Range
Disable Threshold
FN8271 Rev.7.00
Apr 27, 2018
ISL8200AMIRZ
VVSEN-
VMON1 = Tri-state
0.2
1.16
2.5
µA
0
VCC - 1.8
V
-0.2
VCC - 1.8
V
VCC - 0.4
V
Page 8 of 25
ISL8200AM
Electrical Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C for ISL8200AMIRZ and -55°C
to +125°C for ISL8200AMMRZ. (Continued)
PARAMETER
SYMBOL
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNIT
VCC = 5V; ISL8200AMIRZ
89
111
129
µA
VCC = 5V; ISL8200AMMRZ
84
111
129
µA
Comparator offset included
1.16
1.20
1.22
V
TEST CONDITIONS
OVERCURRENT PROTECTION (Note 8)
Channel Overcurrent Limit
Share Pin OC Threshold
ISOURCE
VOC_ISHARE
CURRENT SHARE
External Current Share Accuracy
Up to three phases; ISL8200AMIRZ
±10
%
POWER GOOD MONITOR (Note 8)
Undervoltage Falling Trip Point
VUVF
Undervoltage Rising Hysteresis
VUVR_HYS
Overvoltage Rising Trip Point
VOVR
Overvoltage Falling Hysteresis
VOVF_HYS
Percentage below reference point
-15
-13
11
13
Percentage above UV trip point
Percentage above reference point
-11
%
15
%
4
Percentage below OV trip point
%
4
%
PGOOD Low Output Voltage
IPGOOD = 2mA
0.35
V
Sinking Impedance
IPGOOD = 2mA
70
Ω
Maximum Sinking Current
VPGOOD < 0.8V
10
mA
OVERVOLTAGE PROTECTION (Note 8)
OV Latching Trip Point
EN = UGATE = LATCH Low, LGATE = High
OV Non-latching Trip Point
EN = Low, UGATE = Low, LGATE = High
LGATE Release Trip Point
EN = Low/HIGH, UGATE = Low, LGATE = Low
118
120
122
%
113
%
87
%
Over-temperature Trip
150
°C
Over-temperature Release Threshold
125
°C
RCC
5
Ω
Internal Resistor Between PHASE and
OCSET Pins
RISEN-IN
2.2k
Ω
Internal Resistor Between FSYNC_IN
and PGND1 Pins
RFS
59k
Ω
Internal Resistor Between PGOOD and
VCC Pins
RPG
10k
Ω
Internal Resistor Between CLKOUT and
VCC Pins
RCLK
10k
Ω
Internal Resistor Between PH_CNTRL
and VCC Pins
RPHC
10k
Ω
Internal Resistor Between VOUT_SET
and VSEN_REM- pin
ROS1
2.2k
Ω
OVER-TEMPERATURE PROTECTION CONTROLLER JUNCTION TEMPERATURE
INTERNAL COMPONENT VALUES
Internal Resistor Between PVCC and
VCC pin
NOTES:
6. Parameters with TYP limits are not production tested, unless otherwise specified.
7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN8271 Rev.7.00
Apr 27, 2018
Page 9 of 25
ISL8200AM
RSET 2.2k
VOUT_SET
VSEN_REMISL8200AM
FSYNC_IN
47µF (x8)
GROUND
10nF
PGOOD
CLKOUT
PH_CNTRL
ISHARE_BUS
VCC
VOUT = 1.2V for RSET = 2.2k
Refer to Table 1 for RESET vs VOUT
VCC
PVCC
PGND1
PGND
OCSET
PHASE
ISET
10µF
C209
RISHARE1
ISHARE
ISFETDRV
5k
ISFETDRV1
C9
C205
FF
EN
VOUT
VOUT
VOUT
VIN
1nF
4.12k
C211
GROUND
R2
PVIN
22µF
C203
R1
16.5k
270µF
C3
PVIN
FIGURE 6. TEST CIRCUIT FOR ALL PERFORMANCE AND DERATING GRAPHS
Typical Performance Characteristics
TA = +25°C, PVIN = VIN, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 47µF/ceramic x 8.
100
100
95
95
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency Performance
85
80
3.3V
75
2.5V
1.5V
70
1.2V
0.8V
85
80
75
70
65
65
60
0
60
0
2
4
6
8
10
3.3V
1.5V
1.2V
0.8V
5.0V
2
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY vs LOAD CURRENT (5VIN)
2.5V
4
6
LOAD CURRENT (A)
8
10
FIGURE 8. EFFICIENCY vs LOAD CURRENT (12VIN)
VOUT
100
3.3V
EFFICIENCY (%)
95
2.5V
5.0V
90
VIN = 12V
VOUT = 1.2V
IOUT = 0A TO 5A
85
80
75
70
1.5V
65
60
0
2
4
6
1.2V
8
10
LOAD CURRENT (A)
FIGURE 9. EFFICIENCY vs LOAD CURRENT (20VIN)
FN8271 Rev.7.00
Apr 27, 2018
FIGURE 10. 1.2V TRANSIENT RESPONSE
Page 10 of 25
ISL8200AM
Transient Response Performance
IOUT = 0A to 5A, current slew rate = 2.5A/µs.
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 47µF/ceramic x 8,
VOUT
VOUT
VIN = 12V
VOUT = 1.8V
IOUT = 0A TO 5A
VIN = 12V
VOUT = 1.5V
IOUT = 0A TO 5A
FIGURE 11. 1.5V TRANSIENT RESPONSE
FIGURE 12. 1.8V TRANSIENT RESPONSE
VOUT
VOUT
VIN = 12V
VOUT = 2.5V
IOUT = 0A TO 5A
VIN = 12V
VOUT = 1.8V
IOUT = 0A TO 5A
FIGURE 13. 2.5V TRANSIENT RESPONSE
FIGURE 14. 3.3V TRANSIENT RESPONSE
PHASE1-M
PHASE2-M
PHASE3-M
PHASE4-S
FIGURE 15. FOUR MODULE CLOCK SYNC (VIN = 12V)
FN8271 Rev.7.00
Apr 27, 2018
Page 11 of 25
ISL8200AM
Current Ripple Performance
No Load, 5, 10A.
TA = +25°C, PVIN = VIN = 12V, CIN = 220µFx1, 10µF/ceramic x 2, COUT = 100µF/ceramic x 6 IOUT =
VIN = 0V TO 18V
VOUT = 1.2V
IOUT = NO LOAD
VOUT
EN
PGOOD
VOUT
PHASE
FIGURE 16. OVERCURRENT PROTECTION
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 18. 1.2V OUTPUT RIPPLE
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 20. 2.5V OUTPUT RIPPLE
FN8271 Rev.7.00
Apr 27, 2018
PVIN
PHASE
FIGURE 17. 50% PRE-BIAS START-UP
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 19. 1.5V OUTPUT RIPPLE
VOUT NO LOAD
VOUT 5A
VOUT 10A
FIGURE 21. 3.3V OUTPUT RIPPLE
Page 12 of 25
ISL8200AM
Applications Information
Programming the Output Voltage (RSET)
The ISL8200AM has an internal 0.6V ±0.7% reference voltage.
Programming the output voltage requires a dividing resistor
(RSET) between the VOUT_SET pin and the VOUT regulation point.
The output voltage can be calculated as shown in Equation 1:
R SET

V OUT = 0.6   1 + ---------------
R OS 

stage is at a 5V rail. It is imperative to not cross 5.5V in this setup
as that is the voltage limit on the PVCC pin. Figure 24 is a more
general setup and can accommodate VIN ranges up to 20V; PVCC
is not tied to VIN and hence the control circuitry is powered by the
internal LDO.
The circuit shown in Figure 25 ensures proper start-up by
injecting current into the ISHARE line until all phases are ready to
start regulating.
(EQ. 1)
PVIN = 3.3V
VIN = 5.0V
0.8
1.0
1.2
RSET (Ω)
0
732
1.47k
2.2k
VOUT (V)
1.5
1.8
2.0
2.5
RSET (Ω)
3.32k
4.42k
5.11k
6.98k
VSEN_REM-
FF
ISHARE
PVCC
0.6
RSET
VOUT_SET
EN
PGND
VOUT (V)
COUT
CIN1
VEN
ISET
TABLE 1. VOUT - RSET
ISL8200AM
POWER MODULE
CIN2
R1
PVIN
R2
Note: The ISL8200AM has integrated 2.2kΩ resistances into the
module dividing resistor for the bottom side (ROS). The
resistances for different output voltages in single-phase
operation are listed in Table 1.
VOUT
VOUT
VIN
PGND1
PVCC = 5.0V
10µF
5k
VEN
ISL8200AM
POWER MODULE
PGND1
PVCC = VIN
10µF
5k
FIGURE 23. 5V OPERATION
VIN is the input to the internal LDO that powers the control
circuitry while PVCC is the output of the aforementioned LDO.
PVIN is the power input to the power stage. Figure 22 shows a
scenario in which the power stage is running at 3.3V and the
control circuitry is running at 5V; keep in mind that the PVCC pin
is also at 5V to ensure that the LDO is not functioning. Figure 23
shows a setup in which both the control circuitry and the power
CIN
ISL8200AM
POWER MODULE
VOUT_SET
EN
VSEN_REM-
FF
ISHARE
PVCC
R2
VEN
RSET
COUT
PVIN
R1
(EQ. 3)
For 3.3V input voltage operation, the VIN voltage is
recommended to be 5V for sufficient gate drive voltage. This can
be accomplished by using a voltage greater than or equal to 5V
on VIN, or directly connecting the 5V source to both VIN and PVCC.
VOUT
VOUT
VIN
PGND
VIN = 5V-20V
for the 700kHz switching frequency = 1428ns
FN8271 Rev.7.00
Apr 27, 2018
PVCC
ISHARE
(EQ. 2)
tSW = switching period = 1/fSW
PV IN_MIN = 1.43  V OUT
VSEN_REM-
FF
The equations to determine the minimum PVIN to support the
required VOUT are given by Equations 2 and 3; it is recommended
to add 0.5V to the result to account for temperature variations.
V OUT  t SW
PV IN_MIN = -----------------------------------------t SW – t MIN_OFF
RSET
VOUT_SET
EN
PGND
The module has a minimum input voltage at a given output
voltage, which needs to be a minimum of 1.43 times the output
voltage if operating at fSW = 700kHz switching frequency. This is
due to the minimum PWM OFF time (tMIN-OFF).
PVIN
ISET
The output voltage accuracy can be improved by maintaining the
impedance at VOUTSET (internal VSEN1+) at or below 1kΩ
effective impedance. Note: The impedance between VSEN1+ and
VSEN1- is about 500kΩ.
VOUT
VOUT
VIN
COUT
VIN = 5.0V
DO NOT CROSS 5.5V
ISET
6.0
20k
CIN
5.0
16.2k
R1
3.3
10k
R2
VOUT (V)
RSET (Ω)
FIGURE 22. 3.3V OPERATION
PGND1
10µF
5k
FIGURE 24. 5V TO 20V OPERATION
Page 13 of 25
ISL8200AM
Selection of the Input Capacitor
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, but consideration should be
taken for the higher surge current during power-up. The
ISL8200AM provides the soft-start function that controls and
limits the current surge. The value of the input capacitor can be
calculated by Equation 4:
D  1 – D
C IN  MIN  = I O  ----------------------------------------------f
V
P-P  MAX 
values: RINC = 243k, RPH1 = 15k, QSHR = Small Signal PFET,
CG = 22nF.
VCC (PHASE 1)
RINC
RPH1
ISFETDRV (PHASE 1)
(EQ. 4)
SW
QSHR
DPH2
where:
ISFETDRV (PHASE 2)
CG
DPH2
CIN(MIN) is the minimum input capacitance (µF) required.
IO is the output current (A).
ADD ADDITIONAL
DIODES PER PHASE
D is the duty cycle (VO/VIN).
FIGURE 25. START-UP CIRCUITRY
VP-P(MAX) is the maximum peak-to-peak voltage (V).
fSW is the switching frequency (Hz).
In addition to the bulk capacitance, some low Equivalent Series
Inductance (ESL) ceramic capacitance is recommended to
decouple between the drain terminal of the high-side MOSFET
and the source terminal of the low-side MOSFET. This is used to
reduce the voltage ringing created by the switching current
across parasitic circuit elements.
Output Capacitors
The ISL8200AM is designed for low output voltage ripple. The
output voltage ripple and transient requirements can be met with
bulk output capacitors (COUT) with low enough Equivalent Series
Resistance (ESR); the recommended ESR is <10mΩ. When the
total ESR is below 4mΩ, a capacitor (CFF) between 2.2nF to 10nF
is recommended; CFF is placed in parallel with RSET, in between
the VOUT and VOUT_SET pin. COUT can be a low ESR tantalum
capacitor, a low ESR polymer capacitor, or a ceramic capacitor.
The typical capacitance is 330µF and decoupled ceramic output
capacitors are used per phase. The internally optimized loop
compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total value
of 300µF per phase. Additional output filtering may be needed if
further reduction of output ripple or dynamic transient spike is
required.
Using Multiple Phases
The ISL8200AM can be easily connected in parallel with other
ISL8200AM modules and current share providing an additional
10A per phase. For two phases, simply follow the schematic
shown in Figure 5 on page 6. A rough summary shows that the
modules share VIN, VOUT, and GND and have their ISHARE pins
tied together with a 10kΩ resistor to ground (per phase). When
using three phases or more, it is recommended that you add the
following circuitry (see Figure 25) to ensure proper start-up. The
circuit shown in Figure 25 ensures proper start-up by injecting
current into the ISHARE line until all phases are ready to start
regulating. For additional phases, the RC time constant, using
RINC­ and CG, might have to be adjusted to increase the turn on
time of the PFET (QSHR). For three to four phases, these are the
FN8271 Rev.7.00
Apr 27, 2018
ISFETDRV (PHASE 3)
ISHARE
Functional Description
Initialization
The ISL8200AM requires VCC and PVCC to be biased by a single
supply. Power-On Reset (POR) circuits continually monitor the
bias voltages (PVCC and VCC) and the voltage at the EN pin. The
POR function initiates soft-start operation 384 clock cycles after
the EN pin voltage is pulled above 0.8V, all input supplies exceed
their POR thresholds, and the PLL locking time expires. The
enable pin can be used as a voltage monitor and to set desired
hysteresis with an internal 30µA sinking current going through
an external resistor divider. The sinking current is disengaged
after the system is enabled. This feature is especially designed
for applications that require higher input rail POR for better
undervoltage protection. For example, in 12V applications,
RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold
(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with
1.6V hysteresis (VEN_HYS). These numbers are explained in
Figure 30 on page 15.
During shutdown or fault conditions, the soft-start is quickly reset
while UGATE and LGATE immediately change state (<100ns)
upon the input dropping below POR.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
PVCC POR
EN POR
AND
384
CYCLES
SOFT-START
OF MODULE
PLL LOCKING
FIGURE 26. SOFT-START INITIALIZATION LOGIC
Soft-start
The ISL8200AM has an internal digital precharged soft-start
circuitry, which has a rise time inversely proportional to the
switching frequency and is determined by a digital counter that
increments with every pulse of the phase clock. The full soft-start
time from 0V to 0.6V can be estimated by Equation 5.
2560
t SS = ------------f SW
(EQ. 5)
Page 14 of 25
ISL8200AM
The ISL8200AM can work under a precharged output. The PWM
outputs will not be fed to the drivers until the first PWM pulse is
seen. The low-side MOSFET is held low for the first clock cycle to
provide charge for the bootstrap capacitor. If the precharged output
voltage is greater than the final target level but less than the 113%
setpoint, switching will not start until the output voltage is reduced
to the target voltage and the first PWM pulse is generated. The
maximum allowable precharged level is 113%. If the precharged
level is above 113% but below 120%, the output will hiccup between
113% (LGATE turns on) and 87% (LGATE turns off) while EN is pulled
low. If the precharged load voltage is above 120% of the targeted
output voltage, then the controller will be latched off and not be able
to power-up.
FIRST PWM PULSE
OV = 113%
FIRST PWM PULSE
VOUT TARGET VOLTAGE
FIGURE 29. SOFT-START WITH VOUT BELOW OV BUT ABOVE FINAL
TARGET VOLTAGE
Voltage Feedforward
The voltage applied to the FF pin is fed to adjust the sawtooth
amplitude of the channel. The amplitude the sawtooth is set to is
1.25 times the corresponding FF voltage when the module is
enabled. This configuration helps to maintain a constant gain
(GM = VIN • DMAX/VRAMP) and input voltage to achieve
optimum loop response over a wide input voltage range. The
sawtooth ramp offset voltage is 1V (equal to 0.8V*1.25), and the
peak of the sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V (equal
to 3V); so the feed-forward voltage effective range is typically
3 times as the ramp amplitude ranges from 1V to 3V.
SS SETTLING AT VREF + 100mV
VOUT TARGET VOLTAGE
0.0V
2560
t ss  ------------f SW
-100mV
384
t ss_DLY  ---------f SW
A 384 cycle delay is added after the system reaches its rising
POR and prior to the soft-start. The RC timing at the FF pin should
be sufficiently small to ensure that the input bus reaches its
static state and the internal ramp circuitry stabilizes before
soft-start. A large RC could cause the internal ramp amplitude
not to synchronize with the input bus voltage during output
start-up or when recovering from faults. A 1nF capacitor is
recommended as a starting value for typical applications. The
voltage on the FF pin needs to be above 0.8V prior to soft-start
and during PWM switching to ensure reliable regulation. In a
typical application, the FF pin can be shorted to the EN pin.
FIGURE 27. SOFT-START WITH VOUT = 0V
FIRST PWM PULSE
SS SETTLING AT VREF + 100mV
VOUT TARGET VOLTAGE
INIT. VOUT
-100mV
FIGURE 28. SOFT-START WITH VOUT < TARGET VOLTAGE
V
EN_HYS
= ----------------------------------R
UP
NxI
EN_HYS
R UP  V
EN_REF
R
= --------------------------------------------------------------DOWN
V
–V
EN_FTH
EN_REF
VCC
GRAMP = 1.25
where N is number of EN pins connected together
VCC - 1.4V
UPPER LIMIT

V EN_FTH = V EN_RTH – V EN_HYS
0.8V
V RAMP = max(V CC_FF  G RAMP , VCC - 1.4V - V RAMP_OFFSET 
V CC_FF = max(0.8V, V FF 
VCC_FF
LIMITER
SAWTOOTH
AMPLITUDE
(VRAMP)
VIN
VRAMP_OFFSET = 1.0V
FF
LOWER LIMIT
(RAMP OFFSET)
0.8V
RUP
SYSTEM DELAY
RDOWN
EN
EN_POR
IEN_HYS = 30µA
OV, OT, OC, AND PLL LOCKING FAULTS
FIGURE 30. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
FN8271 Rev.7.00
Apr 27, 2018
Page 15 of 25
ISL8200AM
Power-good
Overvoltage Protection (OVP)
The power-good comparators monitor the voltage on the internal
VMON1 pin. The trip points are shown in Figure 31. PGOOD will
not be asserted until after the completion of the soft-start cycle.
PGOOD pulls low upon both ENs disabling it if the internal
VMON1 pin’s voltage is out of the threshold window. PGOOD will
not be asserted until after the completion of the soft-start cycle.
PGOOD will not pull low until the fault is present for three
consecutive clock cycles.
The OVP indication circuitry monitors the voltage on the internal
VMON1 pin.
The UV indication is not enabled until the end of soft-start. In a UV
event, if the output drops below -13% of the target level due to
some reason (cases when EN is not pulled low) other than OV,
OC, OT, and PLL faults, PGOOD will be pulled low.
Current Share
The IAVG_CS is the current of the module. ISHARE and ISET pins
source a copy of IAVG_CS with 15µA offset. That is, the full scale
will be 126µA.
The share bus voltage (VISHARE) set by an external resistor
(RISHARE = RISET/NCTRL) represents the average current of all
active modules. The voltage (VISET) set by RISET represents the
average current of the corresponding module and is compared
with the share bus (VISHARE). The current share error signal
(ICSH_ER) is then fed into the current correction block to adjust
each module’s PWM pulse accordingly. The current share
function provides at least 10% overall accuracy between ICs, up
to three phases. The current share bus works for up to six phases.
Figure 5 on page 6 further illustrates the current sharing aspects
of the ISL8200AM.
AND
PGOOD
END OF SS1
+20%
+13%
+9%
VREF
-9%
-13%
PGOOD
PGOOD LATCH OFF
AFTER 120% OV
FIGURE 31. POWER-GOOD THRESHOLD WINDOW
When only one module is in the system, the ISET and ISHARE
pins can be shorted together and grounded through a single
resistor to ensure zero share error. A resistor value of 5k
(paralleling 10k on ISET and ISHARE) will allow operation up to
the OCP level.
FN8271 Rev.7.00
Apr 27, 2018
There is another non-latch OVP (113% of target level). At the
condition of EN low and an output over 113% OV, the lower side
MOSFET will turn on until the output drops below 87%. This is to
protect the overall power trains if a single-channel in a
multimodule system detects an OV. The low-side MOSFET always
turns on at the conditions of EN = LOW and an output voltage
above 113% (all EN pins are tied together) and turns off after the
output drops below 87%. Thus, in a high phase count application
(multimodule mode), all cascaded modules can latch off
simultaneously through the EN pins (EN pins are tied together in
multiphase mode), and each IC shares the same sink current to
reduce the stress and eliminate the bouncing among phases.
Over-temperature Protection (OTP)
When the junction temperature of the IC is greater than +150°C
(typically), the EN pin will be pulled low to inform other cascaded
channels through their EN pins. All connected ENs stay low and
release after the IC’s junction temperature drops below +125°C
(typically), a +25°C hysteresis (typically).
Overcurrent Protection (OCP)
CHANNEL 1 UV/OV
VMON1
The OVP is active from the beginning of soft-start. An overvoltage
(OV) condition (>120%) latches the IC off (the high-side MOSFET
to latch off permanently; the low-side MOSFET turns on
immediately at the time of OV trip and then turns off
permanently after the output voltage drops below 87%). The EN
and PGOOD are also latched low at an OV event. The latch
condition can be reset only by recycling VCC.
The OCP function is enabled at start-up. The load current
sampling ICS1 is sensed by sampling the voltage across Q2
MOSFET rDS(ON) during turn on through the resistor between
OCSET and PHASE pin. IC1 is compared with the Channel
Overcurrent Limit ‘111µA OCP’ comparator, and waits seven
cycles before an OCP condition is declared. The module’s output
current (ICS1) plus a fixed internal 15µA offset forms a voltage
(VISHARE) across the external resistor, RISHARE. VISHARE is
compared with a precision internal 1.2V threshold for a second
method to detect the OCP condition.
Multi-module operation can be achieved by connecting the
ISHARE pin of two or more modules together. In multi-module
operation the voltage on the ISHARE pin correlates to the
average current of all active channels. The output current of each
module in multi-module operation is compared to a precise 1.2V
threshold to determine the overcurrent condition. Additionally,
each module has an overcurrent trip point of 111µA with 7-cycle
delay. Note that it is not necessary for the RISHARE to be scaled
to trip at the same level as the 111µA OCP comparator. Typically
the ISHARE pin average current protection level should be higher
than the phase current protection level.
With an internal RISEN-IN of 2.2kΩ, the OCP level is set to the
default value. To lower the OCP level, an external RISEN-EX is
connected between the OCSET and PHASE pins. The
relationships between the external RISEN-EX values and the
typical output current IOUT(MAX) OCP levels for ISL8200AM are
shown in Figures 32 through 34. Note that the OCP level shown
Page 16 of 25
ISL8200AM
in these graphs is the average output current and not the
inductor ripple current.
In a high input voltage, high output voltage application, such as
20V input to 5V output, the inductor ripple becomes excessive
due to the fixed internal inductor value. In such applications, the
output current will be limited from the rating to approximately
70% of the module’s rated current.
16
1.8VOUT
14
2.5VOUT
OCP (A)
12
When OCP is triggered, the controller pulls EN low immediately to
turn off UGATE and LGATE.
10
1.2VOUT
8
6
4
2
0
0
5
10
RSEN (kΩ)
15
20
FIGURE 32. 5VIN
16
1.2VOUT
14
Fault Handshake
5.0VOUT
OCP (A)
12
In a multi-module system with the EN pins wired-OR together, all
modules can immediately turn off at one time when a fault
condition occurs in one or more modules. A fault pulls the EN pin
low, disabling all the modules and therefore not creating current
bounce. Thus, no single channel is overstressed when a fault
occurs.
1.8VOUT
10
8
6
2.5VOUT
4
2
0
0
10
20
30
40
50
RSEN (kΩ)
Because the EN pins are pulled down under fault conditions, the
pull-up resistor (RUP) should be scaled to sink no more than 5mA
current from EN pin. Essentially, the EN pins cannot be directly
connected to VCC.
Oscillator
FIGURE 33. 12VIN
The oscillator is a sawtooth waveform, providing for leading edge
modulation with 350ns minimum dead time. The oscillator
(sawtooth) waveform has a DC offset of 1.0V. Each channel’s
peak-to-peak of the ramp amplitude is set to be proportional to
the voltage applied to its corresponding FF pin.
16
1.8VOUT
14
For overload and hard short conditions, the overcurrent
protection reduces the regulator RMS output current to much
less than a full load by putting the controller into hiccup mode. A
delay time, equal to three soft-start intervals, is entered to allow
the disturbance to be cleared out. After the delay time, the
controller then initiates a soft-start interval. If the output voltage
comes up and returns to the regulation, PGOOD transitions high.
If the OC trip is exceeded during the soft-start interval, the
controller pulls EN low again. The PGOOD signal will remain low
and the soft-start interval will be allowed to expire. Another
soft-start interval will be initiated after the delay interval. If an
overcurrent trip occurs again, this same cycle repeats until the
fault is removed.
OCP (A)
12
1.2VOUT
10
8
2.5VOUT
6
5.0VOUT
4
2
0
0
20
40
60
80
100
RSEN (kΩ)
FIGURE 34. 20VIN
FN8271 Rev.7.00
Apr 27, 2018
Page 17 of 25
ISL8200AM
Frequency Synchronization and
Phase Lock Loop
The FSYNC_IN pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (RFS) to PGND1 from the FSYNC_IN pin, the switching
frequency can be set at any frequency between 700kHz and
1.5MHz. The ISL8200AM has an integrated 59kΩ resistor between
FSYNC_IN and PGND1, which sets the default frequency to
700kHz. The frequency setting curve shown in Figure 35 is
provided to assist in selecting an externally connected resistor
RFS-ext between FSYNC_IN and PGND1 to increase the switching
frequency.
SWITCHING FREQUENCY (kHz)
1500
DECODING
PH_CNTRL RANGE
PHASE FOR CLKOUT WRT
CHANNEL 1
REQUIRED
PH_CNTRL
<29% of VCC
-60°
15% VCC
29% to 45% of VCC
90°
37% VCC
45% to 62% of VCC
120°
53% VCC
62% to VCC
180°
VCC
Layout Guide
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary, which
are illustrated in Figures 36 and 37.
• The ground connection between PGND1 (Pin 15) and PGND
(Pin 18) should be a solid ground plane under the module.
1400
1300
• Place a high frequency ceramic capacitor between (1) PVIN
and PGND (Pin 18) and (2) a 10µF between PVCC and PGND1
(Pin 15) as close to the module as possible to minimize high
frequency noise. High frequency ceramic capacitors close to
the module between VOUT and PGND will help to minimize
noise at the output ripple.
1200
1100
1000
900
• Use large copper areas for power path (PVIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
800
700
TABLE 2.
0
100
200
300
400
RFS-ext (kΩ)
FIGURE 35. RFS-ext vs SWITCHING FREQUENCY
By connecting the FSYNC_IN pin to an external square pulse
waveform (such as the CLKOUT signal, typically 50% duty cycle
from another ISL8200AM), the ISL8200AM will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The voltage range on the FSYNC_IN pin is VCC/2 to
VCC. The Frequency Synchronization feature will synchronize the
leading edge of the CLKOUT signal with the falling edge of
Channel 1’s PWM clock signal. CLKOUT is not available until the
PLL locks.
The locking time is typically 210µs for fSW = 700kHz. EN is not
released for a soft-start cycle until FSYNC_IN is stabilized and the
PLL is in locking. It is recommended to connect all EN pins
together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles causes
the IC to be disabled until the PLL returns locking, at which point
a soft-start cycle is initiated and normal operation resumes.
Holding FSYNC_IN low will disable the IC.
Setting Relative Phase-shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by the VCC
resistor divider output, the ISL8200AM operates with CLKOUT
phase shifted, as shown in Table 2. The phase shift is latched as
VCC raises above POR so it cannot be changed on the fly.
FN8271 Rev.7.00
Apr 27, 2018
• Keep the trace connection to the feedback resistor short.
• Use remote sensed traces to the regulation point to achieve a
tight output voltage regulation, and keep them in parallel.
Route a trace from VSEN_REM- to a location near the load
ground, and a trace from feedback resistor to the point-of-load
where the tight output voltage is desired.
• Avoid routing any sensitive signal traces, such as the VOUT and
VSENREM- sensing point near the PHASE pin or any other
noise-prone areas.
• FSYNC_IN is a sensitive pin. If it is not used for receiving an
external synchronization signal, then keep the trace
connecting to the pin short. A bypass capacitor value of 100pF,
connecting between FSYNC_IN pin and GND1, can help to
bypass the noise sensitivity on the pin.
The recommended layout considerations for operating multiple
modules in parallel follows the single-phase guidelines as well as
these additional points:
• Orient VOUT toward the load on the same layer and connect
with thick direct copper etch directly to minimize the loss.
• Place modules such that Pins 1 to 11 point away from power
pads (PD1-4) so that signal busses (EN, ISHARE,
CLKOUT-to-FSYNCIN) can be routed without going under the
module. Run them along the perimeter as in Figure 37.
• Keep remote sensing traces separate, and connect only at the
regulation point. Four separate traces for VSEN_REM- and
RFBT (which stands for remote feedback) as the example
shows in Figure 37.
Page 18 of 25
ISL8200AM
TO
LOAD GND
TO
VOUT
RFBT
CEN
CPVCC
CIN
PVIN
COUT
PGND
VOUT
FIGURE 36. RECOMMENDED LAYOUT FOR SINGLE PHASE SETUP
CLKOUT to FSYNC_IN
EN
ISHARE
TO LOAD GND
TO VOUT
TO LOAD GND
TO VOUT
RFBT
RFBT
CEN
CEN
CPVCC
CPVCC
CIN
COUT
CIN
COUT
FIGURE 37. RECOMMENDED LAYOUT FOR DUAL PHASE SETUP
FN8271 Rev.7.00
Apr 27, 2018
Page 19 of 25
ISL8200AM
3.5
12
LOSS (W)
2.5
MAX LOAD CURRENT (A)
3.0
3.3V
2.0
1.5V
1.5
0.8V
1.0
0.5
0.0
0
2
6
4
8
10
8
3.3V
1.5V
6
0.8V
4
2
0
60
10
70
90
100
110
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
FIGURE 38. POWER LOSS vs LOAD CURRENT (5VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
FIGURE 39. DERATING CURVE (5VIN) 0 LFM FOR VARIOUS OUTPUT
VOLTAGES
12
5.0
MAX LOAD CURRENT (A)
4.5
5.0V
4.0
3.5
LOSS (W)
80
3.3V
3.0
2.5
0.8V
2.0
1.5V
2.5V
1.5
1.0
0.5
0.0
0
2
4
6
8
10
LOAD CURRENT (A)
FIGURE 40. POWER LOSS vs LOAD CURRENT (12VIN) 0 LFM FOR
VARIOUS OUTPUT VOLTAGES
Thermal Considerations
Empirical power loss curves, shown in Figures 38 to 41, along
with JA from thermal modeling analysis can be used to evaluate
the module’s thermal requirements. The derating curves are
derived from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
The structure of the ISL8200AM belongs to the Quad Flat-pack
No-lead package (QFN). This kind of package has advantages such
as good thermal and electrical conductivity, low weight, and small
size. The QFN package is applicable for surface mounting
technology and is being more readily used in the industry. The
ISL8200AM contains several types of devices, including resistors,
capacitors, inductors, and control ICs. The ISL8200AM is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multiple component assembly is overmolded with
polymer mold compound to protect these devices.
FN8271 Rev.7.00
Apr 27, 2018
10
8
5.0V
3.3V
6
2.5V
1.5V
0.8V
4
2
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 41. DERATING CURVE (12VIN) 0 LFM FOR VARIOUS
OUTPUT VOLTAGES
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing L23.15x15 on page 23. The module has a small size of
15mmx15mmx2.2mm. Figure 42 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to their application.
PCB Layout Pattern Design
The bottom of the ISL8200AM is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing
L23.15x15 on page 23. The PCB layout pattern is essentially 1:1
with the QFN exposed pad and I/O termination dimensions,
except for the PCB lands being a slightly extended distance of
0.2mm (0.4mm max) longer than the QFN terminations, which
allows for solder filleting around the periphery of the package.
This ensures a more complete and inspectable solder joint. The
thermal lands on the PCB layout should match 1:1 with the
package exposed die pads.
Page 20 of 25
ISL8200AM
Thermal Vias
Reflow Parameters
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under
the thermal land. The vias should be from 0.3mm to 0.33mm in
diameter with the barrel plated with 1.0 ounce copper. Although
adding more vias (by decreasing via pitch) will improve the
thermal performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as practical
for the thermal land size and your board design rules allow.
Due to the low mount height of the QFN, “No Clean” Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
QFN. The profile given in Figure 42 is provided as a guideline to
be customized for varying manufacturing practices and
applications.
300
Stencil Pattern Design
FN8271 Rev.7.00
Apr 27, 2018
250
TEMPERATURE (°C)
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to
help prevent solder bridging between adjacent I/O lands. To
reduce solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the stencil
printing area cover 50% to 80% of the PCB layout pattern. A
typical solder stencil pattern is shown in the Package Outline
Drawing L23.15x15 on page 24. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release,
which reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a “brick like” paste
deposit that assists in firm component placement. A 0.1mm to
0.15mm stencil thickness is recommended for this large pitch
(1.3mm) QFN.
PEAK TEMPERATURE +230°C~+245°C;
TYPICALLY 60s-70s ABOVE +220°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
200 SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +180°C FOR 90s~120s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 42. TYPICAL REFLOW PROFILE
Page 21 of 25
ISL8200AM
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Apr 27, 2018
FN8271.7
Updated Ordering Information table by adding tape and reel parts to table, updating brand of ISL8200AMM
parts, updating Note 1 and its reference location, and added tape and reel quantity column.
Removed About Intersil section and updated disclaimer.
May 12, 2017
FN8271.6
Added ISL8200AMMZ device in ordering information table.
Updated Note 2.
Added ISL8200AMMZ parameters in electrical specification table.
Corrected syntax and grammar errors in “Initialization” on page 14, “Overvoltage Protection (OVP)” on
page 16, and “Fault Handshake” on page 17.
Applied header/footer template.
Jul 30, 2015
FN8271.5
On page 1, in Features, changed “Input Voltage Range +4.5V to +20V at 10A” to “Input Voltage Range +3.0V
to +20V at 10A”
Updated Graphic on page 1
Added Evaluation Board ISL8200AMEV1PHZ to Ordering Information on page 2.
Added Note 8 to Electrical Spec Table on page 9.
Mar 7, 2013
FN8271.4
Features on page 1 Input Voltage Range updated from 3V to 20V to 4.5V to 20V.
Jan 24, 2013
FN8271.3
Made correction in Abs Max Ratings Table under Recommended Operating Conditions on page 7 by
separating in the Input Voltage PVIN and VIN. PVIN is 3V to 20V and VIN 4.5V to 20V.
Jan 2, 2013
Abs Max Ratings Table under Recommended Operating Conditions on page 7 changed Input Voltage, PVIN,
VIN from 3V to 20V to 4.5 to 20V.
Oct 8, 2012
Pin Description Table on page 4 changed in Description column operational voltage range for PVCC and VCC
from “4.5V to 5.5V” to “4.5 to 5.6”
Abs Max Ratings Table under Recommended Operating Conditions on page 7 changed Driver Bias Voltage,
PVCC and Signal Bias Voltage, VCC from “3V to 5.6V” to “4.5V to 5.6V”
Sep 13, 2012
FN8271 Rev.7.00
Apr 27, 2018
FN8271.2
Initial Release.
Page 22 of 25
For the most recent package outline drawing, see L23.15x15.
L23.15x15
23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 3, 10/10
A
3.22
2.2
0.2 H AB
1.02
23 22 21 20
20 21 22
0.05 M H AB
1
2
3
4
5
19
6
7
8
9
10
11
9.9
13.8
4.7
4.26
3.4
4.38
X4
17
0.8
2.28
16
0.2 H AB
17
15.0±0.2
3.4
2.36
1.34
18
16
1
2
4.7
19
35x 0.5
0.82
4.8
(35x 0.40)
15.8±0.2
7x 1.9 ±0.05
23
18
15.0±0.2 15.8±0.2
12 13 14 15
18x 1.3 ±0.1
X4
3x 2.6
18x 0.75
3
4
B
5
6
7
8
10x 1.1 ±0.1
9
10
11
15
11x 0.7
0.90
14 13 12
2.0
5.82
11x 1.85 ±0.05
7x 0.8
TOP VIEW
BOTTOM VIEW
8° ALL AROUND
2.2 ±0.2
NOTES:
S 0.2
Page 23 of 25
S
SIDE VIEW
0.25
S 0.05
1.
Dimensions are in millimeters.
2.
Unless otherwise specified, tolerance : Decimal ± 0.2;
Body Tolerance ±0.2mm
3.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
ISL8200AM
FN8271 Rev.7.00
Apr 27, 2018
Package Outline Drawing
5.18
4.73
4.68
4.03
4.08
3.63
8.15
3.58
2.93
6.88
2.98
5.58
2.48
23
1
0.00
0.00
4.13
0.83
1.53
2.13
2.83
3.43
1.07
0.00
1.77
2.37
0.32
0.77
3.02
1.47
3.52
1.92
4.64
4.13
6.03
6.73
6.78
8.09
6.11
5.67
4.97
4.37
3.67
3.07
2.37
1.77
1.07
0.60
6.48
4.88
5.68
0.93
2.75
3.05
4.03
4.83
6.88
8.14
5.53
5.03
2.08
1.58
0.78
0.18
1.82
0.65
0.00
4.12
4.72
5.22
5.82
6.07
2.32
4.07
4.77
5.17
5.87
6.02
3.12
3.02
3.62
3.62
8.15
3.67
3.43
5.62
2.97
2.92
3.62
4.22
4.92
5.52
6.82
8.10
2.52
0.00
2.57
2.83
1.87
2.13
1.47
1.48
0.37
0.77
0.78
0.28
0.88
0.00
1.68
0.13
0.33
4.42
3.07
1.38
2.18
4.92
3.67
1.88
1.43
0.73
6.06
5.72
8.10
6.48
5.48
4.88
4.18
3.58
2.88
2.28
1.58
0.98
0.28
0.00
0.32
1.02
1.62
2.32
0.00
2.53
1.83
4.37
5.78
5.13
4.97
6.03
t
5.72
8.14
6.88
4.68
4.18
0.78
1.02
0.00
1.82
2.32
3.12
3.62
4.42
4.92
5.72
5.83
STENCIL PATTERN WITH SQUARE PADS-1
TYPICAL RECOMMENDED LAND PATTERN
6.73
6.23
4.18
4.68
4.38
3.88
1.83
2.33
1.53
0.00
0.52
0.82
2.87
3.17
4.69
4.99
6.52
0.00
0.52
0.82
2.82
3.67
6.48
4.58
4.28
2.23
1.48
0.88
0.13
0.00
5.50
5.80
6.52
0.60
Page 24 of 25
1.53
STENCIL PATTERN WITH SQUARE PADS-2
ISL8200AM
FN8271 Rev.7.00
Apr 27, 2018
5.98
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2018 Renesas Electronics Corporation. All rights reserved.
Colophon 7.0