ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Automotive High-Speed Low-Power Digital Optocouplers with R2Coupler® Isolation and AEC-Q100 Grade 1 Qualification Data Sheet Description Features The ACPL-K71T and ACPL-K72T are high-speed digital CMOS optocouplers package suitable for emerging electric vehicle applications. The ACPL-K74T and ACPL-K75T are dual-channel equivalents of the ACPL-K71T and ACPL-K72T, respectively. All products are available in the stretched SO-8 package outline, designed to be compatible with standard surface mount processes. ACPL-K71T and ACPL-K74T are high-speed mode with fastest propagation delay (maximum 35 ns at IF = 10 mA) while ACPL-K72T and ACPL-K75T are low-power mode with lowest LED drive current of 4 mA for standard digital isolation switching. Each channel of the digital optocoupler has a CMOS detector IC with an integrated photodiode, a high-speed trans-impedance amplifier, and a voltage comparator with an output driver. Qualified to AEC-Q100 Grade 1 Test Guidelines Automotive wide temperature range: –40°C to 125°C High temperature and reliability, high-speed digital interface for automotive applications 5-V CMOS compatibility 40 kV/μs common-mode rejection at VCM = 1000V typ. Low propagation delay: — ACPL-K71T, ACPL-K74T: 25 ns typ. @ IF = 10 mA — ACPL-K72T, ACPLK75T: 60 ns typ. @ IF = 4 mA Worldwide safety approval: — UL 1577 approval, 5kVRMS /1 min. — CSA approval — IEC/EN/DIN EN 60747-5-5 The Broadcom R2Coupler® provides with reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high-temperature industrial applications. Applications CAUTION Take normal static precautions in handling and assembly of this component to prevent damage. degradation, or both that might be induced by electrostatic discharge (ESD). Broadcom -1- CAN Bus and SPI communications interface High-temperature digital/analog signal isolation Automotive IPM driver for DC-DC converters and motor inverters Power transistor isolation ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Functional Diagrams Functional Diagrams Table 1 Truth Table Figure 1 ACPL-K71T/ACPL-K72T NOTE LED Vo ON LOW OFF HIGH The connection of a 0.1-μF bypass capacitor between pins 5 and 8 is recommended. Table 2 Pin Assignments for ACPL-K71T/ACPL-K72T Pin No. Pin Name Description Pin No. Pin Name Description 1 AN Anode 5 GND Ground 2 CA Cathode 6 NC No Connection 3 NC No Connection 7 VOUT Output 4 NC No Connection 8 VDD Power Supply Figure 2 ACPL-K74T/ACPLK75T NOTE The connection of a 0.1-μF bypass capacitor between pins 5 and 8 is recommended. Table 3 Pin Assignments for ACPL-K74T/ACPL-K75T Pin No. Pin Name Description Pin No. Pin Name Description 1 AN1 Anode 1 5 GND Ground 2 CA1 Cathode 1 6 VOUT2 Output 2 3 CA2 Cathode 2 7 VOUT1 Output 1 4 AN2 Anode 2 8 VDD Power Supply Broadcom -2- ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Ordering Information Ordering Information Part Number ACPL-K71T ACPL-K72T ACPL-K74T ACPL-K75T Option (RoHS Compliant) -000E Package UL 5000 VRMS / IEC/EN/DIN EN 1 Minute Rating 60747-5-5 X X -060E X X -500E X X X -560E X X X -000E Stretched SO-8 Surface Mount Tape and Reel X X -060E X X -500E X X X -560E X X X -000E Stretched SO-8 X X -060E X X -500E X X X -560E X X X -000E Stretched SO-8 Stretched SO-8 X X -060E X X -500E X X X -560E X X X Quantity 80 per tube X 80 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-K71T-560E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Broadcom -3- ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Package Outline Dimensions (Stretched SO8) Package Outline Dimensions (Stretched SO8) RECOMMENDED LAND PATTERN 5.850 ± 0.254 (0.230 ± 0.010) 8 7 6 5 12.650 (0.498) 6.807 ± 0.127 (0.268 ± 0.005) RoHS-COMPLIANCE INDICATOR 1.905 (0.075) 1 2 3 4 0.64 (0.025) 7° 1.590 ± 0.127 (0.063 ± 0.005) 45° 0.450 (0.018) 3.180 ± 0.127 (0.125 ± 0.005) 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 0.200 ± 0.100 (0.008 ± 0.004) 0.381 ± 0.127 (0.015 ± 0.005) 1.270 (0.050) BSG 0.254 ± 0.100 (0.010 ± 0.004) Dimensions in millimeters and (inches). Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25mm (10mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). NOTE Use non-halide flux. Regulatory Information The ACPL-K71T, ACPL-K72T, ACPL-K74T and ACPL-K75T are approved by the following organizations: Table 4 Regulatory Information UL Approval under UL 1577, component recognition program up to VISO = 5 kVRMS. CSA Approval under CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 Approval under IEC/EN/DIN EN 60747-5-5. Broadcom -4- ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Insulation and Safety-Related Specifications Insulation and Safety-Related Specifications Parameter Symbol Units Conditions Minimum External Air Gap (Clearance) L(101) 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 IIIa — Material Group (DIN VDE 0109) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group (DIN VDE0109) IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060 Only) Description Symbol Characteristic Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 600 V rms I-IV for rated mains voltage ≤ 1000 V rms I-III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 1140 VPEAK Input to Output Test Voltage, Method b VIORM × 1.875 = VPR, 100% Production Test with tm = 1 s, Partial Discharge < 5 pC VPR 2137 VPEAK Input to Output Test Voltage, Method a VIORM × 1.6 = VPR, Type and sample test, tm = 10s, Partial Discharge < 5 pC VPR 1824 VPEAK Highest Allowable Overvoltage (Transient Overvoltage, tini = 60s) VIOTM 8000 VPEAK Case Temperature TS 175 °C Input Current IS,INPUT 230 mA Output Power PS,OUTPUT 600 mW RS 109 Safety Limiting Values (Maximum values allowed in the event of a failure) Insulation Resistance at TS, VIO = 500V Broadcom -5- ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min. Max. Units Test Conditions Storage Temperature TS –55 130 °C — Ambient Operating Temperature TA –40 125 °C — Supply Voltages VDD 0 6.5 V — Output Voltage VO –0.5 VDD +0.5 V — Average Forward Input Current IF — 20.0 mA — Peak Transient Input Current IF(TRAN) — 1 A ≤ 1-μs Pulse Width, 300 pps — 80 mA ≤ 1-μs Pulse Width, <10% Duty Cycle Reverse Input Voltage Vr — 5 V — Input Power Dissipation PI — 40 mW — Output Power Dissipation Po — 30 mW — Lead Solder Temperature — 260°C for 10s., 1.6 mm below seating plane Solder Reflow Temperature Profile — See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Supply Voltage VCC 3.0 5.5 V Operating Temperature TA –40 125 °C Forward Input Current IF(ON) 4 15 mA Forward Off State Voltage VF(OFF) — 0.8 V Input Threshold Current ITH — 3.5 mA Note Electrical Specifications Over recommended temperature TA = –40°C to 125°C, 3.0V ≤ VDD ≤ 5.5V. All typical specifications are at TA = 25°C, VDD = 5V. Parameter LED Forward Voltage Symbol VF Min. 1.45 1.25 Typ. 1.5 1.5 Max. 1.75 1.85 Units Test Conditions V V IF=10 mA Figure IF=10 mA, TA=25°C Vf Temperature Coefficient — — –1.5 — mV/°C — Input Capacitance CIN — 90 — pF — Input Reverse Breakdown Voltage BVR 5.0 — — V IR = 10 μA Logic High Output Voltage VOH VDD – 0.6 — — V IOH = –3.2 mA 6 Logic Low Output Voltage VOL — — 0.6 V IOL = 4 mA 5 Logic Low Output Supply Current (per channel) IDDL — 0.9 1.5 mA — Logic High Output Supply Current (per channel) IDDH — 0.9 1.5 mA — Broadcom -6- Notes ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet ACPL-K71T, ACPL-K74T High-Speed Mode Switching Specifications ACPL-K71T, ACPL-K74T High-Speed Mode Switching Specifications Over recommended temperature TA = –40°C to 125°C, 4.5V ≤ VDD ≤ 5.5V. All typical specifications are at TA = 25°C, VDD = 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low tPHL Output — 25 35 ns VIN = 4.5V to 5.5V, RIN = 390 ± 5%, CIN = 100 pF, CL = 15 pF, VTHL = 0.8V, VTLH = 80% of VDD Propagation Delay Time to Logic High Output tPLH — 25 35 ns — Pulse Width Distortion PWD — 0 12 ns — Propagation Delay Skew tPSK — — 15 ns — Output Rise Time (10% – 90%) tR — 10 — ns — Output Fall Time (90% - 10%) tF — 10 — ns — Common Mode Transient Immunity at Logic High Output | CMH | 15 25 — kV/μs Common Mode Transient Immunity at Logic High Output | CML | 15 25 — kV/μs a. Figure Notes 7, 8, 13 a b c VIN = 0V, RIN = 390 ± 5%, CIN = 100 pF, VCM = 1000V, TA = 25°C 14 d VIN = 4.5V to 5.5V, RIN = 390 ± 5%, CIN = 100 pF, VCM = 1000V, TA = 25°C 14 e , , tPHL propagation delay is measured from the 50% (VIN or IF) on the rising edge of the input pulse to the 0.8V of VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (VIN or IF) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal. b. PWD is defined as |tPHL – tPLH|. c. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. d. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. e. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. Broadcom -7- ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet ACPL-K72T, ACPL-K75T Low-Power Mode Switching Specifications ACPL-K72T, ACPL-K75T Low-Power Mode Switching Specifications Over recommended temperature TA = –40°C to 125°C, 3.0V ≤ VDD ≤ 5.5V. All typical specifications are at TA=25°C, VDD= 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low tPHL Output — 60 100 ns IF = 4 mA, CL= 15 pF, VTHL = 0.8V, VTLH = 80% of VDD Propagation Delay Time to Logic High Output tPLH — 35 100 ns — Pulse Width Distortion PWD — 25 50 ns — Propagation Delay Skew tPSK — — 60 ns — Output Rise Time (10%–90%) tR — 10 — ns — Output Fall Time (90%–10%) tF — 10 — ns — Common Mode Transient Immunity at Logic High Output | CMH | 25 40 — kV/μs Common Mode Transient Immunity at Logic High Output | CML | 25 40 — kV/μs a. Figure Notes 9, 10, 11, 12, 15 ab c LED Driving Circuit Fig 13, VIN = 0V, R1 = 350 ± 5%, R2 = 350 ± 5%, VCM = 1000V, TA = 25°C 16 d LED Driving Circuit Fig 14, VIN = 4.5V to 5.5V, R1 = 350 ± 5%, R2 = 350 ± 5%, VCM = 1000V, TA = 25°C 16 e , tPHL propagation delay is measured from the 50% (VIN or IF) on the rising edge of the input pulse to the 0.8V of VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (VIN or IF) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal. b. PWD is defined as |tPHL – tPLH|. c. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. d. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. e. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. Package Characteristics All Typical at TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Notes Input-Output Momentary Withstand Voltage VISO 5000 — — VRMS RH ≤ 50%, t = 1 minute, TA = 25°C a b Input-Output Resistance RI-O — 1014 — VI-O = 500V dc a Input-Output Capacitance CI-O — 0.6 — pF f = 1 MHz, TA = 25°C a a. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. b. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000VRMS for 1 second. Broadcom -8- , ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Performance Plots Performance Plots Figure 4 Typical Output Voltage vs. Input Forward Current Figure 3 Typical Diode Input Forward Current Characteristic 5 100.00 Vo - Output Voltage (V) IF - Forward Current (mA) Ta = 25°C 10.00 1.00 0.10 0.01 1.3 1.4 1.5 VF - Forward Voltage - V 2 1 1.6 VOH - Logic High Output Voltage - V 0.500 0.400 0.300 0.200 0.100 0 2 4 6 8 IOL - Logic Low Output Current - mA 1 1.5 IF - Forward Current - mA 2 4.8 4.6 4.4 4.2 4.0 10 Figure 7 ACPL-K71T/K74T (High Speed) Typical Propagation Delay vs. Temperature 0 -2 -4 -6 -8 IOH - Logic High Output Current - mA -10 Figure 8 ACPL-K71T/K74T (High Speed) Typical Propagation Delay vs. Input Forward Current 40 Tp - Propagation Delay, PWD - Pulse Width Distortion - ns 40 Tp - Propagation Delay, PWD - Pulse Width Distortion - ns 0.5 5.0 0.600 35 30 25 20 TPHL Vin=4.5V, Rin=390:, Cin=100pF TPLH PWD 15 10 5 0 0 Figure 6 Typical Logic High Output Voltage vs. Logic High Output Current 0.700 VOL - Logic Low Output Voltage - V 3 0 1.2 Figure 5 Typical Logic Low Output Voltage vs. Logic Low Output Current 0.000 4 -40 -20 0 20 40 60 80 Temperature - °C 100 120 35 30 25 20 15 10 5 0 -5 140 Broadcom -9- TPHL Rin=390:, Cin=100pF TPLH Ta=25°C PWD 3 4 5 6 7 8 9 10 11 12 13 14 15 IF - Forward Current - mA ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Performance Plots Figure 9 ACPL-K72T/K75T (5V) Typical Propagation Delay vs. Temperature Figure 10 ACPL-K72T/K75T (5V) Typical Propagation Delay vs. Input Forward Current 60 70 40 30 20 TPHL TPLH PWD 10 0 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 40 30 20 10 3 4 5 6 7 8 9 10 11 12 IF - FORWARD CURRENT - mA 13 14 15 Figure 12 ACPL-K72T/K75T (3V) Typical Propagation Delay vs. Input Forward Current 80 IF = 4mA, V DD =3V TPHL TPLH PWD 70 50 40 30 20 TPHL TPLH PWD TA=25°C, V DD =3V 70 60 60 50 40 30 20 10 10 0 -40 50 -10 120 TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns 80 TPHL TPLH PWD 0 Figure 11 ACPL-K72T/K75T (3V) Typical Propagation Delay vs. Temperature 90 TA=25°C, V DD =5V 60 50 TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns IF = 4mA, V DD =5V -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 0 120 Broadcom - 10 - 3 4 5 6 7 8 9 10 11 IF - FORWARD CURRENT - mA 12 13 14 15 ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet ACPL-K71T/K74T High-Speed Mode ACPL-K71T/K74T High-Speed Mode Figure 13 High-Speed Mode Switching Test Circuit and Typical Waveform C IN 100pF V IN 4.5V to 5.5V + ACPL-K71T VDD 5V 1 8 2 7 3 6 R 1 390±5% _ 0.1 μ F V IN VO monitoring node VO V TLH V THL C L = 15pF 4 VIN /2 V IN /2 tPLH tPHL 5 GND2 GND1 Figure 14 High-Speed Mode CMR Test Circuit and Typical Waveform C IN 100pF ACPL-K71T V DD 5V 1 V IN 4.5V to 5.5V 8 R 1 390±5% T r = tf ≤ 80 ns 0.1 μ F 2 7 3 1000V VO monitoring node 6 tr C L = 15pF 4 _ + GND1 V OH 5 90% 10% 90% 10% V CM tf Switch at LED=Off V OL Switch at LED=On GND2 High Voltage Pulse VCM ACPL-K72T/K75T Low-Power Mode: Figure 15 Low-Power Mode Switching Test Circuit and Typical Waveform ACPL-K72T V IN 4.5V to 5.5V + _ V DD 3V to5V 1 8 2 7 3 6 0.1 μ F R IN 700 VO monitoring node C L = 15pF 4 V IN V IN /2 VO V THL V TLH 5 tPHL GND1 V IN /2 GND2 Broadcom - 11 - tPLH ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Recommended Application Circuits Figure 16 Low-Power Mode CMR Test Circuit ACPL-K72T V DD 5V 1 V IN 4.5V to 5.5V 8 R 1 350 T r =t f ≤ 80 ns 0.1 μ F 2 7 3 6 4 5 1000V VO monitoring node C L = 15pF R 2 350 + GND1 90% 10% tr V OH V OL _ 90% 10% V CM tf Switch at LED=Off Switch at LED=On GND2 High Voltage Pulse V CM Recommended Application Circuits Figure 17 Recommended Application Circuit for ACPL-K71T/K74T High-Speed Performance C IN 100pF Truth Table ACPL-K71T V IN 1 V DD 8 R1 GND1 0.1 μ F 2 7 3 6 4 5 VO VIN LED Vo LOW ON LOW HIGH OFF HIGH GND2 Figure 18 Recommended Application Circuit for ACPL-K72T/K75T Low-Power Performance ACPL-K72T V IN 1 8 2 7 3 6 4 5 R1 R1 = R 2 VIN 0.1 μ F VO R2 GND1 Truth Table V DD GND2 Broadcom - 12 - LED Vo LOW ON LOW HIGH OFF HIGH ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Thermal Resistance Model for ACPL-K71T/K72T Thermal Resistance Model for ACPL-K71T/K72T The diagram of ACPL-K71T/K72T for measurement is shown in Figure 19. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 2 by 2 matrix for our case of two heat sources. R11 R12 R21 R22 × P1 P2 = T1 T2 Figure 19 Diagram of ACPL-K71T/K72T for Measurement 1 2 8 Die1: LED Die2: Detector 7 3 6 4 5 R11 R12 R21 R22 : Thermal Resistance of Die1 due to heating of Die1 (°C/W) : Thermal Resistance of Die1 due to heating of Die2 (°C/W) : Thermal Resistance of Die2 due to heating of Die1 (°C/W) : Thermal Resistance of Die2 due to heating of Die2 (°C/W) P1 P2 : Power dissipation of Die1 (W) : Power dissipation of Die2 (W) T1 T2 : Junction temperature of Die1 due to heat from all dice (°C) : Junction temperature of Die2 due to heat from all dice (°C) Ta : Ambient temperature (°C) T1 T2 : Temperature difference between Die1 junction and ambient (°C) : Temperature deference between Die2 junction and ambient (°C) T1 T2 = (R11 × P1 + R12 × P2) + Ta = (R21 × P1 + R22 × P2) + Ta Measurement data on a low K board: R11 = 160°C/W, R12 = R21 = 74°C/W, R22 = 115°C/W Broadcom - 13 - ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Thermal Resistance Model for ACPL-K74T/K75T Thermal Resistance Model for ACPL-K74T/K75T The diagram of ACPL-K74T/K75T for measurement is shown in Figure 20. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second, third and fourth die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of two heat sources.. T1 R11 R12 R13 R14 P1 R21 R22 R23 R24 R31 R32 R33 R34 P3 T3 R41 R42 R43 R44 P4 T4 × P2 = Figure 20 Diagram of ACPL-K74T/K75T for Measurement 1 8 Die1: LED 1 Die2: Detector 1 2 3 4 7 Die3: LED 1 Die4: Detector 2 6 5 R11 R12 R13 R14 : Thermal Resistance of Die1 due to heating of Die1 (°C/W) : Thermal Resistance of Die1 due to heating of Die2 (°C/W) : Thermal Resistance of Die1 due to heating of Die3 (°C/W) : Thermal Resistance of Die1 due to heating of Die4 (°C/W) R21 R22 R23 R24 : Thermal Resistance of Die2 due to heating of Die1 (°C/W) : Thermal Resistance of Die2 due to heating of Die2 (°C/W) : Thermal Resistance of Die2 due to heating of Die3 (°C/W) : Thermal Resistance of Die2 due to heating of Die4 (°C/W) R31 R32 R33 R34 : Thermal Resistance of Die3 due to heating of Die1 (°C/W) : Thermal Resistance of Die3 due to heating of Die2 (°C/W) : Thermal Resistance of Die3 due to heating of Die3 (°C/W) : Thermal Resistance of Die3 due to heating of Die4 (°C/W) R41 R42 R43 R44 : Thermal Resistance of Die4 due to heating of Die1 (°C/W) : Thermal Resistance of Die4 due to heating of Die2 (°C/W) : Thermal Resistance of Die4 due to heating of Die3 (°C/W) : Thermal Resistance of Die4 due to heating of Die4 (°C/W) P1 P2 P3 P4 : Power dissipation of Die1 (W) : Power dissipation of Die2. : Power dissipation of Die3 (W) : Power dissipation of Die4. T1 T2 T3 T4 : Junction temperature of Die1 due to heat from all dice (°C) : Junction temperature of Die2 due to heat from all dice (°C) : Junction temperature of Die3 due to heat from all dice (°C) : Junction temperature of Die4 due to heat from all dice (°C) Broadcom - 14 - T2 ACPL-K71T, ACPL-K72T, ACPL-K74T, and ACPL-K75T Data Sheet Thermal Resistance Model for ACPL-K74T/K75T Ta : Ambient temperature (C) T1 T2 T3 T4 : Temperature difference between Die1 junction and ambient (°C) : Temperature deference between Die2 junction and ambient (°C) : Temperature difference between Die3 junction and ambient (°C) : Temperature deference between Die4 junction and ambient (°C) T1 T2 T3 T4 = (R11 × P1 + R12 × P2 + R13 × P3 + R14 × P4) + Ta -- (1) = (R21 × P1 + R22 × P2 + R23 × P3 + R24 × P4) + Ta -- (2) = (R31 × P1 + R32 × P2 + R33 × P3 + R34 × P4) + Ta -- (3) = (R41 × P1 + R42 × P2 + R43 × P3 + R44 × P4) + Ta -- (4) Measurement data on a low K board: R11 R12 R13 R14 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44 160 76 76 76 76 115 76 76 76 76 160 76 76 76 76 115 Broadcom - 15 - For product information and a complete list of distributors, please go to our web site: www.broadcom.com. Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, the A logo, and R2Coupler are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Copyright © 2012–2017 by Broadcom. All Rights Reserved. The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV02-3786EN – January 25, 2017