The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB90340E Series
F2MC-16LX 16-bit Microcontroller
Datasheet
The MB90340E series with up to 2 FULL-CAN interfaces is especially designed for automotive and other industrial applications. Its
main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message
buffer scheme and so offering more functions than a normal full CAN approach.
The power to the MCU core (3 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior performance in
terms of power consumption and tolerance to EMI.
Features
CPU
Resolution is selectable between 8-bit and 10-bit.
Instruction system best suited to controller
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide
instructions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
Activation by external trigger input is allowed.
Instruction system compatible with high-level language (C
language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
Increased processing speed
- 4-byte instruction queue
Address match detection (program patch) function
Detects address matches against 6 address pointers
Timer
Time-base timer, watch timer, watchdog timer : 1 channel
8/16-bit PPG timer : 8-bit 16 channels, or 16-bit 8
channels
16-bit reload timer : 4 channels
Serial interface
LIN-UART : 4 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial transmission
is available
I2C interface : 2 channels (only for devices with a C suffix in
the part number)
- Up to 400 kbps transfer rate
Interrupt controller
16-bit input/output timer
- 16-bit free-run timer : 2 channels
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/
5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
Full-CAN controller
Up to 2 channels
Compliant with Ver2.0A and Ver2.0B CAN specifications
Powerful 8-level, 34-condition interrupt feature
Up to 16 external interrupts are supported
I/O ports
General-purpose input/output port (CMOS output)
- 80 ports (for devices without an S suffix in the part number i.e. devices that support the sub clock)
- 82 ports (for devices with an S suffix in the part number - i.e.
devices that do not support the sub clock)
8/10-bit A/D converter
16 channels (only for devices without a C suffix in the part
number)
24 channels (only for devices with a C suffix in the part
number)
•
16 built-in message buffers
CAN wake-up function
Automatic data transfer function independent of CPU
- Expanded intelligent I/O service function (EI2OS) : up to 16
channels
Cypress Semiconductor Corporation
Document Number: 002-04498 Rev. *A
Conversion time : 3 s (at 24 MHz machine clock, including
sampling time)
Low power consumption (standby) mode
Sleep mode (a mode that halts CPU operating clock)
Timebase timer mode (a mode where only the oscillation
clock, sub clock, timebase timer and watch timer operate)
Watch mode (a mode that operates sub clock and watch
timer only)
Stop mode (a mode that stops oscillation clock and sub
clock)
CPU intermittent operation mode
Clock modulation circuit
Technology
CMOS technology
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2016
MB90340E Series
Contents
Product Lineup ................................................................ 3
Pin Assignments .............................................................. 6
Pin Description ............................................................... 12
I/O Circuit Type ............................................................... 19
Handling Devices ............................................................ 23
Block Diagrams .............................................................. 26
Memory Map .................................................................... 28
I/O Map ............................................................................ 30
CAN Controllers .............................................................. 41
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 48
Electrical Characteristics ............................................... 50
Absolute Maximum Ratings ....................................... 50
Recommended Operating Conditions ....................... 52
DC Characteristics .................................................... 53
AC Characteristics ..................................................... 55
Clock Timing .............................................................. 55
Reset Standby Input .................................................. 58
Power On Reset ........................................................ 59
Document Number: 002-04498 Rev. *A
Clock Output Timing .................................................. 59
Bus Timing (Read) .................................................... 60
Bus Timing (Write) ..................................................... 61
Ready Input Timing ................................................... 62
Hold Timing ............................................................... 63
LIN-UART0/1/2/3 ....................................................... 64
Trigger Input Timing .................................................. 69
Timer Related Resource Input Timing ....................... 70
Timer Related Resource Output Timing .................... 70
I2C Timing ................................................................. 71
A/D Converter ............................................................ 72
Definition of A/D Converter Terms ........................... 73
Notes on A/D Converter Section ............................... 74
Flash Memory Program/Erase Characteristics ......... 76
Example Characteristics ................................................ 77
Ordering Information ...................................................... 86
Package Dimensions ...................................................... 89
Major Changes ................................................................ 91
Page 2 of 92
MB90340E Series
1. Product Lineup
Part Number
MB90V340E-101,
MB90V340E-102
Parameter
Type
Evaluation products
CPU
F2MC-16LX
System clock
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
Flash memory products
MASK ROM products
CPU
On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL 6)
External
512 Kbytes :
MB90F345E(S), MB90F345CE(S)
256 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90F349E(S), MB90F349CE(S)
128 Kbytes :
MB90F347E(S), MB90F347CE(S)
64 Kbytes :
MB90F346E(S), MB90F346CE(S)
256 Kbytes :
MB90342E(S), MB90342CE(S),
MB90349E(S), MB90349CE(S)
128 Kbytes :
MB90341E(S), MB90341CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S)
64 Kbytes :
MB90346E(S), MB90346CE(S)
RAM
30 Kbytes
20 Kbytes :
MB90F345E(S), MB90F345CE(S)
16 Kbytes :
MB90F342E(S), MB90F342CE(S),
MB90F349E(S), MB90F349CE(S)
6 Kbytes :
MB90F347E(S), MB90F347CE(S)
2 Kbytes :
MB90F346E(S), MB90F346CE(S)
16 Kbytes :
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
6 Kbytes :
MB90347E(S), MB90347CE(S)
2 Kbytes :
MB90346E(S), MB90346CE(S)
Emulator-specific power
supply*
Yes
Technology
0.35 m CMOS with
regulator for built-in
power supply
0.35 m CMOS with built-in power supply regulator
Flash memory with Charge pump for programming voltage
Operating
voltage range
5 V 10
3.5 V to 5.5 V : When normal operating (not using A/D converter)
4.0 V to 5.5 V : When using the A/D converter/Flash programming
4.5 V to 5.5 V : When using the external bus
ROM
Temperature range
40°C to 105°C
Package
PGA-299
QFP-100, LQFP-100
5 channels
4 channels
LIN-UART
I2C (400 kbps)
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2 channels
Devices with a C suffix in the part number : 2 channels
Devices without a C suffix in the part number :
(Continued)
Document Number: 002-04498 Rev. *A
Page 3 of 92
MB90340E Series
Part Number
MB90V340E-101,
MB90V340E-102
Parameter
24 input channels
A/D Converter
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
Devices with a C suffix in the part number
Devices without a C suffix in the part number
: 24 channels
: 16 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function
16-bit Free-run
Timer (2 channels)
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock freq.)
Free-run Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
Free-run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(8 channels)
Generates an interrupt signal when one of the 16-bit free-run timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture
(8 channels)
Captures the value of the 16-bit free-run timer and generates an interrupt when triggered by a pin input (rising
edge, falling edge, or both rising and falling edges).
8/16-bit
Programmable Pulse
Generator
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
3 channels
CAN Interface
2 channels :
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S)
1 channel :
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
2 channels :
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S)
1 channel :
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Document Number: 002-04498 Rev. *A
Page 4 of 92
MB90340E Series
(Continued)
Part Number
MB90V340E-101,
MB90V340E-102
Parameter
MB90F342E(S), MB90F342CE(S),
MB90F345E(S), MB90F345CE(S),
MB90F346E(S), MB90F346CE(S),
MB90F347E(S), MB90F347CE(S),
MB90F349E(S), MB90F349CE(S)
MB90341E(S), MB90341CE(S),
MB90342E(S), MB90342CE(S),
MB90346E(S), MB90346CE(S),
MB90347E(S), MB90347CE(S),
MB90348E(S), MB90348CE(S),
MB90349E(S), MB90349CE(S)
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A Converter
2 channels
Sub clock
(maximum 100 kHz)
Only for
MB90V340E-102
Devices with sub clock : devices without an S suffix in the part number
Devices without sub clock : devices with an S suffix in the part number
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 cycles
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (except for
MB90F346E(S) and MB90F346CE (S) )
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01-E) is used.
Please refer to the Emulator operation manual for details.
Document Number: 002-04498 Rev. *A
Page 5 of 92
MB90340E Series
2. Pin Assignments
MB90341E(S), MB90342E(S), MB90F342E(S), MB90F345E(S), MB90346E(S), MB90F346E(S),
MB90347E(S), MB90F347E(S), MB90348E(S), MB90349E(S), MB90F349E(S)
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
MD2
MD0
MD1
RST
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/INT7
P76/INT6
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
49
82
48
83
47
84
46
85
45
86
44
87
43
88
QFP - 100
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A *
P41/X1A *
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/FRCK0
P45/FRCK1
P46
P47
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14
P34/HRQ/OUT4
P35/HAK/OUT5
P32/WRLX/WRX/INT10R
P33/WRH
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
(Continued)
Document Number: 002-04498 Rev. *A
Page 6 of 92
MB90340E Series
(Continued)
RST
MD0
MD1
MD2
P75/INT5
P74/INT4
P73/INT3
P72/INT2
P71/INT1
P70/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/FRCK0
P45/FRCK1
P46
P47
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
49
77
48
78
47
79
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
LQFP - 100
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
P32/WRL/WR/INT10R
P33/WRH
P34/HRQ/OUT4
P35/HAK/OUT5
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/INT7
P76/INT6
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
(TOP VIEW)
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P4 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A
Page 7 of 92
MB90340E Series
MB90341CE(S), MB90342CE(S), MB90F342CE(S), MB90F345CE(S), MB90346CE(S), MB90F346CE(S), MB90347CE(S),
MB90F347CE(S), MB90348CE(S), MB90349CE(S), MB90F349CE(S)
RST
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14
P33/WRH
P34/HRQ/OUT4
P31/RD/IN5
P32/WRL/WR/INT10R
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
QFP - 100
90
41
91
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
MD0
MD1
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
(TOP VIEW)
(FPT-100P-M06)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
(Continued)
Document Number: 002-04498 Rev. *A
Page 8 of 92
MB90340E Series
(Continued)
RST
MD0
MD1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P33/WRH
P34/HRQ/OUT4
P31/RD/IN5
P32/WRL/WR/INT10R
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
LQFP - 100
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
(TOP VIEW)
(FPT-100P-M20)
* : X0A, X1A : devices without an S suffix in the part number
P40, P41 : devices with an S suffix in the part number
Document Number: 002-04498 Rev. *A
Page 9 of 92
MB90340E Series
MB90V340E-101/MB90V340E-102
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
RST
MD0
MD1
MD2
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
90
41
QFP - 100
91
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA01
P24/A20/IN0
P25/A21/IN1
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P34/HRQ/OUT4
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
P56/AN14/DA00
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
(FPT-100P-M06)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
(Continued)
Document Number: 002-04498 Rev. *A
Page 10 of 92
MB90340E Series
(Continued)
MD0
MD1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
AVRL
AVRH
AVcc
P57/AN15/DA01
P56/AN14/DA00
P55/AN13
P54/AN12/TOT3
P36/RDY/OUT6
P37/CLK/OUT7
P40/X0A*
P41/X1A*
Vcc
Vss
C
P42/IN6/RX1/INT9R
P43/IN7/TX1
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P46/SDA1
P47/SCL1
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P32/WRL/WR/RX2/INT10R
P33/WRH/TX2
P34/HRQ/OUT4
P35/HAK/OUT5
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
38
88
LQFP - 100
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P26/A22/IN2
P27/A23/IN3
P30/ALE/IN4
P31/RD/IN5
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
P81/TOT0/CKOT/INT13R
P80/TIN0/ADTG/INT12R
P77/AN23/INT7
P76/AN22/INT6
RST
P00/AD00/INT8
PA1/TX0
PA0/RX0/INT8R
P97/OUT3
P96/OUT2
P95/OUT1
P94/OUT0
P93/PPG7(6)
P92/PPG5(4)
P91/PPG3(2)
P90/PPG1(0)
Vss
Vcc
P87/SCK1
P86/SOT1
P85/SIN1
P84/SCK0/INT15R
P83/SOT0/TOT2
P82/SIN0/TIN2/INT14R
(TOP VIEW)
(FPT-100P-M20)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
This pin assignment is for using MB90V340E-101/102 via probecable as MB90340E.
Document Number: 002-04498 Rev. *A
Page 11 of 92
MB90340E Series
3. Pin Description
Pin No.
1
QFP100*
LQFP100*
2
Pin name
I/O
Circuit
type*3
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O
port when the corresponding bit in the external address output control register
(HACR) is 1.
P24 to P27
1 to 4
5
6
7
99 to 2
G
A20 to A23
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A20 to A23).
IN0 to IN3
Trigger input pins for input captures.
P30
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
3
G
ALE
Address latch enable output pin. This function is enabled when the external bus
is enabled.
IN4
Trigger input pin for input capture.
P31
General purpose I/O pin.The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
4
G
RD
External read strobe output pin. This function is enabled when the external bus is
enabled.
IN5
Trigger input pin for input capture.
P32
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
WR/WRL pin output is disabled.
5
G
WR / WRL
8
Function
Write strobe output pin for the external data bus. This function is enabled when
both the external bus and the WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
INT10R
External interrupt request input pin.
P33
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.This function is enabled either in single-chip mode or when the
WRH pin output is disabled.
6
G
WRH
Write strobe output pin for the upper 8 bits of the external data bus. This function
is enabled when the external bus is enabled, when the external bus 16-bit mode
is selected, and when the WRH output pin is enabled.
(Continued)
Document Number: 002-04498 Rev. *A
Page 12 of 92
MB90340E Series
Pin No.
1
QFP100*
Pin name
2
LQFP100*
I/O
Circuit
type*3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
P34
9
10
7
G
HRQ
Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
OUT4
Waveform output pin for output compare.
P35
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
hold function is disabled.
8
G
HAK
11
Waveform output pin for output compare.
P36
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
external ready function is disabled.
9
G
Waveform output pin for output compare.
P37
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled either in single-chip mode or when the
clock output is disabled.
10
G
Waveform output pin for output compare
P40, P41
F
General purpose I/O pins.
(devices with an S suffix in the part number and or MB90V340E-101)
X0A, X1A
B
Oscillation pins for sub clock
(devices without an S suffix in the part number and or MB90V340E-102)
11, 12
13
VCC
16
14
VSS
17
15
C
K
16
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
OUT7
15
18
External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
OUT6
CLK
13, 14
Hold acknowledge output pin. This function is enabled when both the external
bus and the hold function are enabled.
OUT5
RDY
12
Function
Power (3.5 V to 5.5 V) input pin
GND pin
This is the power supply stabilization capacitor This pin should be connected
to a ceramic capacitor with a capacitance greater than or equal to 0.1 F.
P42
General purpose I/O pin.
IN6
Trigger input pin for input capture.
RX1
INT9R
F
RX input pin for CAN1 Interface
(MB90341E/342E/F342E/F345E only)
External interrupt request input pin
(Continued)
Document Number: 002-04498 Rev. *A
Page 13 of 92
MB90340E Series
Pin No.
QFP100*1
19
20
LQFP100*2
17
18
I/O
Circuit
type*3
Pin name
P43
General purpose I/O pin.
IN7
Trigger input pin for input capture.
F
TX1
TX Output pin for CAN1
(MB90341E/342E/F342E/F345E only)
P44
General purpose I/O pin.
SDA0
H
FRCK0
19
22
20
23
21
24
22
SCL0
General purpose I/O pin.
H
23
Input pin for the 16-bit Free-run Timer
P46
General purpose I/O pin.
SDA1
P47
SCL1
H
H
AN8
28
26
General purpose I/O pin.
AN9
I
AN10
AN11
27
30, 31
28, 29
32
30
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O pin.
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
General purpose I/O pin.
I
Analog input pin for the A/D converter
TIN3
Event input pin for the reload timer
P54
General purpose I/O pin.
AN12
I
TOT3
29
Analog input pin for the A/D converter
Serial data input pin for UART2
P53
25
Serial clock I/O pin for I2C (devices with a C suffix in the part number)
SIN2
SCK2
27
General purpose I/O pin.
P51
P52
24
Serial data I/O pin for I2C (devices with a C suffix in the part number)
General purpose I/O pin.
O
SOT2
26
Serial clock I/O pin for I2C (devices with a C suffix in the part number)
FRCK1
P50
25
Serial data I/O pin for I2C (devices with a C suffix in the part number)
Input pin for the 16-bit Free-run Timer 0
P45
21
Function
P55
AN13
P56, P57
AN14, AN15
AVCC
Analog input pin for the A/D converter
Output pin for the reload timer
I
J
K
General purpose I/O pin.
Analog input pin for the A/D converter
General purpose I/O pins.
Analog input pins for the A/D converter
Analog power input pin for the A/D Converter
(Continued)
Document Number: 002-04498 Rev. *A
Page 14 of 92
MB90340E Series
Pin No.
1
QFP100*
2
LQFP100*
I/O
Circuit
type*3
Pin name
Function
33
31
AVRH
L
Reference voltage input pin for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or equal to AVRH
is applied to AVCC.
34
32
AVRL
K
Lower reference voltage input pin for the A/D Converter
35
33
AVSS
K
Analog GND pin for the A/D Converter
P60 to P67
36 to 43
34 to 41
AN0 to AN7
PPG0, 2, 4, 6, 8,
A, C, E
44
42
VSS
General purpose I/O pins.
I
Analog input pins for the A/D converter
Output pins for PPGs
P70 to P75
GND pin
General purpose I/O pins.
I
Analog input pins for the A/D converter (devices with a C suffix in the part
number)
MD2
D
Input pin for specifying the operating mode.
45 to 50
43 to 48
AN16 to AN21
51
49
INT0 to INT5
External interrupt request input pins
52, 53
50, 51
MD1, MD0
C
Input pins for specifying the operating mode.
54
52
RST
E
Reset input pin
P76, P77
55, 56
57
58
53, 54
55
56
AN22, AN23
General purpose I/O pins.
I
INT6, INT7
External interrupt request input pins
P80
General purpose I/O pin.
TIN0
ADTG
F
60
57
58
Event input pin for the reload timer
Trigger input pin for the A/D converter
INT12R
External interrupt request input pin
P81
General purpose I/O pin.
TOT0
CKOT
F
INT13R
59
Analog input pins for the A/D converter (devices with a C suffix in the part
number)
Output pin for the reload timer
Output pin for the clock monitor
External interrupt request input pin
P82
General purpose I/O pin.
SIN0
Serial data input pin for UART0
TIN2
M
Event input pin for the reload timer
INT14R
External interrupt request input pin
P83
General purpose I/O pin.
SOT0
TOT2
F
Serial data output pin for UART0
Output pin for the reload timer
(Continued)
Document Number: 002-04498 Rev. *A
Page 15 of 92
MB90340E Series
Pin No.
1
QFP100*
2
LQFP100*
I/O
Circuit
type*3
Pin name
P84
61
59
SCK0
General purpose I/O pin.
F
INT15R
62
63
60
61
P85
SIN1
P86
SOT1
P87
64
62
65
63
VCC
66
64
VSS
67 to 70
65 to 68
SCK1
P90 to P93
PPG1, 3, 5, 7
69 to 72
75
73
OUT0 to OUT3
M
F
F
F
76
74
TX0
85
75 to 82
AD00 to AD07
General purpose I/O pin.
Serial data output pin for UART1
General purpose I/O pin.
Clock I/O pin for UART1
Power (3.5 V to 5.5 V) input pin
GND pin
General purpose I/O pins
Output pins for PPGs
Waveform output pins for output compares. This function is enabled when
the OCU enables waveform output.
F
RX input pin for CAN0 Interface
General purpose I/O pin.
External interrupt request input pin
F
General purpose I/O pin.
TX Output pin for CAN0
General purpose I/O pins. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P00 to P07
77 to 84
Serial data input pin for UART1
F
INT8R
PA1
General purpose I/O pin.
General purpose I/O pins
PA0
RX0
Clock I/O pin for UART0
External interrupt request input pin
P94 to P97
71 to 74
Function
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
INT8 to INT15
External interrupt request input pins.
P10
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
83
G
AD08
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
TIN1
Event input pin for the reload timer
(Continued)
Document Number: 002-04498 Rev. *A
Page 16 of 92
MB90340E Series
Pin No.
QFP100*1
Pin name
LQFP100*2
I/O
Circuit
type*3
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor. This function is enabled in single-chip mode.
P11
86
87
88
89
84
85
AD09
G
Output pin for the reload timer
P12
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD10
N
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin
P13
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
86
G
AD11
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SOT3
Serial data output pin for UART3
P14
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
87
G
AD12
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
SCK3
Clock I/O pin for UART3
90
88
VCC
89
VSS
92
90
X1
93
91
X0
A
P15
95
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
TOT1
91
94
Function
92
G
Power (3.5 V to 5.5 V) input pin
GND pin
Main clock output pin
Main clock input pin
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD13
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
P16
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
93
G
AD14
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
(Continued)
Document Number: 002-04498 Rev. *A
Page 17 of 92
MB90340E Series
(Continued)
Pin No.
QFP100*
1
LQFP100*
2
Pin name
I/O
Circuit
type*3
P17
96
97 to 100
94
G
Function
General purpose I/O pin. The register can be set to select whether to use a
pull-up resistor.
This function is enabled in single-chip mode.
AD15
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
P20 to P23
General purpose I/O pins. The register can be set to select whether to use a
pull-up resistor.In external bus mode, the pin is enabled as a
general-purpose I/O port when the corresponding bit in the external address
output control register (HACR) is 1.
95 to 98
G
A16 to A19
Output pins of the external address bus. When the corresponding bit in the
external address output control register (HACR) is 0, the pins are enabled as
high address output pins (A16 to A19).
PPG9,PPGB,PP
GD,PPGF
Output pins for PPGs
1 : FPT-100P-M06
2 : FPT-100P-M20
3 : For I/O circuit type, refer to “I/O Circuit Type”.
Document Number: 002-04498 Rev. *A
Page 18 of 92
MB90340E Series
4. I/O Circuit Type
Type
Circuit
X1
A
Remarks
Xout
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 M
X0
Standby control signal
X1A
B
Xout
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 M
X0A
Standby control signal
MASK ROM and evaluation products:
CMOS hysteresis input pin
R
C
CMOS hysteresis
inputs
Flash memory products:
CMOS input pin
MASK ROM and evaluation products:
CMOS hysteresis input pin
R
CMOS hysteresis
inputs
D
Pull-down
Resistor
Pull-down resistor value: approx. 50 k
Flash memory products:
CMOS input pin
No pull-down
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 k
E
Pull-up
Resistor
R
CMOS hysteresis
inputs
(Continued)
Document Number: 002-04498 Rev. *A
Page 19 of 92
MB90340E Series
Type
Circuit
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
F
P-ch
Pout
N-ch
Nout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Pull-up control
P-ch
P-ch
N-ch
G
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS hysteresis input (with function to disconnect
input during standby)
Pout
Automotive input (with function to
disconnect input during standby)
TTL input (with function to disconnect
input during standby)
Nout
R
CMOS hysteresis
input
Programmable pull-up resistor: 50 k
approx.
Automotive input
TTL input
Standby control for
input shutdown
CMOS level output
(IOL = 3 mA, IOH 3 mA)
H
P-ch
Pout
N-ch
Nout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
R
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
(Continued)
Document Number: 002-04498 Rev. *A
Page 20 of 92
MB90340E Series
Type
Circuit
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
Pout
N-ch
Nout
CMOS hysteresis input (with function to disconnect
input during standby)
Automotive input (with function to
disconnect input during standby)
A/D converter analog input
R
I
CMOS hysteresis
input
Automotive input
Standby control for
input shutdown
Analog input
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
N-ch
Pout
Nout
Automotive input (with function to
disconnect input during standby)
R
CMOS hysteresis
input
J
D/A analog output
CMOS hysteresis input (with function to disconnect
input during standby)
A/D converter analog input
Automotive input
Standby control for
input shutdown
Analog input
Analog output
Power supply input protection circuit
P-ch
K
N-ch
P-ch
L
ANE
AVR
N-ch
Document Number: 002-04498 Rev. *A
A/D converter reference voltage power supply input
pin, with the protection
circuit
Flash memory devices do not have a protection
circuit against VCC for pin AVRH
ANE
Page 21 of 92
MB90340E Series
(Continued)
Type
Circuit
M
Remarks
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
Pout
N-ch
Nout
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
R
CMOS input
Automotive input
Standby control for
input shutdown
Pull-up control
P-ch
P-ch
Pout
CMOS level output
(IOL = 4 mA, IOH 4 mA)
CMOS input (with function to disconnect input
during standby)
Automotive input (with function to
disconnect input during standby)
N-ch
N
Nout
R
CMOS input
TTL input (with function to disconnect
input during standby)
Programmable pull-up resistor: 50 k
approx
Automotive input
TTL input
Standby control for
input shutdown
CMOS level output
(IOL = 4 mA, IOH 4 mA)
P-ch
Pout
N-ch
Nout
Automotive input (with function to
disconnect input during standby)
R
O
CMOS input (with function to disconnect input
during standby)
A/D converter analog input
CMOS input
Automotive input
Standby control for
input shutdown
Analog input
Document Number: 002-04498 Rev. *A
Page 22 of 92
MB90340E Series
5. Handling Devices
1.Preventing latch-up
CMOS IC may suffer latch-up under the following conditions:
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between VCC and VSS pins.
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage.
2.Handling unused pins
Leaving unused input terminals open may lead to permanent damage due to malfunction and latch-up; pull up or pull down the
terminals through the resistors of 2 k or more.
3.Power supply pins (VCC/VSS)
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected
inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the
standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.
As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 F as a bypass capacitor
between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90340E
Series
Vcc
Vss
Vss
Vcc
4.Mode Pins (MD0 to MD2)
Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pins to V CC or VSS pins and to provide a low-impedance
connection.
Document Number: 002-04498 Rev. *A
Page 23 of 92
MB90340E Series
5. Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the
digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does
not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
6.Connection of Unused A/D Converter Pins when the A/D Converter is Used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH AVRL VSS.
7.Crystal Oscillator Circuit
The X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operation. Make sure to provide bypass capacitors via the
shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to
the utmost effort, that the oscillation circuit lines do not cross the lines of other circuits. It is highly recommended to provide a printed
circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation.
For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator you are using.
8. Pull-up/down resistors
The MB90340E Series does not support internal pull-up/down resistors (except for the pull-up resistors built into ports 0 to 3). Use
external components where needed.
9.Using external clock
To use an external clock, drive the X0 pin and leave the X1 pin open.
MB90340E Series
X0
Open
X1
10.Precautions when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
11.Notes on operation in PLL clock mode
If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external
oscillator or the external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
12.Notes on Power-On
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 s or more (0.2 V to 2.7
V)
Document Number: 002-04498 Rev. *A
Page 24 of 92
MB90340E Series
13.Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range.
Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple
variations (peak- to-peak values) at commercial frequencies (50 MHz/60 MHz) fall below 10 of the standard VCC supply voltage
and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14.Port 0 to Port 3 Output During Power-on (External-bus Mode)
As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of Port 0 to Port 3 might
be unstable irrespective of the reset input.
1/2VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
15.Notes on Using the CAN Function
To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1.
16.Flash Security Function (except for MB90F346E)
A security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Refer to following table for the address of the security bit.
Flash memory size
Address of the security bit
MB90F347E
Embedded 1 Mbit Flash Memory
FE0001H
MB90F342E
MB90F349E
Embedded 2 Mbits Flash Memory
FC0001H
MB90F345E
Embedded 4 Mbits Flash Memory
F80001H
17.Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data
due to the noise.
Document Number: 002-04498 Rev. *A
Page 25 of 92
MB90340E Series
6. Block Diagrams
MB90V340E-101/102
X0,X1
X0A,X1A*
RST
Clock
Controller
16LX
CPU
Free-run
Timer 0
RAM
30 Kbytes
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
DA01, DA00
Input
Capture
8 channels
IN7 to IN0
Output
Compare
8 channels
OUT7 to OUT0
Prescaler
5 channels
Free-run
Timer 1
LIN-UART
5 channels
CAN
Controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit Reload
Timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D converter
24 channels
10-bit
D/A converter
2 channels
FRCK1
AD15 to AD00
F2MC-16 Bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
A23 to A16
ALE
RD
External
Bus
Interface
WR/WRL
WRH
HRQ
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
HAK
8/16-bit
PPG
16/8 channels
I2C
Interface
2 channels
DMAC
RDY
CLK
External
Interrupt
16 channels
Clock
Monitor
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
* : Only for MB90V340E-102
Document Number: 002-04498 Rev. *A
Page 26 of 92
MB90340E Series
MB90341E(S), MB90341CE(S), MB90342E(S), MB90342CE(S), MB90F342E(S), MB90F342CE(S), MB90F345E(S),
MB90F345CE(S), MB90346E(S), MB90346CE(S), MB90F346E(S), MB90F346CE(S), MB90347E(S), MB90347CE(S),
MB90F347E(S), MB90F347CE(S), MB90348E(S), MB90348CE(S), MB90349E(S), MB90349CE(S), MB90F349E(S), MB90F349CE(S)
X0,X1
X0A,X1A*1
RST
Clock
Controller
16LX
CPU
Free-run
Timer 0
RAM
2 K/6 K/16 K/
20 Kbytes
ROM/Flash
64 K/128 K
256 K/384 K/
512 Kbytes
Prescaler
4 channels
AVCC
AVSS
AN15 to AN0
AN23 to
AVRH
AVRL
ADTG
AN16*2
PPGF to PPG0
SDA1, SDA0*2
SCL1, SCL0*2
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
RX0, RX1*3
TX0, TX1*3
16-bit Reload
Timer
4 channels
8/10-bit
A/D Converter
16/24
channels
I 2C
Interface
2 channels
IN7 to IN0
CAN
Controller
1/2 channels*3
LIN-UART
4 channels
8/16-bit
PPG
16/8 channels
Input
Capture
8 channels
Free-run
Timer 1
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
F2MC-16 Bus
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
FRCK0
A23 to A16
ALE
RD
External
Bus
Interface
WR/WRL
WRH
HRQ
HAK
RDY
CLK
External
Interrupt
16 channels
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DMAC
Clock
Monitor
*1 : Only for devices with an S suffix in the part number
*2 : Only for devices with a C suffix in the part number
*3 : Only the MB90341E(S)/ 341CE(S)/ 342E(S)/ 342CE(S)/ F342E(S)/F342CE(S)/F345E(S)/ F345CE(S)
are equipped with 2 CAN channels
Document Number: 002-04498 Rev. *A
CKOT
Page 27 of 92
MB90340E Series
7. Memory Map
MB90V340E-101/102
000000H
0000EFH
000100H
Peripheral
External access area
MB90F345E(S)/F345CE(S)
000000H
0000EFH
000100H
Peripheral
External access area
RAM 20 Kbytes
RAM 30 Kbytes
0050FFH
0078FFH
007900H
007900H
Peripheral
007FFFH
008000H
00FFFFH
ROM
(image of FF bank)
External access area
F80000H
F8FFFFH
F90000H
ROM (F8 bank)
ROM (F9 bank)
F9FFFFH
FA0000H
007FFFH
008000H
00FFFFH
External access area
F8FFFFH
F90000H
F9FFFFH
ROM (F8 bank)
ROM (F9 bank)
FA0000H
ROM (FA bank)
FAFFFFH
FB0000H
ROM (FB bank)
FBFFFFH
FC0000H
ROM (FB bank)
FBFFFFH
FC0000H
ROM (FC bank)
FCFFFFH
FD0000H
ROM (FD bank)
FDFFFFH
FE0000H
ROM (FC bank)
ROM (FD bank)
FDFFFFH
FE0000H
ROM (FE bank)
FEFFFFH
FF0000H
FFFFFFH
ROM
(image of FF bank)
F80000H
ROM (FA bank)
FAFFFFH
FB0000H
FCFFFFH
FD0000H
Peripheral
ROM (FE bank)
FEFFFFH
FF0000H
ROM (FF bank)
FFFFFFH
ROM (FF bank)
: Not accessible
Document Number: 002-04498 Rev. *A
Page 28 of 92
MB90340E Series
MB90342E(S)/342CE(S)
MB90F342E(S)/F342CE(S)
MB90349E(S)/349CE(S)
MB90F349E(S)/F349CE(S)
000000H
0000EFH
Peripheral
MB90341E(S)/341CE(S)
MB90348E(S)/348CE(S)
000000H
0000EFH
External access area
000100H
Peripheral
MB90347E(S)/347CE(S)
MB90F347E(S)/F347CE(S)
000000H
0000EFH
External access area
Peripheral
000000H
0000EFH
External access area
000100H
000100H
MB90346E(S)/346CE(S)
MB90F346E(S)/F346CE(S)
RAM 6 Kbytes
Peripheral
External access area
000100H
0008FFH
RAM 2 Kbytes
0018FFH
RAM 16 Kbytes
RAM 16 Kbytes
003FFFH
003FFFH
007900H
007FFFH
008000H
00FFFFH
ROM (image
of FF bank)
007FFFH
008000H
00FFFFH
External
access area
007900H
007900H
007900H
Peripheral
Peripheral
ROM (image
of FF bank)
007FFFH
008000H
00FFFFH
Peripheral
ROM (image
of FF bank)
007FFFH
008000H
00FFFFH
External
access area
External
access area
Peripheral
ROM (image
of FF bank)
External
access area
FC0000H
FCFFFFH
FD0000H
FDFFFFH
FE0000H
FEFFFFH
FF0000H
ROM (FC bank)
ROM (FD bank)
ROM (FE bank)
FEFFFFH
FF0000H
FEFFFFH
FF0000H
ROM (FF bank)
ROM (FF bank)
FFFFFFH
FFFFFFH
FE0000H
FE0000H
FE0000H
ROM (FE bank)
ROM (FE bank)
FEFFFFH
FF0000H
ROM (FF bank)
FFFFFFH
ROM (FF bank)
FFFFFFH
: Not accessible
Note:
:An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible for the C
compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the same as the lower 16 bits
of addresses in the 00 bank so that tables stored in the ROM can be accessed without using the far specifier in the pointer
declaration.
For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
As a result, the image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
Document Number: 002-04498 Rev. *A
Page 29 of 92
MB90340E Series
8. I/O Map
Address
Register
Abbreviation
Access
Resource name
Initial value
000000H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
000001H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
000002H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
000003H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
000004H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXXB
000008H
Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
000009H
Port 9 Data Register
PDR9
R/W
Port 9
XXXXXXXXB
00000AH
Port A Data Register
PDRA
R/W
Port A
XXXXXXXXB
00000BH
Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111B
00000CH
Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111B
00000DH
Port 7 Analog Input Enable Register
ADER7
R/W
Port 7, A/D
11111111B
00000EH
Input Level Select Register 0
ILSR0
R/W
Ports
XXXXXXXXB
00000FH
Input Level Select Register 1
ILSR1
R/W
Ports
XXXX0XXXB
000010H
Port 0 Direction Register
DDR0
R/W
Port 0
00000000B
000011H
Port 1 Direction Register
DDR1
R/W
Port 1
00000000B
000012H
Port 2 Direction Register
DDR2
R/W
Port 2
00000000B
000013H
Port 3 Direction Register
DDR3
R/W
Port 3
00000000B
000014H
Port 4 Direction Register
DDR4
R/W
Port 4
00000000B
000015H
Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
000016H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
000017H
Port 7 Direction Register
DDR7
R/W
Port 7
00000000B
000018H
Port 8 Direction Register
DDR8
R/W
Port 8
00000000B
000019H
Port 9 Direction Register
DDR9
R/W
Port 9
00000000B
00001AH
Port A Direction Register
DDRA
R/W
Port A
00000100B
00001BH
Reserved
00001CH
Port 0 Pull-up Control Register
PUCR0
R/W
Port 0
00000000B
00001DH
Port 1 Pull-up Control Register
PUCR1
R/W
Port 1
00000000B
00001EH
Port 2 Pull-up Control Register
PUCR2
R/W
Port 2
00000000B
00001FH
Port 3 Pull-up Control Register
PUCR3
W, R/W
Port 3
00000000B
(Continued)
Document Number: 002-04498 Rev. *A
Page 30 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
000020H
Serial Mode Register 0
SMR0
W,R/W
00000000B
000021H
Serial Control Register 0
SCR0
W,R/W
00000000B
000022H
Reception/Transmission Data Register 0
RDR0/TDR0
R/W
00000000B
000023H
Serial Status Register 0
SSR0
R,R/W
00001000B
000024H
Extended Communication Control
Register 0
ECCR0
R,W,
R/W
000025H
Extended Status/Control Register 0
ESCR0
R/W
00000100B
000026H
Baud Rate Generator Register 00
BGR00
R/W
00000000B
000027H
Baud Rate Generator Register 01
BGR01
R/W
00000000B
000028H
Serial Mode Register 1
SMR1
W,R/W
00000000B
000029H
Serial Control Register 1
SCR1
W,R/W
00000000B
00002AH
Reception/Transmission Data Register 1
RDR1/TDR1
R/W
00000000B
00002BH
Serial Status Register 1
SSR1
R,R/W
00001000B
00002CH
Extended Communication Control
Register 1
ECCR1
R,W,
R/W
00002DH
Extended Status/Control Register 1
ESCR1
R/W
00000100B
00002EH
Baud Rate Generator Register 10
BGR10
R/W
00000000B
00002FH
Baud Rate Generator Register 11
BGR11
R/W
00000000B
000030H
PPG 0 Operation Mode Control Register
PPGC0
W,R/W
0X000XX1B
000031H
PPG 1 Operation Mode Control Register
PPGC1
W,R/W
000032H
PPG 0/PPG 1 Count Clock Select Register
PPG01
R/W
000000X0B
PPGC2
W,R/W
0X000XX1B
UART0
UART1
16-bit PPG 0/1
000000XXB
000000XXB
0X000001B
000033H
Reserved
000034H
PPG 2 Operation Mode Control Register
000035H
PPG 3 Operation Mode Control Register
PPGC3
W,R/W
000036H
PPG 2/PPG 3 Count Clock Select Register
PPG23
R/W
000000X0B
0X000XX1B
000037H
Reserved
000038H
PPG 4 Operation Mode Control Register
PPGC4
W,R/W
000039H
PPG 5 Operation Mode Control Register
PPGC5
W,R/W
00003AH
PPG 4/PPG 5 Clock Select Register
PPG45
R/W
00003BH
Address Detect Control Register 1
PACSR1
R/W
00003CH
PPG 6 Operation Mode Control Register
PPGC6
W,R/W
00003DH
PPG 7 Operation Mode Control Register
PPGC7
W,R/W
00003EH
PPG 6/PPG 7 Count Clock Control Register
PPG67
R/W
00003FH
Reserved
16-bit PPG 2/3
16-bit PPG 4/5
0X000001B
0X000001B
000000X0B
Address Match
Detection 1
00000000B
0X000XX1B
16-bit PPG 6/7
0X000001B
000000X0B
(Continued)
Document Number: 002-04498 Rev. *A
Page 31 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
000040H
PPG 8 Operation Mode Control Register
PPGC8
W,R/W
0X000XX1B
000041H
PPG 9 Operation Mode Control Register
PPGC9
W,R/W
0X000001B
000042H
PPG 8/PPG 9 Count Clock Control
Register
PPG89
R/W
000000X0B
000043H
Reserved
000044H
PPG A Operation Mode Control Register
PPGCA
W,R/W
0X000XX1B
000045H
PPG B Operation Mode Control Register
PPGCB
W,R/W
000046H
PPG A/PPG B Count Clock Select
Register
PPGAB
R/W
000000X0B
0X000XX1B
16-bit PPG 8/9
16-bit PPG A/B
0X000001B
000047H
Reserved
000048H
PPG C Operation Mode Control Register
PPGCC
W,R/W
000049H
PPG D Operation Mode Control Register
PPGCD
W,R/W
00004AH
PPG C/PPG D Count Clock Select
Register
PPGCD
R/W
000000X0B
0X000XX1B
00004BH
Reserved
00004CH
PPG E Operation Mode Control Register
PPGCE
W,R/W
00004DH
PPG F Operation Mode Control Register
PPGCF
W,R/W
00004EH
PPG E/PPG F Count Clock Select
Register
PPGEF
R/W
00004FH
Reserved
000050H
Input Capture Control Status 0/1
ICS01
R/W
000051H
Input Capture Edge 0/1
ICE01
R/W, R
000052H
Input Capture Control Status 2/3
ICS23
R/W
000053H
Input Capture Edge 2/3
ICE23
R
000054H
Input Capture Control Status 4/5
ICS45
R/W
000055H
Input Capture Edge 4/5
ICE45
R
000056H
Input Capture Control Status 6/7
ICS67
R/W
000057H
Input Capture Edge 6/7
ICE67
R/W, R
000058H
Output Compare Control Status 0
OCS0
R/W
000059H
Output Compare Control Status 1
OCS1
R/W
00005AH
Output Compare Control Status 2
OCS2
R/W
00005BH
Output Compare Control Status 3
OCS3
R/W
00005CH
Output Compare Control Status 4
OCS4
R/W
00005DH
Output Compare Control Status 5
OCS5
R/W
00005EH
Output Compare Control Status 6
OCS6
R/W
00005FH
Output Compare Control Status 7
OCS7
R/W
16-bit PPG C/D
16-bit PPG E/F
0X000001B
0X000001B
000000X0B
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXX000XXB
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
(Continued)
Document Number: 002-04498 Rev. *A
Page 32 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
000060H
Timer Control Status 0
TMCSR0
R/W
000061H
Timer Control Status 0
TMCSR0
R/W
000062H
Timer Control Status 1
TMCSR1
R/W
000063H
Timer Control Status 1
TMCSR1
R/W
000064H
Timer Control Status 2
TMCSR2
R/W
000065H
Timer Control Status 2
TMCSR2
R/W
000066H
Timer Control Status 3
TMCSR3
R/W
000067H
Timer Control Status 3
TMCSR3
R/W
000068H
A/D Control Status 0
ADCS0
R/W
000XXXX0B
000069H
A/D Control Status 1
ADCS1
R/W
0000000XB
00006AH
A/D Data 0
ADCR0
R
00006BH
A/D Data 1
ADCR1
R
00006CH
ADC Setting 0
ADSR0
R/W
00000000B
00006DH
ADC Setting 1
ADSR1
R/W
00000000B
ROMM
W
00006EH
Reserved
00006FH
ROM Mirror Function Select
000070H
to
00008FH
Reserved for CAN Controller 0/1. Refer to “CAN Controllers”
000090H
to
00009AH
Reserved
00009BH
DMA Descriptor Channel Specified
Register
DCSR
16-bit Reload
Timer 0
00000000B
16-bit Reload
Timer 1
00000000B
16-bit Reload
Timer 2
00000000B
16-bit Reload
Timer 3
00000000B
A/D Converter
ROM Mirror
R/W
00009CH
DMA Status L Register
DSRL
R/W
00009DH
DMA Status H Register
DSRH
R/W
XXXX0000B
XXXX0000B
XXXX0000B
XXXX0000B
00000000B
XXXXXX00B
XXXXXXX1B
00000000B
DMA
00000000B
00000000B
00009EH
Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00009FH
Delayed Interrupt Trigger/Release
Register
DIRR
R/W
Delayed Interrupt
XXXXXXX0B
0000A0H
Low-power Mode Control Register
LPMCR
W,R/W
Low Power
Control Circuit
00011000B
0000A1H
Clock Selection Register
CKSCR
R,R/W
Low Power
Control Circuit
11111100B
0000A2H,
0000A3H
Reserved
0000A4H
DMA Stop Status Register
DSSR
R/W
DMA
00000000B
00000000B
(Continued)
Document Number: 002-04498 Rev. *A
Page 33 of 92
MB90340E Series
Address
0000A5H
Register
Automatic Ready Function Select
Register
0000A6H
External Address Output Control
Register
0000A7H
0000A8H
Abbreviation
ARSR
Access
Resource name
W
Initial value
0011XX00B
External Memory
Access
HACR
W
Bus Control Signal Selection Register
ECSR
W
Watchdog Control Register
WDTC
R,W
Watchdog Timer
XXXXX111B
0000A9H
Time Base Timer Control Register
TBTC
W,R/W
Time Base Timer
1XX00100B
0000AAH
Watch Timer Control Register
WTC
R,R/W
Watch Timer
1X001000B
0000ABH
Reserved
0000ACH
DMA Enable L Register
DERL
R/W
0000ADH
DMA Enable H Register
DERH
R/W
0000AEH
Flash Control Status Register
(Flash memory devices only.
Otherwise reserved)
FMCS
R,R/W
00000000B
0000000XB
DMA
Flash Memory
00000000B
00000000B
000X0000B
0000AFH
Reserved
0000B0H
Interrupt Control Register 00
ICR00
W,R/W
00000111B
0000B1H
Interrupt Control Register 01
ICR01
W,R/W
00000111B
0000B2H
Interrupt Control Register 02
ICR02
W,R/W
00000111B
0000B3H
Interrupt Control Register 03
ICR03
W,R/W
00000111B
0000B4H
Interrupt Control Register 04
ICR04
W,R/W
00000111B
0000B5H
Interrupt Control Register 05
ICR05
W,R/W
00000111B
0000B6H
Interrupt Control Register 06
ICR06
W,R/W
00000111B
0000B7H
Interrupt Control Register 07
ICR07
W,R/W
0000B8H
Interrupt Control Register 08
ICR08
W,R/W
0000B9H
Interrupt Control Register 09
ICR09
W,R/W
00000111B
0000BAH
Interrupt Control Register 10
ICR10
W,R/W
00000111B
0000BBH
Interrupt Control Register 11
ICR11
W,R/W
00000111B
0000BCH
Interrupt Control Register 12
ICR12
W,R/W
00000111B
0000BDH
Interrupt Control Register 13
ICR13
W,R/W
00000111B
0000BEH
Interrupt Control Register 14
ICR14
W,R/W
00000111B
0000BFH
Interrupt Control Register 15
ICR15
W,R/W
00000111B
0000C0H
D/A Converter Data 0
DAT0
R/W
XXXXXXXXB
0000C1H
D/A Converter Data 1
DAT1
R/W
0000C2H
D/A Control 0
DACR0
R/W
0000C3H
D/A Control 1
DACR1
R/W
Interrupt Control
D/A Converter
00000111B
00000111B
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
(Continued)
Document Number: 002-04498 Rev. *A
Page 34 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
0000C4H,
0000C5H
Reserved
0000C6H
External Interrupt Enable 0
0000C7H
External Interrupt Source 0
EIRR0
R/W
0000C8H
External Interrupt Level Setting 0
ELVR0
R/W
0000C9H
External Interrupt Level Setting 0
ELVR0
R/W
00000000B
0000CAH
External Interrupt Enable 1
ENIR1
R/W
00000000B
0000CBH
External Interrupt Source 1
EIRR1
R/W
0000CCH
External Interrupt Level Setting 1
ELVR1
R/W
0000CDH
External Interrupt Level Setting 1
ELVR1
R/W
00000000B
0000CEH
External Interrupt Source Select
EISSR
R/W
00000000B
0000CFH
PLL/Sub clock Control Register
PSCCR
W
0000D0H
DMA Buffer Address Pointer L Register
BAPL
R/W
0000D1H
DMA Buffer Address Pointer M Register
BAPM
R/W
XXXXXXXXB
0000D2H
DMA Buffer Address Pointer H Register
BAPH
R/W
XXXXXXXXB
0000D3H
DMA Control Register
DMACS
R/W
XXXXXXXXB
0000D4H
I/O Register Address Pointer L
Register
IOAL
R/W
0000D5H
I/O Register Address Pointer H
Register
IOAH
R/W
0000D6H
Data Counter L Register
DCTL
R/W
XXXXXXXXB
0000D7H
Data Counter H Register
DCTH
R/W
XXXXXXXXB
0000D8H
Serial Mode Register 2
SMR2
W,R/W
00000000B
0000D9H
Serial Control Register 2
SCR2
W,R/W
00000000B
0000DAH
Reception/Transmission Data
Register 2
RDR2/TDR2
R/W
00000000B
0000DBH
Serial Status Register 2
SSR2
R,R/W
0000DCH
Extended Communication Control
Register 2
ECCR2
R,W,
R/W
0000DDH
Extended Status Control Register 2
ESCR2
R/W
00000100B
0000DEH
Baud Rate Generator Register 20
BGR20
R/W
00000000B
0000DFH
Baud Rate Generator Register 21
BGR21
R/W
00000000B
0000E0H
to
0000EFH
Reserved for CAN Controller 2. Refer to “CAN Controllers”
0000F0H
to
0000FFH
External
ENIR0
R/W
00000000B
External Interrupt 0
XXXXXXXXB
00000000B
XXXXXXXXB
External Interrupt 1
PLL
00000000B
XXXX0000B
XXXXXXXXB
DMA
XXXXXXXXB
XXXXXXXXB
UART2
00001000B
000000XXB
(Continued)
Document Number: 002-04498 Rev. *A
Page 35 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
007900H
Reload Register L0
PRLL0
R/W
007901H
Reload Register H0
PRLH0
R/W
XXXXXXXXB
007902H
Reload Register L1
PRLL1
R/W
007903H
Reload Register H1
PRLH1
R/W
XXXXXXXXB
007904H
Reload Register L2
PRLL2
R/W
XXXXXXXXB
007905H
Reload Register H2
PRLH2
R/W
007906H
Reload Register L3
PRLL3
R/W
007907H
Reload Register H3
PRLH3
R/W
XXXXXXXXB
007908H
Reload Register L4
PRLL4
R/W
XXXXXXXXB
007909H
Reload Register H4
PRLH4
R/W
00790AH
Reload Register L5
PRLL5
R/W
00790BH
Reload Register H5
PRLH5
R/W
XXXXXXXXB
00790CH
Reload Register L6
PRLL6
R/W
XXXXXXXXB
00790DH
Reload Register H6
PRLH6
R/W
00790EH
Reload Register L7
PRLL7
R/W
00790FH
Reload Register H7
PRLH7
R/W
XXXXXXXXB
007910H
Reload Register L8
PRLL8
R/W
XXXXXXXXB
007911H
Reload Register H8
PRLH8
R/W
007912H
Reload Register L9
PRLL9
R/W
007913H
Reload Register H9
PRLH9
R/W
XXXXXXXXB
007914H
Reload Register LA
PRLLA
R/W
XXXXXXXXB
007915H
Reload Register HA
PRLHA
R/W
007916H
Reload Register LB
PRLLB
R/W
007917H
Reload Register HB
PRLHB
R/W
XXXXXXXXB
007918H
Reload Register LC
PRLLC
R/W
XXXXXXXXB
007919H
Reload Register HC
PRLHC
R/W
00791AH
Reload Register LD
PRLLD
R/W
00791BH
Reload Register HD
PRLHD
R/W
XXXXXXXXB
00791CH
Reload Register LE
PRLLE
R/W
XXXXXXXXB
00791DH
Reload Register HE
PRLHE
R/W
00791EH
Reload Register LF
PRLLF
R/W
00791FH
Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H
Input Capture 0
IPCP0
R
XXXXXXXXB
007921H
Input Capture 0
IPCP0
R
007922H
Input Capture 1
IPCP1
R
007923H
Input Capture 1
IPCP1
R
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-04498 Rev. *A
Page 36 of 92
MB90340E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
007924H
Input Capture 2
IPCP2
R
007925H
Input Capture 2
IPCP2
R
XXXXXXXXB
007926H
Input Capture 3
IPCP3
R
007927H
Input Capture 3
IPCP3
R
XXXXXXXXB
007928H
Input Capture 4
IPCP4
R
XXXXXXXXB
007929H
Input Capture 4
IPCP4
R
00792AH
Input Capture 5
IPCP5
R
00792BH
Input Capture 5
IPCP5
R
XXXXXXXXB
00792CH
Input Capture 6
IPCP6
R
XXXXXXXXB
00792DH
Input Capture 6
IPCP6
R
00792EH
Input Capture 7
IPCP7
R
00792FH
Input Capture 7
IPCP7
R
XXXXXXXXB
007930H
Output Compare 0
OCCP0
R/W
XXXXXXXXB
007931H
Output Compare 0
OCCP0
R/W
007932H
Output Compare 1
OCCP1
R/W
007933H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
007934H
Output Compare 2
OCCP2
R/W
XXXXXXXXB
007935H
Output Compare 2
OCCP2
R/W
007936H
Output Compare 3
OCCP3
R/W
007937H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
007938H
Output Compare 4
OCCP4
R/W
XXXXXXXXB
007939H
Output Compare 4
OCCP4
R/W
00793AH
Output Compare 5
OCCP5
R/W
00793BH
Output Compare 5
OCCP5
R/W
XXXXXXXXB
00793CH
Output Compare 6
OCCP6
R/W
XXXXXXXXB
00793DH
Output Compare 6
OCCP6
R/W
00793EH
Output Compare 7
OCCP7
R/W
00793FH
Output Compare 7
OCCP7
R/W
XXXXXXXXB
007940H
Timer Data 0
TCDT0
R/W
00000000B
007941H
Timer Data 0
TCDT0
R/W
007942H
Timer Control Status 0
TCCSL0
R/W
007943H
Timer Control Status 0
TCCSH0
R/W
0XXXXXXXB
007944H
Timer Data 1
TCDT1
R/W
00000000B
007945H
Timer Data 1
TCDT1
R/W
007946H
Timer Control Status 1
TCCSL1
R/W
007947H
Timer Control Status 1
TCCSH1
R/W
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
Free-run Timer 0
Free-run Timer 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
0XXXXXXXB
(Continued)
Document Number: 002-04498 Rev. *A
Page 37 of 92
MB90340E Series
Address
007948H
007949H
00794AH
00794BH
00794CH
00794DH
00794EH
00794FH
Register
Abbreviation
Timer 0/Reload 0
TMR0/TMRLR0
Timer 1/Reload 1
TMR1/TMRLR1
Timer 2/Reload 2
TMR2/TMRLR2
Timer 3/Reload 3
TMR3/TMRLR3
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Resource name
16-bit Reload
Timer 0
16-bit Reload
Timer 1
16-bit Reload
Timer 2
16-bit Reload
Timer 3
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007950H
Serial Mode Register 3
SMR3
W,R/W
00000000B
007951H
Serial Control Register 3
SCR3
W,R/W
00000000B
007952H
Reception/Transmission Data
Register 3
RDR3/TDR3
R/W
00000000B
007953H
Serial Status Register 3
SSR3
R,R/W
007954H
Extended Communication Control
Register 3
ECCR3
R,W,
R/W
007955H
Extended Status Control Register
ESCR3
R/W
00000100B
007956H
Baud Rate Generator Register 30
BGR30
R/W
00000000B
007957H
Baud Rate Generator Register 31
BGR31
R/W
00000000B
007958H
Serial Mode Register 4
SMR4
W,R/W
00000000B
007959H
Serial Control Register 4
SCR4
W,R/W
00000000B
00795AH
Reception/Transmission Data
Register 4
RDR4/TDR4
R/W
00000000B
00795BH
Serial Status Register 4
SSR4
R,R/W
00795CH
Extended Communication Control
Register 4
ECCR4
R,W,
R/W
00795DH
Extended Status Control Register
ESCR4
R/W
00000100B
00795EH
Baud Rate Generator Register 40
BGR40
R/W
00000000B
00795FH
Baud Rate Generator Register 41
BGR41
R/W
00000000B
007960H
to
00796BH
Reserved
00796CH
Clock Output Enable Register
CLKR
R/W
Clock Monitor
XXXX0000B
UART3
00001000B
000000XXB
UART4
00001000B
000000XXB
00796DH
Reserved
00796EH
CAN Direct Mode Register
CDMR
R/W
CAN Clock sync
XXXXXXX0B
00796FH
CAN Switch Register
CANSWR
R/W
CAN 0/1
XXXXXX00B
(Continued)
Document Number: 002-04498 Rev. *A
Page 38 of 92
MB90340E Series
Address
Register
007970H
I2 C
007971H
I2C Bus Control Register 0
007972H
007973H
Bus Status Register 0
I2C 10-bit Slave Address Register 0
Abbreviation
Access
Resource name
Initial value
IBSR0
R
00000000B
IBCR0
W,R/W
00000000B
ITBAL0
R/W
00000000B
ITBAH0
R/W
00000000B
I2
I2C 10-bit Slave Address Mask
Register 0
ITMKL0
R/W
ITMKH0
R/W
00111111B
007976H
I2C 7-bit Slave Address Register 0
ISBA0
R/W
00000000B
007977H
I2C 7-bit Slave Address Mask Register 0
ISMK0
R/W
01111111B
IDAR0
R/W
00000000B
ICCR0
R/W
007974H
007975H
2
C Interface 0
11111111B
007978H
I C Data Register 0
007979H,
00797AH
Reserved
00797BH
I2C Clock Control Register 0
00797CH
to
00797FH
Reserved
007980H
I2C Bus Status Register 1
IBSR1
R
00000000B
007981H
I2C Bus Control Register 1
IBCR1
W,R/W
00000000B
ITBAL1
R/W
00000000B
ITBAH1
R/W
007982H
007983H
I2C 10-bit Slave Address Register 1
I2C Interface 0
00011111B
00000000B
2
I2C 10-bit Slave Address Mask
Register 1
ITMKL1
R/W
ITMKH1
R/W
00111111B
007986H
I2C 7-bit Slave Address Register 1
ISBA1
R/W
00000000B
007987H
I2C 7-bit Slave Address Mask Register 1
ISMK1
R/W
01111111B
007988H
I2 C
IDAR1
R/W
00000000B
007989H,
00798AH
Reserved
00798BH
I2C Clock Control Register 1
ICCR1
R/W
I2C Interface 1
00011111B
00798CH
to
0079C1H
Reserved
0079C2H
Clock Modulator Control Register
CMCR
R, R/W
Clock Modulator
0001X000B
0079C3H
to
0079DFH
Reserved
007984H
007985H
Data Register 1
I C Interface 1
11111111B
(Continued)
Document Number: 002-04498 Rev. *A
Page 39 of 92
MB90340E Series
(Continued)
Address
Register
Abbreviation
Access
Resource name
Initial value
0079E0H
Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E1H
Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E2H
Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E3H
Detect Address Setting 1
PADR1
R/W
0079E4H
Detect Address Setting 1
PADR1
R/W
0079E5H
Detect Address Setting 1
PADR1
R/W
0079E6H
Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E7H
Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E8H
Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E9H
to
0079EFH
Reserved
0079F0H
Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F1H
Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F2H
Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F3H
Detect Address Setting 4
PADR4
R/W
0079F4H
Detect Address Setting 4
PADR4
R/W
0079F5H
Detect Address Setting 4
PADR4
R/W
0079F6H
Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F7H
Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F8H
Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F9H
to
0079FFH
Reserved
007A00H
to
007AFFH
Reserved for CAN Controller 0. Refer to “CAN Controllers
007B00H
to
007BFFH
Reserved for CAN Controller 0. Refer to “CAN Controllers”
007C00H
to
007CFFH
Reserved for CAN Controller 1. Refer to “CAN Controllers”
007D00H
to
007DFFH
Reserved for CAN Controller 1. Refer to “CAN Controllers”
007E00H
to
007FFFH
Reserved
Note:
Address Match
Detection 0
Address Match
Detection 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Initial value of “X” represents unknown value.
Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
Document Number: 002-04498 Rev. *A
Page 40 of 92
MB90340E Series
9. CAN Controllers
The CAN controller has the following features:
Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmission/reception message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID
acceptance mask
Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address
CAN0
Register
CAN1
000070H
000080H
000071H
000081H
000072H
000082H
000073H
000083H
000074H
000084H
000075H
000085H
000076H
000086H
000077H
000087H
000078H
000088H
000079H
000089H
00007AH
00008AH
00007BH
00008BH
00007CH
00008CH
00007DH
00008DH
00007EH
00008EH
00007FH
00008FH
Abbreviation
Access
Initial Value
Message Buffer
Valid Register
BVALR
R/W
00000000B
00000000B
Transmit Request
Register
TREQR
R/W
00000000B
00000000B
Transmit Cancel
Register
TCANR
W
00000000B
00000000B
Transmission
Complete Register
TCR
R/W
00000000B
00000000B
Receive Complete
Register
RCR
R/W
00000000B
00000000B
Remote Request
Receiving Register
RRTRR
R/W
00000000B
00000000B
Receive Overrun
Register
ROVRR
R/W
00000000B
00000000B
Reception Interrupt
Enable Register
RIER
R/W
00000000B
00000000B
Document Number: 002-04498 Rev. *A
Page 41 of 92
MB90340E Series
List of Control Registers (2)
Address
CAN0
Register
CAN1
007B00H
007D00H
007B01H
007D01H
007B02H
007D02H
007B03H
007D03H
007B04H
007D04H
007B05H
007D05H
007B06H
007D06H
007B07H
007D07H
007B08H
007D08H
007B09H
007D09H
007B0AH
007D0AH
007B0BH
007D0BH
007B0CH
007D0CH
007B0DH
007D0DH
007B0EH
007D0EH
007B0FH
007D0FH
007B10H
007D10H
007B11H
007D11H
007B12H
007D12H
007B13H
007D13H
007B14H
007D14H
007B15H
007D15H
007B16H
007D16H
007B17H
007D17H
007B18H
007D18H
007B19H
007D19H
007B1AH
007D1AH
007B1BH
007D1BH
Abbreviation
Access
Initial Value
Control Status
Register
CSR
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Last Event
Indicator Register
LEIR
R/W
000X0000B
XXXXXXXXB
Receive And Transmit
Error Counter
RTEC
R
00000000B
00000000B
Bit Timing
Register
BTR
R/W
11111111B
X1111111B
IDE Register
IDER
R/W
XXXXXXXXB
XXXXXXXXB
Transmit RTR
Register
TRTRR
R/W
00000000B
00000000B
Remote Frame
Receive Waiting
Register
RFWTR
R/W
XXXXXXXXB
XXXXXXXXB
Transmit Interrupt
Enable Register
TIER
R/W
00000000B
00000000B
Acceptance Mask
Select Register
Acceptance Mask
Register 0
Acceptance Mask
Register 1
Document Number: 002-04498 Rev. *A
AMSR
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR1
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Page 42 of 92
MB90340E Series
List of Message Buffers (ID Registers) (1)
Address
CAN0
Register
CAN1
007A00H
to
007A1FH
007C00H
to
007C1FH
007A20H
007C20H
007A21H
007C21H
007A22H
007C22H
007A23H
007C23H
007A24H
007C24H
007A25H
007C25H
007A26H
007C26H
007A27H
007C27H
007A28H
007C28H
007A29H
007C29H
007A2AH
007C2AH
007A2BH
007C2BH
007A2CH
007C2CH
007A2DH
007C2DH
007A2EH
007C2EH
007A2FH
007C2FH
007A30H
007C30H
007A31H
007C31H
007A32H
007C32H
007A33H
007C33H
007A34H
007C34H
007A35H
007C35H
007A36H
007C36H
007A37H
007C37H
007A38H
007C38H
007A39H
007C39H
007A3AH
007C3AH
007A3BH
007C3BH
007A3CH
007C3CH
007A3DH
007C3DH
007A3EH
007C3EH
007A3FH
007C3FH
GeneralPurpose RAM
ID Register 0
Abbreviation
IDR0
Access
R/W
R/W
Initial Value
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 1
IDR1
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 2
IDR2
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 3
IDR3
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 4
IDR4
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 5
IDR5
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 6
IDR6
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 7
Document Number: 002-04498 Rev. *A
IDR7
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Page 43 of 92
MB90340E Series
List of Message Buffers (ID Registers) (2)
Address
CAN0
Register
CAN1
007A40H
007C40H
007A41H
007C41H
007A42H
007C42H
007A43H
007C43H
007A44H
007C44H
007A45H
007C45H
007A46H
007C46H
007A47H
007C47H
007A48H
007C48H
007A49H
007C49H
007A4AH
007C4AH
007A4BH
007C4BH
007A4CH
007C4CH
007A4DH
007C4DH
007A4EH
007C4EH
007A4FH
007C4FH
007A50H
007C50H
007A51H
007C51H
007A52H
007C52H
007A53H
007C53H
007A54H
007C54H
007A55H
007C55H
007A56H
007C56H
007A57H
007C57H
007A58H
007C58H
007A59H
007C59H
007A5AH
007C5AH
007A5BH
007C5BH
007A5CH
007C5CH
007A5DH
007C5DH
007A5EH
007C5EH
007A5FH
007C5FH
ID Register 8
Abbreviation
IDR8
Access
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 9
IDR9
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 10
IDR10
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 11
IDR11
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 12
IDR12
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 13
IDR13
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 14
IDR14
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID Register 15
Document Number: 002-04498 Rev. *A
IDR15
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Page 44 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN0
Register
CAN1
007A60H
007C60H
007A61H
007C61H
007A62H
007C62H
007A63H
007C63H
007A64H
007C64H
007A65H
007C65H
007A66H
007C66H
007A67H
007C67H
007A68H
007C68H
007A69H
007C69H
007A6AH
007C6AH
007A6BH
007C6BH
007A6CH
007C6CH
007A6DH
007C6DH
007A6EH
007C6EH
007A6FH
007C6FH
007A70H
007C70H
007A71H
007C71H
007A72H
007C72H
007A73H
007C73H
007A74H
007C74H
007A75H
007C75H
007A76H
007C76H
007A77H
007C77H
007A78H
007C78H
007A79H
007C79H
007A7AH
007C7AH
007A7BH
007C7BH
007A7CH
007C7CH
007A7DH
007C7DH
007A7EH
007C7EH
007A7FH
007C7FH
Abbreviation
Access
Initial Value
DLC Register 0
DLCR0
R/W
XXXXXXXXB
DLC Register 1
DLCR1
R/W
XXXXXXXXB
DLC Register 2
DLCR2
R/W
XXXXXXXXB
DLC Register 3
DLCR3
R/W
XXXXXXXXB
DLC Register 4
DLCR4
R/W
XXXXXXXXB
DLC Register 5
DLCR5
R/W
XXXXXXXXB
DLC Register 6
DLCR6
R/W
XXXXXXXXB
DLC Register 7
DLCR7
R/W
XXXXXXXXB
DLC Register 8
DLCR8
R/W
XXXXXXXXB
DLC Register 9
DLCR9
R/W
XXXXXXXXB
DLC Register 10
DLCR10
R/W
XXXXXXXXB
DLC Register 11
DLCR11
R/W
XXXXXXXXB
DLC Register 12
DLCR12
R/W
XXXXXXXXB
DLC Register 13
DLCR13
R/W
XXXXXXXXB
DLC Register 14
DLCR14
R/W
XXXXXXXXB
DLC Register 15
DLCR15
R/W
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 45 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
CAN0
Register
CAN1
Abbreviation
Access
Initial Value
007A80H
to
007A87H
007C80H
to
007C87H
Data Register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
007A88H
to
007A8FH
007C88H
to
007C8FH
Data Register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
007A90H
to
007A97H
007C90H
to
007C97H
Data Register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
007A98H
to
007A9FH
007C98H
to
007C9FH
Data Register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
007AA0H
to
007AA7H
007CA0H
to
007CA7H
Data Register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
007AA8H
to
007AAFH
007CA8H
to
007CAFH
Data Register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
007AB0H
to
007AB7H
007CB0H
to
007CB7H
Data Register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
007AB8H
to
007ABFH
007CB8H
to
007CBFH
Data Register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
007AC0H
to
007AC7H
007CC0H
to
007CC7H
Data Register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
007AC8H
to
007ACFH
007CC8H
to
007CCFH
Data Register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
007AD0H
to
007AD7H
007CD0H
to
007CD7H
Data Register 10
(8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
007AD8H
to
007ADFH
007CD8H
to
007CDFH
Data Register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
007AE0H
to
007AE7H
007CE0H
to
007CE7H
Data Register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
007AE8H
to
007AEFH
007CE8H
to
007CEFH
Data Register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 46 of 92
MB90340E Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
CAN0
Register
CAN1
Abbreviation
Access
Initial Value
007AF0H
to
007AF7H
007CF0H
to
007CF7H
Data Register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
007AF8H
to
007AFFH
007CF8H
to
007CFFH
Data Register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
Document Number: 002-04498 Rev. *A
Page 47 of 92
MB90340E Series
10. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
Interrupt cause
DMA
channel
number
EI2OS
Support
Number
Address
Exception
N
CAN 0 RX
N
CAN 0 TX/NS
N
CAN 1 RX / Input Capture 6
Y1
CAN 1 TX/NS / Input Capture 7
Y1
CAN 2 RX / I2C0
N
CAN 2 TX/NS
N
16-bit Reload Timer 0
Y1
0
#17
FFFFB8H
16-bit Reload Timer 1
Y1
1
#18
FFFFB4H
16-bit Reload Timer 2
Y1
2
#19
16-bit Reload Timer 3
Y1
#20
FFFFACH
PPG 0/1/4/5
N
#21
FFFFA8H
PPG 2/3/6/7
N
#22
FFFFA4H
PPG 8/9/C/D
N
#23
FFFFA0H
PPG A/B/E/F
N
#24
FFFF9CH
Time Base Timer
N
FFFFB0H
#25
FFFF98H
External Interrupt 0 to 3, 8 to 11
Y1
3
#26
Watch Timer
N
FFFF94H
#27
FFFF90H
External Interrupt 4 to 7, 12 to 15
Y1
4
#28
FFFF8CH
A/D Converter
Y1
5
#29
Free-run Timer 0 / Free-run Timer 1
N
FFFF88H
#30
FFFF84H
Input Capture 4/5 / I2C1
Y1
6
#31
FFFF80H
Output Compare 0/1/4/5
Y1
7
#32
FFFF7CH
Input Capture 0 to 3
Y1
8
#33
FFFF78H
Output Compare 2/3/6/7
Y1
9
#34
FFFF74H
UART 0 RX
Y2
10
#35
FFFF70H
UART 0 TX
Y1
11
#36
FFFF6CH
UART 1 RX / UART 3 RX
Y2
12
#37
FFFF68H
UART 1 TX / UART 3 TX
Y1
13
#38
FFFF64H
Reset
N
INT9 instruction
N
Interrupt control
register
Interrupt vector
#08
FFFFDCH
#09
FFFFD8H
#10
FFFFD4H
#11
FFFFD0H
#12
FFFFCCH
#13
FFFFC8H
#14
FFFFC4H
#15
FFFFC0H
#16
FFFFBCH
Number
Address
ICR00
0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03
0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
(Continued)
Document Number: 002-04498 Rev. *A
Page 48 of 92
MB90340E Series
(Continued)
EI2OS
Support
Interrupt cause
DMA
channel
number
Interrupt vector
Number
Address
UART 2 RX / UART 4 RX
Y2
14
#39
FFFF60H
UART 2 TX / UART 4 TX
Y1
15
#40
FFFF5CH
Flash Memory
N
#41
FFFF58H
Delayed Interrupt
N
#42
FFFF54H
Y1
Y2
N
Note:
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
: Usable
: Usable, with EI2OS stop function
: Unusable
The peripheral resources sharing the ICR register have the same interrupt level.
When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
Document Number: 002-04498 Rev. *A
Page 49 of 92
MB90340E Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Parameter
Symbol
VCC
Rating
Min
VSS 0.3
AVCC
VSS 0.3
AVRH,
AVRL
Input voltage*1
VI
Output voltage*1
VO
Power supply voltage*1
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
Operating temperature
Storage temperature
VSS 6.0
Unit
Remarks
V
VSS 6.0
V
VSS 0.3
VSS 6.0
V
VSS 0.3
VSS 6.0
AVCC AVRH, AVCC AVRL, AVRH
AVRL
V
*3
V
*3
4.0
mA
*5
40
mA
*5
15
mA
*4, *6
4
mA
*4, *7
VSS 0.3
4.0
|ICLAMP|
IOL
IOLAV
IOL
IOLAV
IOH
IOHAV
IOH
IOHAV
PD
40
TA
55
TSTG
ICLAMP
Max
VSS 6.0
VCC AVCC*2
100
mA
*4
50
mA
*4, *8
mA
*4, *6
mA
*4, *7
15
4
100
50
450
105
150
mA
*4
mA
*4, *8
mW
°C
°C
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does
not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an
input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0, PA1
*5: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (Evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
Use within recommended operating conditions.
Use with DC voltage (current)
The B signal should always be applied by using a limiting resistance placed between the B signal and the microcontroller.
The value of the limiting resistance should be set so that when the B signal is applied, the input current to
the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
(Continued)
Document Number: 002-04498 Rev. *A
Page 50 of 92
MB90340E Series
(Continued)
Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the B input pin open.
Sample recommended circuits:
Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
B input
P-ch
(0 V to 16 V)
N-ch
R
*6: The maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*7: The average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins.
*8: The average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04498 Rev. *A
Page 51 of 92
MB90340E Series
11.2 Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
VCC,
AVCC
(VSS AVSS 0 V)
Value
Min
Typ
Unit
Max
Remarks
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation, when not using the A/D
converter and not Flash
programming.
4.5
5.0
5.5
V
When External bus is used.
3.0
5.5
V
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of better AC
characteristics. Capacitor at the VCC should be
greater than this
capacitor.
Smoothing capacitor
CS
0.1
1.0
F
Operating temperature
TA
40
105
°C
C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-04498 Rev. *A
Page 52 of 92
MB90340E Series
11.3 DC Characteristics
Parameter
Symb
ol
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Pin
Condition
Min
Value
Typ
Max
Unit
Remarks
VIHS
0.8 VCC
VCC 0.3
V
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VIHA
0.8 VCC
VCC 0.3
V
Port inputs if
Automotive input levels are selected
VIHT
2.0
VCC 0.3
V
Port inputs if TTL input levels are
selected
VIHS
0.7 VCC
VCC 0.3
V
P12, P50, P82, P85
inputs if CMOS input levels are
selected
VIHI
0.7 VCC
VCC 0.3
V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
V
VCC 0.3
VCC 0.3
VCC 0.3
RST input pin
(CMOS hysteresis)
VIHM
V
MD input pin
VILS
VSS 0.3
0.2 VCC
V
Port inputs if CMOS
hysteresis input levels are selected
(except P12, P44, P45, P46, P47,
P50, P82, P85)
VILA
VSS 0.3
0.5 VCC
V
Port inputs if
Automotive input levels are selected
VILT
VSS 0.3
0.8
V
Port inputs if TTL
input levels are selected
VILS
VSS 0.3
0.3 VCC
V
P12, P50, P82, P85
inputs if CMOS input levels are
selected
VILI
VSS 0.3
0.3 VCC
V
P44, P45, P46, P47
inputs if CMOS hysteresis
input levels are selected
VSS 0.3
V
VSS 0.3
RST input pin
(CMOS hysteresis)
V
MD input pin
Output H
voltage
VOH
Normal
outputs
VCC 0.5
0.2 VCC
VILM
V
Output H
voltage
VOHI
I2C current
outputs
VCC 0.5
V
Output L
voltage
VOL
Normal
outputs
0.4
V
Output L
voltage
VOLI
I2C current
outputs
0.4
V
Input H
voltage
(At VCC
5 V 10)
VIHR
Input L
voltage
(At VCC
5 V 10)
VILR
VCC 4.5 V,
IOH 4.0 mA
VCC 4.5 V,
IOH 3.0 mA
VCC 4.5 V,
IOL 4.0 mA
VCC 4.5 V,
IOL 3.0 mA
0.8 VCC
VSS 0.3
(Continued)
Document Number: 002-04498 Rev. *A
Page 53 of 92
MB90340E Series
(Continued)
Parameter
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbo
l
Pin
Condition
Min
Value
Typ
Max
Unit
Remarks
IIL
VCC 5.5 V, VSS VI VCC
1
1
A
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
25
50
100
k
Pull-down
resistance
RDOWN
MD2
25
50
100
k
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
55
70
mA
70
85
mA
Flash
memory
devices
75
90
mA
Flash
memory
devices
25
35
mA
0.3
0.8
mA
ICTSPLL6 VCC
VCC 5.0 V,
Internal frequency : 24 MHz,
In PLL Timer mode,
external frequency 4 MHz
4
7
mA
ICCL
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub operation
TA = 25C
70
140
A
ICCLS
VCC = 5.0 V
Internal frequency : 8 kHz,
In sub sleep
TA = 25C
20
50
A
ICCT
VCC = 5.0 V
Internal frequency : 8 kHz,
In watch mode
TA = 25C
10
35
A
VCC 5.0 V,
In Stop mode,
TA 25C
7
25
A
5
15
pF
Input leak current
VCC 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
ICC
VCC 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
VCC 5.0 V,
Internal frequency : 24 MHz,
In Sleep mode.
ICCS
VCC 5.0 V,
Internal frequency : 2 MHz,
In Main Timer mode
ICTS
Power supply
current*
ICCH
Input capacitance
CIN
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS
Except Flash
memory
devices
* : The power supply current is measured with an external clock.
Document Number: 002-04498 Rev. *A
Page 54 of 92
MB90340E Series
11.4 AC Characteristics
11.4.1 Clock Timing
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Clock frequency
Symbol
fC
X0, X1
fCL
Clock cycle time
tCYL
tCYLL
Value
Pin
Min
Typ
16
MHz
When using an oscillation circuit
4
16
MHz
PLL multiplied by 1
When using an oscillation circuit
4
12
MHz
PLL multiplied by 2
When using an oscillation circuit
4
8
MHz
PLL multiplied by 3
When using an oscillation circuit
4
6
MHz
PLL multiplied by 4
When using an oscillation circuit
4
MHz
PLL multiplied by 6
When using an oscillation circuit
3
24
MHz
When using an external clock*
—
X0, X1
62.5
X0, X1
41.67
X0A, X1A
10
32.768
30.5
PWH, PWL
X0
10
X0A
5
15.2
Input clock rise and fall time
tCR, tCF
X0
Internal operating clock
frequency (machine clock)
fCP
Internal operating clock
cycle time (machine clock)
fCPL
tCP
tCPL
Remarks
X0A, X1A
Unit
3
PWHL, PWLL
Input clock pulse width
Max
1.5
100
kHz
333
ns
333
ns
When using an external clock
s
—
When using an oscillation circuit
ns
s
Duty ratio is about 30 to 70.
5
ns
When using external clock
24
MHz
When using main clock
8.192
50
kHz
When using sub clock
41.67
666
ns
When using main clock
20
122.1
s
When using sub clock
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within the range as
mentioned in “Relation between the external clock frequency and machine clock frequency”.
Document Number: 002-04498 Rev. *A
Page 55 of 92
MB90340E Series
Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
Document Number: 002-04498 Rev. *A
tCR
Page 56 of 92
MB90340E Series
Guaranteed PLL operation range
Guaranteed operation range
Power supply voltage
VCC (V)
5.5
Guaranteed A/D Converter
operation range
4.0
3.5
Guaranteed PLL operation range
1.5
24
4
Machine clock fCP (MHz)
Guaranteed operation range of MB90340E series
Guaranteed oscillation frequency range
x6
Internal clock
fCP (MHz)
24
x4
x3
x2
x1
16
x 1/2
(PLL off)
12
8
4.0
1.5
3
4
8
12
16
24
External clock fC (MHz) *
* : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
Document Number: 002-04498 Rev. *A
Page 57 of 92
MB90340E Series
11.4.2 Reset Standby Input
Parameter
Reset input time
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0.0 V)
Symbol
tRSTL
Value
Pin
Min
RST
Unit
Max
Remarks
500
ns
Under normal operation
Oscillation time of oscillator*
100 s
s
In Stop mode, Sub Clock mode,
Sub Sleep mode and Watch
mode
100
s
In Time Timer mode
* : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred s and several ms, and for an external clock, the time is 0 ms.
Under
normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
Document Number: 002-04498 Rev. *A
Page 58 of 92
MB90340E Series
11.4.3 Power On Reset
Parameter
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0.0 V)
Symbol
Pin
Power on rise time
tR
VCC
Power off time
tOFF
VCC
Value
Condition
Min
Max
Unit
0.05
30
ms
1
ms
Remarks
Waiting time until power-on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note:
: If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup
smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below.
Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL
clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
Holds RAM data
VSS
11.4.4 Clock Output Timing
Parameter
Symbol
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Pin
Condition
Cycle time
tCYC
CLK
CLK CLK
tCHCL
CLK
Document Number: 002-04498 Rev. *A
Value
Min
62.5
41.67
20
13
Max
Unit
ns
ns
ns
ns
Remarks
fCP 16 MHz
fCP 24 MHz
fCP 16 MHz
fCP 24 MHz
Page 59 of 92
MB90340E Series
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
Document Number: 002-04498 Rev. *A
Page 60 of 92
MB90340E Series
11.4.5 Bus Timing (Read)
Parameter
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Symbol
Pin
Value
Condition
Min
Max
Unit
tLHLL
ALE
tCP/2 10
ns
tAVLL
ALE, A23 to A16, AD15 to
AD00
tCP/2 20
ns
tLLAX
ALE, AD15 to AD00
tCP/2 15
ns
tAVRL
A23 to A16,
AD15 to AD00, RD
tCP 15
ns
Valid address
Valid data input
tAVDV
A23 to A16,
AD15 to AD00
5 tCP/2 60
ns
RD pulse width
tRLRH
RD
3 tCP/2 20
ns
Valid data input
tRLDV
RD, AD15 to AD00
Data hold time
tRHDX
RD, AD15 to AD00
0
ALE time
tRHLH
RD, ALE
tCP/2 15
Address valid time
tRHAX
RD, A23 to A16
tCP/2 10
tAVCH
A23 to A16,
AD15 to AD00, CLK
tCP/2 16
tRLCH
RD, CLK
tCP/2 15
tLLRL
ALE, RD
ALE pulse width
Valid address
ALE time
ALE
Address valid time
Valid address
RD time
RD
RD
RD
RD
Valid address
CLK time
RD
ALE
CLK time
RD time
tCP/2 15
ns
ns
ns
ns
ns
ns
ns
tRLCH
tAVCH
CLK
3 tCP/2 50
2.4 V
2.4 V
0.8 V
tLLAX
tAVLL
2.4 V
ALE
tRHLH
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
AD15 to AD00
2.4 V
0.8 V
Document Number: 002-04498 Rev. *A
Address
2.4 V
VIH
0.8 V
VIL
Read data
VIH
VIL
Page 61 of 92
MB90340E Series
11.4.6 Bus Timing (Write)
Parameter
WR
WR
Value
Condition
Min
tCP15
tWLWH
WR
3 tCP/2 20
tDVWH
AD15 to AD00, WR
Data hold time
tWHDX
AD15 to AD00, WR
Address valid time
tWHAX
A23 to A16, WR
ALE time
tWHLH
WR, ALE
CLK time
tWLCH
WR, CLK
Valid data output
WR
Pin
A23 to A16, AD15
to AD00, WR
WR time
WR pulse width
WR
Symbol
tAVWL
Valid address
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
WR time
3 tCP/2 20
15
tCP/2 10
tCP/2 15
tCP/2 15
Max
Unit
ns
ns
ns
ns
ns
ns
ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
WR (WRL, WRH)
2.4 V
0.8 V
tWHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
0.8 V
Document Number: 002-04498 Rev. *A
Address
2.4 V
0.8 V
Write data
tWHDX
2.4 V
0.8 V
Page 62 of 92
MB90340E Series
11.4.7 Ready Input Timing
Parameter
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Note:
Rated Value
Test
Condition
Min
45
Max
32
0
Unit
ns
ns
Remarks
fCP 16 MHz
fCP 24 MHz
ns
: If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
RDY
When WAIT is not used.
RDY
When WAIT is used.
Document Number: 002-04498 Rev. *A
tRYHS
tRYHH
VIH
VIH
VIL
Page 63 of 92
MB90340E Series
11.4.8 Hold Timing
(TA 40°C to 105°C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Parameter
HAK time
HAK time Pin valid time
Pin floating
Note:
Symbol
Pin
tXHAL
HAK
tHAHV
HAK
Value
Condition
Min
Max
Unit
30
tCP
ns
tCP
2 tCP
ns
: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Each pin
Document Number: 002-04498 Rev. *A
2.4 V
0.8 V
Hi-Z
2.4 V
0.8 V
Page 64 of 92
MB90340E Series
11.4.9 LIN-UART0/1/2/3
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Parameter
Symbol
Pin
Value
Condition
Min
Max
Unit
5 tCP
ns
50
50
ns
tCP + 80
ns
0
ns
Serial clock cycle time
tSCYC
SCK0 to SCK3
SCK SOT delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN SCK
tIVSHI
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
tSHIXI
SCK0 to SCK3,
SIN0 to SIN3
Serial clock “L” pulse width
tSHSL
SCK0 to SCK3
3 tCP - tR
Serial clock “H” pulse width
tSLSH
SCK0 to SCK3
tCP + 10
SCK SOT delay time
tSLOVE
SCK0 to SCK3,
SOT0 to SOT3
2 tCP + 60
ns
Valid SIN SCK
tIVSHE
SCK0 to SCK3,
SIN0 to SIN3
30
ns
SCK Valid SIN hold time
tSHIXE
SCK0, SCK1,
SIN0 to SIN3
tCP + 30
ns
SCK fall time
tF
SCK0 to SCK3
10
ns
SCK rise time
tR
SCK0 to SCK3
10
ns
Note:
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
External shift clock
mode output pins are
CL 80 pF 1 TTL.
ns
ns
AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
Internal Shift Clock Mode
tSCYC
SCK0 to SCK3
2.4 V
0.8 V
0.8 V
tSLOVI
SOT0 to SOT3
2.4 V
0.8 V
tIVSHI
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
tSHIXI
VIH
VIH
VIL
VIL
Page 65 of 92
MB90340E Series
External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK0 to SCK3
VIL
VIL
tSLOVE
tF
tR
2.4 V
SOT0 to SOT3
0.8 V
tIVSHE
SIN0 to SIN3
tSHIXE
VIH
VIH
VIL
VIL
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Parameter
Serial clock cycle time
Symbol
Pin
Max
Unit
ns
50
50
ns
tCP + 80
ns
SCK0 to SCK3,
SIN0 to SIN3
0
ns
tSHSL
SCK0 to SCK3
3 tCP - tR
tSLSH
SCK0 to SCK3
tCP + 10
tSHOVE
SCK0 to SCK3,
SOT0 to SOT3
2 tCP + 60
ns
30
ns
tCP + 30
ns
10
ns
10
ns
SCK0 to SCK3
SCK SOT delay time
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN SCK
tIVSLI
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
Valid SIN SCK
tIVSLE
SCK0 to SCK3,
SIN0 to SIN3
SCK Valid SIN hold time
tSLIXE
SCK0 to SCK3,
SIN0 to SIN3
SCK fall time
tF
SCK0 to SCK3
SCK rise time
tR
SCK0 to SCK3
Note:
Min
5 tCP
tSCYC
SCK SOT delay time
Value
Condition
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
External shift clock
mode output pins are
CL 80 pF 1 TTL.
ns
ns
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Document Number: 002-04498 Rev. *A
Page 66 of 92
MB90340E Series
Internal Shift Clock Mode
tSCYC
SCK0 to SCK3
2.4 V
0.8 V
tSHOVI
2.4 V
SOT0 to SOT3
0.8 V
tIVSLI
SIN0 to SIN3
tSLIXI
VIH
VIH
VIL
VIL
External Shift Clock Mode
tSHSL
VIL
tR
SOT0 to SOT3
VIH
VIH
SCK0 to SCK3
tSLSH
tSHOVE
VIL
tF
2.4 V
0.8 V
tIVSLE
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
tSLIXE
VIH
VIH
VIL
VIL
Page 67 of 92
MB90340E Series
Bit setting: ESCR:SCES 0, ECCR:SCDE 1
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Parameter
Symbol
Pin
Value
Condition
Min
Max
Unit
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
ns
SCK SOT delay time
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
50
50
ns
Valid SIN SCK
tIVSLI
SCK0 to SCK3,
SIN0 to SIN3
ns
SCK Valid SIN hold time
tSLIXI
SCK0 to SCK3,
SIN0 to SIN3
ns
SOT SCK delay time
tSOVLI
SCK0 to SCK3,
SOT0 to SOT3
ns
Note:
Internal clock operation output
tCP 80
pins are
CL 80 pF 1 TTL.
0
3 tCP 70
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
tSCYC
2.4 V
SCK0 to SCK3
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT0 to SOT3
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
VIH
VIL
tSLIXI
VIH
VIL
Page 68 of 92
MB90340E Series
Bit setting: ESCR:SCES 1, ECCR:SCDE 1
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Parameter
Symbol
Pin
Value
Condition
Min
Max
Unit
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
ns
SCK SOT delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
50
50
ns
Valid SIN SCK
tIVSHI
SCK0 to SCK3,
SIN0 to SIN3
tCP 80
ns
SCK Valid SIN hold time
tSHIXI
SCK0 to SCK3,
SIN0 to SIN3
0
ns
SOT SCK delay time
tSOVHI
SCK0 to SCK3,
SOT0 to SOT3
3 tCP 70
ns
Note:
Internal clock operation
output pins are
CL 80 pF 1 TTL.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
tSCYC
2.4 V
2.4 V
SCK0 to SCK3
0.8 V
tSLOVI
tSOVHI
SOT0 to SOT3
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN0 to SIN3
Document Number: 002-04498 Rev. *A
tSHIXI
VIH
VIH
VIL
VIL
Page 69 of 92
MB90340E Series
11.4.10 Trigger Input Timing
Parameter
Input pulse width
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0.0 V)
Symbol
tTRGH
tTRGL
INT0 to INT15,
INT0R to INT15R,
ADTG
Document Number: 002-04498 Rev. *A
Pin
Condition
INT0 to INT15,
INT0R to INT15R,
ADTG
Value
Min
5 tCP
Max
Unit
ns
VIH
VIH
VIL
VIL
tTRGH
tTRGL
Page 70 of 92
MB90340E Series
11.4.11 Timer Related Resource Input Timing
Parameter
(TA 40°C to 105°C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Symbol
Pin
tTIWH
Input pulse width
TIN0 to TIN3,
IN0 to IN7
tTIWL
Value
Condition
Min
4 tCP
TIN0 to TIN3,
IN0 to IN7
VIL
VIL
tTIWH
Parameter
tTO
CLK
tTIWL
(TA = –40C to +105C, VCC 5.0 V 10, fCP 24 MHz, VSS = 0.0 V)
Symbol
CLK TOUT change time
ns
VIH
VIH
11.4.12 Timer Related Resource Output Timing
Unit
Max
Pin
Value
Condition
TOT0 to TOT3,
PPG0 to PPGF
Min
30
Unit
Max
ns
2.4 V
2.4 V
TOT0 to TOT3,
PPG0 to PPGF
0.8 V
tTO
Document Number: 002-04498 Rev. *A
Page 71 of 92
MB90340E Series
11.4.13 I2C Timing
(TA –40C to +105C, VCC 5.0 V 10, VSS 0.0 V)
Parameter
Symbol
Condition
Fast-mode*1
Standard-mode
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA SCL
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
“H” width of the SCL clock
tHIGH
4.0
0.6
s
s
Set-up time (repeated) START condition
SCL SDA
tSUSTA
4.7
0.6
s
Data hold time
SCL SDA
tHDDAT
0
3.45*3
0
0.9*4
s
Data set-up time
SDA SCL
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL SDA
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START condition
tBUS
4.7
1.3
s
R 1.7 k,
C 50 pF*2
1.3
*1:For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2:R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3:The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4:A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be
met.
VIH
VIH
VIH
VIH
SDA
VIL
VIL
tSUDAT
VIH
tLOW
VIH
SCL
VIH
VIH
VIL
tHDSTA
VIH
tBUS
VIH
VIL
VIL VIL
tHDSTA
VIL
tHDDAT
Document Number: 002-04498 Rev. *A
tHIGH
tSUSTA
tSUSTO
Page 72 of 92
MB90340E Series
11.5 A/D Converter
(TA 40°C to 105°C, 3.0 V AVRH AVRL, VCC AVCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Symbol
Value
Pin
Min
Typ
Max
Unit
Nonlinearity error
Differential
nonlinearity error
1.9
LSB
Zero reading
voltage
VOT
AN0 to AN23
AVRL
1.5 LSB
AVRL
0.5 LSB
AVRL
2.5 LSB
V
Full scale reading
voltage
VFST
AN0 to AN23
AVRH
3.5 LSB
AVRH
1.5 LSB
AVRH
0.5 LSB
V
Compare time
1.0
16500
s
0.5
Resolution
Total error
Sampling time
Analog port input
current
IAIN
AN0 to AN23
Analog input
voltage range
VAIN
Reference
voltage range
Power supply
current
Reference
voltage current
Offset between
input channels
2.0
10
3.0
2.5
bit
LSB
LSB
s
0.3
0.3
A
AN0 to AN23
AVRL
AVRH
V
AVRH
AVRL 2.7
AVCC
V
AVRL
0
1.2
IR
AVRH
IRH
AVRH
AN0 to AN23
IA
AVCC
IAH
AVCC
AVRH 2.7
Remarks
4.5 V AVCC 5.5 V
4.0 V AVCC
< 4.5 V
4.0 V AVCC
< 4.5 V
4.5 V AVCC 5.5 V
V
3.5
7.5
5
600
900
5
A
A
A
mA
4
LSB
*
*
*: If the A/D convertor is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Note: : The accuracy gets worse as |AVRH AVRL| becomes smaller.
Document Number: 002-04498 Rev. *A
Page 73 of 92
MB90340E Series
11.6 Definition of A/D Converter Terms
Resolution
Non linearity
error
: Analog variation that is recognized by the A/D converter.
Differential
linearity error
Total error
:
: The deviation between the actual conversion characteristics and a line that joins the
zero-transition line ( “00 0000 0000” “00 0000 0001” ) to the full-scale transition line
( “11 1111 1110” “11 1111 1111” ) .
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
: Difference between the actual value and the ideal value. The total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
Actual conversion
characteristics
1.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVRL
AVRH
Analog input
Total error of digital output “N”
1 LSB (Ideal value)
VNT {1 LSB (N 1)
1 LSB
AVRH AVRL
[V]
1024
0.5 LSB}
[LSB]
N : Value of the digital output from the A/D converter
AVRL 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VOT (Ideal value)
VNT : A voltage at which the digital output transitions from (N 1)H to NH.
(Continued)
Document Number: 002-04498 Rev. *A
Page 74 of 92
MB90340E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Digital output
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
(N + 1)H
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
003H
Actual conversion
characteristics
Digital output
3FEH
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
(N − 1)H
002H
Ideal characteristics
Actual conversion
characteristics
(N − 2)H
001H
VOT (actual measurement value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Non linearity error of digital output N
VNT {1 LSB (N 1)
1 LSB
Differential linearity error of digital output N
1 LSB
V (N+1) T VNT
1 LSB
VFST VOT
1022
VOT} [LSB]
1 LSB [LSB]
[V]
N : Value of the digital output from the A/D converter
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
11.7 Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 k or lower (4.0 V AVCC 5.5 V,
sampling period 0.5 s)
If an external capacitor is used, in consideration of the capacitive voltage dividing effect between the external capacitor and the
internal on-chip capacitor, it is recommended that the capacitance of the external capacitor be several thousand times greater than
the capacitance of the internal capacitor.
Document Number: 002-04498 Rev. *A
Page 75 of 92
MB90340E Series
If the output impedance of the external circuit is too high, a sampling period for an analog voltage may be insufficient.
A Analog input circuit model
Analog input
R
Comparator
C
4.5 V AVCC 5.5 V : R =: 2.52 k, C =: 10.7 pF
4.0 V AVCC < 4.5 V : R =: 13.6 k, C =: 10.7 pF
Note:
: Use the values in the figure only as a guideline.
Document Number: 002-04498 Rev. *A
Page 76 of 92
MB90340E Series
11.8 Flash Memory Program/Erase Characteristics
Parameter
Sector erase time
Chip erase time
Value
Conditions
TA 25°C
VCC 5.0 V
Word (16-bit width)
programming time
Min
Typ
Unit
Max
Remarks
1
15
s
Excludes programming prior to
erasure
9
s
Excludes programming prior to
erasure
16
3600
s
Except for the over head time of
the system
Program/Erase cycle
10000
cycle
Flash Data Retention Time
Average
TA 85°C
20
year
*
* : This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to translate high
temperature measurements into normalized value at 85°C) .
Document Number: 002-04498 Rev. *A
Page 77 of 92
MB90340E Series
12. Example Characteristics
MB90F346E, MB90F346ES, MB90F346CE, MB90F346CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
ICC (mA)
f = 20 MHz
40
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
30
20
10
0
2.5
3.5
4.5
5.5
ICCL ( A)
f = 24 MHz
50
6.5
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
35
30
ICCS (mA)
f = 20 MHz
20
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
15
10
5
0
ICCLS ( A)
f = 24 MHz
25
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
50
45
40
35
30
25
20
15
10
5
0
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTS VCC
ICCT VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, external clock operation, f Internal operation frequency
400
ICTS ( A)
300
f = 2 MHz
250
200
150
ICCT ( A)
350
100
50
0
2.5
3.5
4.5
5.5
6.5
20
18
16
14
12
10
8
6
4
2
0
f = 8 kHz
2.5
3.5
VCC (V)
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
5.5
6.5
ICCH ( A)
ICTSPLL6 (mA)
f = 24 MHz
10
9
8
7
6
5
4
3
2
1
0
2.5
5.5
6.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
ICCH VCC
TA 25°C, external clock operation, f Internal operation frequency TA 25°C, stopped
10
9
8
7
6
5
4
3
2
1
0
4.5
3.5
4.5
VCC (V)
Page 78 of 92
MB90340E Series
MB90F347E, MB90F347ES, MB90F347CE, MB90F347CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
ICC (mA)
f = 20 MHz
40
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
30
20
10
0
2.5
3.5
4.5
5.5
ICCL ( A)
f = 24 MHz
50
6.5
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
30
ICCS (mA)
f = 20 MHz
20
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
15
10
5
0
ICCLS ( A)
f = 24 MHz
25
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
50
45
40
35
30
25
20
15
10
5
0
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICTS VCC
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
ICTS ( A)
300
f = 2 MHz
250
200
150
ICCT ( A)
350
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
ICTSPLL6 (mA)
TA 25°C, external clock operation f Internal operation frequency
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
f = 8 kHz
2.5
3.5
5.5
6.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH ( A)
0
2.5
20
18
16
14
12
10
8
6
4
2
0
10
9
8
7
6
5
4
3
2
1
0
2.5
3.5
4.5
VCC (V)
Page 79 of 92
MB90340E Series
MB90F349E, MB90F349ES, MB90F349CE, MB90F349CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
70
60
ICC (mA)
f = 20 MHz
f = 16 MHz
40
f = 12 MHz
f = 10 MHz
f = 8 MHz
30
20
f = 4 MHz
f = 2 MHz
10
0
ICCL (µA)
f = 24 MHz
50
2.5
3.5
4.5
5.5
6.5
100
90
80
70
60
50
40
30
20
10
0
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
f = 24 MHz
25
f = 20 MHz
20
f = 16 MHz
15
f = 12 MHz
f = 10 MHz
f = 8 MHz
10
5
ICCLS (µA)
ICCS (mA)
30
f = 4 MHz
f = 2 MHz
0
2.5
3.5
4.5
5.5
50
45
40
35
30
25
20
15
10
5
0
f = 8 kHz
2.5
6.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCT VCC
ICTS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
ICTS (µA)
300
f = 2 MHz
250
200
150
ICCT (µA)
350
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
ICTSPLL6 (mA)
TA 25°C, external clock operation f Internal operation frequency
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
f = 8 kHz
2.5
3.5
5.5
6.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH (µA)
0
2.5
20
18
16
14
12
10
8
6
4
2
0
10
9
8
7
6
5
4
3
2
1
0
2.5
3.5
4.5
VCC (V)
Page 80 of 92
MB90340E Series
MB90F342E, MB90F342ES, MB90F342CE, MB90F342CES
ICC VCC
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
70
60
ICC (mA)
f = 20 MHz
f = 16 MHz
40
f = 12 MHz
f = 10 MHz
f = 8 MHz
30
20
f = 4 MHz
f = 2 MHz
10
0
ICCL (µA)
f = 24 MHz
50
2.5
3.5
4.5
5.5
6.5
100
90
80
70
60
50
40
30
20
10
0
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS VCC
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
35
f = 24 MHz
25
f = 20 MHz
20
f = 16 MHz
15
f = 12 MHz
f = 10 MHz
f = 8 MHz
10
5
ICCLS (µA)
ICCS (mA)
30
f = 4 MHz
f = 2 MHz
0
2.5
3.5
4.5
5.5
50
45
40
35
30
25
20
15
10
5
0
f = 8 kHz
2.5
6.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCT VCC
ICTS VCC
TA 25°C, external clock operation f Internal operation frequency TA 25°C, external clock operation f Internal operation frequency
400
ICTS (µA)
300
f = 2 MHz
250
200
150
ICCT (µA)
350
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
ICTSPLL6 (mA)
TA 25°C, external clock operation f Internal operation frequency
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
f = 8 kHz
2.5
3.5
5.5
6.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH (µA)
0
2.5
20
18
16
14
12
10
8
6
4
2
0
10
9
8
7
6
5
4
3
2
1
0
2.5
3.5
4.5
VCC (V)
Page 81 of 92
MB90340E Series
MB90F345E, MB90F345ES, MB90F345CE, MB90F345CES
ICC VCC
TA 25°C, external clock operation f Internal operation frequency
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
70
60
ICC (mA)
f = 20 MHz
f = 16 MHz
40
f = 12 MHz
f = 10 MHz
f = 8 MHz
30
20
f = 4 MHz
f = 2 MHz
10
0
ICCL ( A)
f = 24 MHz
50
2.5
3.5
4.5
5.5
100
90
80
70
60
50
40
30
20
10
0
6.5
VCC (V)
ICCS VCC
TA 25°C, external clock operation f Internal operation frequency
f = 20 MHz
20
f = 16 MHz
15
f = 12 MHz
f = 10 MHz
f = 8 MHz
10
f = 4 MHz
f = 2 MHz
5
0
2.5
3.5
4.5
5.5
200
150
ICCT ( A)
ICTS ( A)
f = 2 MHz
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 (mA)
ICTSPLL6 VCC
TA 25°C, external clock operation f Internal operation frequency
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
5.5
6.5
6.5
f = 8 kHz
2.5
3.5
20
18
16
14
12
10
8
6
4
2
0
4.5
5.5
6.5
f = 8 kHz
2.5
3.5
10
9
8
7
6
5
4
3
2
1
0
2.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH ( A)
0
2.5
5.5
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
350
250
4.5
VCC (V)
400
300
50
45
40
35
30
25
20
15
10
5
0
6.5
ICTS VCC
TA 25°C, external clock operation f Internal operation frequency
3.5
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
ICCLS ( A)
ICCS (mA)
f = 24 MHz
25
2.5
VCC (V)
35
30
f = 8 kHz
3.5
4.5
VCC (V)
Page 82 of 92
MB90340E Series
MB90346E, MB90346ES, MB90346CE, MB90346CES
ICC VCC
TA 25°C, external clock operation f Internal operation frequency
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
70
60
f = 12 MHz
f = 10 MHz
f = 8 MHz
30
20
f = 4 MHz
f = 2 MHz
10
0
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICCS (mA)
ICCS VCC
TA 25°C, external clock operation f Internal operation frequency
50
30
f = 24 MHz
25
f = 20 MHz
20
f = 16 MHz
15
f = 12 MHz
f = 10 MHz
f = 8 MHz
45
40
35
30
25
20
15
10
5
0
f = 4 MHz
5
0
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICTS VCC
TA 25°C, external clock operation f Internal operation frequency
150
ICCT (µA)
ICTS (µA)
300
200
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
ICTSPLL6 (mA)
TA 25°C, external clock operation f Internal operation frequency
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
5.5
6.5
5.5
6.5
f = 8 kHz
2.5
3.5
20
18
16
14
12
10
8
6
4
2
0
4.5
5.5
6.5
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH (µA)
0
2.5
4.5
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
350
f = 2 MHz
3.5
VCC (V)
400
250
2.5
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
35
10
f = 8 kHz
VCC (V)
ICCLS (µA)
ICC (mA)
f = 20 MHz
f = 16 MHz
40
ICCL (µA)
f = 24 MHz
50
100
90
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
0
2.5
3.5
4.5
VCC (V)
Page 83 of 92
MB90340E Series
MB90347E, MB90347ES, MB90347CE, MB90347CES
ICC VCC
TA 25°C, external clock operation f Internal operation frequency
ICCL VCC
TA 25°C, external clock operation f Internal operation frequency
70
60
ICC (mA)
f = 20 MHz
f = 16 MHz
40
f = 12 MHz
f = 10 MHz
f = 8 MHz
30
20
f = 4 MHz
f = 2 MHz
10
0
ICCL (µA)
f = 24 MHz
50
2.5
3.5
4.5
5.5
100
90
80
70
60
50
40
30
20
10
0
6.5
VCC (V)
ICCS VCC
TA 25°C, external clock operation f Internal operation frequency
25
f = 20 MHz
20
f = 16 MHz
15
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
5
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
VCC (V)
ICTS VCC
TA 25°C, external clock operation f Internal operation frequency
5.5
6.5
200
150
ICCT (µA)
300
f = 2 MHz
100
50
3.5
4.5
5.5
6.5
VCC (V)
ICTSPLL6 VCC
TA 25°C, external clock operation f Internal operation frequency
f = 24 MHz
2.5
3.5
4.5
VCC (V)
Document Number: 002-04498 Rev. *A
2.5
3.5
20
18
16
14
12
10
8
6
4
2
0
5.5
6.5
4.5
5.5
6.5
f = 8 kHz
2.5
3.5
4.5
5.5
6.5
5.5
6.5
VCC (V)
ICCH VCC
TA 25°C, stopped
ICCH (µA)
0
2.5
f = 8 kHz
ICCT VCC
TA 25°C, external clock operation f Internal operation frequency
350
250
45
40
35
30
25
20
15
10
5
0
VCC (V)
400
ICTS (µA)
4.5
ICCLS VCC
TA 25°C, external clock operation f Internal operation frequency
ICCLS (µA)
ICCS (mA)
f = 24 MHz
10
ICTSPLL6 (mA)
3.5
50
30
10
9
8
7
6
5
4
3
2
1
0
2.5
VCC (V)
35
0
f = 8 kHz
10
9
8
7
6
5
4
3
2
1
0
2.5
3.5
4.5
VCC (V)
Page 84 of 92
MB90340E Series
I/O characteristics
(VCCVOH)
IOH
VOL IOL
TA 25°C, VCC 4.5 V
TA 25°C, VCC 4.5 V
800
600
VOL (mV)
VCC VOH (mV)
700
500
400
300
200
100
0
0
1
2
3
4
5
7
6
8
9
10
VIN (V)
VIN (V)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VCC (V)
TTL VIN VCC
VIN (V)
VIN (V)
4
5
6
7
8
9
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.5
7.0
VIHS
VILS
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
UART-SIN pin, I2C pin
TA 25°C
VIHT
VILT
2.5
3
CMOS VIN VCC
TA 25°C
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
2
Other than UART-SIN pin and I2C pin
TA 25°C
VIHA
VILA
2.5
1
CMOS VIN VCC
TA 25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
IOL (mA)
IOH (mA)
Automotive VIN VCC
1000
900
800
700
600
500
400
300
200
100
0
3.0
3.5
4.0
4.5
5.0
VCC (V)
Document Number: 002-04498 Rev. *A
5.5
6.0
6.5
7.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIHS
VILS
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VCC (V)
Page 85 of 92
MB90340E Series
13. Ordering Information
Part number
Package
Remarks
MB90F342EPF
MB90F342ESPF
MB90F342CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F342CESPF
MB90F342EPMC
MB90F342ESPMC
MB90F342CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F342CESPMC
MB90F345EPF
MB90F345ESPF
MB90F345CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F345CESPF
MB90F345EPMC
MB90F345ESPMC
MB90F345CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F345CESPMC
MB90F346EPF
MB90F346ESPF
MB90F346CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F346CESPF
MB90F346EPMC
MB90F346ESPMC
MB90F346CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F346CESPMC
(Continued)
Document Number: 002-04498 Rev. *A
Page 86 of 92
MB90340E Series
Part number
Package
Remarks
MB90F347EPF
MB90F347ESPF
MB90F347CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F347CESPF
MB90F347EPMC
MB90F347ESPMC
MB90F347CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F347CESPMC
MB90F349EPF
MB90F349ESPF
MB90F349CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F349CESPF
MB90F349EPMC
MB90F349ESPMC
MB90F349CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90F349CESPMC
MB90341EPF
MB90341ESPF
MB90341CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90341CESPF
MB90341EPMC
MB90341ESPMC
MB90341CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90341CESPMC
MB90342EPF
MB90342ESPF
MB90342CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90342CESPF
MB90342EPMC
MB90342ESPMC
MB90342CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90342CESPMC
(Continued)
Document Number: 002-04498 Rev. *A
Page 87 of 92
MB90340E Series
(Continued)
Part number
Package
Remarks
MB90346EPF
MB90346ESPF
MB90346CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90346CESPF
MB90346EPMC
MB90346ESPMC
MB90346CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90346CESPMC
MB90347EPF
MB90347ESPF
MB90347CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90347CESPF
MB90347EPMC
MB90347ESPMC
MB90347CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90347CESPMC
MB90348EPF
MB90348ESPF
MB90348CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90348CESPF
MB90348EPMC
MB90348ESPMC
MB90348CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90348CESPMC
MB90349EPF
MB90349ESPF
MB90349CEPF
100-pin plastic QFP
(FPT-100P-M06)
MB90349CESPF
MB90349EPMC
MB90349ESPMC
MB90349CEPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90349CESPMC
MB90V340E-101CR
MB90V340E-102CR
Document Number: 002-04498 Rev. *A
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
Page 88 of 92
MB90340E Series
14. Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
25
C
0.20±0.05
(.008±.002)
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
Document Number: 002-04498 Rev. *A
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 89 of 92
MB90340E Series
(Continued)
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7
Document Number: 002-04498 Rev. *A
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 90 of 92
MB90340E Series
15. Major Changes
Spansiion Publication Number: DS07-13747-4E
Page
51
Section
Change Results
Deleted the part numbers;
MB90F343E(S), MB90F343CE(S)
Electrical
Characteristics
Absolute Maximum Ratings
Added “*6” in remark for “L" level maximum output current and “H” level maximum
output current.
Added “*7” in remark for “L" level average output current and “H” level average
output current.
Added “*8” in remark for “L"level average overall output current and “H” level
average overall output current.
Added as follows.
“*6:The maximum output current is defined as the peak value of the current of any
one of the corresponding pins.”
“*7:The average output current is defined as the value of the average current
flowing over 100 ms at any one of the corresponding pins.”
“*8:The average total output current is defined as the value of the average current
flowing over 100 ms at all of the corresponding pins.”
52
NOTE: Please see “Document History” about later revised information.
Document History
Document Title: MB90340E Series F2MC-16LX 16-bit Microcontroller Datasheet
Document Number: 002-04498
Revision
ECN
**
*A
5221535
Orig. of
Change
Submission
Date
AKIH
08/23/2010
Migrated to Cypress and assigned document number 002-04498.
No change to document contents or format.
AKIH
05/04/2016
Updated to Cypress template
Document Number: 002-04498 Rev. *A
Description of Change
Page 91 of 92
MB90340E Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2006-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 002-04498 Rev. *A
Revised May 4,2016
Page 92 of 92